A digital frequency storage device with low spurious and large delay and its application method

Abstract

The present invention provides a digital frequency storage device with low spurious and large delay and its application method, belonging to the technical field of electronic warfare. The device includes: a QDR module, an ADC module, an FPGA module, and a DAC module. The implementation method adopted by the present invention reduces the memory capacity requirement of the QDR module and improves the placement and routing capabilities of the FPGA module. On the basis of reducing the spurious caused by AD devices, the target analog distance is increased by seven times, and at the same time, the normal temperature spurious of the AD device is reduced to more than -55 dBc. In addition, the programmable logic device FPGA adopted provides hardware guarantee for software upgrade; the ADC module adopted can simultaneously achieve 2.5 GSPS sampling of two intermediate frequency signals, and cooperate with the DAC module to simultaneously achieve two low-spurious and large-delay target simulations, increasing the flexibility of the system.

Description

Technical Field

[0001] The present invention relates to the technical field of signal processing and analysis, and particularly relates to a digital frequency storage device with low spurious and large delay and an application method thereof. Background Art

[0002] An ADC device includes an AD device and a DA device. The former quantizes an analog intermediate frequency signal into a digital signal, and the latter restores the digital signal into an analog intermediate frequency signal. In order to simulate realistic target types, AD devices and DA devices with higher effective bits are often required; in order to adapt to rich signal types, AD devices and DA devices with larger sampling rates have to be used. However, higher effective bits and larger sampling rates are also a pair of industry difficulties in themselves. At the same time, AD devices are more difficult to manufacture than DA devices because DA devices can be replaced by DDS devices, etc., and it is relatively easy to achieve better sampling rates and effective bits. Therefore, at the same sampling rate of 2.5 GSPS, the spurious of the DRFM signal is limited by the AD device. In the prior art, in the sampling rate of 2.5 GSPS and the input intermediate frequency range of 1.35 - 2.4 GHz, the spurious of the AD device can already reach -50 dBc, but it is expensive and the interface is generally 204B or 204C, with a large transmission response. Under the same conditions, the output intermediate frequency spurious of the DA device can easily reach -55 dBc.

[0003] As the first core component of the DRFM device, the storage device is used to store digital signals. By setting the storage delay, the set position of the target can be formed after processing at the radar end. Based on the sampling rate of 2.5 GSPS and the quantization bit number of 10 bits, the memory throughput rate can be calculated as 3.125 GBytes / s. In order to ensure the fastest and definite read and write delays, RAM - type memories such as QDR devices need to be used. However, such devices often have a small capacity, basically 72 Mbits. According to the above conditions, the maximum delay can be calculated as 2.88 milliseconds. According to the radar equation, the maximum simulated distance of the target is 432 kilometers, which poses a great limitation to the target movement, as Figure 1 shown.

[0004] As the second core component of the DRFM device, the FPGA device is used to generate the analog modulation of the radar target. Since the radar may transmit signals with agile frequencies, and the Doppler frequencies of signals with different frequencies in the same target echo are different, it is necessary to measure the frequencies of sub - pulses (or know the transmitted waveform frequency in advance), and track the sub - pulses. According to the measured signal frequencies, different Doppler frequencies are modulated for each sub - pulse, as Figure 2 . The FGPA also needs to complete device control, storage delay control, etc., which poses a severe challenge to the FPGA resources. Summary of the Invention

[0005] Objective of the Invention: To provide a digital frequency storage device with low spurious and large delay and its application method, and implement the functions of the device through the hardware programming language HDL, so as to solve the above problems existing in the prior art. Without increasing the hardware costs of AD devices and memories and the requirements of domestic production process indicators, develop a radar test device with lower spurious and larger delay, and meet the generation of target analog signals with low spurious and large delay.

[0006] Technical Solution: In the first aspect, a digital frequency storage device with low spurious and large delay is provided. The device specifically includes the following modules: ADC module, FPGA module, QDR module, and DAC module.

[0007] Among them, the ADC module is used for analog intermediate frequency sampling to generate a digital intermediate frequency signal; the FPGA module is connected to the ADC module and is used to receive the digital intermediate frequency sampling signal output by the ADC module, and perform target simulation on the digital intermediate frequency sampling signal according to the preset target time delay and echo Doppler to generate a digital intermediate frequency target simulation signal; the QDR module is connected to the FPGA module and is used to receive the digital intermediate frequency target simulation signal output by the FPGA, and perform storage reading and writing on the output signal of the FPGA module; at the same time, according to the read-write control input by the FPGA module, delay and output the digital zero intermediate frequency sampling signal to generate a zero intermediate frequency delay signal; the DAC module is connected to the FPGA module and is used to quantize the signal output by the FPGA module and generate an analog intermediate frequency signal.

[0008] In some realizable modes of the first aspect, the ADC module samples the input analog intermediate frequency to generate a digital intermediate frequency signal and outputs it to the FPGA module; the DAC module quantizes the digital signal of the FPGA module and outputs an analog intermediate frequency signal; the QDR module realizes the storage reading and writing of the digital signal of the FPGA module; the FPGA module performs target simulation on the analog intermediate frequency signal to generate a low-spurious and large-delay DRFM signal, and is connected to the ADC module, DAC module, and QDR module.

[0009] In some realizable modes of the first aspect, the program design of the FPGA module unit adopts a module unit with a pipeline structure of low coupling and high cohesion, including an ADC sampling unit, a DAC sampling unit, an intermediate frequency fast frequency measurement unit, a QDR storage delay unit, a first frequency shift modulation unit, an instantaneous octal decimation unit, and an instantaneous octal interpolation unit.

[0010] Inside the FPGA module, the ADC sampling unit is connected to the intermediate frequency fast frequency measurement unit and the instantaneous octal decimation unit. The QDR storage delay unit is connected to the instantaneous octal decimation unit and the frequency shift modulation unit. The frequency shift modulation unit is connected to the instantaneous octal interpolation unit. The instantaneous octal interpolation unit is simultaneously connected to the DAC sampling unit. The intermediate frequency fast frequency measurement unit is connected to the instantaneous octal decimation unit and the instantaneous octal interpolation unit.

[0011] Among them, the ADC sampling unit configures the registers of the ADC module and samples the intermediate frequency input at 2.5 GSPS. The intermediate frequency fast frequency measurement unit performs fast intermediate frequency measurement on the digital samples. The instantaneous octal decimation unit performs zero intermediate frequency transformation on the intermediate frequency digital samples and decimates by eight times to generate zero intermediate frequency digital signals. The QDR storage delay unit stores and delays the zero intermediate frequency digital signals. The first frequency shift modulation unit performs Doppler frequency shift on the zero intermediate frequency delayed digital signals. The instantaneous octal interpolation unit interpolates the octal decimated target analog signals by eight times and performs intermediate frequency transformation to generate digital intermediate frequency target analog signals. The DAC sampling unit configures the registers of the DAC module and converts the intermediate frequency digital target analog signals into the required data format of the DAC module.

[0012] In some realizable ways of the first aspect, the ADC sampling unit completes 2.5 GSPS sampling of the intermediate frequency input to obtain the digital intermediate frequency sampling signal y(n) = A(n)cos(2πf c nT s + φ(n)), n ∈ [0, 1, 2, …, N - 1]. Among them, T s represents the sampling time, f c represents the carrier frequency of the input signal; φ(n) represents the initial phase of the intermediate frequency input signal; A represents the amplitude of the intermediate frequency input signal; N represents the number of samples.

[0013] The intermediate frequency fast frequency measurement unit obtains the instantaneous frequency estimation of the intermediate frequency signal by looking up the table based on the phase difference of the digital intermediate frequency sampling signal

[0014] The instantaneous octal decimation unit generates 16-channel digital zero intermediate frequency sampling signals y for octal decimation based on the instantaneous frequency estimation of the intermediate frequency signal of the digital intermediate frequency sampling signal D2 (n), with a bit width of 10 bits and an operating clock frequency of 19.53125 MHz.

[0015] The QDR storage delay unit stores the digital zero intermediate frequency sampling signal y D2 (n) based on the indication of the 3.3V width-preserving pulse signal and outputs the zero intermediate frequency delayed digital signal y D2 (n - τ), where τ is the target delay beat number, and the expression is:

[0016]

[0017] In the formula, R 0 represents the relative distance between the radar and the simulated target; V represents the speed between the radar and the simulated target; a represents the acceleration between the radar and the simulated target; C represents the speed of light in air; T clk represents the operating cycle of the FPGA digital signal clock; t represents the target motion time.

[0018] The frequency shift modulation unit frequency-shifts the zero intermediate frequency delayed digital signal y D2 (n - τ) to become an eight-fold decimated target analog signal where f d is the target motion Doppler, and the corresponding expression is:

[0019]

[0020] In the formula, V represents the speed between the radar and the simulated target; a represents the acceleration between the radar and the simulated target; X represents the speed of light in air; represents the instantaneous frequency estimation of the intermediate frequency signal.

[0021] The instantaneous eight-fold interpolation unit generates a 16-channel digital intermediate frequency target analog signal with eight-fold interpolation based on the instantaneous frequency estimation of the intermediate frequency signal of the digital intermediate frequency signal The bit width is 10 bits, and the operating clock frequency is 156.25 MHz. Its bit width is 10 bits, and the operating clock frequency is 156.25 MHz.

[0022] The DAC sampling unit performs intermediate frequency output on the 16-channel digital intermediate frequency target analog signal whose bit width is 10 bits and the operating clock frequency is 156.25 MHz.

[0023] The instantaneous eight-fold decimation unit includes: an orthogonal digital down-conversion unit, a second frequency shift modulation unit, and a filtering and decimation unit, which are used to generate a zero intermediate frequency digital signal and filter out spurs within a preset floating range;

[0024] The instantaneous eight-fold interpolation unit includes: a filtering and interpolation unit, a third frequency shift modulation unit, and an orthogonal digital up-conversion unit; it is used to perform zero intermediate frequency transformation on the eight-fold decimated target analog signal, interpolate the zero intermediate frequency digital signal eight-fold, and generate a digital intermediate frequency target analog signal.

[0025] In a second aspect, an application method of a digital frequency storage device with low spurs and large delay is proposed. The method specifically includes the following steps:

[0026] Step 1: After the device is powered on, initialize the relevant configuration parameters to make the relevant modules in a normal working state;

[0027] Specifically, the ADC sampling unit completes the configuration of two channels at 2.5 GSPS in the ADC module, enabling the ADC module to normally sample the intermediate-frequency input at 2.5 GSPS to obtain y(n); the DAC sampling unit completes the 2.5 GSPS configuration of the DAC module, and the QDR storage delay unit completes the initialization of the QDR module;

[0028] Step 2: The ADC module collects the digital intermediate-frequency sampling signal and transmits it to the FPGA module;

[0029] Step 3: Use the intermediate-frequency fast frequency measurement unit in the FPGA module to obtain the instantaneous frequency estimation of the intermediate-frequency signal

[0030] Step 4: The instantaneous octal decimation unit in the FPGA module is based on the instantaneous frequency estimation of the intermediate-frequency signal Generate the zero-intermediate-frequency digital signal y D1 (n) of octal decimation, and through the FIFO bit-width transformation technology, generate 16-channel digital zero-intermediate-frequency sampling signals y D2 (n);

[0031] Step 5: Based on the indication of the 3.3V width-preserving pulse signal, the QDR storage delay unit in the FPGA module stores the digital zero-intermediate-frequency sampling signal y D2 (n) and outputs the zero-intermediate-frequency delayed digital signal y D2 (n - τ);

[0032] Step 6: The frequency shift modulation unit in the FPGA module performs frequency shift based on the zero-intermediate-frequency delayed digital signal y D2 (n - τ) to generate the octal decimation target analog signal

[0033] Step 7: The instantaneous octal interpolation unit in the FPGA module is based on the instantaneous frequency estimation of the intermediate-frequency signal and the octal decimation target analog signal of the frequency shift modulation unit Generate the octal interpolation digital intermediate-frequency target analog signal

[0034] Step 8: The DAC sampling unit in the FPGA module outputs the intermediate frequency of the low-spurious large-delay DRFM target analog 2.5 GSPS digital intermediate-frequency target analog signal for intermediate frequency output.

[0035] Beneficial effects: The present invention provides a digital frequency storage device with low spurs and large delay and its application method. The method uses instantaneous octal decimation and instantaneous octal interpolation to reduce the memory capacity requirement of the QDR module and improve the FPGA module placement and routing ability. On the basis of reducing the spurs caused by the AD device, it also increases the target analog distance by seven times and reduces the room-temperature spurs of the AD device. The programmable logic device FPGA used provides a device guarantee for software upgrade. The ADC module can simultaneously sample two intermediate-frequency signals at 2.5 GSPS. Cooperating with the DAC module, it can simultaneously achieve two low-spur and large-delay target simulations, increasing the system flexibility. The low-spur and large-delay DRFM device and method can be used for testing the detection and tracking functions of a radar for long-distance targets. During testing, it can be separated from its actual working environment, making it easy to test whether the product can work properly. The low-spur and large-delay DRFM device has a small volume and a simple hardware circuit, which is convenient for popularization and use. The complex Doppler modulation technology can achieve the target simulation of two intermediate-frequency signals sampled at 2.5 GSPS with fewer FPGA resources. Description of the Drawings

[0036] Figure 1 It is a schematic diagram of radar target distance simulation in the prior art.

[0037] Figure 2 It is a Doppler simulation diagram of a frequency-agile signal in the prior art.

[0038] Figure 3 It is a connection diagram of each module within the FPGA module of the present invention.

[0039] Figure 4 It is a connection diagram of each unit within the instantaneous octal decimation unit of the present invention.

[0040] Figure 5 It is a connection diagram of each unit within the instantaneous octal interpolation unit of the present invention.

[0041] Figure 6 It is the overall working flow chart of the present invention. Detailed Embodiments

[0042] In the following description, numerous specific details are given to provide a more thorough understanding of the present invention. However, it is obvious to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, some well-known technical features are not described to avoid confusion with the present invention.

[0043] In view of the performance requirements for DRFM devices in the prior art, the present invention proposes a digital frequency storage device with low spurs and large delay and its application method. By generating a target analog signal with low spurs and large delay, a radar test device with lower spurs and larger delay is developed without increasing the hardware costs of AD devices and memories and the requirements of domestic production process indicators, so as to achieve the purpose of adapting to but not limited to frequency agile radars, especially detecting whether radars with high sensitivity and long-distance detection functions can work properly.

[0044] Embodiment 1

[0045] In one embodiment, a digital frequency storage device with low spurs and large delay is proposed. As Figure 3 shown, the device specifically includes the following modules: ADC module, FPGA module, QDR module, and DAC module.

[0046] Specifically, the ADC module samples the input analog intermediate frequency to generate a digital intermediate frequency signal and outputs it to the FPGA module; the DAC module quantizes the digital signal of the FPGA module and outputs an analog intermediate frequency signal; the QDR module realizes the storage read and write of the digital signal of the FPGA module; the FPGA module performs target simulation on the analog intermediate frequency signal to generate a DRFM signal with low spurs and large delay, and is connected to the ADC module, DAC module, and QDR module.

[0047] In a further embodiment, the QDR module stores the intermediate frequency signal input by the FPGA module, and according to the read and write control input by the FPGA module, delays the output of the intermediate frequency signal and is connected to the FPGA module. The ADC module samples the analog input intermediate frequency signal at 2.5 GSPS and outputs it to the FPGA module, and is connected to the FPGA module. The FPGA module performs low-spur and large-delay DRFM target simulation on the digital intermediate frequency signal according to the intermediate frequency sampling signal and the set target time delay and echo Doppler, and is connected to the ADC module, DAC module, and QDR module. The DAC module converts the 2.5 GSPS digital intermediate frequency signal into an analog intermediate frequency output signal and is connected to the FPGA module.

[0048] Embodiment 2

[0049] In a further embodiment based on Embodiment 1, according to the requirement that the Nyquist sampling rate is greater than twice the input bandwidth, an ADC device ev10aq190 with a sampling rate of 2.5 GSPS and a quantization bit number of 10 is selected. This device has four 1.25 GSPS sampling modules, which can be flexibly combined into two 2.5 GSPS intermediate frequency samplings.

[0050] The QDR module selects CY7C1565KV18-500BZC, with a storage capacity of 72 Mbits, strong stability, and a throughput rate of 144 * 500 / 2 Bits / s = 4.5 GBytes / s, which is greater than the memory throughput requirement of 3.125 GBytes / s.

[0051] The FPGA module selects SMQ7K410T-FFG900 with rich programmable resources, laying a foundation for software free upgrade and two-way DRFM target simulation.

[0052] According to the requirement that the Nyquist sampling rate is greater than twice the input bandwidth, the DAC module selects the DAC device DA9739 with a sampling rate of 2.5 GSPS and a quantization bit number of 14. In the output intermediate frequency range of 1.35 - 2.4 GHz, the theoretical spurious of this device can reach -55 dBc.

[0053] Embodiment 3

[0054] In a further embodiment based on Embodiment 1, the program design of the FPGA module adopts module units with a low-coupling and high-cohesion pipeline structure, including an ADC sampling unit, a DAC sampling unit, an intermediate frequency fast frequency measurement unit, a QDR storage delay unit, a first frequency shift modulation unit, an instantaneous octal decimation unit, and an instantaneous octal interpolation unit. Inside the FPGA module, the ADC sampling unit is connected to the intermediate frequency fast frequency measurement unit and the instantaneous octal decimation unit, the QDR storage delay unit is connected to the instantaneous octal decimation unit and the frequency shift modulation unit, the frequency shift modulation unit is connected to the instantaneous octal interpolation unit, the instantaneous octal interpolation unit is simultaneously connected to the DAC sampling unit, and the intermediate frequency fast frequency measurement unit is connected to the instantaneous octal decimation unit and the instantaneous octal interpolation unit.

[0055] Among them, the ADC sampling unit configures the registers of the ADC module and samples the intermediate frequency input at 2.5 GSPS. The intermediate frequency fast frequency measurement unit performs fast intermediate frequency measurement on the digital samples. The instantaneous octal decimation unit performs zero intermediate frequency transformation on the intermediate frequency digital samples and decimates by eight times to generate zero intermediate frequency digital signals. The QDR storage delay unit stores and delays the zero intermediate frequency digital signals. The first frequency shift modulation unit performs Doppler frequency shift on the zero intermediate frequency digital signals. The instantaneous octal interpolation unit interpolates the zero intermediate frequency digital signals by eight times and performs intermediate frequency transformation to generate intermediate frequency digital target analog signals. The DAC sampling unit configures the registers of the DAC module and converts the intermediate frequency digital target analog signals into the required data format of the DAC module, as Figure 4 shown.

[0056] Embodiment 4

[0057] In a further embodiment based on the first embodiment, the ADC sampling unit, configured based on a 2.5 GSPS register, outputs the sampled intermediate-frequency signal in parallel in 16 channels as y(n), with a data sampling bit width of 10 bits and an operating clock frequency of 156.25 MHz.

[0058] Based on the 16-channel digital intermediate-frequency sampling signals y(n), the intermediate-frequency fast frequency measurement unit performs a 16-point parallel Fourier transform on the intermediate-frequency signal, outputs the complex signal Y(n) of the signal branch in the second region and the index channel ∈ (8, …, 15), and finally estimates the instantaneous frequency of the intermediate-frequency signal based on the measured complex signal Y(n) of the signal branch. Output the instantaneous frequency estimation of the intermediate-frequency signal. The corresponding expression is:

[0059]

[0060] As Figure 4 shown, based on the 16-channel 156.25 MHz digital intermediate-frequency sampling signals y(n) and the instantaneous frequency estimation of the intermediate-frequency signal, the instantaneous octal decimation unit generates 2-channel zero-intermediate-frequency digital signals y (n) with a bit width of 10 bits, and through the FIFO bit width conversion technology, generates 16-channel digital zero-intermediate-frequency sampling signals y D1 (n) with a bit width of 10 bits and an operating clock frequency of 19.53125 MHz. D2 (n) with a bit width of 10 bits and an operating clock frequency of 19.53125 MHz.

[0061] The quadrature digital down-conversion unit in the instantaneous octal decimation unit digitalizes the 16-channel 156.25 MHz digital intermediate-frequency sampling signals y(n) to generate 8-channel 156.25 MHz complex intermediate-frequency signals Z(n).

[0062] The second frequency shift modulation unit in the instantaneous octal decimation unit shifts the frequency of the 8-channel 156.25 MHz complex intermediate-frequency signals Z(n) to zero frequency to generate 8-channel 156.25 MHz complex zero-intermediate-frequency signals Zo(n) according to the instantaneous frequency estimation of the intermediate-frequency signal. Shift the frequency of the 8-channel 156.25 MHz complex intermediate-frequency signals Z(n) to zero frequency to generate 8-channel 156.25 MHz complex zero-intermediate-frequency signals Zo(n).

[0063] When the instantaneous octal decimation unit generates the zero-intermediate-frequency digital signals y D1 (n), the order of the FIR filter in the filter decimation unit is set to the optimal 64-order filter, with an in-band ripple of 0.1 dB and an out-of-band rejection depth of 60 dB. Therefore, spurs outside about 78.125 MHz on both sides of the instantaneous frequency estimation of the intermediate-frequency signal are filtered out, thereby reducing the spurs of the AD device. Spurs outside about 78.125 MHz on both sides of the instantaneous frequency estimation of the intermediate-frequency signal are filtered out, thereby reducing the spurs of the AD device.

[0064] The filtering and decimation unit filters the 8-channel 156.25 MHz complex baseband signals Zo(n), and after decimation by a factor of eight, outputs 2-channel baseband digital signals y D1 (n), and through the FIFO bit-width transformation technology, generates 16-channel digital baseband sampling signals with a bit-width of 10 bits and an operating clock frequency of 19.53125 MHz.

[0065] The QDR storage delay unit sets the QDR address bit-width to 19 bits and the data bit-width to 144 bits. When the 3.3V width-preserving pulse signal indicates a high level, the 16-channel digital baseband sampling signals y D2 (n) are truncated to 9 bits and then written into the QDR. The read address lags behind the write address by τ clock beats, and the duration of each beat is the reciprocal of the operating clock frequency of 19.53125 MHz (it can be seen that by reducing the clock speed, the maximum target simulation distance is expanded to eight times, 500 km * 8 = 4000 km). According to the read data, the baseband delayed digital signal y D2 (n - τ) is output, with a bit-width of 9 bits and an operating clock frequency of 19.53125 MHz, where τ is the number of target delay beats:

[0066]

[0067] In the formula, R 0 represents the relative distance between the radar and the simulated target; V represents the speed between the radar and the simulated target; a represents the acceleration between the radar and the simulated target; C represents the speed of light in air; T clk represents the operating cycle of the FPGA digital signal clock; t represents the target movement time.

[0068] The frequency shift modulation unit is based on the baseband delayed digital signal y D2 (n - τ), with a bit-width of 9 bits and an operating clock frequency of 19.53125 MHz, and shifts the frequency to become an eight-fold decimated target analog signal with a bit-width of 10 bits and an operating clock frequency of 19.53125 MHz, where f d is the target movement Doppler, and the corresponding expression is:

[0069]

[0070] In the formula, V represents the speed between the radar and the simulated target; a represents the acceleration between the radar and the simulated target; C represents the speed of light in air; represents the instantaneous frequency estimation of the intermediate frequency signal.

[0071] As Figure 5 shown, the instantaneous eight-fold interpolation unit is based on the instantaneous frequency value of the digital intermediate frequency signal and the octupled decimated target analog signal output by the frequency shift modulation unit It has a bit width of 10 bits and an operating clock frequency of 19.53125 MHz, generating 16-channel parallel digital intermediate frequency target analog signals with octupled interpolation It has a bit width of 10 bits and an operating clock frequency of 156.25 MHz

[0072] The instantaneous octupled interpolation unit generates 16-channel parallel digital intermediate frequency target analog signals When this happens, the FIR filter order of the filter interpolation unit is set to the optimal 64-order filter, with an in-band ripple of 0.1 dB and an out-of-band rejection depth of 60 dB. Therefore, at the intermediate frequency signal frequency Aliasing signals outside about 78.125 MHz can be filtered out, which ensures the spuriousness of the signal

[0073] The filter interpolation unit in the instantaneous octupled interpolation unit processes the octupled decimated target analog signal output by the frequency shift modulation unit It has a bit width of 10 bits and an operating clock frequency of 19.53125 MHz. After octupled interpolation and filtering, it generates 8-channel 156.25 MHz target analog complex zero intermediate frequency signals Co(n).

[0074] The third frequency shift modulation unit in the instantaneous octupled interpolation unit, based on the estimation of the instantaneous frequency of the intermediate frequency signal superimposes the frequency of the 8-channel 156.25 MHz target analog complex zero intermediate frequency signals Co(n) with the estimation of the instantaneous frequency of the intermediate frequency signal to generate 8-channel 156.25 MHz target analog complex intermediate frequency signals C(n).

[0075] The quadrature digital upconversion unit in the instantaneous octupled interpolation unit performs digital inverse quadrature on the 8-channel 156.25 MHz target analog complex intermediate frequency signals C(n) to generate 16-channel parallel digital intermediate frequency target analog signals It has a bit width of 10 bits and an operating clock frequency of 156.25 MHz

[0076] The DAC sampling unit processes the 16-channel parallel digital intermediate frequency target analog signals It has a bit width of 10 bits and an operating clock frequency of 156.25 MHz, and divides them into two 1.25 GSPS intermediate frequencies and outputs them to the DAC module

[0077] Embodiment 5

[0078] In a further embodiment based on the first embodiment, for the intermediate-frequency fast frequency measurement unit of an FPGA module that targets simulating a 2.5 GSPS digital signal with 16-phase low spurious and large delay DRFM, the consumption of its logic units Slice LUT and Register, storage unit RAMB18E1, and multiplier DSP48E1 is shown in Table 1 below.

[0079] Table 1 Resource Occupation for Frequency Estimation

[0080] Resource Type Used Total Used Percentage Registers 33656 508400 6.63 SliceLUTs 18734 254200 7.37 RAMB18E1s 20 1590 1.26 DSP48E1s 192 1540 12.47

[0081] The static timing analysis results show that the maximum working period of the critical path of the intermediate-frequency fast frequency measurement unit is 4.436 ns, and the highest working frequency is 225.428 MHz. Therefore, the highest working frequency of the system cannot exceed 225.428 MHz. Based on the above discussion, a 2.5 GSPS intermediate-frequency signal of the system is divided into 16 paths for operation in the FPGA, and the digital system clock is 156.25 MHz, meeting the timing requirements.

[0082] For the instantaneous octal decimation unit, QDR control, frequency shift modulation unit, and instantaneous octal interpolation unit of an FPGA module that targets simulating a 2.5 GSPS digital signal with 16-phase low spurious and large delay DRFM, the consumption of its logic units Slice LUT and Register, storage unit RAMB18E1, and multiplier DSP48E1 is shown in Table 2 below.

[0083] Table 2 DRFM Resource Occupation

[0084] Resource Type Used Total Used Percentage Registers 113274 508400 22.28 SliceLUTs 68578 254200 26.98 RAMB18E1s 406 1590 25.53 DSP48E1s 338 1540 21.95

[0085] The static timing analysis results show that the maximum working period of the critical path of the instantaneous octal decimation unit, QDR control, frequency shift modulation unit, and instantaneous octal interpolation unit is 5.217 ns, and the highest working frequency is 191.681 MHz. Therefore, the highest working frequency of the system cannot exceed 191.681 MHz. Based on the above discussion, a 2.5 GSPS intermediate-frequency signal of the system is divided into 16 paths for operation in the FPGA, and the digital system clock is 156.25 MHz. Among them, the system clock of the QDR control and frequency shift modulation unit is only 19.531 MHz, meeting the timing requirements.

[0086] The product test results of the digital frequency storage device with low spurious and large delay based on FPGA and its application method of the present invention in preliminary debugging show that: within the input intermediate-frequency range of 1.35 - 2.4 GHz, the target ambient temperature spurious can already reach -55 dBc, and the target simulation distance is as far as 4000 km.

[0087] The ambient temperature spurious test results are shown in Table 3, with slight differences for different devices.

[0088] Table 3 Spurious test results at room temperature

[0089] Intermediate Frequency 1.35 - 2.4GH Spurious Intermediate Frequency 1.35 - 2.4GHz Spurious 1.35GHz -56dBc 1.95GHz -57dBc 1.45GHz -58dBc 2.05GHz -57dBc 1.55GHz -57dBc 2.15GHz -56dBc 1.65GHz -57dBc 2.25GHz -56dBc 1.75GHz -58dBc 2.35GHz -56dBc 1.85GHz -61dBc 2.40GHz -55dBc

[0090] Embodiment 6

[0091] In one embodiment, an application method of a low-spurious and large-delay digital frequency storage device is provided, and the method specifically comprises the following steps:

[0092] Step 1: After the device is powered on, initialize the relevant configuration parameters to make the relevant modules in normal working state;

[0093] Specifically, the ADC sampling unit completes the 2.5GSPS configuration of the two channels in the ADC module, so that the ADC module can normally sample the intermediate frequency input 2.5GSPS to obtain y(n); the DAC sampling unit completes the 2.5GSPS configuration of the DAC module; the QDR storage delay unit completes the initialization of the QDR module;

[0094] Step 2: After the ADC module works normally, the ADC module collects the digital intermediate frequency sampling signal y(n) and transmits it to the FPGA module;

[0095] Step 3: Use the intermediate frequency fast frequency measurement unit in the FPGA module to process the received signal and obtain the instantaneous frequency estimation of the intermediate frequency signal.

[0096] Step 4: The instantaneous eight-fold extraction unit in the FPGA module estimates the instantaneous frequency of the intermediate frequency signal Generate eight times the digital zero intermediate frequency sampling signal y D2 (n);

[0097] Step 5: The QDR storage delay unit in the FPGA module converts the digital zero intermediate frequency sampling signal y into a digital zero intermediate frequency sampling signal y based on the 3.3V width-maintained pulse signal indication. D2 (n) Store and output zero intermediate frequency delay digital signal y D2 (n-τ);

[0098] Step 6: The frequency shift modulation unit in the FPGA module is based on the zero intermediate frequency delay digital signal y D2 (n-τ) is used to shift the frequency and generate an eight-fold decimation target analog signal.

[0099] Step 7: The instantaneous eight interpolation units in the FPGA module estimate the instantaneous frequency based on the intermediate frequency signal The target analog signal is extracted eight times by the frequency shift modulation unit Generate eight times interpolated digital intermediate frequency target analog signal

[0100] Step 8: The DAC sampling unit in the FPGA module performs intermediate frequency output on the low spurious and large delay DRFM target analog 2.5 GSPS digital intermediate frequency target analog signal. Output the intermediate frequency.

[0101] In summary, the present invention has the following advantages:

[0102] 1. The instantaneous octal decimation and instantaneous octal interpolation methods adopted by the present invention reduce the memory capacity requirement of the QDR module and improve the placement and routing ability of the FPGA module. On the basis of reducing the spurs brought by the AD device, the target analog distance is increased by seven times, and at the same time, the normal temperature spurs of the AD device are reduced to above -55 dBc.

[0103] 2. The programmable logic device FPGA adopted provides a device guarantee for software upgrade.

[0104] 3. The ADC module adopted can simultaneously achieve 2.5 GSPS sampling of two intermediate frequency signals. Cooperating with the DAC module, it can simultaneously achieve two-channel low spurious and large delay target simulation, increasing the system flexibility.

[0105] 4. The low spurious and large delay DRFM device and method adopted can be used for the detection and tracking function tests of long-distance targets by radar. When testing, it can be separated from its actual working environment, making it easy to test whether the product can work properly.

[0106] 5. The low spurious and large delay DRFM device adopted has a small volume and a simple hardware circuit, which is convenient for popularization and use.

[0107] 6. The complex Doppler modulation technology adopted can achieve the target simulation of 2.5 GSPS sampling signals of two intermediate frequency signals under the condition of less FPGA resources.

[0108] As described above, although the present invention has been shown and described with reference to specific preferred embodiments, it should not be construed as a limitation of the present invention itself. Various changes can be made in its form and details without departing from the spirit and scope of the present invention defined by the appended claims.

Claims

1. A digital frequency storage device with low spurious and large delay, Characterized in that, The device specifically includes the following modules: An ADC module for analog intermediate frequency sampling to generate a digital intermediate frequency sampling signal; An FPGA module connected to the ADC module, for receiving the digital intermediate frequency sampling signal output by the ADC module, and performing target simulation on the digital intermediate frequency sampling signal according to a preset target time delay and echo Doppler to generate a digital intermediate frequency target simulation signal; the FPGA module includes an instantaneous octal decimation unit and a QDR storage delay unit; The instantaneous octal decimation unit is used to generate two zero-IF digital signals y D1 (n) of octal decimation, and generate a digital zero-IF sampling signal y D2 (n) through FIFO bit-width transformation; The instantaneous octal decimation unit generates a zero-IF digital signal y D1 (n), the corresponding FIR filter order is preset to an optimal filter of 64 orders, with an in-band ripple of 0.1 dB and an out-of-band rejection depth of 60 dB; The QDR storage delay unit indicates based on a 3.3V pulse signal with constant width, stores the digital zero IF sampling signal y D2 (n) and outputs the zero IF delayed digital signal y D2 (n - τ), where τ is the number of target delay beats, and the expression is: Wherein, R 0 represents the relative distance between the radar and the simulated target; V represents the velocity between the radar and the simulated target; a represents the acceleration between the radar and the simulated target; C represents the speed of light in air; T clk represents the running period of the FPGA digital signal clock; t represents the target motion time; A QDR module connected to the FPGA module, for receiving the digital intermediate frequency target simulation signal output by the FPGA, and performing storage read and write on the output signal of the FPGA module; at the same time, according to the read and write control input by the FPGA module, delaying the output of the digital zero intermediate frequency sampling signal to generate a zero intermediate frequency delay signal; A DAC module connected to the FPGA module, for quantifying the digital intermediate frequency target simulation signal output by the FPGA module and generating an analog intermediate frequency signal.

2. The digital frequency storage device with low spurious and large delay according to claim 1, Characterized in that, The program design of the FPGA module adopts a low-coupling and high-cohesion module unit with a pipeline structure, and further includes: An ADC sampling unit for configuring the registers in the ADC module and sampling the digital intermediate frequency sampling signal; An intermediate frequency fast frequency measurement unit connected to the ADC sampling unit for performing fast intermediate frequency frequency measurement on the digital sampling; An instantaneous octal decimation unit connected to the ADC sampling unit and the intermediate frequency fast frequency measurement unit, for decimating the digital intermediate frequency sampling signal by eight times to generate a digital zero intermediate frequency sampling signal; A QDR storage delay unit connected to the instantaneous octal decimation unit for storing and delaying the zero intermediate frequency digital signal; A first frequency shift modulation unit connected to the QDR storage delay unit for performing Doppler frequency shift on the zero intermediate frequency digital signal; An instantaneous octal interpolation unit connected to the intermediate frequency fast frequency measurement unit and the frequency shift modulation unit for performing zero intermediate frequency transformation on the octal decimation target simulation signal and interpolating the zero intermediate frequency digital signal by eight times to generate a digital intermediate frequency target simulation signal; A DAC sampling unit connected to the instantaneous octal interpolation unit for configuring the registers of the DAC module and converting the digital intermediate frequency target simulation signal into the data format required by the DAC module.

3. The digital frequency storage device with low spurious and large delay according to claim 2, Characterized in that, Based on the 16-channel 156.25 MHz digital intermediate frequency sampling signal y(n) and the instantaneous frequency estimation of the intermediate frequency signal The instantaneous octal decimation unit is used to generate 2-channel zero intermediate frequency digital signals y D1 (n) with a bit width of 10 bits, and through the FIFO bit width transformation technology, generate 16-channel digital zero intermediate frequency sampling signals y D2 (n) with a bit width of 10 bits and an operating clock frequency of 19.53125 MHz.

4. The digital frequency storage device with low spurious and large delay according to claim 3, Characterized in that, The QDR storage delay unit preset the QDR address bit width to 19 bits and the data bit width to 144 bits; when the 3.3V width-preserved pulse signal indicates a high level, 9 bits are intercepted from 16-channel digital zero-IF sampling signals y D2 (n) and written into the QDR module; The read address is τ clock beats slower than the write address, and the duration of each beat is the digital zero IF sampling signal y D2 (n) The operating clock frequency is the reciprocal of, and according to the read data control, the zero IF delay digital signal y is output D2 (n - τ), and its bit width is 9 bits.

5. The digital frequency storage device with low spurious and large delay according to claim 4, Characterized in that, In the zero-IF delayed digital signal y D2 When the operating clock frequency is 19.53125 MHz for D2 , the first frequency shift modulation unit is based on the zero-IF delayed digital signal y D2 (n - τ) with a bit width of 9 bits, and shifts the frequency of the signal to become an octupled decimated target analog signal with a bit width of 10 bits, f d as the target motion Doppler, and the corresponding expression is: Where, V represents the velocity between the radar and the simulated target; a represents the acceleration between the radar and the simulated target; C represents the speed of light in air; represents the instantaneous frequency estimation of the intermediate frequency signal.

6. The digital frequency storage device with low spurious and large delay according to claim 3, Characterized in that, The instantaneous octal interpolation unit is based on the instantaneous frequency estimation of the intermediate frequency signal of the digital intermediate frequency signal and the octal decimation target analog signal output by the frequency shift modulation unit When the operating clock frequency of the octal decimation target analog signal is 19.53125 MHz, 16-channel digital intermediate frequency target analog signals for octal interpolation are generated Its bit width is 10 bits and the operating clock frequency is 156.25 MHz.

7. The digital frequency storage device with low spurious and large delay according to claim 3, Characterized in that, The digital intermediate frequency target analog signal is generated by the instantaneous octuple interpolation unit When the corresponding FIR filter order is preset to the optimal 64-order filter with an in-band ripple of 0.1 dB and an out-of-band rejection depth of 60 dB, the instantaneous frequency estimation of the intermediate frequency signal is filtered Aliasing signals outside about ±78.125 MHz are removed 8. The digital frequency storage device with low spurious and large delay according to claim 2, Characterized in that, The instantaneous octal decimation unit includes: an orthogonal digital down-conversion unit, a second frequency shift modulation unit, and a filtering and decimation unit, which are used to generate a digital zero-IF sampling signal and filter out spurs within a preset floating range; The instantaneous octal interpolation unit includes: a filtering and interpolation unit, a third frequency shift modulation unit, and an orthogonal digital up-conversion unit; it is used to perform zero-IF transformation on the intermediate-frequency digital sampling, interpolate the zero-IF digital signal by eight times, and generate a digital intermediate-frequency target analog signal.

9. An application method of a digital frequency storage device with low spurs and large delay, based on the device according to any one of claims 1 to 8, characterized in that, specifically includes the following steps: Step 1: After the device is powered on, initialize relevant configuration parameters to make relevant modules in a normal working state; Step 2: The ADC module collects the digital intermediate-frequency sampling signal y(n) and transmits it to the FPGA module; Step 3: Use the intermediate frequency fast frequency measurement unit in the FPGA module to obtain the instantaneous frequency estimation of the intermediate frequency signal Step 4: The instantaneous octal decimation unit in the FPGA module generates a zero-intermediate-frequency digital signal y produced by instantaneous frequency estimation of the intermediate-frequency signal, D1 and through the FIFO bit-width transformation technology, generates 16-channel digital zero-intermediate-frequency sampling signals y D2 (n); Step 5: Based on the indication of the width-preserved pulse signal, the QDR storage delay unit in the FPGA module stores the digital zero IF sampling signal y D2 (n) and outputs the zero IF delayed digital signal y D2 (n - τ); Step 6: The frequency shift modulation unit in the FPGA module performs frequency shift on the zero intermediate frequency delayed digital signal y D2 (n - τ) to generate an eight-fold decimated target analog signal Step 7: The instantaneous octal interpolation unit in the FPGA module estimates the instantaneous frequency based on the intermediate frequency signal and the eight-fold decimated target analog signal of the frequency shift modulation unit to generate a digital intermediate frequency target analog signal with eight-fold interpolation Step 8: The DAC sampling unit in the FPGA module performs intermediate frequency output on the low-spurious large-delay DRFM target analog 2.5 GSPS digital intermediate frequency target analog signal. Perform intermediate frequency output.

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