EUV-level substrate, EUV mask base, EUV mask and manufacturing method thereof

Abstract

The present invention provides an EUV-grade substrate, an EUV mask blank, an EUV mask plate, and a manufacturing method thereof. By alternately injecting titanium ions and oxygen ions into the surface layer of a blank quartz substrate multiple times and performing heat treatment, the surface layer of the blank quartz substrate is converted into a quartz film layer containing titanium oxide silicate, and the relatively rough surface of the quartz film layer containing titanium oxide silicate is further flattened, thereby utilizing the mutual offsetting effect of the thermal expansion of titanium oxide and silicon oxide to make the thermal expansion coefficient of the surface of the EUV-grade substrate less than or equal to 0.1 ppm / °C, thereby obtaining a low-cost, high-performance, low-defect EUV-grade substrate, an EUV mask blank, and an EUV mask plate with a flat working surface.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit manufacturing, and in particular to an EUV-level substrate, an EUV mask base, an EUV mask and a manufacturing method thereof. Background Art

[0002] With the continuous development of the integrated circuit manufacturing industry, advanced lithography technologies such as extreme ultraviolet lithography (EUVL) have become widely used. Among them, the EUV photo mask is a key component in the lithography process. The lithography process typically involves coating a photoresist layer, such as photoresist, on the wafer surface. After the photoresist layer dries, an exposure device exposes the pattern on the EUV mask to a specific light source (such as extreme ultraviolet (EUV)). Subsequently, the exposed photoresist layer is developed with a developer. The developed photoresist pattern serves as a mask for etching and other processes on the wafer, ultimately completing the transfer of the pattern from the EUV mask to the wafer.

[0003] Since EUV lithography uses a reflective optical system, the accuracy of EUV lithography is affected by the slight thermal expansion of the EUV mask. Therefore, it is crucial to manufacture EUV-grade substrates, EUV mask bases, and EUV masks with low thermal expansion and high flatness. Summary of the Invention

[0004] The object of the present invention is to provide an EUV-grade substrate, an EUV mask base, an EUV mask and a manufacturing method thereof, which can help reduce defects of the EUV mask and thus improve the effect of EUV lithography.

[0005] To achieve the above object, the present invention provides a method for manufacturing an EUV-grade substrate, comprising:

[0006] Provide blank quartz substrates;

[0007] Alternately implanting titanium ions and oxygen ions into the surface layer of the blank quartz substrate and performing heat treatment so that the surface layer of the blank quartz substrate forms a quartz film layer containing titanium oxide silicate;

[0008] The surface of the titanium oxide silicate-containing quartz film layer is planarized to form an EUV-grade substrate, and the thermal expansion coefficient of the EUV-grade substrate surface at a working temperature is less than or equal to 0.1 ppm / °C.

[0009] Optionally, the blank quartz substrate is a DUV grade or lower grade quartz substrate, and the thermal expansion coefficient at the working temperature is less than or equal to 1 ppm / °C.

[0010] Optionally, the energy range of the implanted titanium ions and oxygen ions is 10KeV~1MeV respectively, and the implantation dose range is 1014 cm-3~1015cm-3; and / or, the heat treatment includes a high-temperature annealing step, the temperature of the high-temperature annealing is greater than or equal to 1000°C, and the annealing time is greater than or equal to 1 min.

[0011] Optionally, before, after, or during the alternating injection of titanium ions and oxygen ions into the surface layer of the blank quartz substrate, and before the heat treatment, a dopant is also injected into the surface layer of the blank quartz substrate, and the dopant includes at least one of B, Al, Mg, Ca, Nb, Ta, Mn, Cu, Sn, F, and Cl.

[0012] Optionally, the planarization process includes: spin-on film planarization and / or chemical mechanical planarization.

[0013] Optionally, the planarization of the spin-on film layer includes forming a spin-on carbon layer.

[0014] Optionally, the thickness of the spin-on carbon layer is less than or equal to 20 nm.

[0015] Optionally, the thickness of the titanium oxide silicate-containing quartz film layer ranges from 0.1 μm to 3 μm.

[0016] Optionally, the titanium content in the titanium oxide silicate-containing quartz film layer gradually increases from bottom to top.

[0017] Based on the same inventive concept, the present invention provides a method for manufacturing an EUV mask blank, which comprises:

[0018] Adopting the manufacturing method of the EUV-grade substrate according to the present invention to form an EUV-grade substrate;

[0019] A reflective film stack layer and an absorption layer are sequentially formed on the EUV-grade substrate to form an EUV mask blank.

[0020] Optionally, the method for manufacturing the EUV mask blank further comprises, after forming the reflective film stack layer and before forming the absorption layer: forming a covering layer on the reflective film stack layer; and

[0021] After forming the absorption layer, the method further includes: forming a back conductive layer on a surface of the EUV-grade substrate facing away from the reflective film stack layer.

[0022] Based on the same inventive concept, the present invention also provides a method for manufacturing an EUV mask, which comprises:

[0023] The EUV mask blank manufacturing method of the present invention is adopted to form the EUV mask blank;

[0024] etching the absorption layer of the EUV mask blank to form a first pattern in the absorption layer;

[0025] The absorption layer and the reflective film stack layer of the EUV mask blank around the first pattern are etched, and the etching stops on the surface of the EUV grade substrate of the EUV mask blank to form a second pattern.

[0026] Based on the same inventive concept, the present invention further provides an EUV-grade substrate, wherein the thermal expansion coefficient of the surface of the EUV-grade substrate is less than or equal to 0.1 ppm / °C, and the EUV-grade substrate comprises:

[0027] blank quartz substrate;

[0028] A quartz film layer containing titanium oxide silicate is formed on the surface of a blank quartz substrate.

[0029] Optionally, the quartz film layer containing titanium oxide silicate further contains a dopant, and the dopant includes at least one of B, Al, Mg, Ca, Nb, Ta, Mn, Cu, Sn, F, and Cl.

[0030] Optionally, the titanium content in the titanium oxide silicate-containing quartz film layer gradually increases from bottom to top.

[0031] Optionally, the thickness of the titanium oxide silicate-containing quartz film layer is 0.1 μm to 3 μm.

[0032] Optionally, the EUV-grade substrate further includes a removable spin-on carbon layer formed on a surface of the titanium oxide silicate-containing quartz film layer.

[0033] Based on the same inventive concept, the present invention further provides an EUV mask blank, comprising:

[0034] The EUV-grade substrate according to the present invention;

[0035] a reflective film stack layer formed on the EUV-grade substrate;

[0036] An absorption layer is formed on the reflective film stack layer.

[0037] Optionally, the EUV mask base also includes:

[0038] a capping layer formed between the top reflective film of the reflective film stack layer and the absorption layer; and a back conductive layer formed on the surface of the EUV-grade substrate facing away from the reflective film stack layer.

[0039] Based on the same inventive concept, the present invention also provides an EUV mask, which has an EUV mask base as described in the present invention, and the EUV mask also has a first pattern and a second pattern, the first pattern is formed in the absorption layer of the EUV mask base, and the second pattern penetrates the absorption layer and the reflective film stack layer of the EUV mask base and exposes the surface of the EUV-level substrate of the EUV mask base.

[0040] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0041] 1. By alternately implanting titanium ions and oxygen ions into the surface layer of a blank quartz substrate and then heat-treating it, the surface layer of the blank quartz substrate is converted into a quartz film layer containing titanium oxide silicate. The relatively rough surface of the quartz film layer containing titanium oxide silicate is further planarized. Thus, by utilizing the mutually canceling thermal expansion of titanium oxide and silicon oxide, the coefficient of thermal expansion (CTE) of the EUV-grade substrate surface is reduced to less than or equal to 0.1 ppm / °C (e.g., the CTE is close to 0). Thus, a high-performance, low-defect, and flat working surface EUV-grade substrate, EUV mask blank, and EUV reticle can be obtained. When the EUV mask blank or EUV reticle is operated at a temperature above 100°C (e.g., an EUV exposure temperature of 100°C to 200°C), an induced tensile stress is generated in the quartz film layer containing titanium oxide silicate, causing the quartz film layer containing titanium oxide silicate to serve as a stress transition buffer layer, bringing the thermal expansion coefficient of the EUV-grade substrate surface toward 0, thereby improving EUV lithography performance.

[0042] 2. A spin-on carbon layer is formed on the surface of a titanium oxide silicate-containing quartz film. This spin-on carbon layer can be used to flatten and repair defects on the rough surface of the titanium oxide silicate-containing quartz film (to achieve surface defect flatness below 10nm), thereby enhancing the surface flatness and adhesion of EUV-grade substrates. Furthermore, the spin-on carbon layer can serve as a regenerated "sacrificial layer" and is easily removed by oxygen plasma ashing. This allows the EUV-grade substrate to be recycled without degrading its surface quality and used in the manufacture of new EUV reticles, further reducing the manufacturing cost of new EUV reticles. Spin-on carbon layers are commercially available, including from companies such as Brewer Science in the United States. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 This is a schematic diagram of the cross-sectional structure of an existing EUV mask.

[0044] Figures 2 to 4It is a structural schematic diagram of five typical defects in existing EUV masks or EUV mask bases.

[0045] Figure 5 It is a schematic flow chart of a method for manufacturing an EUV-grade substrate according to an embodiment of the present invention.

[0046] Figure 6 It is a schematic cross-sectional structure diagram of a method for manufacturing an EUV-grade substrate according to a specific embodiment of the present invention.

[0047] Figures 7 and 8 Schematic diagram of the filling capacity and surface flatness of the spin-coated carbon layer.

[0048] Figure 9 It is a schematic cross-sectional structure diagram of a method for manufacturing an EUV mask blank according to an embodiment of the present invention.

[0049] Figure 10 It is a schematic flow chart of a method for manufacturing an EUV mask according to a specific embodiment of the present invention.

[0050] Figure 11 It is a schematic cross-sectional structure diagram of a method for manufacturing an EUV mask according to a specific embodiment of the present invention.

[0051] Figure 12 It is a schematic cross-sectional structure diagram of a substrate recovery method according to a specific embodiment of the present invention. DETAILED DESCRIPTION

[0052] In the following description, a large number of specific details are given in order to provide a more thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present invention, some technical features known in the art are not described. It should be understood that the present invention can be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, providing these embodiments will make the disclosure thorough and complete and will fully convey the scope of the present invention to those skilled in the art. In the accompanying drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. The same reference numerals represent the same elements throughout.

[0053] It should be understood that when an element or layer is referred to as "on..." other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on..." other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, areas, layers, parts and / or processes, these elements, components, areas, layers, parts and / or processes should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, part and / or process from another element, component, area, layer, part and / or process. Therefore, without departing from the teachings of the present invention, the first element, component, area, layer, part and / or process discussed below can be expressed as a second element, component, area, layer, part and / or process.

[0054] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," "on the top," "on the bottom," "front," "back," etc., may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that the spatially relative terms are intended to include different orientations of the device in use and operation in addition to the orientations shown in the figures. For example, if the device in the drawings is turned over, then the element or feature described as "under the other elements" or "under it" or "beneath it" or "on the bottom" or "on the back" will be oriented as "on" or "top" or "front" of the other elements or features. Thus, the exemplary terms "under," "under," and "on the back" may include both the top and bottom orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0055] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present invention. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0056] As described in the background art, it is crucial to manufacture low-cost, low-defect, high-performance EUV masks.

[0057] EUV reticles are key components of EUV lithography (EUVL) systems. EUV lithography employs a scanner that uses light in the extreme ultraviolet (EUV) region (i.e., exposure light) with a wavelength ranging from approximately 1 nm to approximately 100 nm, for example, 13.6 nm. Because optical materials are opaque to EUV radiation, EUV reticles are reflective. An EUV reticle blank typically comprises a sequentially stacked substrate (such as glass or quartz), a reflective film stack (e.g., alternating layers of molybdenum (Mo) and silicon (Si), also known as a reflective structure), and an absorber layer (which can be a single layer or a multilayer film). The reflective film stack reflects the exposure light, while the absorber absorbs it and is etched into the specified pattern (i.e., the circuit pattern) required for integrated circuit manufacturing. The absorber layer has a low EUV reflectivity, for example, less than 3-5%.

[0058] Among them, please refer to Figures 1 to 4 A conventional EUV mask base (also known as an EUV mask blank, a blank EUV mask) generally includes a substrate 100, a reflective film stack layer 101, a cover layer 102, and an absorption layer 103. A conventional EUV mask forms a first pattern 103a and a second pattern 104 in the EUV mask base.

[0059] The inventors have found that EUV lithography is very sensitive to defects in EUV masks and EUV reticles. One of the sources of defects is defects induced by surface defects of the substrate 100 (such as pits, slits, grooves, bumps, contamination particles or scratches, etc.). Specifically, the following defects are induced: a) first type of defects 101a caused by existing large (>10nm) pits (or slits, scratches) 100a on the surface of the substrate 100, such as Figure 2 As shown in FIG. 1 , these pit defects 100a on the substrate 100 are formed on the surface of the substrate 100 by processes such as chemical mechanical polishing (CMP) and cleaning, and are induced in the film layers of the reflective film stack 101 deposited upward from the substrate 100, thereby forming a first type of defect 101a; b) a second type of defect 101b is caused by large-sized (>10nm) bump defects or contamination particles already existing on the surface of the substrate 100, such as Figure 3As shown, the bump defects 101b or contamination particles on these substrates 100 are formed on the surface of the substrate 100 by processes such as chemical mechanical polishing (CMP) and cleaning, and are induced from the substrate directly upward to the various film layers of the reflective film stack layer 101 deposited upward. In the process of upward induction, the defect size may increase due to factors such as stress and thickness change, thereby forming the second type of defect 101b; c) the third type of defect 101c caused by the existing large-sized (>10nm) defects 100c (such as pits, slits, bumps, contamination particles or scratches) on the surface of the substrate 100, as shown in FIG. Figure 4 As shown, the defect 100c on the substrate 100 is induced from the substrate 100 directly upward to the various film layers of the reflective film stack layer 101 deposited upward, and in the process of upward induction, it may cause lateral position displacement due to factors such as stress and thickness change, thereby forming a third type of defect 101c.

[0060] All of the above-mentioned defects on the substrate surface will cause defects in the EUV mask, thereby affecting the final effect of EUV lithography performed using the EUV mask.

[0061] In the prior art, to reduce defects introduced by substrate 100, quartz glass, with its relatively flat and smooth surface, is generally selected. However, with technological advancements, to address the issue of further defects introduced by thermal expansion of substrate 100 during subsequent processing, the use of silicon, Zerodur glass, and ultra-low expansion quartz glass (ULE, also known as zero-expansion glass) as substrate 100 has been proposed as an alternative to glass.

[0062] However, no matter what material the substrate 100 is made of in the prior art, its synthesis difficulty and processing cost are very high, and defects on its surface caused by processes such as chemical mechanical polishing (CMP) and cleaning of the substrate will affect the performance of the EUV mask.

[0063] Based on this, the present invention provides an EUV-grade substrate, an EUV mask base, an EUV mask plate and a manufacturing method thereof, which can provide an EUV-grade substrate with a process surface with a thermal expansion coefficient close to 0, and thus can manufacture low-cost, low-thermal expansion, high-flatness EUV-grade substrates, EUV mask bases, and EUV mask plates.

[0064] The following combination Figures 5 to 12 and specific embodiments to illustrate the technical solution of the present invention in detail.

[0065] Please refer to Figure 5 An embodiment of the present invention provides a method for manufacturing an EUV-grade substrate, which includes:

[0066] S11, providing a blank quartz substrate;

[0067] S12, alternately implanting titanium ions and oxygen ions into the surface layer of the blank quartz substrate, and performing heat treatment, so that the surface layer of the blank quartz substrate forms a quartz film layer containing titanium oxide silicate;

[0068] S13, spin-coating a carbon material on the surface of the titanium oxide silicate-containing quartz film layer to form a spin-coated carbon layer, thereby forming an EUV-grade substrate, wherein the thermal expansion coefficient of the EUV-grade substrate surface is less than or equal to 0.1 ppm / °C.

[0069] Please refer to Figure 6 In step S11, the blank quartz substrate 200 provided can be a DUV-grade or lower-grade quartz substrate made of synthetic quartz glass with a low positive thermal expansion coefficient, for example, less than or equal to 1 ppm / °C at a corresponding operating temperature (e.g., DUV exposure temperature or EUV exposure temperature). DUV-grade quartz substrates are standard substrates for blank masks for DUV lithography at 193 nm, 248 nm, or 365 nm. The blank quartz substrate 200 can have a high transmittance within the DUV range (e.g., a transmittance greater than 80%).

[0070] Please continue to refer to Figure 6 In step S12, the surface layer (ie, the working surface) of the blank quartz substrate 200 may be subjected to titanium ion (Ti 2+ ) implantation and oxygen ion (O 2- ) is implanted, with the implantation depth being, for example, 0.1 μm to 3 μm. After the ion implantation, a heat treatment such as a high-temperature rapid annealing treatment or a laser annealing treatment is performed, so that the surface layer of the blank quartz substrate 200 is fully combined and reacted with the implanted titanium ions and oxygen ions to form a quartz film layer 200 b containing titanium oxide silicate. The remaining blank quartz substrate 200 below the quartz film layer 200 b containing titanium oxide silicate is marked as 200 a.

[0071] The energy and dose of two adjacent titanium ion implantations can be different, and the energy and dose of two adjacent oxygen ion implantations can be different, so as to optimize the performance of the quartz film layer 200b containing titanium oxide silicate. Furthermore, the titanium content and oxygen content in the quartz film layer 200b containing titanium oxide silicate gradually increase from bottom to top, and the closer to the upper surface (i.e., the working surface of the blank quartz substrate 200), the higher the titanium content and oxygen content. Thus, on the one hand, the titanium dioxide concentration in the quartz film layer 200b containing titanium oxide silicate is unevenly distributed in the thickness direction, so as to produce a corresponding texture and Structural strain points are formed in the quartz film layer 200b containing titanium oxide silicate, so that the quartz film layer 200b containing titanium oxide silicate can serve as a stress transition buffer layer in the subsequent formation of the spin-on carbon layer and the manufacturing process of the EUV mask blank and the EUV mask blank, thereby avoiding the overall warping of the manufactured EUV-grade substrate, EUV mask blank and EUV mask blank; on the other hand, it can also prevent the defects in the blank quartz substrate below the quartz film layer 200b containing titanium oxide silicate (SiO2·TiO2) from being induced directly upward into the various film layers of the reflective film stack layer 202 above due to factors such as stress, thereby causing the following problems: Figure 3 The second type of defects shown and Figure 4 The problem of the third type of defect shown in the figure is solved, which ensures the deposition effect of the subsequently formed reflective stack layer and the absorption layer; furthermore, SiO2 and TiO2 in the quartz film layer 200b containing titanium oxide silicate achieve the effect of offsetting thermal expansion, thereby making the thermal expansion coefficient CTE of the surface of the formed EUV-grade substrate close to 0 to the greatest extent; in addition, during the process of EUV lithography using the EUV mask, the EUV mask can also be prevented from being warped by heat, thereby ensuring the effect of EUV lithography.

[0072] The thickness of the titanium oxide silicate-containing quartz film 200b formed in step S12 can be adaptively adjusted by adjusting the implantation parameters such as the implantation energy of titanium ions and oxygen ions. As an example, the implantation energy range of titanium ions and oxygen ions is 10 KeV to 1 MeV, and the implantation dose range is 10 14 cm -3 ~10 15 cm -3 .

[0073] Optionally, in step S12, before, after, or during the multiple alternating injections of titanium ions and oxygen ions into the surface of the blank quartz substrate 200, and before the high-temperature annealing treatment, dopants may be injected into the surface of the blank quartz substrate 200. The dopants include at least one of B, Al, Mg, Ca, Nb, Ta, Mn, Cu, Sn, F, and Cl. These dopants can be beneficial in adjusting the spatial coefficient of thermal expansion (CTE) distribution of the quartz film layer 200b containing titanium oxide silicate, so as to further make the coefficient of thermal expansion (CTE) of the quartz film layer 200b containing titanium oxide silicate as close to 0 as possible, and the surface flatness is as high as possible.

[0074] Optionally, in step S12, after the ion implantation is completed, the implanted titanium ions and oxygen ions are heat treated at different temperature ranges and at different temperature change rates. The entire heat treatment process, for example, includes: first, performing rapid annealing (RTA) on the implanted titanium ions and oxygen ions at a high temperature of more than 1000°C for a time greater than or equal to 1 minute; then reducing the temperature to approximately 850°C; then cooling to 650°C to 800°C at a cooling rate of 0.1°C / hr to 30°C / hr and maintaining the temperature for more than 10 hours; then cooling to room temperature at a cooling rate of less than 1°C / hr and continuing for more than 10 hours. In this way, the silicon dioxide in the blank quartz substrate 200 and the implanted titanium ions and oxygen ions fully combine and react, forming a sufficiently thick and uniform quartz film layer 200b containing titanium oxide silicate.

[0075] In this step, by alternately injecting titanium ions and oxygen ions multiple times, the thickness of the formed titanium oxide silicate-containing quartz film layer 200b can be precisely controlled, and the distribution of the titanium content as the thickness of the titanium oxide silicate-containing quartz film layer 200b changes can be precisely controlled, so that the CTE of the EUV-grade substrate surface formed can ultimately be as close to 0 as possible.

[0076] Among them, the specific principle that the titanium oxide silicate-containing quartz film layer 200b with an appropriate thickness can ultimately make the thermal expansion coefficient CTE of the EUV-grade substrate surface formed as close to 0 as possible is that SiO2 in the titanium oxide silicate-containing quartz film layer 200b has a positive thermal expansion coefficient, and TiO2 has a negative thermal expansion coefficient. The SiO2 and TiO2 in the titanium oxide silicate-containing quartz film layer 200b achieve the effect of offsetting thermal expansion, thereby making the CTE of the EUV-grade substrate surface formed as close to 0 as possible.

[0077] Please continue to refer to Figure 6In step S13, a carbon material is spin-coated on the surface of the titanium oxide silicate-containing quartz film layer 200b via a spin-coating process to form a spin-coated carbon layer 201. The specific process includes: first, wet-cleaning the surface of the titanium oxide silicate-containing quartz film layer 200b; then, spin-coating the carbon material on the surface of the titanium oxide silicate-containing quartz film layer 200b to a desired thickness; then, soft-baking the spin-coated carbon material at a first temperature (e.g., 100°C to 200°C, such as 170°C); and finally, hard-baking the spin-coated carbon material at a second temperature (e.g., 250°C to 500°C), wherein the second temperature is higher than the first temperature, thereby forming the spin-coated carbon layer 201. The carbon material spin-coated on the surface of the titanium oxide silicate-containing quartz film layer 200b is heated at the first temperature to trigger a cross-linking reaction, thereby partially cross-linking the carbon backbone polymer therein. The spin-coated carbon material is then maintained with a certain degree of reflow, which facilitates the formation of a flatter surface. Furthermore, the spin-coated carbon material is heated at the second temperature and undergoes a more intense cross-linking reaction to further cross-link the carbon main chain polymer therein, and the backflow of the spin-coated carbon material is reduced, ultimately forming a solid spin-coated carbon layer 201 with a flat top surface.

[0078] As an example, the spin-coated carbon material (which has been commercialized by companies including Brewer Science in the United States) is a liquid spin-coated carbon composition, which includes a solvent, a carbon backbone polymer, and a cross-linking agent. The carbon backbone polymer includes, for example, at least one of propylene glycol methyl ether (PGME), propylene glycol methyl ether acetate (PGMEA), cyclopentanone, cyclohexanone, polyhydroxystyrene, polyacrylate, or polymethyl methacrylate. The cross-linking agent includes A-(OR) x 、A-(NR) x 、A-(OH) x 、A-(C=C) x and A-(C≡C) x At least one of the group consisting of: A is a single molecule, a multimer or a second polymer having a molecular weight ranging from 100 to 20,000, and R is a hydrocarbon group, a cycloalkyl group, a cycloalkyl epoxy group or a C3-C 15 heterocyclic group; OR is alkoxy, cycloalkoxy, carbonate, alkyl carbonate, alkyl carboxylate, tosylate or mesylate; NR is alkylamide or alkylamino; x ranges from 2 to 1000 or C3-C 15heterocyclic group; OR is an alkoxy group, a cycloalkoxy group, a carbonate group, an alkyl carbonate group, an alkyl carboxylate group, a tosylate group, or a mesylate group; NR is an alkylamide group or an alkylamino group, and x ranges from 2 to 1000. The carbon backbone polymer and the crosslinking agent are uniformly dissolved in a solvent and spin-coated onto the surface of the organic polymer substrate 200. In some embodiments, the solvent is an organic solvent, for example, comprising at least one of ketones, alcohols, polyols, ethers, glycol ethers, cyclic ethers, aromatic hydrocarbons, esters, propionates, lactates, lactates, alkylene glycol monoalkyl ethers, alkyl lactates, alkyl alkoxypropionates, cyclic lactones, monoketone compounds containing a ring, alkylene carbonates, alkyl alkoxy acetates, alkyl pyruvates, lactates, ethylene glycol alkyl ether acetates, diethylene glycol, propylene glycol alkyl ether acetates, alkylene glycol alkyl ether esters, alkylene glycol monoalkyl esters, and the like.

[0079] As an example, in step S13, liquid carbon material is spin-coated onto the surface of the titanium oxide silicate-containing quartz film layer 200b at a speed of 1500pm / 60s until the thickness of the spin-coated carbon material meets the requirements; then, the spin-coated carbon material is soft-baked at 100℃~200℃ in an N2 atmosphere for 1min~5min; thereafter, the spin-coated carbon material is hard-baked at 200℃~400℃ in an N2 atmosphere for 5min~20min, finally forming a solid, top-surface flat spin-coated carbon layer 201 with a thickness h2 not greater than 20nm, thereby obtaining an EUV-grade substrate.

[0080] In step S13, a spin-coated carbon layer 201 is formed by spin coating. This process is simple and low-cost. Compared with carbon layers formed by other methods such as CVD, ALD, or sputtering, it has a stronger deep gap filling capability and local and global planarization capability. It can form a globally flat process surface on the quartz film layer 200b containing titanium oxide silicate (its top surface can be flattened to a scale of less than 10nm). For example, the density of defects (such as textures, protrusions, pits, etc.) on the quartz film layer 200b containing titanium oxide silicate is uneven (such as Figure 7 Some intervals L1 are large, some intervals L2 are small), and the defects are also of different sizes (such as Figure 7 Some defects have a large line width W1, while others have a small line width W2). Using a spin coating method to form a spin-coated carbon layer can also fill defects such as pits, cracks, and scratches, and bury protruding defects, thereby forming a globally flat process surface on the quartz film layer 200b containing titanium oxide silicate. For another example, the defect on the surface of the quartz film layer 200b containing titanium oxide silicate is a crack with a high aspect ratio, such as Figure 8As shown, after a spin-on carbon layer is formed by spin coating, the carbon atoms can be filled into the bottom of the slit due to their smaller size, and a globally flat process surface is formed on the titanium oxide silicate-containing quartz film layer 200b after the slit is filled.

[0081] On the premise that the carbon layer is formed with the same thickness as that formed by the spin coating method, the carbon layer formed by other methods such as CVD, ALD or sputtering is Figure 7 In the case of defects shown in FIG, pits or convex hulls may be generated due to the sparse and dense effects of defects, and the flatness of the top surface of the carbon layer finally formed is insufficient; Figure 8 In the case of the defects shown, inability to fill the bottom of the slit or prematurely sealing the slit can lead to voids, or conformal deposition can cause pits or bumps on the top surface. Consequently, the resulting carbon layer has insufficient top surface flatness. In other words, forming a carbon layer on a substrate using other methods, such as CVD, ALD, or sputtering, cannot meet the top surface flatness requirements of higher-performance EUV mask blanks or EUV reticles, and thus cannot achieve the technical benefits of the present invention.

[0082] The technical solution of this embodiment is that, on the one hand, the titanium content and oxygen content in the quartz film layer 200b containing titanium oxide silicate gradually increase from bottom to top, and the titanium dioxide concentration in the quartz film layer 200b containing titanium oxide silicate is unevenly distributed in the thickness direction of the quartz film layer 200b containing titanium oxide silicate. This not only produces corresponding textures and forms structural strain points in the textures, so that the quartz film layer 200b containing titanium oxide silicate can serve as a stress transition buffer layer in subsequent processes to avoid adverse effects caused by internal stress, but also utilizes the effect of offsetting the positive thermal expansion coefficient of silicon oxide and the negative thermal expansion coefficient of titanium oxide therein, so that the CTE of the EUV-grade substrate is close to 0; on the other hand, covering the surface of the quartz film layer 200b containing titanium oxide silicate with a spin-on carbon layer 201 can flatten and repair defects of the rough surface of the quartz film layer 200b containing titanium oxide silicate formed after ion implantation and annealing, and also enhances surface adhesion; more importantly, the quartz film layer 200b containing titanium oxide silicate and the spin-on carbon layer 201 are sequentially stacked on top of each other. The thermal expansion of the blank quartz substrate 200a is fixed by the titanium and oxygen injected, whose concentration gradually increases from the bottom to the surface, and the quality of the titanium oxide silicate-containing quartz film layer 200b is improved. As a result, thermal and mechanical stresses are initiated from the bottom blank quartz substrate 200a and shared by the titanium oxide silicate-containing quartz film layer 200b on the surface. Ultimately, the thermal expansion coefficient of the EUV-grade substrate surface is close to zero (for example, less than 0.01 ppm / °C), achieving the near-zero CTE required for EUV mask applications. This provides favorable process conditions for subsequent deposition and etching of reflective film stack layers and absorber layers, and prevents surface defects and internal stresses in the titanium oxide silicate-containing quartz film layer 200b from inducing defects during the deposition of subsequent reflective film stack layers. This reduces defects in the resulting EUV mask blank or EUV reticle, significantly improves the reflectivity of the reflective film stack layer (i.e., Bragg reflector) of the EUV reticle, eliminates hard defects and phase defects, and improves the resolution and contrast of the reflective EUV reticle.

[0083] It should be understood that the cost of the EUV-grade substrate provided in this embodiment is lower than that of existing EUV-grade glass substrates. Furthermore, the spin-on carbon layer 201 formed therein is, on the one hand, sufficiently thick to fill defects such as pits or slits on the surface of the titanium oxide silicate-containing quartz film layer 200b, and to bury defects such as bumps or ridges on the surface of the titanium oxide silicate-containing quartz film layer 200b, thereby providing a sufficiently flat top surface and preventing these defects from inducing defects in the subsequently deposited reflective film stack 202 and absorber layer 204. On the other hand, it is sufficiently thin and opaque to "reset" the surface of the titanium oxide silicate-containing quartz film layer 200b to a new, flatter and less defective substrate, while also bringing the thermal expansion coefficient of the EUV-grade substrate surface close to zero. This facilitates the manufacture of EUV mask blanks and EUV reticles with lower costs, fewer defects, and higher performance.

[0084] Please refer to Figure 6 This embodiment also provides an EUV-grade substrate for an EUV mask base or EUV mask, comprising a blank quartz substrate 200a, a quartz film layer 200b containing titanium oxide silicate, and a spin-on carbon layer 201 stacked in sequence. The top surface of the spin-on carbon layer 201 is flat, and the thickness h2 is less than or equal to 20 nm, for example, 10 nm. The spin-on carbon layer 201 can bury surface defects of the quartz film layer 200b containing titanium oxide silicate and provide a flat process surface. The stacking of the spin-on carbon layer 201 and the quartz film layer 200b containing titanium oxide silicate results in a thermal expansion coefficient of the EUV-grade substrate surface of less than 0.1 ppm / °C, for example, less than 0.01 ppm / °C.

[0085] Optionally, the titanium oxide silicate-containing film layer 200 b further comprises a dopant, and the dopant includes at least one of B, Al, Mg, Ca, Nb, Ta, Mn, Cu, Sn, F, and Cl.

[0086] Optionally, the thickness h1 of the quartz film layer 200 b containing titanium oxide silicate is 0.1 μm to 3 μm, and the titanium content in the quartz film layer 200 b containing titanium oxide silicate gradually increases from bottom to top.

[0087] In addition, the spin-on carbon layer 201 can serve as a removable sacrificial layer and can be removed by an oxygen plasma ashing process when the EUV-grade substrate needs to be reworked, recycled, or reused.

[0088] Please refer to Figure 9 This embodiment further provides a method for manufacturing an EUV mask blank, which includes:

[0089] First, an EUV-grade substrate is formed by using the method for manufacturing an EUV-grade substrate according to the present invention. The EUV-grade substrate includes a blank quartz substrate 200 a , a quartz film layer 200 b containing titanium oxide silicate, and a spin-on carbon layer 201 .

[0090] Then, a reflective film stack layer 202 is formed on the spin-on carbon layer 201 of the EUV-grade substrate. Figure 9 The reflective film stack 202 is typically required to have a high reflectivity for exposure light of a specific wavelength. For example, the reflectivity for 13.6nm extreme ultraviolet light should be greater than 60%, and preferably greater than 65%. In this embodiment, the reflective film stack 202 is primarily composed of a first reflective film (not shown) and a second reflective film (not shown) alternately stacked in pairs, with a total of 40 to 50 pairs of layers. The thickness of each of the first and second reflective films is approximately 3 to 4 nm. The thickness of the first and second reflective films can be any suitable material that can achieve a high reflectivity (e.g., greater than 70%) for extreme ultraviolet light of a specific wavelength (e.g., 13.6nm). For example, the first reflective film can be made of silicon (Si) and the second reflective film can be made of molybdenum (Mo). Another example is the first reflective film can be made of Mo and the second reflective film can be made of beryllium (Be). Specifically, the first reflective film and the second reflective film can be alternately formed by any suitable deposition process, such as sputtering (PVD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), plasma enhanced ALD (PEALD), ion beam deposition (IBD), or jet vapor deposition (JVD), thereby forming the desired reflective film stack 202. To minimize thermal stress-induced defects during the formation of the reflective film stack 202, the deposition temperature of each film layer in the reflective film stack 202 is kept as close to room temperature as possible, for example, controlled between room temperature and 100°C.

[0091] Next, a capping layer 203 is formed on the surface of the reflective film stack 202. Specifically, the capping layer 203 is formed on the top surface of the reflective film stack 202 by any suitable deposition process, such as sputtering (PVD), CVD, PECVD, ALD, PEALD, IBD, JVD, or the like. The capping layer 203 protects the reflective film stack 202 from damage during the etching process. Its material may include at least one of ruthenium (Ru), a ruthenium alloy (e.g., RuB, RuSi, or RuNb), or ruthenium oxide (e.g., RuO2 or RuNbO). It may be a single-layer structure or a multi-layer structure. The thickness of the capping layer 203 is, for example, 2 nm to 4 nm. In other embodiments of the present invention, when the top film of the reflective film stack 202 is silicon, the formation of the capping layer 203 may be omitted. Alternatively, when forming the reflective film stack 202, an additional silicon film (i.e., the top first reflective film) may be deposited to serve as the capping layer 203.

[0092] Subsequently, an absorption layer 204 can be formed on the top surface of the capping layer 203 by any suitable deposition process, such as sputtering (PVD), CVD, PECVD, ALD, PEALD, IBD, JVD, etc. The absorption layer 204 can be a single-layer structure or a composite structure formed by stacking multiple layers. Its material includes at least one of cobalt (Co), tellurium (Te), hafnium (Hf), nickel (Ni), tantalum (Ta), chromium (Cr), a tantalum-based material, a chromium-based material, etc. The total thickness of the absorption layer 204 is, for example, 50 nm to 75 nm. When the absorption layer 204 is a composite structure formed by stacking multiple layers, the thickness of a single layer is, for example, 3 nm to 6 nm. To minimize thermal stress-induced defects during the formation of the reflective film stack 202, the deposition temperature of each layer in the absorption layer 204 is as close to room temperature as possible, for example, controlled between room temperature and 100°C.

[0093] Please continue to refer to Figure 9 Alternatively, a back conductive layer 206 can be deposited on the surface of the EUV-grade substrate facing away from the absorber layer 204 by any suitable deposition process, such as sputtering, evaporation, CVD, PECVD, ALD, PEALD, molecular beam epitaxy, IBD, or JVD. The material of the back conductive layer 206 can include at least one of chromium, a chromium-based material (e.g., chromium nitride (CrN) or chromium oxynitride (CrON), tantalum, or a tantalum-based material (e.g., tantalum boride (TaB), tantalum oxide (TaO), tantalum nitride (TaN), tantalum boron oxide (TaBO), or tantalum boronitride (TaBN). The thickness of the back conductive layer 206 is, for example, 60 nm to 75 nm.

[0094] At this point, the manufacture of the EUV mask base is completed.

[0095] It should be understood that, in this embodiment, the back conductive layer 206 is formed after the deposition of the absorption layer 204, but the technical solution of the present invention is not limited thereto. In other embodiments of the present invention, the deposition of the back conductive layer 206 may be performed before the deposition of the reflective film stack layer 202, or after the deposition of the reflective film stack layer 202 and before the deposition of the covering layer 203, or after the deposition of the covering layer 203 and before the deposition of the absorption layer 204.

[0096] The method for manufacturing the EUV mask blank described in this embodiment is based on the EUV-grade substrate of the present invention, so it has low thermal expansion and few defects, which can help improve the EUV lithography effect.

[0097] Please refer to Figure 9 This embodiment also provides an EUV mask blank, which is preferably manufactured using the EUV mask blank manufacturing method of this embodiment. The EUV mask blank includes the EUV-grade substrate described in the present invention (i.e., a blank quartz substrate 200a, a titanium oxide silicate-containing quartz film layer 200b, and a spin-on carbon layer 201), a reflective film stack 202, and an absorption layer 204, which are stacked in sequence.

[0098] Optionally, the reflective film stack layer 202 includes first reflective films and second reflective films stacked alternately in pairs, and the number of stacked layers of the first reflective films and the second reflective films is 30 to 60 pairs.

[0099] Optionally, the EUV mask blank further includes a capping layer 203 and a back conductive layer 206. The capping layer 203 is formed between the top reflective film of the reflective film stack 202 and the absorption layer 204, and the back conductive layer 206 is formed on the surface of the blank quartz substrate 200a facing away from the spin-on carbon layer 201.

[0100] In addition, the selection of materials for the EUV-grade substrate, the reflective film stack layer 202 , the absorption layer 204 , the cover layer 203 and the back conductive layer 206 can refer to the description of the EUV mask base plate manufacturing method of the present invention above, and will not be repeated here.

[0101] Based on the same invention concept, please refer to Figure 10 This embodiment further provides a method for manufacturing an EUV mask, which includes:

[0102] S21, forming an EUV mask blank using the EUV mask blank manufacturing method of the present invention;

[0103] S22, etching the absorption layer of the EUV mask blank to form a first pattern in the absorption layer;

[0104] S23 , etching the absorption layer and the reflective film stack layer of the EUV mask blank around the first pattern, and stopping the etching on the surface of the spin-on carbon layer of the EUV mask blank to form a second pattern.

[0105] The process of step S21 is the above-mentioned method for manufacturing the EUV mask blank of the present invention, which will not be described in detail here.

[0106] In step S22, first, refer to Figure 11 A hard mask layer 205 is formed on the top surface of the absorption layer 204 by any suitable deposition process such as sputtering, CVD, PECVD, ALD, PEALD, IBD, or JVD. The material of the hard mask layer 205 can be at least one of tantalum (Ta), a tantalum-based material (e.g., tantalum boride TaB, tantalum oxide TaO, tantalum nitride TaN, tantalum boron oxide TaBO, or tantalum boronitride TaBN), silicon, a silicon-based material (e.g., silicon nitride SiN or silicon oxynitride SiON), ruthenium, or a ruthenium-based material (e.g., ruthenium boride RuB). The thickness of the hard mask layer 205 is, for example, 4 nm to 20 nm.

[0107] The hard mask layer 205 may be deposited after the absorption layer 204 is deposited and before the back conductive layer 206 is deposited, or may be deposited after the absorption layer 204 is deposited and after the back conductive layer 206 is deposited.

[0108] In step S22, please continue to refer to Figure 11 After depositing the hard mask layer 205, the following process is performed:

[0109] First, a first photoresist layer 207 is coated, and then the first photoresist layer 207 is exposed and developed to pattern the first photoresist layer 207 .

[0110] Then, using the patterned first photoresist layer 207 as a mask, the hard mask layer 205 is etched to the top surface of the absorption layer 204 by any suitable process such as atomic layer etching and plasma etching to transfer the pattern of the first photoresist layer 207 to the hard mask layer 205 to form a patterned hard mask layer 205'.

[0111] The first photoresist layer 207 is then removed by a dry stripping process such as plasma ashing or a suitable wet stripping process. For example, the first photoresist layer 207 is first dry ashed using oxygen (O2) plasma, and then wet stripped using various organic acids, inorganic sulfuric acid, or H2O2 at high temperature. The first photoresist layer 207 is then rinsed with isopropyl alcohol (IPA) and then with CO2 to remove the first photoresist layer 207.

[0112] Next, using the patterned hard mask layer 205' as a mask, the absorption layer 204 is etched to the top surface of the cover layer 203 or the top surface of the reflective film stack layer 202 through a suitable etching process such as atomic layer etching to form a first pattern 204a in the absorption layer 204. The first pattern 204a is the pattern of the circuit and / or device required for integrated circuit manufacturing.

[0113] Please refer to Figure 11 In step S23, first, a second photoresist layer 208 is coated on the patterned hard mask layer 205' and the EUV mask blank, and the second photoresist layer 208 is exposed and developed to pattern the second photoresist layer 208. The patterned second photoresist layer 208 can protect the formation area of ​​the first pattern 204a of the EUV mask blank and expose the area of ​​the EUV mask blank where the second pattern is to be formed, which is located outside the first pattern 204a.

[0114] Then, using the patterned second photoresist layer 208 as a mask, the hard mask layer 205', the absorption layer 204, the cover layer 203 and the reflective film stack layer 202 are etched through a suitable etching process such as atomic layer etching. The etching stops on the surface of the spin-on carbon layer 201 to form a second pattern 209, thereby obtaining an EUV mask, wherein the second pattern 209 is the frame of the EUV mask.

[0115] Afterwards, the second photoresist layer 208 is removed by dry stripping such as plasma ashing or a suitable wet stripping process, and the hard mask layer 205' is further removed, thereby forming an EUV mask having the first pattern 204a and the second pattern 209.

[0116] The EUV mask manufacturing method of this embodiment is based on the EUV mask blank of the present invention, so it is possible to manufacture an EUV mask with lower cost, fewer defects and higher performance.

[0117] Please refer to Figure 11 This embodiment also provides an EUV mask, which is formed using the manufacturing method of the EUV mask of this embodiment. It not only has the EUV mask base of this embodiment, but also has a desired pattern. Specifically, Figure 11 As shown in the last figure, the EUV reticle has a first pattern 204a and a second pattern 209. The first pattern 204a penetrates the absorber layer 204 and is located above the top reflective film of the EUV reticle's reflective film stack 202. The second pattern 209 penetrates the absorber layer 204 and the reflective film stack 202 of the EUV reticle and exposes the top surface of the EUV reticle's spin-on carbon layer 201. The first pattern 204a represents the desired circuit pattern, and the second pattern 209 represents the border pattern required around the circuit.

[0118] In addition, it is worth noting that during the manufacturing process of the EUV mask blank and EUV mask of the present invention, as well as during the EUV lithography process using the EUV mask, if the corresponding operations are performed at a suitable ambient temperature (e.g., 100°C to 200°C), during the operation, induced tensile stress can be generated in the titanium oxide silicate-containing quartz film layer 200b, which can serve as a stress transition buffer layer, thereby avoiding the generation of unnecessary deformation and defects and ensuring the effectiveness of the corresponding operations.

[0119] Moreover, due to the existence of the spin-on carbon layer 201, the spin-on carbon layer 201 can be regarded as a regenerated "sacrificial layer" and then removed by O2 plasma ashing to achieve the recovery and reuse of the substrate.

[0120] Taking the recycling of the EUV mask substrate of the present invention as an example, the substrate recycling method of this embodiment specifically includes: first, using any process such as wet etching, plasma etching, chemical mechanical polishing, etc., to sequentially remove the absorption layer 204, the cover layer 203, and the reflective film stack layer 202 of the EUV mask to expose the spin-on carbon layer 201 of the EUV mask; then, plasma ashing is performed to remove the spin-on carbon layer 201 to expose the surface of the titanium oxide silicate-containing quartz film layer 200b of the EUV mask. The EUV mask substrate is thus recycled and can be used to make new EUV masks or other devices.

[0121] Optionally, in this embodiment, before removing the absorption layer 204, or after removing the reflective film stack layer 202 and before removing the spin-on carbon layer 201, or after removing the spin-on carbon layer 201, the back conductive layer 206 on the surface of the blank quartz substrate 200a facing away from the spin-on carbon layer 201 is also removed.

[0122] Further optionally, the method of step S13 described above can be used to spin-coat a carbon material again on the exposed surface of the quartz film layer 200 b containing titanium oxide silicate to form a new spin-coated carbon layer to repair the surface defects of the quartz film layer 200 b containing titanium oxide silicate, thereby obtaining the EUV-grade substrate for the EUV mask of the present invention again.

[0123] Obviously, in this embodiment, the spin-on carbon layer 201 serves as a sacrificial layer, which is relatively thin and can be easily removed by plasma ashing. It will not damage the surface of the titanium oxide silicate-containing quartz film layer 200b, thereby causing a decrease in the surface smoothness and thermal expansion coefficient of the titanium oxide silicate-containing quartz film layer 200b. It can be used for the recycling and reuse of EUV mask bases and EUV mask substrates, with low recycling costs. Moreover, since the substrates recycled from old EUV mask bases and EUV mask plates can be used to further make new EUV mask bases and EUV mask plates, the manufacturing costs of new EUV mask bases and EUV mask plates can be further reduced.

[0124] It should be noted that, in each of the above embodiments, a spin-on carbon layer is used to planarize the relatively rough top surface of the formed titanium oxide silicate-containing quartz film layer 200 b. However, the technical solutions of the present invention are not limited thereto. In other embodiments of the present invention, the relatively rough top surface of the formed titanium oxide silicate-containing quartz film layer 200 b can also be planarized by performing chemical mechanical planarization (CMP) on the top surface of the titanium oxide silicate-containing quartz film layer 200 b.

[0125] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure are within the scope of the technical solution of the present invention.

Claims

1. A method for manufacturing an EUV-grade substrate, characterized in that: include: Provide blank quartz substrates; Alternately implanting titanium ions and oxygen ions into the surface layer of the blank quartz substrate and performing heat treatment so that the surface layer of the blank quartz substrate is fully combined with and reacted with the implanted titanium ions and oxygen ions to be converted into a quartz film layer containing titanium oxide silicate, with the blank quartz substrate being located below the quartz film layer containing titanium oxide silicate; The surface of the titanium oxide silicate-containing quartz film layer is planarized to form an EUV-grade substrate, wherein the thermal expansion of silicon oxide and titanium oxide in the titanium oxide silicate-containing quartz film layer offsets each other, so that the thermal expansion coefficient of the EUV-grade substrate surface at the operating temperature is less than or equal to 0.1 ppm / °C, and the titanium oxide silicate-containing quartz film layer is also used to reduce defects introduced by the EUV-grade substrate during EUV lithography, thereby improving the EUV lithography effect.

2. The method for manufacturing an EUV-grade substrate according to claim 1, wherein: The blank quartz substrate is a DUV grade or lower grade quartz substrate, and has a thermal expansion coefficient less than or equal to 1 ppm / ° C. at the working temperature.

3. The method for manufacturing an EUV-grade substrate according to claim 1, wherein: The energy range of titanium ion and oxygen ion implantation is 10KeV~1MeV, and the implantation dose range is 10 14 cm -3 ~10 15 cm -3 ; and / or, the heat treatment includes a high-temperature annealing step, the temperature of the high-temperature annealing is greater than or equal to 1000°C, and the annealing time is greater than or equal to 1 minute.

4. The method for manufacturing an EUV-grade substrate according to claim 1, wherein: Before, after, or during the alternate implantation of titanium ions and oxygen ions into the surface layer of the blank quartz substrate, and before the heat treatment, a dopant is also implanted into the surface layer of the blank quartz substrate, wherein the dopant includes at least one of B, Al, Mg, Ca, Nb, Ta, Mn, Cu, Sn, F, and Cl.

5. The method for manufacturing an EUV-grade substrate according to claim 1, wherein: The planarization process includes: spin-on film planarization and / or chemical mechanical planarization.

6. The method for manufacturing an EUV-grade substrate according to claim 5, wherein: The planarization of the spin-on film layer includes forming a spin-on carbon layer.

7. The method for manufacturing an EUV-grade substrate according to claim 6, wherein: The thickness of the spin-on carbon layer is less than or equal to 20 nm.

8. The method for manufacturing an EUV-grade substrate according to claim 1, wherein: The thickness of the titanium oxide silicate-containing quartz film layer ranges from 0.1 μm to 3 μm.

9. The method for manufacturing an EUV-grade substrate according to claim 1, wherein: The titanium content in the titanium oxide silicate-containing quartz film layer gradually increases from bottom to top.

10. A method for manufacturing an EUV mask blank, characterized in that: include: Forming an EUV-grade substrate by adopting the method for manufacturing an EUV-grade substrate according to any one of claims 1 to 9; A reflective film stack layer and an absorption layer are sequentially formed on the EUV-grade substrate to form an EUV mask blank.

11. The method for manufacturing an EUV mask blank according to claim 10, wherein: After forming the reflective film stack layer and before forming the absorption layer, the method further includes: forming a covering layer on the reflective film stack layer; and After forming the absorption layer, the method further includes: forming a back conductive layer on a surface of the EUV-grade substrate facing away from the reflective film stack layer.

12. A method for manufacturing an EUV mask, characterized in that: include: Adopting the manufacturing method of the EUV mask blank according to claim 10 or 11 to form the EUV mask blank; etching an absorption layer of the EUV mask blank to form a first pattern in the absorption layer; The absorption layer and the reflective film stack layer of the EUV mask blank around the first pattern are etched, and the etching stops on the surface of the EUV grade substrate of the EUV mask blank to form a second pattern.

13. An EUV-grade substrate, characterized in that: include: blank quartz substrate; A quartz film layer containing titanium oxide silicate is formed on the surface of a blank quartz substrate; The titanium oxide silicate-containing quartz film layer is formed by alternately injecting titanium ions and oxygen ions into the surface layer of the blank quartz substrate and performing heat treatment, so that the surface layer of the blank quartz substrate is fully combined with and reacted with the injected titanium ions and oxygen ions; The thermal expansion of silicon oxide and titanium oxide in the titanium oxide silicate-containing quartz film offsets each other, so that the thermal expansion coefficient of the EUV-grade substrate surface at the operating temperature is less than or equal to 0.1 ppm / °C; Furthermore, the quartz film layer containing titanium oxide silicate is also used to reduce defects introduced by the EUV-grade substrate during EUV lithography, thereby improving the EUV lithography effect.

14. The EUV-grade substrate according to claim 13, wherein The quartz film layer containing titanium oxide silicate also contains a dopant, and the dopant includes at least one of B, Al, Mg, Ca, Nb, Ta, Mn, Cu, Sn, F, and Cl.

15. The EUV-grade substrate according to claim 13, wherein The titanium content in the titanium oxide silicate-containing quartz film layer gradually increases from bottom to top.

16. The EUV-grade substrate according to any one of claims 13 to 15, wherein The thickness of the titanium oxide silicate-containing quartz film layer is 0.1 μm to 3 μm.

17. The EUV-grade substrate according to any one of claims 13 to 15, wherein The EUV-grade substrate further includes a removable spin-on carbon layer formed on a surface of the titanium oxide silicate-containing quartz film layer.

18. An EUV mask blank, characterized in that: include: The EUV-grade substrate according to any one of claims 13 to 17; a reflective film stack layer formed on the EUV-grade substrate; An absorption layer is formed on the reflective film stack layer.

19. The EUV mask blank according to claim 18, wherein: Also includes: a capping layer formed between the top reflective film of the reflective film stack layer and the absorption layer; And, a back conductive layer is formed on the surface of the EUV-grade substrate facing away from the reflective film stack layer.

20. An EUV mask, characterized in that: The EUV mask has an EUV mask base as described in any one of claims 18 or 19, and the EUV mask also has a first pattern and a second pattern, the first pattern is formed in the absorption layer of the EUV mask base, and the second pattern penetrates the absorption layer and the reflective film stack layer of the EUV mask base and exposes the surface of the EUV-level substrate of the EUV mask base.

Images