An SRAM type FPGA reconfiguration system with self-refresh function based on heterogeneous SIP and a working method thereof

Abstract

The application provides a SRAM type FPGA reconfiguration system with a self-refresh function based on a heterogeneous SIP and a working method, which comprises a heterogeneous SIP chip, a program memory NOR FLASH and a bus interface chip; the CPU, the SRAM type FPGA and the data memory DDR are integrated in the heterogeneous SIP chip; the CPU is used for refreshing the SRAM type FPGA, receiving reconfiguration instructions and reconfiguration data uploaded by a satellite-ground communication interface and reconfiguring the SRAM type FPGA; the SRAM type FPGA is used for on-orbit function reconfiguration; the data memory DDR is used for writing configuration bit streams of the FPGA; the program memory NOR FLASH is used for storing CPU programs and configuration bit streams of the FPGA; and the bus interface chip is used for transmitting the reconfiguration data uploaded by the satellite-ground communication interface to the CPU. The application can complete the refreshing and reconfiguration of the SRAM type FPGA in the SIP without additional external devices, reduces the influence of space single particles on the FPGA work, meets the space reliable application requirements, greatly reduces the cost, and reduces the volume, weight and power consumption.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of SRAM FPGA on-orbit reliability, and in particular to a SRAM FPGA reconfiguration system with self-refresh function based on heterogeneous SIP and a working method thereof. BACKGROUND

[0002] With the increasingly stringent requirements of satellites on the volume, weight and cost of on-board products, SIP technology (i.e. system-in-package technology) is used to package chips with different functions in the system together to form a micro-system-level SIP product, which has become an important means for miniaturization of on-board products. Compared with system integration on a printed circuit board, SIP can improve integration, reduce weight, shorten development cycle and reduce cost. Heterogeneous SIP refers to a SIP that integrates different computing units internally.

[0003] The on-board data management device is mainly responsible for the collection, processing and control of on-board data. A CPU is usually used for calculation and processing, and an FPGA is responsible for interface control. In order to adapt to subsequent demand changes and expansion, SRAM FPGA is usually used for on-orbit function reconfiguration. SRAM FPGA is a programmable logic gate array based on SRAM cells that can be reconfigured. Due to the single event effect in space, SRAM FPGA is prone to single event upset, which mainly occurs in the configuration memory and interconnection line configuration bits. In order to avoid the risk of product function error caused by single event upset, in addition to three-mode redundancy of FPGA, a timing refresh is usually performed on the configuration area to ensure that the FPGA can work normally in the space environment. This is usually done by an anti-single event capable antifuse FPGA or a dedicated refresh chip.

[0004] In order to avoid the influence of space environment on the normal operation of SRAM FPGA, the present application proposes a method for refreshing and reconfiguring SRAM FPGA in a heterogeneous SIP that integrates SRAM FPGA and CPU as two computing units without the need to add external devices, ensuring the reliability of space application. SUMMARY

[0005] In order to achieve the above-mentioned target, the present application provides a SRAM FPGA reconfiguration system with self-refresh function based on heterogeneous SIP and a working method thereof, which solves the problem of high cost and large volume of additional peripheral circuits required for SRAM FPGA refresh and reconfiguration in existing SIP.

[0006] In the first aspect, the present application provides a SRAM FPGA reconfiguration system with self-refresh function based on heterogeneous SIP, which comprises a heterogeneous SIP chip, a program memory NOR FLASH and a bus interface chip.

[0007] The isomerization SIP chip integrates a CPU, an SRAM type FPGA and a data storage DDR, the CPU is used for refreshing the SRAM type FPGA, and is used for receiving reconstruction instructions and reconstruction data uploaded on a satellite-ground communication interface, and reconstructing the SRAM type FPGA, the SRAM type FPGA is used for on-orbit function reconstruction, and the data storage DDR is used for writing configuration bit streams of the FPGA;

[0008] The program memory NOR FLASH is used for storing CPU programs and configuration bit streams of the FPGA;

[0009] The bus interface chip is used for transmitting the reconstruction data uploaded on the satellite-ground communication interface to the CPU.

[0010] Further, the CPU adopts a P2020 chip, the SRAM type FPGA adopts a V4 type FPGA, programs of the P2020 chip and the V4 type FPGA are placed in the program memory NOR FLASH, the P2020 chip is connected with the program memory NOR FLASH through a Local Bus, interface voltages of SPI and GPIO of the P2020 chip are set to be consistent with a Bank voltage of a V4 type FPGA configuration interface, M[2:0] of the V4 type FPGA are all connected to a V4 type FPGA configuration interface Bank power supply, a V4 type FPGA configuration mode is set to be a serial mode, SPICLK and SPIMOSI of the P2020 chip are connected to CCLK and D_IN of the V4 type FPGA respectively, SPICS of the P2020 chip is set to be in a suspended state, SPIMISO of the P2020 chip is connected to GND, DOUT of the V4 type FPGA is set to be in a suspended state, GPIO5, GPIO6, GPIO7 and GPIO12 of the P2020 chip are connected to INIT_B, PROGRAM_B, DONE and a global I / O pin of the V4 type FPGA respectively;

[0011] Before the system works, the program of P2020 chip and the program of V4 type FPGA are respectively written into the starting position and the terminal position of program memory NOR FLASH, after power on, P2020 chip firstly loads the program from the starting address of program memory NOR FLASH, and moves to data memory DDR to run, V4 type FPGA is configured to be from serial mode after power on, and waits for P2020 chip to configure, after P2020 chip initializes eSPI interface, SPICLK outputs clock, P2020 chip transmits V4 type FPGA program to V4 type FPGA through the serial mode of eSPI interface of P2020 chip from the entry address of V4 type FPGA configuration program stored in program memory NOR FLASH, and detects the DONE signal output by V4 type FPGA, after configuration is completed, P2020 chip resets V4 type FPGA to start normal work, and starts refresh in time.

[0012] In the second aspect, the application provides a working method of a SRAM type FPGA reconfiguration system with a self-refresh function based on a heterogeneous SIP, comprising the following steps:

[0013] Step 1, after the CPU is powered on, the CPU program is read from the program memory NOR FLASH, and self-boosting start is completed;

[0014] Step 2, the CPU controls the SRAM type FPGA to clear the internal configuration RAM area, and waits for the internal configuration RAM area to be cleared;

[0015] Step 3, the CPU reads three copies of FPGA configuration bit streams from the program memory NOR FLASH through the Local Bus, and writes the FPGA configuration bit streams into the corresponding three fixed areas in the data memory DDR;

[0016] Step 4, the CPU reads the FPGA configuration bit streams from the data memory DDR, and makes a two-out-of-three decision, and sends the FPGA configuration bit streams to the SRAM type FPGA byte by byte, so that the SRAM type FPGA is loaded;

[0017] Step 5, the CPU outputs a reset signal to the SRAM type FPGA, so that the SRAM type FPGA is reset and starts normal work after the reset is completed;

[0018] Step 6, the CPU repeatedly reads the FPGA configuration bit streams from the data memory DDR according to a preset time period, and sends the FPGA configuration bit streams to the FPGA byte by byte, so that the FPGA is refreshed in time;

[0019] Step 7, after receiving the reconstruction instruction uploaded by the satellite-ground communication interface, the CPU receives the reconstruction data uploaded by the satellite-ground communication interface through the bus interface chip, carries out data format analysis and conversion to obtain the configuration bit stream, and stores the configuration bit stream into the data storage memory DDR in a position different from the original configuration bit stream, and carries out three backups;

[0020] Step 8, after the CPU judges the configuration bit stream from the data storage memory DDR, writes it into the program storage memory NOR FLASH in another sector different from the sector where the original configuration bit stream is located, and carries out three backups, the CPU suspends the timing refresh of the SRAM type FPGA, the address of the configuration bit stream from the program storage memory NOR FLASH is updated to a new storage address by the CPU, steps 2-6 are repeated, and the on-orbit function reconstruction of the SRAM type FPGA is completed.

[0021] Compared with the prior art, the advantages and beneficial effects of the present application are as follows:

[0022] 1. The refresh and reconstruction of the SRAM type FPGA are completed, the single event upset problem is fully considered, the influence of space single particles on the work of the SRAM type FPGA is greatly reduced, and the space reliable application requirements are met.

[0023] 2. Compared with the prior art method of refreshing the SRAM type FPGA through the Selectmap interface, the JTAG interface or the serial interface by using an external anti-fuse FPGA or a refresh chip, the present application directly uses the eSPI interface of the SIP internal CPU to load the SRAM type FPGA in the SIP through a serial mode, which can save the external anti-fuse FPGA or the refresh chip; at the same time, the CPU and the SRAM type FPGA in the SIP can share the program storage memory, which saves the required memory of the FPGA, greatly reduces the cost, and reduces the volume, weight and power consumption.

[0024] 3. Compared with the prior art method of using the GPIO of the CPU to simulate the timing required for FPGA configuration, the software resource consumption of the CPU in the present application is small, the implementation difficulty is low, and the operation is more convenient.

[0025] It should be understood that the content described in the above summary section is not intended to limit the key or important features of the embodiments of the present application, nor to limit the scope of the present application. Other features of the present application will become apparent through the following description. BRIEF DESCRIPTION OF DRAWINGS

[0026] In order to more clearly illustrate the technical solutions of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0027] Figure 1 A structural schematic diagram of a SRAM type FPGA reconfiguration system with self-refresh function based on heterogeneous SIP provided by the embodiment of the present application is shown in

[0028] Figure 2 A SPI interface timing diagram of P2020 chip is shown in

[0029] Figure 3 A V4 type FPGA interface timing diagram is shown in

[0030] The above drawings have shown the specific embodiments of the present application, and more detailed description will be given in the following. These drawings and textual descriptions are not intended to limit the scope of the present application concept by any means, but to illustrate the present application concept to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0031] The embodiments of the present application will be described in more detail below with reference to the drawings. Although some embodiments of the present application are shown in the drawings, it should be understood that the present application can be implemented in various forms, and should not be interpreted as being limited to the embodiments described herein, but rather these embodiments are provided to more thoroughly and completely understand the present application. It should be understood that the drawings and embodiments of the present application are only for exemplary purposes, and are not intended to limit the scope of protection of the present application.

[0032] The technical solutions of the present application will be described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and some embodiments may not be described again for the same or similar concepts or processes.

[0033] Figure 1 A structural schematic diagram of a SRAM type FPGA reconfiguration system with self-refresh function based on heterogeneous SIP provided by the embodiment of the present application is shown in Figure 1 As shown, it includes a heterogeneous SIP chip, a program memory NOR FLASH, and a bus interface chip.

[0034] The isomerization SIP chip integrates a CPU, an SRAM type FPGA and a data storage DDR, the CPU is used for refreshing the SRAM type FPGA, and is used for receiving reconstruction instructions and reconstruction data uploaded on a satellite-ground communication interface, and reconstructing the SRAM type FPGA, the SRAM type FPGA is used for on-orbit function reconstruction, and the data storage DDR is used for writing configuration bit streams of the FPGA;

[0035] The program memory NOR FLASH is used for storing CPU programs and FPGA configuration bit streams;

[0036] The bus interface chip is used for transmitting the reconstruction data uploaded on the satellite-ground communication interface to the CPU.

[0037] In a possible implementation, the CPU adopts a P2020 chip, the P2020 chip internally integrates an eSPI interface, the eSPI is a master-slave structure, when the P2020 chip is a master node, at most 4 slave nodes can be supported, the signal definition is shown in Table 1, the SRAM type FPGA adopts a V4 type FPGA, the configuration mode of the V4 type FPGA is shown in Table 2, the programs of the P2020 chip and the V4 type FPGA are placed in the program memory NOR FLASH, the P2020 chip is connected with the program memory NOR FLASH through a Local Bus, the interface voltage of the SPI and the GPIO of the P2020 chip is set to be consistent with the Bank voltage of the V4 type FPGA configuration interface, the M[2:0] of the V4 type FPGA is connected to the Bank power supply of the V4 type FPGA configuration interface, the V4 type FPGA configuration mode is set to be a slave serial mode, the SPICLK and the SPIMOSI of the P2020 chip are connected to the CCLK and the D_IN of the V4 type FPGA respectively, the SPICS of the P2020 chip is set to be in a suspended state, the SPIMISO of the P2020 chip is connected to the GND, the DOUT of the V4 type FPGA is set to be in a suspended state, the GPIO5, the GPIO6, the GPIO7 and the GPIO12 of the P2020 chip are connected to the INIT_B, the PROGRAM_B, the DONE and a global I / O pin of the V4 type FPGA respectively.

[0038] Table 1

[0039]

[0040] Table 2

[0041]

[0042] Before the system works, the program of the P2020 chip and the program of the V4 type FPGA are respectively written into the starting position and the terminal position of the program memory NOR FLASH, after power-on, the P2020 chip firstly loads the program from the starting address of the program memory NOR FLASH and moves to the data memory DDR to run, the V4 type FPGA is configured to be in the serial mode after power-on, waits for the P2020 chip to configure, after the P2020 chip initializes the eSPI interface, the SPICLK outputs the clock, the P2020 chip transmits the V4 type FPGA program to the V4 type FPGA through the serial mode of the eSPI interface of the P2020 chip from the entry address of the V4 type FPGA configuration program stored in the program memory NOR FLASH, and detects the DONE signal output by the V4 type FPGA, after the configuration is completed, the P2020 chip resets the V4 type FPGA to start normal work, and starts the refresh in time.

[0043] It can be seen that the SRAM type FPGA reconfiguration system with the self-refresh function based on the heterogeneous SIP provided in the embodiment directly connects the eSPI interface of the P2020 chip in the heterogeneous SIP with the serial configuration port of the V4 type FPGA, stores the CPU program and the FPGA program in the program memory NOR FLASH, and outputs the clock and the configuration bit stream to the V4 type FPGA through the eSPI interface of the P2020 chip, so that the configuration, refresh and reconfiguration of the V4 type FPGA can be completed by only controlling and resetting the V4 type FPGA through the GPIO port.

[0044] The SRAM type FPGA reconfiguration system with the self-refresh function based on the heterogeneous SIP in the embodiment works as follows:

[0045] Step 1, after the P2020 chip is powered on, the CPU program is read from the NOR FLASH, the bootstrap is started (including the DDR interface initialization, the SPI interface initialization, the GPIO initialization and the like), wherein the GPIO5 of the P2020 chip is set as input, the GPIO6 is set as output, the GPIO7 is set as input, the GPIO12 is set as output, the P2020 chip sets the SPI interface register, and the parameters CL and CP are both 0, that is, the middle position of the SPI clock and data is aligned;

[0046] Step 2, the P2020 chip sets the GPIO6 as low-level output and keeps 1ms, controls the PROGRAM_B of the V4 type FPGA to clear the internal configuration RAM area, and the P2020 chip reads the INIT_B state of the V4 type FPGA through the GPIO5, when the INIT_B state becomes high level, it indicates that the internal configuration RAM area is cleared;

[0047] Step 3, P2020 chip reads three copies of FPGA configuration bit stream from NOR FLASH through Local Bus and writes into corresponding three fixed areas in DDR respectively;

[0048] Step 4, P2020 chip reads FPGA configuration bit stream from DDR and makes a two-out-of-three decision, P2020 chip sends to V4 FPGA through SPI interface byte by byte, V4 FPGA samples D_IN data on the rising edge of CCLK clock, the SPI interface timing diagram is shown as Figure 2 , P2020 chip reads the DONE signal state of V4 FPGA through GPIO7, when it becomes high level, it indicates that FPGA loading is completed, the V4 FPGA interface timing diagram is shown as Figure 3 ;

[0049] Step 5, P2020 chip outputs reset signal through GPIO12 to reset V4 FPGA, after V4 FPGA is reset, it starts to work normally;

[0050] Step 6, P2020 chip sets 2s timer, reads FPGA configuration bit stream from DDR every 2s and sends to V4 FPGA through SPI interface byte by byte, to complete the timing refresh of V4 FPGA;

[0051] Step 7, after P2020 chip receives the reconstruction instruction uploaded by the satellite-ground communication interface, the on-orbit spacecraft enters the reconstruction mode, P2020 chip receives the reconstruction data uploaded by the satellite-ground communication interface through the bus interface chip, analyzes and converts the data format to obtain the configuration bit stream, and stores it in DDR at a different location from the original configuration bit stream, and makes three backups;

[0052] Step 8, P2020 chip writes the configuration bit stream into NOR FLASH after two-out-of-three decision from DDR, in a different sector from the original configuration bit stream, and makes three backups, P2020 chip suspends the timing refresh of V4 FPGA, updates the address of P2020 chip from NOR FLASH to obtain the configuration bit stream to the new storage location, repeats steps 2-6, and completes the on-orbit function reconstruction of V4 FPGA.

[0053] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, but not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A heterogeneous SIP-based SRAM-type FPGA reconfiguration system with self-refresh function, characterized in that, The application relates to a heterogeneous SIP chip, a program memory NOR FLASH and a bus interface chip. The CPU is used for refreshing the SRAM type FPGA, receiving reconfiguration instructions and reconfiguration data uploaded by a satellite-ground communication interface and reconfiguring the SRAM type FPGA; the SRAM type FPGA is used for on-orbit function reconfiguration; and the data storage DDR is used for writing configuration bit streams of the FPGA. The program memory NOR FLASH is used for storing CPU programs and configuration bit streams of the FPGA. The bus interface chip is used for transmitting reconfiguration data uploaded by the satellite-ground communication interface to the CPU. The CPU adopts a P2020 chip, the SRAM type FPGA adopts a V4 type FPGA, programs of the P2020 chip and the V4 type FPGA are placed in the program memory NOR FLASH, the P2020 chip is connected with the program memory NOR FLASH through a Local Bus, the interface voltage of SPI and GPIO of the P2020 chip is set to be consistent with the Bank voltage of a V4 type FPGA configuration interface, M[2:0] of the V4 type FPGA are all connected to the Bank power supply of the V4 type FPGA configuration interface, the V4 type FPGA configuration mode is set to be from a string mode, SPICLK and SPIMOSI of the P2020 chip are connected to CCLK and D_IN of the V4 type FPGA respectively, SPICS of the P2020 chip is set to be in a suspended state, SPIMISO of the P2020 chip is connected to GND, DOUT of the V4 type FPGA is set to be in a suspended state, GPIO5, GPIO6, GPIO7 and GPIO12 of the P2020 chip are connected to INIT_B, PROGRAM_B, DONE and a global I / O pin of the V4 type FPGA respectively. Before the system works, the programs of the P2020 chip and the V4 type FPGA are respectively burned into the starting position and the terminal position in the program memory NOR FLASH, after power-on, the P2020 chip firstly loads the program from the starting address in the program memory NOR FLASH and moves to the data storage DDR to run, the V4 type FPGA is configured to be in a from string mode after power-on and waits for the P2020 chip to be configured, after the P2020 chip initializes the eSPI interface, SPICLK outputs a clock, the P2020 chip transmits the V4 type FPGA program to the V4 type FPGA through the serial mode of the eSPI interface of the P2020 chip from the entry address of the V4 type FPGA configuration program stored in the program memory NOR FLASH and detects the DONE signal output by the V4 type FPGA, the P2020 chip resets the V4 type FPGA to start normal work and starts refreshing in a timing mode. The application further relates to a reconfiguration method of the heterogeneous SIP chip.

2. A method for operating a heterogeneous SIP-based SRAM-type FPGA reconfiguration system with self-refresh function, characterized in that, ​ Step 1, after the CPU is powered on, read the CPU program from the program memory NOR FLASH, complete the bootstrap start; Step 2, the CPU controls the SRAM type FPGA to clear the internal configuration RAM area, and waits for the completion of the internal configuration RAM area clearing; Step 3, the CPU reads three copies of the FPGA configuration bit stream from the program memory NOR FLASH through the Local Bus, and writes them into the corresponding three fixed areas in the data storage memory DDR; Step 4, the CPU reads the FPGA configuration bit stream from the data storage memory DDR, and makes a three-to-two decision, sends it to the SRAM type FPGA byte by byte, and completes the SRAM type FPGA loading; Step 5, the CPU outputs a reset signal to the SRAM type FPGA, so that the SRAM type FPGA resets and starts normal work after completion of the reset; Step 6, the CPU repeats reading the FPGA configuration bit stream from the data storage memory DDR according to the preset time period, and sends it to the FPGA byte by byte, to complete the timing refresh of the FPGA; Step 7, after receiving the reconstruction instruction uploaded by the satellite-ground communication interface, the CPU receives the reconstruction data uploaded by the satellite-ground communication interface through the bus interface chip, analyzes and converts the data format to obtain the configuration bit stream, and stores the configuration bit stream in the data storage memory DDR at a different location from the original configuration bit stream, and makes three backups; Step 8, the CPU reads the configuration bit stream from the data storage memory DDR, makes a three-to-two decision, and writes it into the program memory NOR FLASH at a different sector from the original configuration bit stream, and makes three backups, the CPU pauses the timing refresh of the SRAM type FPGA, updates the address of the CPU configuration bit stream from the program memory NOR FLASH to the new storage address, repeats steps 2-6, and completes the on-orbit function reconstruction of the SRAM type FPGA.

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