Adjustment of trim settings based on usage of memory device

Abstract

This application relates to adjustment of trim settings based on usage of a memory device. An apparatus can include an array of memory cells and control circuitry coupled to the array of memory cells. The control circuitry can be configured to store a plurality of trim settings and receive signaling indicative of usage of the array of memory cells. The control circuitry can be configured to determine an adjustment to the plurality of trim settings based at least in part on the signaling.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure generally relate to computing systems and, more particularly, to determining adjustments to trim settings of a memory device based on usage of the memory device. BACKGROUND

[0002] Trim settings can be stored on a memory device, such as a NAND memory device. The trim settings can be maintained in a trim table. The trim settings can include, but are not limited to, voltage changes and / or timing settings for performing various memory operations, such as program (write) operations, erase operations, and read operations. Different trim settings can be used in response to errors occurring when using other trim settings, such as errors occurring during power-up of a NAND memory device. A trim table can be loaded to recover from errors during operation of a NAND memory device. SUMMARY

[0003] An aspect of the present disclosure provides an apparatus comprising: an array of memory cells; and control circuitry coupled to the array of memory cells and configured to: store a plurality of trim settings; receive signaling indicative of usage of the array of memory cells; and determine an adjustment to the plurality of trim settings based at least in part on the signaling.

[0004] Another aspect of the present disclosure provides a system comprising: a memory device comprising: an array of memory cells; and control circuitry; and artificial intelligence (AI) circuitry hosted on a remote server communicatively coupled to the memory device, wherein the AI circuitry is configured to: receive, from the memory device, first signaling indicative of a performance throughput of the array of memory cells; determine, corresponding to respective usage of a plurality of other memory devices, respective adjustments to a plurality of trim settings of the plurality of other memory devices; determine, based at least in part on the first signaling and the determined adjustments to the plurality of trim settings, an adjustment to a trim setting of the memory device; and provide, to the control circuitry, second signaling indicative of the determined adjustment to the trim setting.

[0005] Another aspect of the present disclosure provides an apparatus comprising: an array of memory cells; and control circuitry coupled to the array of memory cells and configured to: receive signaling indicative of an operating temperature of the array of memory cells; determine whether the operating temperature is greater than a first threshold operating temperature; determine whether the operating temperature is less than a second threshold operating temperature; and in response to determining that the operating temperature is greater than the first threshold operating temperature or less than the second threshold operating temperature, adjust a trim setting of the array of memory cells to improve performance of the array of memory cells.

[0006] Another aspect of the disclosure provides a method comprising: receiving, by control circuitry of a memory device, signaling indicative of at least one of: a performance throughput of the memory device; an operating temperature of the memory device; and a type of data written to the memory device; and determining, based at least in part on the signaling, an adjustment to a tuning setting of the memory device. BRIEF DESCRIPTION OF DRAWINGS

[0007] The disclosure will be more fully understood from the following detailed description taken in connection with the accompanying drawings, in which:

[0008] Figure 1 An example computing system including a memory sub-system according to some embodiments of the disclosure is described.

[0009] Figure 2 A flowchart to represent a process to determine a tuning setting via artificial intelligence (AI) circuitry of a controller of a memory device based on usage of the memory device.

[0010] Figure 3 A flowchart to represent a process to determine a tuning setting via AI circuitry of a remote server communicatively coupled to a controller of a memory device based on usage of the memory device.

[0011] Figure 4 A flowchart to represent a process to determine a tuning setting via AI circuitry of a controller of a memory device based on usage of the memory device.

[0012] Figure 5 A flowchart to represent an example method for operating a memory device according to some embodiments of the disclosure.

[0013] Figure 6 A block diagram of an example computer system in which embodiments of the disclosure can operate. DETAILED DESCRIPTION

[0014] At least one embodiment of the present disclosure provides a controller and memory device (e.g., NAND array) memory that is capable of determining and implementing respective trim settings and / or trim tables for a plurality of usage conditions. As described herein, artificial intelligence (AI) can be used to determine during operation of the memory device and implement trim settings based on the manner, time, location, and / or reason for using and / or operating the memory device. In some embodiments, a controller coupled to the memory device has AI capability to dynamically (e.g., “on-the-fly”) determine trim settings based on signaling indicative of the manner, time, location, and / or reason for using and / or operating the memory device. In some embodiments, a controller coupled to the memory device communicates with a remote server hosting AI capability to dynamically determine trim settings based on signaling provided by the controller indicative of the manner, time, location, and / or reason for using the memory device. As described herein, embodiments of the present disclosure provide flexibility and adaptability of trim settings that are not possible by the aforementioned approaches.

[0015] The aforementioned approaches of operating a memory device with respect to the programming trim, timing, and / or voltage used by the memory device are limited. For example, a memory device can be provided with a single combination of programming trim, timing, and / or voltage for the lifetime of the memory device. Due to this limitation, the memory device can not be optimized to account for one or more particular usage cases of the memory device. A usage case for a memory device can be referred to herein as a use of the memory device. A usage case for a memory device can be characterized by factors internal to the memory device and / or factors external to the memory device. For example, a usage case can be characterized by the environment in which the memory device is operated. Non-limiting examples of external environmental factors of a usage case include exposure of the memory device to high or low temperatures, humidity, and vibration / shock. A usage case can be characterized by the manner in which the memory device is used. Non-limiting examples of internal factors of a usage case driven by the manner in which the memory device is used can include performance goals of the memory device, throughput of the memory device, length of life of the memory device, expected program-erase cycles of the memory device, data retention of the memory device, and reliability.

[0016] Some of the foregoing methods include providing predetermined trim settings based on predetermined use cases. Such predetermined trim settings can be set as initial settings by a manufacturer of the memory device or by a user of the memory device. These predetermined trim settings cannot be modified and do not provide the ability to customize the operation and / or performance of the memory device to meet changes in use cases. When the use case favors performance and / or reliability of data over the lifetime of the memory device, the performance of the memory device can be limited by using a single set of programmed trim settings. Some of the foregoing methods can use a trim table to adjust trim settings (e.g., voltage and timing settings). For example, a trim table can be used to increase the speed of a controller to re-rate a memory array of a memory device after an error by applying trim setting changes from the trim table rather than re-rating the memory array with trim setting changes. Errors that occur during the lifetime of the memory device can be recovered by applying trim setting changes from the trim table. Some of the foregoing methods can include providing default trim settings to comply with user specifications, but cannot adjust the default trim settings. Some of the foregoing methods can include adding a trim table to cover extreme cases identified during the rating or lifetime of the memory device. However, such foregoing methods are limited to recovery from errors and / or improving the reliability of the memory device.

[0017] At least one embodiment of the present disclosure provides the ability to adjust trim settings of a memory device that are not provided by the foregoing methods. At least one embodiment enables dynamically updating a trim table stored (e.g., stored on a controller and / or a memory array) by a memory device. The trim table can be controlled by AI circuitry, external data sources, and / or machine learning to adjust trim settings of the memory device to account for multiple use cases of the memory device. As used herein, “external data sources” refers to repositories of data associated with the type of memory device and / or the use of the memory device. Non-limiting uses of the memory device include improving the performance of the memory device, increasing the reliability of the memory device, supporting the operation of the memory device when subjected to extreme temperatures, and extending the lifetime of the memory device.

[0018] The AI circuitry can be configured to use iterative processing and algorithms to combine data such that the AI circuitry learns from patterns and / or features in the data. A non-limiting example of AI circuitry can be a neural network. As used herein, a "neural network" refers to software, hardware, or a combination thereof, configured to process data in a manner analogous to neurons of the human brain. Artificial neural networks can include various techniques such as deep learning and machine learning. As used herein, "machine learning" refers to the ability of software, hardware, or a combination thereof, to learn and improve from experience without being explicitly programmed for improvement. As used herein, "deep learning" refers to a machine learning method based on artificial neural networks with representational learning, which can be supervised, semi-supervised, or unsupervised.

[0019] At least one embodiment of the present disclosure includes determining trim settings for a memory device based on usage (e.g., use case) of the memory device. The use case of the memory device can be described, for example, by an environment in which the memory device is operated. The use case of the memory device can be described by one or more performance targets of the memory device, such as throughput, lifetime of the memory device, program-erase cycles, data retention, and reliability. At least one embodiment can utilize AI circuitry, external data sources, and / or machine learning to determine trim settings based on the use case of the memory device. The AI circuitry can be a component of the memory device (e.g., control circuitry of the memory device). The memory device can communicate with a server (e.g., a cloud server) that hosts the AI circuitry, external data sources, and / or machine learning.

[0020] At least one embodiment can include analyzing trim setting adjustments to characterize tradeoffs of adjusting voltage and / or timing settings to modify, for example, program time, data retention, read time, reliability, read disturb, cross-temperature support, and / or program / erase cycle capacity. In at least one embodiment, the AI circuitry can perform an analysis of default trim settings of the memory device and subsequently determine additional trim settings to improve performance and / or reliability of the memory device. The AI circuitry can update default trim settings for a particular die of the memory device based on lot data and / or trends of dies and wafer characteristics of the dies, such as manufacturing data, test data, and measurements taken during manufacturing. This can enable dynamic optimization (e.g., real-time updating) of respective trim tables associated with each die or group of dies of the memory device during operation of the memory device.

[0021] In at least one embodiment, AI circuitry can determine trends in usage of a memory device and requirements of the memory device associated with usage trends. AI circuitry can determine trim settings of the memory device to adjust to meet determined requirements. For example, AI circuitry can monitor operating temperature of a memory device to determine trim settings to adjust to improve performance of the memory device at operating temperature.

[0022] In at least one embodiment, AI circuitry can monitor storage of data in a memory array of a memory device. A user profile can be created by AI circuitry based on, for example, screen time, application type, and storage time. A user profile can indicate respective usage of a memory device, and trim setting adjustments can be associated with each user profile. AI circuitry can identify which type of data is stored on a memory device for a long amount of time. AI circuitry can use a flag system in which flag data is stored with user data. Flag data can indicate a type of user data. Flag data can be read to predict a length of storage time of user data on a memory device.

[0023] In at least one embodiment, AI circuitry can determine trim setting adjustments to account for problems caused by manufacturing process shifts. For example, AI circuitry can determine trim setting adjustments to improve low reliability of a memory device caused by manufacturing process variations.

[0024] In at least one embodiment, AI circuitry can monitor a bit error rate (BER) of a memory device (per page, byte, block, etc.). AI circuitry can adjust trim settings of a memory device to overcome increased BER over a lifetime of the memory device or high BER in particular blocks, pages, or bytes of the memory device.

[0025] At least one embodiment can include determining adjustments to trim settings based on usage of the memory device and thus updating the trim table stored on the memory device. Non-limiting examples of adjustments to trim settings based on usage of the memory device are as follows. If the AI circuitry determines that a particular data is frequently read from the memory device, the trim settings can be adjusted to reduce read disturb when the data is read. If the AI circuitry determines that the operating temperature of the memory device is extremely low or extremely high, the trim settings can be adjusted to improve performance (e.g., reliability) of the memory device at the operating temperature. If the AI circuitry determines that particular data stored on the memory device will be read occasionally, the trim settings can be adjusted so that the data is written to the memory device quickly but with reduced reliability. If the AI circuitry determines that the memory device is frequently affected by cross-temperature events, the trim settings can be adjusted to improve reliability of write operations performed by the memory device. If the AI circuitry determines that particular data is stored on the memory device for a long period of time, the trim settings can be adjusted to increase reliability. If the AI circuitry determines that the retention rate of the memory device is low, the trim settings can be adjusted to improve performance of the memory device.

[0026] In at least one embodiment, the AI circuitry can determine trim setting adjustments to achieve a desired usage lifetime of the memory device. For example, the AI circuitry can determine adjustments to the trim table (e.g., adjustments to trim settings maintained in the trim table) to improve performance of the memory device, which can reduce the usage lifetime of the memory device if a short usage lifetime is desired (rather than a longer usage lifetime). Conversely, the AI circuitry can determine adjustments to the trim table to improve reliability and / or retention rate of the memory device, which can decrease performance of the memory device if a longer usage lifetime of the memory device is desired. The desired length of the usage lifetime of the memory device can be based on user input. The AI circuitry can determine the desired usage lifetime of the memory device based on usage of the memory device. For example, if the AI circuitry determines that performance of the memory device is consistently high, the AI circuitry can determine that a short usage lifetime (or not a longer usage lifetime) is desired.

[0027] The figures herein follow a convention relating to the numbering in which the first one or more digits correspond to the figure number and the remaining digits identify an element or component in the figure. For example, 119 can refer to element “19” in Figure 1 and like elements can be denoted with a like numbering reference in Figure 2 e.g., 219 in the figure. Like elements can be generally referred to without the hyphen and extra numbers or letters using a shortened version of the elements’ numbers throughout the drawings. For example, Figure 3Elements 347-1...347-N in the figures can collectively be referred to as 347. As used herein, the designator “N” as in reference to a number in the figures indicates that a specific feature can include one of several particular features. As will be appreciated, elements shown in various embodiments herein can be added, exchanged, and / or removed so as to provide a number of additional embodiments of the present disclosure. In addition, as will be appreciated, the proportions and relative scales of the various elements provided in the figures are intended to illustrate certain embodiments of the application and should not be taken in a limiting sense.

[0028] Figure 1 An example computing system 101 including a memory sub-system 103 in accordance with some embodiments of the present disclosure is illustrated. The memory sub-system 103 can include media, such as one or more volatile memory devices 117, one or more non-volatile memory devices 119, or a combination thereof. The volatile memory devices 117 can be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and resistive RAM (ReRAM).

[0029] The memory sub-system 103 can be a storage device, a memory module, or a hybrid of a storage device and a memory module. Examples of storage devices include SSDs, flash drives, universal serial bus (USB) flash drives, embedded Multi-Media Controllers (eMMC) drives, Universal Flash Storage (UFS) drives, Secure Digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0030] The computing system 101 can be a computing device, such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, a car, or other means of transportation), an Internet of Things (IoT) enabled device, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or such computing device including a memory and a processing device.

[0031] The computing system 101 includes a host system 105 coupled to one or more of the memory sub-systems 103. In some embodiments, the host system 105 is coupled to different types of memory sub-systems 103. Figure 1 An example of a host system 105 coupled to a single memory sub-system 103 is illustrated. As used herein, “coupled to” or “coupled with” generally refers to a connection between components that can be an indirect communicative connection or a direct communicative connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

[0032] The host system 105 includes or is coupled to processing resources, memory resources, and network resources. As used herein, a "resource" is a physical or virtual component with limited availability within the computing system 101. For example, processing resources include processing devices, memory resources include the memory subsystem 103 for secondary storage and main memory devices (not specifically illustrated) for primary storage, and network resources include network interfaces (not specifically illustrated). The processing devices can be one or more processor chipsets that can execute a software stack. The processing devices can include one or more cores, one or more caches, memory controllers (e.g., NVDIMM controllers), and storage protocol controllers (e.g., PCIe controllers, SATA controllers, etc.). The host system 105 can use the memory subsystem 103, e.g., to write data to and / or read data from the memory subsystem 103.

[0033] The host system 105 can be coupled to the memory subsystem 104 via a physical host interface. Examples of physical host interfaces include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a PCIe interface, a Universal Serial Bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), Small Computer System Interface (SCSI), Double Data Rate (DDR) memory bus, Dual In-Line Memory Module (DIMM) interface (e.g., DIMM socket interface supporting Double Data Rate (DDR)), Open NAND Flash Interface (ONFI), Double Data Rate (DDR), Low Power Double Data Rate (LPDDR), or any other interface. The physical host interface can be used to transmit data between the host system 105 and the memory subsystem 103. When the memory subsystem 103 is coupled with the host system 105 through a PCIe interface, the host system 105 can further utilize a Non-Volatile Memory (NVMe) interface to access the non-volatile memory devices 119. The physical host interface can provide an interface for communicating control, address, data, and other signals between the memory subsystem 103 and the host system 105. The host system 105 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0034] The host system 105 can send requests to the memory sub-system 103, e.g., to store data on and / or read data from the memory sub-system 103. Data to be written or read as specified by a host request can be referred to as "host data." A host request can include logical address information. The logical address information can be a logical block address (LBA), which can include or be accompanied by a partition number. The logical address information is a location associated with the host data by the host system. The logical address information can be part of metadata for the host data. The LBA can also correspond to (e.g., dynamically map to) a physical address, such as a physical block address (PBA), which indicates a physical location in the memory where the host data is stored.

[0035] Examples of the non-volatile memory devices 116 include NAND-type flash memory. NAND-type flash memory includes, e.g., two-dimensional NAND (2-D NAND) and three-dimensional NAND (3-D NAND). The non-volatile memory devices 119 can be other types of non-volatile memory, such as read only memory (ROM), phase change memory (PCM), self-selecting memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive-bridge RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), or NOR flash memory, electrically erasable programmable read only memory (EEPROM), and 3-D cross point memory. Cross point arrays of non-volatile memory can store bits based on changes in bulk resistance in conjunction with stackable cross-gridded data access arrays. In addition, in contrast to many flash-based memories, cross point non-volatile memory can perform in-place write operations, where a non-volatile memory cell can be programmed without first erasing the non-volatile memory cell.

[0036] Each of the non-volatile memory devices 119 can include one or more arrays of memory cells. One type of memory cell, for example, single-level cells (SLCs), can store one bit per cell. Other types of memory cells, for example, multi-level cells (MLCs), triple-level cells (TLCs), quad-level cells (QLCs), and penta-level cells (PLCs), can store multiple bits per cell. In some embodiments, each of the non-volatile memory devices 119 can include one or more arrays of memory cells, for example, SLCs, MLCs, TLCs, QLCs, or any combination of such. In some embodiments, a particular memory device can include an SLC portion of memory cells, as well as an MLC portion, a TLC portion, a QLC portion, or a PLC portion. The memory cells of the non-volatile memory devices 119 can be grouped into pages, which can refer to a logical unit of the memory device to store data. For some types of memory (e.g., NAND), pages can be grouped to form blocks.

[0037] The memory sub-system controller 100, which can be referred to simply as controller 100 for simplicity, can communicate with the non-volatile memory devices 119 to perform operations such as reading data, writing data, erasing data, and other such operations at the non-volatile memory devices 119. The controller 100 can include hardware such as one or more integrated circuits and / or discrete components, a buffer memory, or a combination thereof. The hardware can include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The controller 100 can be a microcontroller, special purpose logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable circuitry.

[0038] The controller 100 can include a processing device 115 (e.g., a processor) configured to execute instructions stored in local memory 111. In the illustrated example, the local memory 111 of the controller 100 is an embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that handle operations of the memory sub-system 103, including handling communications between the memory sub-system 103 and the host system 105.

[0039] In some embodiments, the local memory 111 can include memory registers that store memory pointers, fetched data, and the like. For example, the local memory 111 can also include a ROM for storing microcode.

[0040] In general, the controller 100 can receive information or operations from the host system 105 and can convert the information or operations into instructions or appropriate information to effectuate desired accesses to the non-volatile memory devices 119 and / or volatile memory devices 117. The controller 100 can be responsible for other operations such as wear leveling operations, error detection and / or correction operations, encryption operations, caching operations, and address translations between logical addresses (e.g., LBAs) and physical addresses (e.g., physical block addresses) associated with the non-volatile memory devices 119. The memory sub-system controller 100 can further include host interface circuitry (not shown) to communicate with the host system 105 via the physical host interface. The host interface circuitry can convert queries received from the host system 105 into commands to access the non-volatile memory devices 119 and / or volatile memory devices 117, as well as convert responses associated with the non-volatile memory devices 119 and / or volatile memory devices 117 into information for the host system 105.

[0041] In at least one embodiment, the controller 100 can include AI circuitry 113. The AI circuitry 113 can be configured to determine adjustments to trim settings for the non-volatile memory devices 119 and / or volatile memory devices 117 as described herein. For example, the controller 100 can store a plurality of trim settings (in, e.g., local memory 111). The AI circuitry 113 can receive signaling indicative of usage for the non-volatile memory devices 119 and / or volatile memory devices 117. The AI circuitry 113 can determine adjustments to the plurality of trim settings based at least in part on the usage for the non-volatile memory devices 119 and / or volatile memory devices 117.

[0042] Although Figure 1 Although Figure 3 Although

[0043] Figure 2 A flow diagram to represent determining trim settings via AI circuitry of a controller 200 of a memory device based on usage of the memory device 219. The memory device 219 and controller 200 can be components of a memory sub-system, such as the memory sub-system 103 described in association with Figure 1 Although Figure 2The controller 200 determines the trim settings using AI circuitry of the controller 200, although embodiments of the disclosure are not limited thereto. For example, the controller 200 can communicate with AI circuitry hosted remotely (e.g., on a cloud server) to receive trim settings based on usage of the memory device. Further associated Figure 3 Such embodiments are described in association with

[0044] The controller 200 can receive signaling indicative of usage of the memory array. As illustrated at 202, the controller 200 can monitor performance throughput of one or more memory arrays coupled to the controller 200. As illustrated at 204, at an early stage of the lifetime of the memory device, increased data loading, application loading, and / or software loading can occur. For example, in embodiments where the memory device is a component of a mobile device (e.g., a mobile phone or tablet device), initial use of the mobile device can include a user setting up the mobile device with data, software, and applications. Accordingly, the controller 200 can determine that no adjustment to the trim settings is needed, and continue monitoring (at 202) performance throughput of the memory array. As illustrated at 216, the controller 200 can periodically monitor performance throughput during a sample period of operation.

[0045] As illustrated at 222, the controller 200 can receive, from a host device (not shown) coupled to the memory device, signaling indicative of events that are occurring frequently on the memory array (and / or events that the memory array is frequently subjected to). As illustrated at 221, the controller 200 can provide, to the host device, signaling indicative of the monitored performance throughput. The signaling indicative of the monitored performance throughput can be used to determine events that are occurring frequently. The signaling can be indicative of a number of write operations performed by the controller 200 during a particular time period. As illustrated at 224, the controller 200 can identify, based on the signaling indicative of frequent events, a trigger event that frequently requires improved performance of the memory array. In response to the trigger event, the controller 200 can determine a trim setting adjustment to improve performance as described herein accordingly. As illustrated at 226, after the trigger event, the controller 200 can adjust the trim setting to a previous value.

[0046] As explained at 206, the controller 200 can determine whether the performance throughput of the memory array requires the total bandwidth available for greater than a threshold amount of time (a trigger level). As explained at 207, if the performance throughput of the memory array requires the total bandwidth available for less than the threshold amount of time, then (at 210) the controller 200 can determine a number of operating periods (sample periods) for which the performance throughput did not require the total bandwidth. As explained at 212, if the number of operating periods is less than a threshold number of operating periods, then the controller 200 can continue (at 202) to monitor the performance throughput of the memory array. As explained at 214, if the number of operating periods is at least the threshold number of operating periods, then the controller 200 can adjust the trim settings of the memory array to improve the retention and / or reliability of the memory array. As explained at 218, the controller 200 can increase a read window budget (RWB) to improve the retention and / or reliability of the memory array. As used herein, a “read window budget” refers to a difference in different program verify voltages for different program states or in magnitudes of program verify voltages and erase verify voltages for different data states. Increasing the RWB can adversely affect the performance of the memory array because increasing the RWB increases the voltages required to read data from and write data to the memory array.

[0047] As explained at 208, if the performance throughput of the memory array requires the total bandwidth available for at least the threshold amount of time, then (at 220) the controller 200 can adjust the trim settings to improve the performance of the memory array. As explained at 220, the controller 200 can decrease the RWB. Decreasing the RWB improves the performance of the memory array by reducing the voltages required to read data from and write data to the memory array. In response to determining that the performance throughput requires the total bandwidth available for at least the threshold amount of time, the number of operating periods for which the performance throughput did not require the total bandwidth can be reset.

[0048] As explained at 209, if the controller 200 determines that the performance of the memory array has been improved as much as possible (further trim setting adjustments to improve performance cannot be made), then (at 222) the trim settings are not adjusted. The controller 200 can continue (at 202) to monitor the performance throughput of the memory array.

[0049] Figure 3 A flowchart to represent the determination of trim settings by an AI circuitry of a remote server 340 based on usage of a memory device 319 via a controller 330 communicatively coupled to the memory device 319. The remote server 340 can be a cloud server hosting the AI circuitry. The controller 330 can be similar to the controller 100 described in association with Figure 1

[0050] ​As illustrated at 331, controller 330 can monitor performance throughput of one or more memory arrays coupled to controller 330. As illustrated at 332, controller 330 can provide signaling indicative of the monitored performance throughput to AI circuitry hosted on remote server 340. A host device (not shown) including memory device 319 can provide signaling indicative of whether storage is needed. As illustrated at 341, AI circuitry can identify a type of data stored on memory device 319 based on the signaling from controller 330. AI circuitry can determine a use case for memory device 319 based on the signaling from controller 330. In the illustrated example, the use case for memory device 319 benefits from improved performance. However, embodiments of the disclosure are not limited to use cases that benefit from improved performance of memory device 316. Figure 3

[0051] As illustrated at 342, AI circuitry can provide signaling indicative of the type of data and / or the use case of the memory device identified by AI circuitry to a pool of external data sources. The external data sources can include one or more storage locations of a large amount of data indicative of use of different memory devices, such as memory devices 347-1...347-N. For example, the external data sources can include data indicative of a particular type or model of memory device associated with. The external data sources can provide AI circuitry with the ability to consider previously determined tuning settings based on a particular use case for a memory device (e.g., memory device 347-1) in determining tuning settings for another memory device (e.g., memory device 319) based on the particular use case for the other memory device. A tuning setting previously determined to meet requirements associated with a particular use case for a memory device can be provided to another memory device to meet the requirements associated with the particular use case.

[0052] As illustrated at 343, AI circuitry 340 can check data sets, applications, websites, web content, and / or software associated with memory device 319 and / or data stored on memory device 319 that are hosted on the internet, and the AI circuitry can compare the information with data from the pool of external data sources to determine tuning settings.

[0053] As illustrated at 344, AI circuitry 340 can request an indication of performance throughput of memory device 319 from controller 330. Based on the indication of performance throughput of memory device 319, AI circuitry 340 can determine a likelihood that data stored by memory device 319 will be used with a larger data set.

[0054] ​As illustrated at 345, the controller 330 can request access to data that the AI circuitry 340 stores or has access to.

[0055] As illustrated at 346, the AI circuitry 340 can provide an indication of data usage for independent throughput and / or multi-data concurrent throughput to the controller 330. As used herein, “independent throughput” refers to separate usage of data. As used herein, “multi-data concurrent throughput” refers to data usage that is simultaneous with other data and / or simultaneous with multiple applications. Multi-data concurrent throughput can require increased performance from the memory device as compared to independent throughput.

[0056] As illustrated at 333, the controller 330 can receive an input level from the AI circuitry 340. As illustrated at 334, the controller 330 can adjust a trim setting based on the input level from the AI circuitry 340. For example, the controller 330 can increase the RWB of the memory device 319 to improve the retention and / or reliability of the memory device 319. Increasing the RWB can adversely affect the performance of the memory device 319 because increasing the RWB increases the voltage required to read data from and write data to the memory device 319. The controller 330 can decrease the RWB of the memory device 319 to improve the performance of the memory device 319 by decreasing the voltage required to read data from and write data to the memory device 319.

[0057] As illustrated at 335, the controller 330 can perform a storage operation (e.g., read operation, write operation) using the adjusted trim setting. As illustrated at 336, the controller 330 can flag the beginning and / or end of a storage operation that involves a particular large file type, such as a video file, and / or a group of data that storage operations frequently involve, as illustrated at 337, the controller 330 can determine whether to perform operations concurrently. As illustrated at 331, the controller 330 can continue to monitor the performance throughput of the memory device 319. As illustrated at 338, in response to the controller 330 determining that the performance throughput does not meet expectations, the controller 330 adjusts the translation table.

[0058] Figure 4 A flowchart to represent determining a trim setting via AI circuitry of a controller of a memory device based on usage of the memory device. The AI circuitry can be similar to the AI circuitry 113 described in association with Figure 1 The controller 460 can be similar to the controller 100. For clarity and ease of illustration, Figure 4 a memory device is not illustrated. However, the memory device includes the controller 460 and at least one memory array coupled to the controller. AlthoughFigure 4 The controller 460 determines the trim setting using AI circuitry of the controller 460, but embodiments of the disclosure are not limited thereto. For example, the controller 460 can communicate with AI circuitry hosted remotely (e.g., on a cloud server) to receive a trim setting based on usage of the memory device.

[0059] As illustrated at 462, the controller 460 can monitor an operating temperature of one or more memory arrays coupled to the controller 460. The operating temperature can be affected by an environment in which the memory device is used. As illustrated at 486, at an early stage of a lifetime of the memory device, the trim setting can not be adjusted when the AI circuitry is aware of and monitors changes in the operating temperature.

[0060] As illustrated at 464, the controller 460 can determine whether the operating temperature exceeds a threshold operating temperature. The threshold operating temperature can be offset from a minimum operating temperature of the memory array or a maximum operating temperature of the memory array. For example, the threshold operating temperature can be a number of degrees less than the maximum operating temperature. The threshold operating temperature can be a number of degrees greater than the minimum operating temperature. The controller 460 can determine whether the memory device experienced a cross-temperature event.

[0061] As illustrated at 468, the controller 460 can determine that the operating temperature is such that performance of the memory device is not adversely affected by the operating temperature. As illustrated at 470, the controller 460 can return the trim setting that was previously adjusted to a default value (e.g., reduce the RWB to a default RWB). As illustrated at 488, the controller 460 can continue to periodically monitor the operating temperature during a sample operating period.

[0062] As illustrated at 466, the controller 460 can determine that the operating temperature can decrease reliability and / or retention of the memory array based on whether the operating temperature exceeds the threshold operating temperature and / or whether the memory device experienced a cross-temperature event. As illustrated at 472, the controller 460 can provide an indication that the operating temperature exceeds the threshold operating temperature (to, for example, a host device). For example, the controller 460 can provide an indication that the operating temperature is high or low.

[0063] As illustrated at 474, the controller 460 can adjust the trim setting of the memory array to account for the operating temperature exceeding the threshold operating temperature and improve retention and / or reliability of the memory array. For example, the controller 460 can increase the RWB to improve retention and / or reliability of the memory array. As illustrated at 488, the controller 460 can continue to periodically monitor the operating temperature during a sample operating period.

[0064] As illustrated at 476, in response to determining that the memory device has experienced a cross-temperature event that resulted in an operating temperature that exceeds the threshold operating temperature, the controller 460 can store occurrence data associated with the cross-temperature event. For example, the controller 460 can mark the time at which the cross-temperature event occurred and / or the amount of time at which the cross-temperature event occurred.

[0065] As illustrated at 478, the controller 460 can mark and / or count the number of times the memory device experiences a cross-temperature event within a certain amount of time (e.g., daily, weekly, monthly, etc.). As illustrated at 482 and 470, in response to determining that the memory device has experienced less than a threshold number of cross-temperature events, the controller 460 can return the trim setting that was previously adjusted to a default value (e.g., reduce the RWB to a default RWB).

[0066] As illustrated at 480, the controller 460 can adjust the trim setting of the memory array to account for the memory device experiencing a cross-temperature event and improve the retention and / or reliability of the memory array. For example, the controller 460 can increase the RWB to improve the retention and / or reliability of the memory array.

[0067] As illustrated at 484, the controller 460 can monitor the time and / or date. In at least one embodiment, the controller 460 can receive an indication of the time and / or date outside of the memory device, e.g., from a host device. The controller 460 can anticipate a cross-temperature event based on the time (e.g., time of day) at which the memory device previously experienced a cross-temperature event. The controller 460 can adjust the trim setting in advance (e.g., increase the RWB) so that the performance (e.g., reliability, retention) of the memory array is not adversely affected by the anticipated cross-temperature event. As illustrated at 488, the controller 460 can continue to periodically monitor the operating temperature during a sample operating period.

[0068] Figure 5 A flow diagram for an example method for operating a memory device in accordance with some embodiments of the present disclosure. The method can be performed by processing logic that can comprise hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method can be performed by or using the same processing logic as Figure 1The associated memory subsystem controller 100, processing device 115, AI circuit system 113, and / or non-volatile memory device 119 and / or volatile memory device 117 are used for execution. Although shown in a specific sequence or order, the order of processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0069] exist Figure 5 At block 550 in the example method, signaling indicating the type of performance throughput, operating temperature, and / or data written to a memory device (e.g., non-volatile memory device 116) can be received by the control circuitry of the memory device (e.g., controller 100).

[0070] In some embodiments, the signaling may indicate the date, time, or location of a previous increase in the performance throughput of the memory device. The expected date, time, and / or location of a subsequent increase in the performance throughput of the memory device may be determined based on the signaling. Adjustments to the fine-tuning settings may be applied to the memory device in advance based on the expected date, time, or location of a subsequent increase in performance throughput.

[0071] In some embodiments, the signaling may indicate the date, time, or location of a previous change in the operating temperature of the memory device. The expected date, time, or location of a subsequent significant change in the operating temperature of the memory device may be determined based on the signaling. Adjustments to the fine-tuning settings may be applied to the memory device in advance of the expected date, time, or location of a subsequent significant change in the operating temperature.

[0072] In some embodiments, the signaling may indicate the date, time, or location of a previous write of a specific type of data (e.g., video data) to the memory device. The expected date, time, or location of a subsequent write of a specific type of data to the memory device may be determined based on the signaling. Adjustments to the fine-tuning settings may be applied to the memory device in advance to determine the expected date, time, or location of a subsequent write of a specific type of data to the memory device.

[0073] exist Figure 5 In the instance method at block 552, it can be based on, for example, with Figures 2 to 4The signaling described in association with determines adjustment of trim settings of the memory device. Application metadata (rather than file system metadata) can be written with video data within the second portion. The memory device can be operated to provide storage for a black box application of a vehicle executed by a host, and the video data can be data from one or more cameras associated with the vehicle.

[0074] Figure 6 is a block diagram of an example computer system 601 in which embodiments of the disclosure can operate. Within the computing system 601, a set of instructions that when executed implement the methods discussed herein can be executed. The computing system 601 includes a processing device 615, a main memory 691, a static memory 619 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 603, which communicate with each other via a bus 692. The data storage system 603 can be similar to the data storage system 103 described in association with Figure 1 The memory subsystem 103 described in association with.

[0075] The processing device 615 represents one or more general-purpose processing devices such as a microprocessor, a central processing unit, or the like. More particularly, the processing device can be a complex instruction set computing (CISC) microprocessor, reduced instruction set computing (RISC) microprocessor, very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets, or processors implementing a combination of instruction sets. The processing device 615 can also be one or more special-purpose processing devices such as an ASIC, a FPGA, a digital signal processor (DSP), network processor, or the like. The processing device 615 is configured to execute instructions 693 for performing the operations and steps discussed herein. The computing system 601 can further include a network interface device 694 to communicate over the network 695.

[0076] The data storage system 603 can include a machine-readable storage medium 696 (also known as a computer-readable medium) on which is stored one or more sets of instructions 693 or software embodying one or more of the methodologies or functions described herein. The instructions 693 can also reside completely, or at least partially, within the main memory 691 and / or within the processing device 615 during execution thereof by the computing system 603, the main memory 691 and the processing device 615 also constituting machine-readable storage media that

[0077] In some embodiments, the instructions 693 can include instructions to implement a microprocessor-based black box application of a vehicle, as described in association with Figure 1instructions 691 can include trim setting instructions 697 to determine adjustments to trim settings of the static memory 619 based on usage of the static memory 619. While the machine-readable storage medium 696 is shown in an example embodiment to be a single medium, the term "machine-readable storage medium" should be taken to include a single medium or multiple media that store one or more sets of instructions. The term "machine-readable storage medium" shall also be taken to include any medium that is capable of storing or encoding a set of instructions for execution by the machine and that cause the machine to perform any one or more of the methodologies of the present disclosure. The term "machine-readable storage medium" shall accordingly be taken to include, but not be limited to, solid-state memories, optical media, and magnetic media.

[0078] Some portions of the preceding detailed descriptions have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. In this context, and for purposes of brevity and clarity, it is to be understood that these algorithms descriptions and representations have been simplified to some extent to aid readability and to convey the substance of the work to others skilled in the art. In this context, the term "algorithm" is to be understood to encompass a self-consistent sequence of operations leading to a desired result. The operations are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0079] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The disclosure can refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage systems.

[0080] The disclosure also relates to an apparatus for performing the operations herein. This apparatus can be specially constructed for the required purposes, or it can include a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program can be stored in a computer readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions.

[0081] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general purpose systems can be used with programs in accordance with the teachings herein, or it can prove convenient to construct a more specialized apparatus to perform the method. The structure for a variety of these systems will appear as described in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages can be used to implement the teachings of the disclosure as described herein.

[0082] The present disclosure can be provided as a computer program product, or software, that can include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic devices) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form accessible by a machine (e.g., a computer). In some embodiments, a machine- readable (e.g., computer-readable) medium includes a machine (e.g., a computer) readable storage medium, such as a read only memory (“ROM”), a random access memory (“RAM”), a magnetic disk storage medium, an optical storage medium, a flash memory device, etc.

[0083] In the foregoing specification, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be evident that various modifications can be made to the disclosure without departing from the broader spirit and scope of embodiments of the present disclosure as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.

Claims

1. An apparatus comprising: an array of memory cells; and control circuitry (100, 200) coupled to the array of memory cells and configured to: store a plurality of trim settings; receive signaling indicative of usage of the array of memory cells; and determine, based at least in part on the signaling, an adjustment to the plurality of trim settings; and the control circuitry (100, 200) comprises artificial intelligence, AI, circuitry (113), and the AI circuitry is configured to determine, based at least in part on the signaling and the determined adjustment to the plurality of trim settings, an adjustment to the plurality of trim settings.

2. The apparatus of claim 1, wherein the signaling is indicative of at least one of: a performance throughput of the array of memory cells; a number of write operations performed by the control circuitry (100, 200) during a particular time period; a type of data frequently written to the array of memory cells; and a number of data frequently written to the array of memory cells during respective write operations.

3. The apparatus of any one of claims 1-2, wherein the plurality of trim settings includes a read window budget, RWB, and wherein the control circuitry (100, 200) is further configured to determine, based at least in part on the signaling, an adjustment to the RWB.

4. The apparatus of any one of claims 1-2, wherein the plurality of trim settings are maintained in a trim table stored on the array of memory cells, and wherein the control circuitry (100, 200) is further configured to: retrieve the plurality of trim settings from the trim table; and update the trim table according to the determined adjustment to the plurality of trim settings.

5. The apparatus of any one of claims 1-2, wherein the signaling indicative of usage characteristics is indicative of a bit error rate, BER, of the array of memory cells, and wherein the control circuitry (100, 200) is further configured to determine the adjustment to the plurality of trim settings to reduce the BER.

6. A system comprising: a memory device (303) comprising: an array of memory cells; and control circuitry (330); and artificial intelligence, AI, circuitry hosted on a remote server (340) communicatively coupled to the memory device, wherein the AI circuitry is configured to: receive, from the memory device, first signaling indicative of a performance throughput of the array of memory cells; determine, corresponding to respective usage of a plurality of other memory devices, respective adjustments to a plurality of trim settings of the plurality of other memory devices; determine, based at least in part on the first signaling and the determined adjustments to the plurality of trim settings, an adjustment to a trim setting of the memory device; and provide, to the control circuitry, second signaling indicative of the determined adjustment to the trim setting.

7. The system of claim 6, wherein the control circuitry (330) is configured to: ​ monitoring the performance throughput of the array of memory cells; providing the first signaling to the AI circuitry based at least in part on the monitored performance throughput; and adjusting a read window budget, RWB, based on the second signaling received from the AI circuitry.

8. The system of any one of claims 6-7, wherein the AI circuitry is further configured to: receive third signaling from the plurality of other memory devices indicating respective performance throughputs of the plurality of other memory devices; and determine the respective adjustments to the plurality of trim settings based at least in part on the third signaling.

9. An apparatus comprising: an array of memory cells; and control circuitry (100, 460) coupled to the array of memory cells and configured to: receive signaling indicating an operating temperature of the array of memory cells; determine whether the operating temperature is greater than a first threshold operating temperature; determine whether the operating temperature is less than a second threshold operating temperature; and in response to determining that the operating temperature is greater than the first threshold operating temperature or less than the second threshold operating temperature, adjust a trim setting of the array of memory cells to improve performance of the array of memory cells.

10. The apparatus of claim 9, wherein the control circuitry (100, 460) is further configured to: determining whether the array of memory cells experienced a cross-temperature event, wherein the cross-temperature event includes the operating temperature changing by at least a threshold number of degrees within a particular amount of time; and in response to determining that the array of memory cells experienced the cross-temperature event: store occurrence data corresponding to the cross-temperature event; and immediately after experiencing the cross-temperature event, adjust the trim setting to improve performance of the array of memory cells, wherein the occurrence data indicates at least one of: a date on which the array of memory cells experienced the cross-temperature event; a time at which the array of memory cells experienced the cross-temperature event; and a location at which the array of memory cells experienced the cross-temperature event.

11. The apparatus of claim 10, wherein the occurrence data indicates a number of cross-temperature events experienced by the array of memory cells, and wherein the control circuitry (100, 460) is further configured to adjust the trim setting in response to the occurrence data indicating that the array of memory cells experienced at least a threshold number of cross-temperature events.

12. The apparatus of claim 10, wherein the control circuitry (100, 460) is further configured to: anticipate, based at least in part on the occurrence data, that the array of memory cells will experience another cross-temperature event; and prospectively adjust the trim setting prior to another cross-temperature event to improve the performance of the array of memory cells when experiencing another cross-temperature event.

13. The apparatus of claim 12, wherein the control circuitry (100, 460) is further configured to: determine, based at least in part on the occurrence data, an anticipated date, time, or location of another cross-temperature event; and adjust the trim setting at the anticipated time, date, or location.

14. The apparatus of any one of claims 9-10, wherein the first threshold operating temperature is a first degree less than a maximum operating temperature of the array of memory cells, and wherein the second threshold operating temperature is a second degree greater than a minimum operating temperature of the array of memory cells.

15. A method comprising: receiving (550), by control circuitry (100) of a memory device (119), signaling indicative of at least one of: a performance throughput of the memory device; an operating temperature of the memory device; and a type of data written to the memory device; and determining (552), based at least in part on the signaling, an adjustment to a tuning setting of the memory device; wherein the control circuitry (100, 200) comprises artificial intelligence, AI, circuitry (113), and the AI circuitry is configured to determine an adjustment to the tuning setting based at least in part on the signaling and the determined adjustment to the tuning setting.

16. The method of claim 15, wherein the signaling is further indicative of a date, time, or location of a previous increase in the performance throughput of the memory device (119) corresponding to the performance throughput of the memory device, and wherein the method further comprises: determining, based at least in part on the signaling, an expected date, time, or location of a subsequent increase in the performance throughput of the memory device; and applying the adjustment to the tuning setting to the memory device in advance of the expected date, time, or location of the subsequent increase in the performance throughput.

17. The method of claim 15, wherein the signaling is further indicative of a date, time, or location of a previous change in the operating temperature of the memory device (119) corresponding to the operating temperature of the memory device, and wherein the method further comprises: determining, based at least in part on the signaling, an expected date, time, or location of a subsequent significant change in the operating temperature of the memory device; and applying the adjustment to the tuning setting to the memory device in advance of the expected date, time, or location of the subsequent significant change in the operating temperature.

18. The method of claim 15, wherein the signaling is further indicative of a date, time, or location of a previous write of a particular type of data to the memory device (119) corresponding to the particular type of data, and wherein the method further comprises: determining, based at least in part on the signaling, an expected date, time, or location of a subsequent write of the particular type of data to the memory device; and applying the adjustment to the tuning setting to the memory device in advance of the expected date, time, or location of the subsequent write of the particular type of data to the memory device.

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