Memory device and method of manufacturing the same

Abstract

A memory device includes a substrate and a stack structure including first dielectric layers and electrode layers arranged alternately. In a first lateral direction, the memory device includes an intermediate region and an array region. In a second lateral direction, the stack structure includes a first block storage region and a second block storage region each including a wall structure region. In the intermediate region, the wall structure regions of the first block storage region and the second block storage region are separated by a staircase structure. The memory device further includes a beam structure located in the intermediate region and including at least a plurality of discrete first beam structures each extending along the second lateral direction and connecting the wall structure regions of the first block storage region and the second block storage region, and a plurality of second dielectric layers located in the beam structure. In the first beam structure, the second dielectric layers are alternating with the first dielectric layers.

Description

[0001] This application is a divisional application of the invention patent application filed on October 9, 2020, entitled "Storage Device and Manufacturing Method Thereof", with application number 202080002635.9. Technical Field

[0002] In general, this disclosure relates to the field of semiconductor manufacturing technology, and more specifically, to memory devices and methods of manufacturing them. Background Technology

[0003] With the development of planar flash memory, the manufacturing process of semiconductor electronic devices has made tremendous progress. However, in recent years, the continued development of planar flash memory has encountered many challenges, such as physical limitations, limitations of existing photolithography technology, and limitations of storage electron density. In this context, in order to solve the difficulties encountered by planar flash memory and to pursue lower production costs per storage cell, various three-dimensional (3D) flash memory structures, including 3D NOR and 3D NAND, have emerged.

[0004] In NOR-type 3D NAND flash memory, memory cells are arranged in parallel between bit lines and ground lines, while in NAND-type 3D NAND flash memory, memory cells are arranged serially between bit lines and ground lines. NAND flash memory with a serial structure has a lower read speed but higher write and erase speeds. Therefore, NAND flash memory is suitable for data storage. Furthermore, NAND flash memory exhibits many advantages for data storage, such as small cell size and large storage capacity.

[0005] A 3D NAND flash memory includes multiple memory array structures, each comprising multiple memory cells arranged in a 3D array. The 3D NAND flash memory further includes multiple ladder structures for creating electrical connections to the memory cells at different layers. In many designs, each ladder structure corresponds to one memory array structure and is located on one side of that memory array structure. All electrical connections from the ladder structures extend in the same direction to connect the memory array structures. As the number of stacked layers in the memory array structure increases, the resistance of the connections from the ladder structures to the memory array structures increases, causing RC delay problems. Therefore, the performance of the 3D NAND flash memory may be undesirable.

[0006] To reduce the length of the connections between the ladder structure and the corresponding memory cells, some designs arrange the ladder structure between two memory array structures, and the electrical connections from the ladder structure can extend in both directions to connect the memory array structures. Therefore, the total resistance of the connections can be low, and thus, RC delay issues can be suppressed. When a ladder structure is formed between two memory array structures, some electrical connections formed on the ladder structure need to pass through wall structures to connect to the two memory structures. However, as the number of stacked layers in 3D NAND flash memory increases, the height of the wall structures can increase, and therefore, wall structure collapse can become a problem for 3D NAND flash memory.

[0007] The disclosed storage devices and manufacturing methods are intended to solve one or more of the problems described above, as well as other problems in the art. Summary of the Invention

[0008] One aspect of this disclosure provides a memory device. The memory device includes: a substrate; and a stacked structure including a plurality of first dielectric layers and a plurality of electrode layers alternately disposed on the substrate. In a first lateral direction with respect to the substrate, the memory device includes an array region and an intermediate region disposed between the array regions. In a second lateral direction with respect to the substrate, the stacked structure includes a first memory region and a second memory region, each including a wall structure region. In the intermediate region, the wall structure regions of the first memory region and the second memory region are separated by a stepped structure. The memory device further includes: a bundle structure located in the intermediate region, and including at least a plurality of discrete first bundle structures, each extending along the second lateral direction and connecting the wall structure regions of the first memory region and the second memory region; and a plurality of second dielectric layers located in the bundle structure. In the plurality of discrete first bundle structures, the plurality of second dielectric layers alternate with the plurality of first dielectric layers.

[0009] Another aspect of this disclosure provides a method for forming a memory device. The method includes: forming a stacked structure comprising a plurality of first dielectric layers and a plurality of second dielectric layers alternately disposed on a substrate. In a first lateral direction relative to the substrate, the stacked structure is formed in an array region and an intermediate region disposed between the array regions. The method includes: forming a stepped structure and a plurality of discrete first bundle structures in the intermediate region. Each of the plurality of discrete first bundle structures extends along a second lateral direction relative to the substrate. The method further includes: forming a plurality of gate slots (GLSs) perpendicularly through the stacked structure and into the substrate, and extending along the first lateral direction. In the second lateral direction, the plurality of GLSs at least define a first memory region and a second memory region. The plurality of GLSs includes a GLS formed in each array region at the boundary between the first memory region and the second memory region. The method further includes: removing the plurality of second dielectric layers from the array region and partially from the intermediate region. After the plurality of second dielectric layers are removed from the array region and partially from the intermediate region, portions of the plurality of second dielectric layers remain in the plurality of discrete first bundle structures.

[0010] Other aspects of this disclosure will be understood by those skilled in the art based on the specification, claims, and drawings. Attached Figure Description

[0011] The following figures are merely illustrative examples based on various disclosed embodiments and are not intended to limit the scope of this disclosure.

[0012] Figure 1 A schematic diagram illustrating a 3D storage device having a stepped structure located at the edge of a chip storage area;

[0013] Figure 2 A schematic diagram illustrating another 3D storage device having a stepped structure located in the middle area of ​​the chip storage area;

[0014] Figure 3 A plan view of a 3D storage device with a stepped structure located at the center of the chip storage area is shown.

[0015] Figure 4 This explains the process along line A-A'. Figure 3 A cross-sectional view of the 3D storage device shown;

[0016] Figure 5 The image shows a front top perspective view of a stepped structure for a 3D storage device.

[0017] Figure 6-23A schematic diagram illustrating a semiconductor structure at a specific stage of an exemplary method according to various embodiments of the present disclosure;

[0018] Figure 24 A flowchart illustrating an exemplary method for forming a storage device according to various embodiments of the present disclosure is provided.

[0019] Figure 25-38 A schematic diagram illustrating a semiconductor structure at a specific stage of an exemplary method according to various embodiments of the present disclosure;

[0020] Figure 39 A flowchart illustrating an exemplary method for forming a storage device according to various embodiments of the present disclosure is provided.

[0021] Figure 40 A schematic top view illustrating an exemplary semiconductor structure according to various embodiments of this disclosure is shown; and

[0022] Figure 41 A schematic top view illustrating another exemplary semiconductor structure according to various embodiments of this disclosure is provided. Detailed Implementation

[0023] Exemplary embodiments of the invention will now be described in detail with reference to the accompanying drawings. Wherever possible, the same reference numerals will be used throughout the drawings to refer to the same or similar parts.

[0024] Although specific configurations and arrangements have been discussed, it should be understood that this is for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of this disclosure. It will be apparent to those skilled in the art that this disclosure can also be used in a variety of other applications.

[0025] It should be noted that references to "one embodiment," "an embodiment," "an example embodiment," "some embodiments," etc., in this specification indicate that the described embodiment may include a specific feature, structure, or characteristic, but each embodiment may not necessarily include that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Moreover, when a specific feature, structure, or characteristic is described in connection with an embodiment, those skilled in the art will understand that such a feature, structure, or characteristic arises in conjunction with other embodiments, whether or not explicitly described.

[0026] In general, terms can be understood at least in part based on their use in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least in part on the context, terms such as "a," "an," or "that" can again be understood to convey either singular or plural usage. Furthermore, again depending at least in part on the context, the term "based on" can be understood not necessarily to convey an exclusive set of factors, but rather to allow for the presence of additional factors that do not necessarily need to be explicitly described.

[0027] It should be obvious that the meanings of “above,” “on top of,” and “above” in this disclosure should be interpreted in the broadest possible sense, such that “above” means not only “directly on something,” but also “on something” with an intermediate feature or layer in between, and that “on top of” or “above” means not only “on something” or “above something,” but may also mean “on something” or “above something” without any intermediate feature or layer in between (i.e., directly on something).

[0028] Furthermore, for ease of description, spatial relative terms (such as "below," "under," "lower," "above," "higher," etc.) may be used herein to describe the relationship between one element or feature and another element(s) as illustrated in the accompanying drawings. In addition to the orientations depicted in the drawings, spatial relative terms are intended to also include different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 degrees or oriented in other orientations), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0029] As used herein, the term "substrate" refers to the material on which subsequent layers of material are added. The substrate itself can be imaged. The material added on top of the substrate can be imaged, or it can remain unimaged. Furthermore, the substrate can include a variety of semiconductor materials (such as silicon, germanium, gallium arsenide, indium phosphide, etc.). Alternatively, the substrate can be made of a non-conductive material (such as glass, plastic, or sapphire wafer).

[0030] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer may extend over the entire underlying or overlying structure, or may have a width less than that of the underlying or overlying structure. Further, a layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness less than that of the continuous structure. For example, a layer may lie between or between any pair of horizontal planes between or at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, and / or may have one or more layers above, on, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (in which interconnects and / or via contacts are formed) and one or more dielectric layers.

[0031] As used herein, the term "nominal / nominally" refers to the expected or target value of a characteristic or parameter of a component or process operation set during the design phase of a product or process, and the range of values ​​above and / or below the expected value. The range of values ​​may result from minor variations or tolerances during the manufacturing process. As used herein, the term "about" indicates a value of a given quantity that can be varied based on a specific technology node associated with the subject semiconductor device. Based on a specific technology node, the term "about" can indicate a value of a given quantity that can be varied, for example, within 10-30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0032] As used herein, the term "3D memory device" refers to a semiconductor device having strings (referred to herein as "memory strings," such as NAND memory strings) of vertically oriented memory cell transistors located on a laterally oriented substrate, such that the memory strings extend vertically with respect to the substrate. As used herein, the term "vertical" means nominally perpendicular to the lateral surface of the substrate.

[0033] In some 3D storage devices, memory cells for storing data are vertically stacked through a stacked memory structure (e.g., a memory stack layer). 3D storage devices typically include stepped structures formed on one or more sides (edges) of the stacked memory structure for purposes such as word line fan-out. Since the stepped structures are typically formed at the edges of each slice of memory, the memory cells are driven unilaterally by line decoders (also known as "x-decoders") that are also arranged at the edges of each slice of memory, through word lines and the corresponding stepped structures.

[0034] Figure 1 A schematic diagram illustrating a 3D memory device with a stepped structure located at the edge of a slice memory area is shown. (Reference) Figure 1The 3D memory device 100 (e.g., a 3D NAND memory device) includes two slice memory regions 102, each having an array of memory cells located in a memory array structure 106. It should be noted that in Figure 1 The X and Y axes are included to illustrate two orthogonal (perpendicular) directions in the wafer plane. The X direction is the word line direction of the 3D memory device 100, while the Y direction is the bit line direction of the 3D memory device 100. The 3D memory device 100 also includes two step structures 104 located on opposite sides of each memory array structure 106 in the X direction. Each word line of the chip memory region 102 extends laterally in the X direction across the entire chip memory region 102 to a respective step (level) in the step structure 104. Row decoders (not shown) are formed directly above, below, or near the respective step structures 104 to reduce interconnect length. That is, each row decoder drives half of the memory cell unilaterally (in the positive or negative X direction, but not in both directions) through half of the word line, and each of these word lines spans the entire chip memory region 102.

[0035] The load of a single-sided word line drive scheme therefore includes the resistance of the entire word line across the chip memory region 102. Furthermore, as the demand for higher storage capacity continues to grow, the number of vertical layers in stacked memory structures increases, and the thickness of the stacked layers (including the thin film of each word line) decreases. Therefore, high resistance may be introduced into the load, thus causing significant RC delay. Accordingly, the performance of the 3D memory device 100 (such as read and write speeds) may be affected by the single-sided word line drive scheme with the side-step structure 104.

[0036] To reduce RC latency, some other 3D memory devices employ a stepped structure between chip memory areas to implement a dual-sided word line driving scheme. By replacing the conventional side stepped structure with, for example, a central stepped structure, each line decoder can drive word lines dually in opposite directions starting from the center of the chip memory area. This reduces the resistance in the load by, for example, halving the length of the word lines driven by the line decoder. In some 3D memory devices, wall structures are introduced as part of the stepped structure to connect word lines separated by central / transition stepped structures. Furthermore, multi-partition stepped structures, where each step of the stepped structure includes multiple partitions for fan-out multiple word lines, are used to improve the utilization of the stepped structure and reduce manufacturing complexity. Additionally, multiple cutting processes are used to form multiple steps at different depths to reduce the number of trimming etching processes, thus further reducing manufacturing complexity and increasing yield. Furthermore, partitions are formed after the steps are formed to reduce the number of material layer pairs (e.g., silicon nitride and silicon dioxide pairs) in the stacked structure to be etched, thus reducing the thickness requirement of the hard mask covering the area outside the steps (e.g., wall structure).

[0037] Figure 2 A schematic diagram illustrates another 3D memory device with a stepped structure located in the middle area of ​​the chip memory region. (Reference) Figure 2 The 3D storage device 200 includes two chip storage areas 202. Each chip storage area 202 includes storage array structures 206-1 / 206-2 and an intermediate area. A stepped structure 204 formed in the intermediate area laterally divides the storage array structures 206-1 / 206-2 into a first storage array structure 206-1 and a second storage array structure 206-2 in the X direction (word line direction). That is, the stepped structure 204 is formed between the first storage array structure 206-1 and the second storage array structure 206-2. Unlike in which the stepped structure 104 is located on opposite sides of each storage array structure 106, this step structure 104 is not located on the opposite side of each storage array structure 106. Figure 1 The 3D memory device 100 shown in the diagram has each step structure 204 located between the first memory array structure 206-1 and the second memory array structure 206-2. (See also...) Figure 2 As shown, in some examples, for each slice of memory 202, the step structure 204 is located in the middle of the memory array structures 206-1 / 206-2. That is, the step structure 204 may be a central step structure that equally divides the memory array structures 206-1 / 206-2 into a first memory array structure 206-1 and a second memory array structure 206-2 with the same number of memory cells. For example, the first memory array structure 206-1 and the second memory array structure 206-2 may be symmetrical about the central step structure 204 in the X direction. It should be understood that in some other examples, the step structure 204 may not be located in the middle of the memory array structures 206-1 / 206-2 (i.e., at the exact center), so that the first memory array structure 206-1 and the second memory array structure 206-2 may have different sizes and / or different numbers of memory cells. In some examples, the 3D memory device 200 is a NAND flash memory device, in which memory cells are provided in the form of an array of NAND memory strings (not shown) in a first memory array structure 206-1 and a second memory array structure 206-2. The first memory array structure 206-1 and the second memory array structure 206-2 may include any other suitable components, including but not limited to gate gaps (GLS), through-array contacts (TAC), array common-source (ACS), etc.

[0038] Each word line (not shown) of the lateral, X-direction-extending chip memory region 202 is divided into two parts by a corresponding step structure 204: a first word line portion across a first memory array structure 206-1 and a second word line portion across a second memory array structure 206-2. As described in detail below, the two parts of each word line are electrically connected by wall structures (not shown) in the step structure 204 located at the respective steps of the step structure 204. Line decoders (not shown) are formed directly above, below, or near the respective step structures 204 to reduce interconnect length. Therefore, not used for Figure 1 The 3D memory device 100 shown in the figure has row decoders. Each row decoder of the 3D memory device 200 drives the memory cells in the first memory array structure 206-1 and the second memory array structure 206-2 bilaterally (in both the positive and negative X directions). That is, by replacing the conventional side stepped structure (e.g., in the middle of the memory array structure 206-1 / 206-2) with a stepped structure 204, for example, in the middle of the memory array structure 206-1 / 206-2. Figure 1 As shown in the stepped structure 104, each row decoder drives word lines on both sides in opposite directions, starting from the middle of the slice storage area 202, so that the resistance in the load can be reduced by reducing the length of the portion of each word line driven by the row decoder to, for example, half (when the stepped structure 204 is arranged in the middle of the storage array structure 206-1 / 206-2). That is, the row decoder of the 3D storage device 200 only needs to drive either the first word line portion or the second word line portion of each word line.

[0039] Figure 3 A plan view of a 3D memory device with a stepped structure located at the center of the chip storage area is shown, and Figure 4 This explains the process along line AA'. Figure 3 A cross-sectional view of the 3D storage device is shown in the image. (Reference) Figure 3-4 The spatial relationships of components in the 3D memory device 300 are illustrated using the X, Y, and Z axes. The 3D memory device 300 includes a substrate 350 and a stacked structure comprising multiple dielectric layers 321 and multiple sacrificial layers 322. The multiple dielectric layers 321 and multiple sacrificial layers 322 are arranged alternately. In the X direction, the 3D memory device 300 includes an intermediate region 301 located at the center of a chip memory region (not shown). The 3D memory device 200 may include a stepped structure 204 formed in the intermediate region of the chip memory region 202. Figure 2 An example of chip storage area 202 is shown, and the intermediate area 301 of the 3D storage device 300 may be an example corresponding to the intermediate area in chip storage area 202. As shown in Figure 3As shown, the 3D memory device 300 is divided in the Y direction (bit line direction) into multiple block memory regions 302 separated by multiple parallel GLS 308s. In some examples, the 3D memory device 300 is a NAND flash memory device, and accordingly, each block memory region 302 is the smallest erasable cell of the NAND flash memory device. Each block memory region 302 further includes multiple finger memory regions 304 separated in the Y direction by some GLS 308s having "H" cutouts 310. Each block memory region 302 also includes wall structure regions 306 that separate the block memory region 302 from adjacent block memory regions 302.

[0040] refer to Figure 3 The 3D storage device 300 also includes two array regions 303 separated by an intermediate region 301. Multiple top select gates (TSGs) can be formed in the array regions 303, and these TSGs can be electrically connected to interconnects in the intermediate region 301. As described in detail below, the intermediate region 301 includes multiple stepped regions, each corresponding to a respective pointer storage region 304, and also includes multiple wall structures (not labeled) corresponding to wall structure regions 306. That is, each wall structure is formed in the region overlapping the intermediate region 301 and the corresponding wall structure region 306. Therefore, the wall structures do not extend into any array region 303 along the X direction. The 3D storage device 300 includes multiple dummy channel structures 314 located in the intermediate region 301, which includes the stepped regions and wall structures, to provide mechanical support and / or load balancing. The 3D memory device 300 further includes a plurality of word line contacts 312 located in a stepped area of ​​the intermediate region 301, and each word line contact 312 reaches a separate word line (not shown) at each step in the intermediate region 301 for word line driving. The 3D memory device 300 may also include a plurality of channel structures 318 formed in two array regions 303.

[0041] To achieve a dual-sided word line driving scheme, each wall structure (physically and electrically) connects to a first memory array structure and a second memory array structure (not shown) respectively formed in two array regions 303. In the memory device, each word line is driven dual-sided (in both the positive and negative x directions) from the respective word line contacts 312 in the stepped area of ​​the intermediate region 301 at the center of the 3D memory device 300 via the wall structures. Figure 3 The current path of the dual-sided word line drive scheme with a wall structure is further illustrated schematically. The first current path, indicated by the solid arrow, and the second current path, indicated by the dashed arrow, represent the current passing through the two separate word lines at different levels.

[0042] Figure 5 This image illustrates a front top perspective view of the central region 400 of a 3D storage device. The central region 400 can be... Figure 2An example of the middle area of ​​the 3D storage device 200 shown, or possibly related to... Figure 3 This corresponds to the intermediate region 301 of the 3D memory device 300 shown in the figure. The intermediate region 400 includes a stacked structure 401 formed on a substrate (not shown).

[0043] exist Figure 5 In this document, the X, Y, and Z axes are used to illustrate the spatial relationships of components in the intermediate region 400. The substrate of the 3D memory device includes two lateral surfaces extending laterally in the XY plane: a top surface on the front side of the wafer on which a stepped structure is formed, and a bottom surface on the back side opposite the front side of the wafer. The Z axis is perpendicular to both the X and Y axes. As used herein, when the substrate is located in the lowest plane of the 3D memory device in the Z direction, whether a component (e.g., a layer or device) of the 3D memory device is "above," "above," or "below" another component (e.g., a layer or device) is determined relative to the substrate of the 3D memory device in the Z direction (a direction perpendicular to the XY plane).

[0044] The stack structure 401 includes a plurality of first material layers (not shown) and a plurality of second material layers (not shown) alternately stacked in the Z direction. The material used to form the plurality of first material layers is different from the material used to form the plurality of second material layers. That is, the stack structure 401 includes a plurality of material layer pairs stacked vertically in the Z direction, wherein each material layer pair includes one first material layer and one second material layer. The number of material layer pairs in the stack structure 401 (e.g., 32, 64, 96, 128, 160, 192, 224, or 256) determines the number of memory cells stacked in the Z direction.

[0045] For example, the 3D memory device is a NAND flash memory device, and the stacked structure 401 is a stacked memory structure through which NAND memory strings are formed. Each of the first material layers in the first material layer includes a conductor layer, and each of the second material layers in the second material layer includes a dielectric layer. That is, the stacked structure 401 includes interlaced conductor layers and dielectric layers (not shown). Further, each conductor layer serves as a gate line and a word line of the NAND memory string, the word line extending laterally from the gate line and ending at a stepped structure formed in the intermediate region 400 for word line fan-out.

[0046] Each step (as shown as a "level") of the stepped structure formed in the intermediate zone 400 comprises one or more pairs of material layers. Reference Figure 5The top material layer of each step is a conductive layer for interconnection in the vertical direction (Z direction), and every two adjacent steps of the stepped structure are offset by the same nominal distance in the Z direction and by the same nominal distance in the X direction. Each offset thus forms an "arrival area" for interconnection with the corresponding word line contacts (not shown) of the 3D storage device in the Z direction.

[0047] As in Figure 5 As shown, the intermediate zone 400 includes a first stepped zone 402, a second stepped zone 412, and a wall structure 404 located between the first stepped zone 402 and the second stepped zone 412 in the Y direction (word line direction). Each of the first stepped zone 402 and the second stepped zone 412 includes a stepped structure. The stepped structure of the first stepped zone 402 includes multiple pairs of steps in the X direction (word line direction), including a first pair of steps 406-1 and 406-2, a second pair of steps 410-1 and 410-2, a third pair of steps 414-1 and 414-2, and a fourth pair of steps 416-1 and 416-2. Each step (e.g., 406-1, 406-2, 410-1, 410-2, 414-1, 414-2, 416-1, or 416-2) includes multiple steps in the X direction. In addition, each step is the opposite of the virtual step, and is a functional step used to reach the interconnect (e.g., word line via contact).

[0048] Further, the first step area 402 includes three pointer storage areas located in the Y direction, and correspondingly, each step in 406-1, 406-2, 410-1, 410-2, 414-1, 414-2, 416-1, and 416-2 includes three partitions 408-1, 408-2, and 408-3 located in the Y direction. In step 406-2, each step in partition 408-2 is located below any step in partition 408-1 and above any step in partition 408-3.

[0049] Furthermore, at least one step in the steps of the first step region 402 or the second step region 412 is electrically connected to each item in the first and second memory array structures via the wall structure 404. For example, as in Figure 5 As shown, the steps in the staircase 410-2 can be electrically connected to both the first and second memory array structures via wall structure 404 through separate word line portions extending in the negative and positive X directions, as indicated by the current paths (represented by arrows).

[0050] refer to Figure 5As the number of material layer pairs in the stacked structure 401 increases, the steps exposing the bottom material layer pairs have a greater depth about the top of the wall structure 404. That is, the aspect ratio of the wall structure (the height in the Z direction and the width in the Y direction) is larger. Furthermore, the increase in the number of material layer pairs in the stacked structure 401 also leads to an increase in the length of the wall structure 404 along the X direction. Further, referring to… Figure 3-4 In the manufacturing process of 3D storage devices, multiple GLSs can be fabricated after the steps are formed. For example, refer to... Figure 3 To separate adjacent stepped regions, a GLS needs to be formed that runs through the entire wall structure in the X direction. However, due to the wall structure's large aspect ratio and length, the wall structure may easily collapse when forming a GLS that traverses its entire length. Therefore, the performance of the 3D storage device may be undesirable.

[0051] This disclosure provides a method for forming a storage device. According to the disclosed method, the formed stepped structure includes a plurality of sub-stepped structures, and adjacent sub-stepped structures are separated from each other by a first bundle structure connected to the wall structure along the length direction of the wall structure. The first bundle structure provides mechanical support to the wall structure, thus preventing the wall structure from collapsing during the formation of the GLS passing through the wall structure. Furthermore, for adjacent block storage areas where memory regions are disposed between their wall structure regions, the GLS formed between the two block storage areas is truncated in an intermediate region by two first isolation structures formed on both sides of the intermediate region. In the intermediate region spanning the two block storage areas, a second bundle structure connects the first isolation structures formed on each side of the intermediate region. In the second bundle structure, after the second dielectric layer is removed from the array region, portions of the second dielectric layer are retained between adjacent first dielectric layers. Therefore, the second dielectric layer and the first dielectric layer located in the second bundle structure not only provide mechanical support for subsequent manufacturing processes but also provide electrical isolation between the two block storage areas. In addition, after the second dielectric layer is removed from the array region, at least a portion of the second dielectric layer remains in each first bundle structure, which also provides mechanical support for the subsequent manufacturing process.

[0052] Figure 24 A flowchart illustrating an exemplary method for forming a storage device according to various embodiments of the present disclosure is provided. Figure 6-23 A schematic diagram illustrating the semiconductor structure at a specific stage of this exemplary method is shown.

[0053] refer to Figure 24A stacked structure comprising a plurality of first dielectric layers and a plurality of second dielectric layers alternately arranged on a substrate can be formed; in a first lateral direction about the substrate, the stacked structure may include two array regions and an intermediate region arranged between the array regions; in a second lateral direction about the substrate, the stacked structure may be divided into a plurality of block storage regions, wherein each block storage region includes a wall structure region and a plurality of finger storage regions arranged on one side of the wall structure region; and adjacent block storage regions may allow the wall structure region to be configured between the finger storage regions of one block storage region and the finger storage regions of another block storage region, or allow the finger storage regions of all two block storage regions to be configured between the wall structure regions (S601). Figure 6-7 A schematic diagram illustrating an exemplary semiconductor structure according to various embodiments of the present disclosure is provided. Specifically, Figure 6 A schematic planar diagram illustrating the semiconductor structure is provided. Figure 7 This explains the process along line B-B'. Figure 6 The diagram shows a schematic cross-sectional view of the semiconductor structure.

[0054] refer to Figure 6-7 A stacked structure comprising multiple first dielectric layers 521 and multiple second dielectric layers 522 can be formed on the substrate 550. Multiple second dielectric layers 522 and multiple first dielectric layers 521 can be alternately arranged on the substrate 550. Figure 6-7 In this disclosure, the X, Y, and Z axes are used to illustrate the spatial relationships of components in a semiconductor structure. The same concepts used to describe spatial relationships are applied throughout this disclosure. In a first lateral direction (e.g., the X direction), the stacked structure may include two array regions 503 and an intermediate region 501 disposed between the two array regions 503. In a second lateral direction (Y direction), the stacked structure may be divided into multiple block memory regions 502. In one embodiment, each block memory region 502 may be used to form an erase cell of a 3D NAND flash memory. Further, in the Y direction, each block memory region 502 may include multiple pointer memory regions 504 and wall structure regions 506.

[0055] Furthermore, in the plurality of block storage areas 502, adjacent block storage areas 502 may have their wall structure areas 506 adjacent to each other so that a wall structure can be formed in the intermediate area 501 of the boundary between the two block storage areas 502, or the pointer storage areas 504 of the two block storage areas 502 may be configured between the wall structure areas 506. For example, along the Y direction, the plurality of block storage areas 502 may include block storage areas 5021, 5022, 5023 and 5024 arranged successively along the Y direction. Block storage areas 5021 and 5022 can be connected to each other using multiple pointer storage areas 504 of block storage area 5021 adjacent to multiple pointer storage areas 504 of block storage area 5022; block storage areas 5022 and 5023 can be connected to each other using a wall structure area 506 of block storage area 5022 adjacent to a wall structure area 506 of block storage area 5023; and block storage areas 5023 and 5024 can be connected to each other using multiple pointer storage areas 504 of block storage area 5024 adjacent to multiple pointer storage areas 504 of block storage area 5024. It should be noted that, for illustrative purposes, in Figure 6 The diagram shows four block memory regions 502 (block memory region 5021, block memory region 5022, block memory region 5023, and block memory region 5024). However, in practical applications, the semiconductor structure may include at least two block memory regions where the pointer memory regions of two block memory regions are configured between the wall structure regions. It should also be noted that in... Figure 6 Only the portion of each array region 503 adjacent to the middle region 501 is shown.

[0056] In the subsequent manufacturing process, multiple memory cells (e.g., a memory array structure) can be formed in each array region 503. Furthermore, a stepped structure can be formed in the intermediate region 501 between adjacent block memory regions 502, where the memory regions 504 spanning two block memory regions 502 are configured between wall structure regions 506. Correspondingly, wall structures can be simultaneously formed in the intermediate region 501 between adjacent block memory regions 502 that are immediately adjacent to each other across the wall structure regions 506.

[0057] In one embodiment, the substrate 550 may be made of silicon, germanium, silicon-germanium, or any other suitable semiconductor material. In other embodiments, the substrate may be made of silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable semiconductor composite material.

[0058] In one embodiment, the plurality of first dielectric layers 521 may be made of oxide (e.g., silicon dioxide), and the plurality of second dielectric layers 522 may be made of nitride (e.g., silicon nitride). Therefore, the stacked structure may be a nitrogen-oxygen (NO) stacked structure comprising a plurality of NO stacked layers.

[0059] Furthermore, returning to Figure 24 A first isolation structure can be formed on each side of the intermediate area between the two block storage areas where the pointer storage areas of the two block storage areas are configured between the wall structure areas; a step structure can be formed from the stack structure in the intermediate area of ​​the multiple pointer storage areas of the two block storage areas; along the first lateral direction, the step structure can include multiple sub-step structures separated from each other by a first bundle structure, the first bundle structure extending along the second lateral direction and connected to the wall structure areas of the two block storage areas; within each block storage area, and along the second lateral direction, the sub-step structure can include multiple rows of sub-steps formed in the multiple pointer storage areas (S602). Figure 8-11 A schematic diagram illustrating an exemplary semiconductor structure according to various embodiments of the present disclosure is provided. Specifically, Figure 8 A schematic planar diagram illustrating the semiconductor structure is shown. Figure 9 This explains the process along line D-D'. Figure 8 The schematic cross-sectional view of the semiconductor structure shown in the figure is as follows. Figure 10 This explains the process along line C-C'. Figure 8 A schematic cross-sectional view of the semiconductor structure shown in the figure, and Figure 11 This explains the process along line B-B'. Figure 8 The diagram shows a schematic cross-sectional view of the semiconductor structure.

[0060] refer to Figure 8-11 Between the plurality of finger storage areas 504 and two block storage areas 502 that are in contact with each other (e.g., between block storage areas 5021 and 5022, and between block storage areas 5023 and 5024, respectively), a first isolation structure 516 passing through the stacked structure can be formed on each side of the intermediate region 501. Furthermore, a stepped structure (not labeled) can be formed from the stacked structure in the intermediate region 501 of the plurality of finger storage areas 504 of the two block storage areas 502; along the X direction, the stepped structure may include a plurality of sub-stepped structures 520, and adjacent sub-stepped structures 520 may be spaced apart from each other by a first bundle structure 518 extending along the Y direction. The first bundle structure 518 may be connected to the wall structure region 506 of each block storage area 520. In one embodiment, the width of each first bundle structure 518 in the X direction may be L0.

[0061] In one embodiment, within each block memory area 502, the sub-staircase structure 520 may include multiple rows of sub-steps (not shown) extending in the Y direction. In a subsequent process, word line contacts 512 may be formed on the sub-steps formed in the staircase structure. For example, word line contacts 512 may be formed in each finger memory area 504 to electrically connect the sub-steps formed in the finger memory area 504. It should be noted that the word line contacts 512 may be formed in a subsequent process, and Figure 8 The circles in the middle and Figure 10 The dotted plugs in the diagram are only intended to schematically indicate the expected locations for forming word line contacts 512 in subsequent processes. It should also be noted that portions of the second dielectric layer 522 located longitudinally below each expected word line contact 512 may be replaced with electrode layers in subsequent processes to establish an electrical connection with the corresponding word line contact 512.

[0062] refer to Figure 8-9 A first isolation structure 516, formed along the D-D' line in the array region 503 near the middle region 501, can penetrate the stacked structure, allowing multiple pointer storage regions 504 to contact each other with block storage regions 502. (See reference...) Figure 8 and 10 Along the C-C' line parallel to the Y direction and cutting off the sub-step structure 520, word line contacts 512 can be formed in each finger storage area 504 in a subsequent process to electrically connect the corresponding step. Additionally, after forming the step structure including multiple sub-step structures 520, a wall structure (not labeled) extending in the X direction can be simultaneously formed in the intermediate area 501 between the wall structure area 506 and adjacent block storage areas 502 that contact each other. Therefore, the wall structure in the Y direction (refer to...) Figure 10 The width of ) is approximately the total width of two adjacent wall structure zones 506. (Reference) Figure 8 and 11 By arranging the B-B' line of the first bundle structure 518 parallel to the Y direction and cutting off the adjacent sub-step structures 520, the stacked structure can remain unchanged after forming the first isolation structure 516 and the step structure. Therefore, the first bundle structure 518 extending along the Y direction prevents the wall structure from having a narrow width (approximately the total width of the two wall structure regions 506) along the path from one side of the intermediate region 501 to the other side. Thus, the wall structure is less prone to collapse when manufacturing the GLS that passes through the wall structure along the X direction.

[0063] For each pair of block memory regions 502 that bring multiple memory regions 504 into contact with each other, a first isolation structure 516 formed on each side of the intermediate region 501 can be used to protect the central portion of the second dielectric layer 522 in the stepped structure between the two block memory regions 502, so that when the second dielectric layer 522 is replaced with a metal electrode layer in a subsequent process, the central portion of the second dielectric layer 522 in the stepped structure between the two block memory regions 502 can be retained without removal. The remaining central portion of the second dielectric layer 522 (which may be made of nitride) in the stepped structure between the two block memory regions 502 and the first dielectric layer 521 (which may be made of oxide) can provide not only mechanical support for subsequent manufacturing processes but also electrical isolation for the two block memory regions 502 formed in the storage device.

[0064] In one embodiment, the first isolation structure 516 may have a rectangular shape. The dimension of the first isolation structure 516 in the X direction may be larger than its dimension in the Y direction. For example, the dimension of the first isolation structure 516 in the Y direction may be in the range of approximately 10 nm to 40 nm. The dimension of the first isolation structure 516 in the Y direction may not be too large, otherwise the process of filling the corresponding gaps to form the first isolation structure 516 may take more time and use more material. The dimension of the first isolation structure 516 in the Y direction may not be too small, otherwise the first isolation structure 516 may not be able to provide sufficient protection for the central portion of the second dielectric layer 522 in the stepped structure between the two block memory regions 502 during subsequent etching processes. Furthermore, the dimension of the first isolation structure 516 in the X direction may be greater than half the dimension of the finger memory region 504 in the Y direction. Additionally, the dimension of each finger memory region 504 in the Y direction may be approximately the same as the dimension of the wall structure region 506 in the Y direction. In other embodiments, the first isolation structure may have any other suitable shape.

[0065] In one embodiment, a portion of the first isolation structure 516 formed in the array region 503 may be significantly larger than the portion of the first isolation structure 516 formed in the intermediate region 501. For example, the entire first isolation structure 516 may be formed in the array region 503 with an edge overlapping the boundary between the array region 503 and the intermediate region 501, or the portion of the first isolation structure 516 formed in the array region 503 may be twice as large as the portion of the first isolation structure 516 formed in the intermediate region 501. In other embodiments, the portion of the first isolation structure formed in the array region may be equal to or smaller than the portion of the first isolation structure formed in the wall structure region.

[0066] The first isolation structure 516 may be made of an insulating material (e.g., silicon dioxide). It should be noted that when the second dielectric layer 522 is removed during a subsequent etching process, the etching rate of the material used to form the first isolation structure 516 may be significantly lower than the etching rate of the material used to form the second dielectric layer 522.

[0067] refer to Figure 8 In a stepped structure formed by multiple memory regions 502 that are in contact with each other, the region near the boundary between two memory regions 502 is called the second bundle structure 519. In a subsequent process, after partially replacing the second dielectric layer 522 in the stepped structure with an electrode layer, the second dielectric layer 522 (refer to...) Figure 10 A portion of this can be retained in the second bundle structure 519 to provide mechanical support for the material layer and electrical isolation for the two block storage areas 502. It should be noted that in Figure 8 In the diagram, the rectangular regions connecting the first isolation structures 516 formed on each side of the intermediate region 501 are used to schematically indicate the location of the second bundle structure 519. In practical applications, after partially removing multiple second dielectric layers 522 from the intermediate region, the remaining portion of the second dielectric layer in each sub-step structure 520 can have the same characteristics as... Figure 8 The rectangles shown have different shapes. Additionally, as in... Figure 10 As shown, because sub-steps are formed in each sub-step structure 520, the top layer of the first dielectric layer 521 located at the boundary between block storage areas 5021 and 5022, or between block storage areas 5023 and 5024, can be lower than the top surface of the initially formed stacked structure. Therefore, the top surface of the second bundle structure 519 can be lower than the top surface of the first bundle structure 518. Figure 8 In the schematic top view shown, since the first bundle structure 518 and the second bundle structure 519 have different heights, the second bundle structure 519 is shown as a discrete part cut by multiple first bundle structures 518.

[0068] Furthermore, returning to Figure 24 Multiple gate slots (GLS) extending in a first lateral direction can be formed at the boundary of each finger storage area and each wall structure area of ​​the block storage area, and each GLS formed between the multiple finger storage areas and the adjacent block storage areas that are in contact with each other can be truncated in the middle area by two first isolation structures formed on both sides of the middle area (S603). Figure 12-15 A schematic diagram illustrating an exemplary semiconductor structure according to various embodiments of the present disclosure is provided. Specifically, Figure 12 A schematic planar diagram illustrating the semiconductor structure is shown. Figure 13 This explains the process along line D-D'. Figure 12 The schematic cross-sectional view of the semiconductor structure shown in the figure is as follows. Figure 14 This explains the process along line C-C'. Figure 12 A schematic cross-sectional view of the semiconductor structure shown in the figure, and Figure 15 This explains the process along line B-B'. Figure 12 The diagram shows a schematic cross-sectional view of the semiconductor structure.

[0069] refer to Figure 12-15 Multiple GLS 508s extending in the X direction can be formed perpendicularly through the stacked structure and at the boundaries of each finger storage area 504 and each wall structure area 506 of the multiple block storage areas 502. The GLS 508s (also referred to as second separators) formed between the wall structure areas 506 and adjacent block storage areas 502 that are in contact with each other can extend through the array area 503 and the intermediate area 501, and thus can electrically separate two adjacent block storage areas 502. For example, refer to... Figure 12 The GLS 508, formed between the second storage area 5022 and the third storage area 5023, can extend along the X direction through the entire stack structure.

[0070] A GLS 508 (also referred to as a first partition structure) formed between multiple pointer storage areas 504 and adjacent block storage areas 502 that are in contact with each other can be confined within two array regions 503. That is, at each side of the intermediate region 501, the GLS 508 formed between the multiple pointer storage areas 504 and two block storage areas 502 that are in contact with each other can be connected to a corresponding first partition structure 516, and therefore, the GLS 508 (e.g., the first partition structure) does not need to extend into the intermediate region 501. For example, refer to Figure 12 Between the first storage area 5021 and the second storage area 5022 or between the third storage area 5023 and the fourth storage area 5024, each GLS 508 can only be formed in the array area 503 on one side of the intermediate area 501, and can be connected to (or terminated by) the first isolation structure 516 formed on the same side of the intermediate area 501.

[0071] Furthermore, within each block storage area 502 (including the first block storage area 5021, the second block storage area 5022, the third block storage area 5023, and the fourth block storage area 5024), GLS 508 may also be formed between adjacent finger storage areas 504 and between the wall structure area 506 and adjacent finger storage areas 504. For example, each GLS 508 formed between the wall structure area 506 and adjacent finger storage areas 504 may also be referred to as a third partition structure, and each GLS 508 formed between adjacent finger storage areas 504 may also be referred to as a fourth partition structure. It should be noted that within each block storage area 502, the GLS 508 formed in the intermediate area 501 may not be precisely located between adjacent finger storage areas 504 or at the boundary between the wall structure area 506 and adjacent finger storage areas 504; additionally, the formed GLS 508 may not extend into the first bundle structure 518 in the X direction. For example, a GLS 508 can be formed at the edge of the sub-staircase structure 520, and the length of the GLS 508 can be less than the width of the sub-staircase structure 520 in the X direction. Similarly, a GLS 508 can be formed in the sub-staircase structure 520 between adjacent memory areas 504, and the length of the GLS 508 can be less than the width of the sub-staircase structure 520 in the X direction. It should also be noted that within each block memory area 502, the GLS 508 formed in the array area 503 can extend along the X direction through the entire array area 503.

[0072] refer to Figure 12-13 Along the D-D' line in the array region 503 near the middle region 501, a GLS 508 can be formed at the boundary between the wall structure region 506 and the adjacent block storage regions 502 that are in contact with each other, passing through the stacked structure. (Reference) Figure 12 and 14 Along the C-C' line parallel to the Y direction and cutting off the sub-step structure 520, in addition to the GLS 508 formed at the boundary between the wall structure region 506 and two block storage regions 502 that are in contact with each other, a GLS 508 can also be formed within each block storage region 502 to separate the multiple finger storage regions 504 and the wall structure region 506. It should be noted that in the intermediate region 501, the GLS 508 may not be formed at the boundary between the multiple finger storage regions 504 and adjacent block storage regions 502 that are in contact with each other. (See reference...) Figure 12 and 15 Along the B-B' line parallel to the Y direction and cutting off the first bundle of structures 518 between adjacent sub-step structures 520, a GLS 508 through the stacked structure can be formed at the boundary between the wall structure area 506 and the adjacent block storage areas 502 that are in contact with each other.

[0073] Multiple GLS 508s can serve as process references for replacing multiple second dielectric layers 522 in the array region 503 and the stepped structure during subsequent processes. In one embodiment, GLS 508s can be formed in only two array regions 503 at the boundary between multiple pointer memory regions 504 and adjacent block memory regions 502 that are in contact with each other (see reference). Figure 12 and Figure 14 Furthermore, during the subsequent removal of multiple second dielectric layers 522 from array region 503, the first isolation structure 516 formed on both sides of intermediate region 501 can provide protection for the central portion of the second dielectric layer 522 in intermediate region 501 adjacent to the boundary between the two block memory regions 502. Therefore, after the removal of the second dielectric layer 522 from array region 503, the central portion of the second dielectric layer 522 (located in the second bundle structure 519) can remain in intermediate region 501 between the two block memory regions 502 that bring multiple finger memory regions into contact with each other. Thus, the remaining central portion of the second dielectric layer 522 in intermediate region 501 between the two block memory regions 502 can provide the necessary mechanical support and electrical isolation for subsequently formed memory devices. Additionally, the etching process can also remove portions of the second dielectric layer 522 located longitudinally below the intended word line contacts 512.

[0074] For example, refer to Figure 12 The distance from point E, located in the intermediate region 501 and at the boundary between the plurality of finger memory areas 504 and two block memory areas 502 (e.g., a third block memory area 5023 and a fourth block memory area 5024) that are in contact with each other, to the nearest GLS 508 can be L1, while the distance from the location of the word line contact 512 to be formed to the nearest GLS 508 can be L3. To ensure that the central portion of the second dielectric layer 522 in the intermediate region 501 between the two block memory areas 502 is retained after removing a portion of the second dielectric layer 522 located longitudinally below the intended word line contact 512, L1 can always be greater than L3. That is, the shortest distance from the point located in the intermediate region 501 and at the boundary between the plurality of finger memory areas 504 and two block memory areas 502 that are in contact with each other to the nearest GLS 508 can be greater than the longest distance from the location of the word line contact 512 to the nearest GLS 508. Similarly, in order to ensure that the central portion of the second dielectric layer 522 in the intermediate region 501 between the two block storage regions 502 is retained after a portion of the second dielectric layer 522 in the array region 503 is removed, the shortest distance from the point located in the intermediate region 501 and at the boundary between the two block storage regions 502 that make the plurality of finger storage regions 504 contact each other to the nearest GLS 508 can be greater than the longest distance from the point located in the array region 503 to the nearest GLS 508.

[0075] Furthermore, after removing a portion of the second dielectric layer 522 located longitudinally below the intended word line contact 512, at least a portion of the second dielectric layer 522 in the first bundle structure 518 can be retained. Therefore, the removed portion of the second dielectric layer 522, along with the plurality of first dielectric layers 521, can provide mechanical support for the material structure in the intermediate region 501. For example, refer to... Figure 12 The distance from point F in the first bundle structure 518 to the nearest GLS 508 can be L2, and to ensure that at least a portion of the second dielectric layer 522 in the first bundle structure 518 is retained after removing the portion of the second dielectric layer 522 located below the intended word line contact 512 in the longitudinal direction, the maximum value of L2 can be greater than the maximum value of L3. That is, the longest distance from a point in the first bundle structure 518 to the nearest GLS 508 can be longer than the longest distance from the location of the word line contact 512 to be formed to the nearest GLS 508. Therefore, by appropriately selecting the etching time, at least a portion of the second dielectric layer 522 in the first bundle structure 518 is retained after removing the portion of the second dielectric layer 522 located below the intended word line contact 512 in the longitudinal direction. Similarly, in order to ensure that at least a portion of the second dielectric layer 522 in the first bundle structure 518 is retained after a portion of the second dielectric layer 522 in the array region 503 is removed, the longest distance from a point in the first bundle structure 518 to the nearest GLS 508 can be longer than the longest distance from a point in the array region 503 to the nearest GLS 508.

[0076] In addition, refer to Figure 12 In the X direction, the GLS 508 formed in each sub-step structure 520 between adjacent finger storage regions 504 or between wall structure regions 506 and finger storage regions 504 can be equal to or shorter than the size of the sub-step structure 520. Therefore, in the X direction, the distance L0' between GLS 508 can be equal to or greater than the distance L0 between sub-step structures 520. That is, in the X direction, the length of each GLS 508 formed in the sub-step structure 520 can be equal to or less than the width of the sub-step structure 520. Therefore, when removing the second dielectric layer 522, a smaller portion of the second dielectric layer 522 in the first bundle structure 518 can be removed, thus helping to retain at least a portion of the second dielectric layer 522 in the first bundle structure 518 after the etching process.

[0077] Furthermore, returning to Figure 24Multiple second dielectric layers can be removed from the array region and partially from the intermediate region. After removing multiple second dielectric layers from the array region and partially from the intermediate region, the central portion of the second dielectric layer located in the intermediate region spanning the multiple pointer memory regions and adjacent block memory regions in contact with each other can be retained, and at least a portion of the second dielectric layer located in each first bundle structure can also be retained (S604). Figure 16-19 Schematic cross-sectional views illustrating semiconductor structures consistent with various embodiments of this disclosure are provided. Specifically, Figure 16 The cross-sectional view shown is from Figure 13 It is derived from the cross-sectional view shown in the figure. Figure 17 The cross-sectional view shown is from Figure 14 The cross-sectional view shown in the figure is derived from, and Figure 18-19 The cross-sectional view shown is from Figure 15 Two examples derived from the cross-sectional views shown are illustrated. It should be noted that, since the second dielectric layer is initially located between adjacent first dielectric layers, the planar view of the semiconductor structure remains consistent after the second dielectric layer is removed from the array region and partially from the intermediate region. Figure 12 The plane shown in Figure 1 That is, Figure 12 A schematic plan view of the semiconductor structure after removing the second dielectric layer from the array region and the stepped structure is also provided.

[0078] refer to Figure 12 and 16 -19, multiple second dielectric layers 522 can be removed from array region 503 and partially from intermediate region 501. Because Figure 16 A schematic cross-sectional view of the semiconductor structure along the D-D' line located in array region 503 is shown, so that the multiple second dielectric layers 522 at the cross-sectional view are completely removed. (As shown in...) Figure 17 As shown, the central portion of a plurality of second dielectric layers 522 spanning the boundary between a plurality of finger memory regions 504 and two block memory regions 502 in contact with each other can be retained in the semiconductor structure. (As shown in...) Figure 18 As shown in the diagram, in one embodiment, portions of a plurality of second dielectric layers 522 may be retained within the first bundle structure 518, and each second dielectric layer 522 may continue to extend across two block memory regions 502 that bring the plurality of pointer memory regions 504 into contact with each other. Figure 19As shown in other embodiments, the remaining portion of each second dielectric layer 522 may include multiple discrete sub-parts, and the multiple second dielectric layers 522 and the multiple first dielectric layers 521 may form multiple vertical pillars, which may further provide mechanical support for subsequent manufacturing processes. It should be noted that whether the remaining portion of each second dielectric layer 522 is a continuous thin film layer located between two first dielectric layers 521 or a discrete island depends on the pattern designed for GLS 508; this disclosure only requires that at least a portion of the second dielectric layer 522 be retained in each first bundle structure 518 to provide sufficient mechanical support for the semiconductor structure.

[0079] Furthermore, returning to Figure 24 Multiple electrode layers can be formed in the blank space between adjacent first dielectric layers (S605). Figure 20-23 Schematic cross-sectional views illustrating semiconductor structures consistent with various embodiments of this disclosure are provided. Specifically, Figure 20 The cross-sectional view shown is from Figure 16 It is derived from the cross-sectional view shown in the figure. Figure 21 The cross-sectional view shown is from Figure 17 The cross-sectional view shown in the figure is derived from, and Figure 22 and 23 The cross-sectional views shown are respectively from Figure 18 and 19 The cross-sectional views shown are two examples derived from this. It should be noted that, because the electrode layers are formed between adjacent first dielectric layers, the planar view of the semiconductor structure remains consistent after multiple electrode layers have been formed. Figure 12 The plane shown in Figure 1 That is, Figure 12 A schematic plan view of a semiconductor structure is also provided after multiple electrode layers are formed in the blank space between adjacent first dielectric layers.

[0080] refer to Figure 12 and 20 -23, multiple electrode layers 531 can be formed in the blank space between adjacent first dielectric layers 521. Therefore, multiple second dielectric layers 522 formed in array region 503 can be replaced by multiple electrode layers 531 (see reference). Figure 13 ), and portions of the second dielectric layer 522 can be replaced by multiple electrode layers 531 (see reference). Figure 14-15 In one embodiment, the plurality of electrode layers 531 may be made of tungsten.

[0081] In one embodiment, for two block storage regions 502 (e.g., second block storage region 5022 and third block storage region 5023) that make the wall structure region 506 contact each other, a portion of the electrode layer 531 formed in one block storage region 502 (e.g., second block storage region 5022) can be isolated from a portion of the electrode layer 531 formed in the other block storage region 502 (e.g., third block storage region 5023) by passing through the GLS 508 formed by the stacked structure. For multiple memory regions 504 that are in contact with adjacent block memory regions 502 (e.g., first block memory region 5021 and second block memory region 5022, or third block memory region 5023 and fourth block memory region 5024), a first isolation structure 516 is formed on each side of the intermediate region 501. A GLS 508 is formed in the array region 503 and connected to the first isolation structure 516. The remaining central portion of the second dielectric layer 522 in the intermediate region 501 across the two block memory regions 502 can electrically isolate a portion of the electrode layer 531 formed in one block memory region 502 (e.g., first block memory region 5021 or third block memory region 5023) from a portion of the electrode layer 531 formed in the other block memory region 502 (e.g., second block memory region 5022 or fourth block memory region 5024).

[0082] Furthermore, after forming multiple electrode layers 531, multiple word line contacts 512 can be formed in the intermediate region 501 to electrically connect to the sub-steps formed in the sub-step structure. Additionally, multiple channel structures (not shown) can be formed in the array region.

[0083] According to the disclosed method, the formed stepped structure includes multiple sub-stepped structures, and along the length of the wall structure, adjacent sub-stepped structures are separated from each other by a first bundle structure connected to the wall structure. The first bundle structure provides mechanical support to the wall structure, thus preventing the wall structure from collapsing during the formation of the GLS passing through the wall structure. Furthermore, for adjacent block memory areas where memory regions are configured between their wall structure regions, the GLS formed between the two block memory areas is truncated in the intermediate region by two first isolation structures formed on both sides of the intermediate region. In the intermediate region spanning the two block memory areas, a second bundle structure connects the first isolation structures formed on each side of the intermediate region. In the second bundle structure, after the second dielectric layer is removed from the array region, a portion of the second dielectric layer is retained between adjacent first dielectric layers. Therefore, the second dielectric layer and the first dielectric layer located in the second bundle structure not only provide mechanical support for subsequent manufacturing processes but also provide electrical isolation for the two block memory areas. Additionally, after the second dielectric layer is removed from the array region, at least a portion of the second dielectric layer is retained in each first bundle structure, which also provides mechanical support for subsequent manufacturing processes.

[0084] This disclosure also provides another method for forming storage devices. Figure 39 A flowchart illustrating an exemplary method for forming a storage device according to various embodiments of the present disclosure is provided. Figure 25-38 A schematic diagram illustrating the semiconductor structure at a specific stage of this exemplary method is shown.

[0085] refer to Figure 39 A stacked structure comprising a plurality of first dielectric layers and a plurality of second dielectric layers alternately arranged on a substrate can be formed; in a first lateral direction about the substrate, the stacked structure may include two array regions and an intermediate region arranged between the two array regions; in a second lateral direction about the substrate, the stacked structure may be divided into a plurality of block storage regions, wherein each block storage region includes a plurality of finger storage regions and a wall structure region that separates the block storage region from adjacent block storage regions; and adjacent block storage regions may make the wall structure regions of the two block storage regions contact each other or make the plurality of finger storage regions of the two block storage regions contact each other (S701).

[0086] The formation of the stacked structure on the substrate can be substantially the same as that described in the embodiments provided above. For details on the formation of the stacked structure and the definition of the multiple block storage areas, array areas and intermediate areas, please refer to the corresponding descriptions in the embodiments provided above.

[0087] Furthermore, returning to Figure 39 A first isolation structure can be formed through the stacked structure on each side of the intermediate area between the two block storage areas where the pointer storage areas of the two block storage areas are configured between the wall structure areas; a stepped structure can be formed from the stacked structure in the intermediate area of ​​the multiple pointer storage areas of the two block storage areas; along the first lateral direction, the stepped structure can include a first bundle structure and multiple sub-step structures spaced apart from each other by means of a first bundle structure extending along the second lateral direction and connected to the wall structure areas of the two block storage areas; within each block storage area, and along the second lateral direction, the sub-step structure can include a single row of sub-steps formed in the pointer storage area adjacent to the wall structure area (S702). Figure 25-28 A schematic diagram illustrating an exemplary semiconductor structure according to various embodiments of the present disclosure is provided. Specifically, Figure 25 A schematic planar diagram illustrating the semiconductor structure is shown. Figure 26 This explains the process along line D-D'. Figure 25 The schematic cross-sectional view of the semiconductor structure shown in the figure is as follows. Figure 27 This explains the process along line C-C'. Figure 25 A schematic cross-sectional view of the semiconductor structure shown in the figure, and Figure 28 This explains the process along line B-B'. Figure 25 The diagram shows a schematic cross-sectional view of the semiconductor structure.

[0088] refer to Figure 25-28 Between the plurality of finger storage areas 504 and two block storage areas 502 that are in contact with each other (e.g., between block storage areas 5021 and 5022, and between block storage areas 5023 and 5024, respectively), a first isolation structure 516 passing through the stacked structure can be formed on each side of the intermediate region 501. Furthermore, a stepped structure (not labeled) can be formed from the stacked structure in the intermediate region 501 of the plurality of finger storage areas 504 of the two block storage areas 502; along the X direction, the stepped structure may include a plurality of sub-stepped structures 520, and adjacent sub-stepped structures 520 may be spaced apart from each other by a first bundle structure 518 extending along the Y direction. The first bundle structure 518 can be connected to the wall structure region 506 of each block storage area 502. In one embodiment, the width of each first bundle structure 518 in the X direction may be L0.

[0089] In one embodiment, within each block storage area 502, the sub-step structure 520 may include a single row of sub-steps (not shown) extending in the Y direction. This single row of sub-steps may be formed in the finger storage area 504 adjacent to the wall structure area 506. In a subsequent process, word line contacts 512 may be formed on the sub-steps formed in the step structure. For example, word line contacts 512 may be formed in the finger storage area 504 adjacent to the wall structure area 506 to electrically connect the sub-steps formed in the finger storage area 504. It should be noted that word line contacts 512 may be formed in a subsequent process, and Figure 25 The circles in the middle and Figure 27 The dotted plugs in the diagram are only intended to schematically indicate the expected locations for forming word line contacts 512 in subsequent processes. It should also be noted that portions of the second dielectric layer 522 located longitudinally below each expected word line contact 512 may be replaced with electrode layers in subsequent processes to establish an electrical connection with the corresponding word line contact 512.

[0090] refer to Figure 25-26 A first isolation structure 516, formed along the D-D' line in the array region 503 near the middle region 501, can penetrate the stacked structure, allowing multiple pointer storage regions 504 to contact each other with block storage regions 502. (See reference...) Figure 25 and 27Along the C-C' line parallel to the Y direction and cutting off the sub-step structure 520, word line contacts 512 can be formed in the finger storage area 504 adjacent to the wall structure area 506 in a subsequent process to electrically connect the corresponding steps. Additionally, after forming the step structure including multiple sub-step structures 520, a wall structure (not labeled) extending in the X direction can be simultaneously formed in the intermediate area 501 between the wall structure area 506 and adjacent block storage areas 502 that contact each other. Therefore, the wall structure in the Y direction (refer to...) Figure 27 The width of ) is approximately the total width of two adjacent wall structure zones 506. (Reference) Figure 25 and 28 By arranging the B-B' line of the first bundle structure 518 parallel to the Y direction and cutting off the adjacent sub-step structures 520, the stacked structure can remain unchanged after forming the first isolation structure 516 and the step structure. Therefore, the first bundle structure 518 extending along the Y direction prevents the wall structure from having a narrow width (approximately the total width of the two wall structure regions 506) along the path from one side of the intermediate region 501 to the other. Thus, the wall structure is less prone to collapse when manufacturing the GLS that passes through the wall structure along the X direction.

[0091] For each pair of block memory regions 502 that bring multiple memory regions 504 into contact with each other, a first isolation structure 516 formed on each side of the intermediate region 501 can be used to protect the central portion of the second dielectric layer 522 in the stepped structure between the two block memory regions 502, so that when the second dielectric layer 522 is replaced with a metal electrode layer in a subsequent process, the central portion of the second dielectric layer 522 in the stepped structure between the two block memory regions 502 can be retained without removal. The remaining central portion of the second dielectric layer 522 (which may be made of nitride) in the stepped structure between the two block memory regions 502 and the first dielectric layer 521 (which may be made of oxide) can provide not only mechanical support for subsequent manufacturing processes but also electrical isolation for the two block memory regions 502 formed in the storage device.

[0092] In one embodiment, the first isolation structure 516 may have a rectangular shape. The dimension of the first isolation structure 516 in the X direction may be larger than its dimension in the Y direction. For example, the dimension of the first isolation structure 516 in the Y direction may be in the range of approximately 10 nm to 40 nm. The dimension of the first isolation structure 516 in the Y direction may not be too large, otherwise the process of filling the corresponding gaps to form the first isolation structure 516 may take more time and use more material. The dimension of the first isolation structure 516 in the Y direction may not be too small, otherwise the first isolation structure 516 may not be able to provide sufficient protection for the central portion of the second dielectric layer 522 in the stepped structure between the two block memory regions 502 during subsequent etching processes. Furthermore, the dimension of the first isolation structure 516 in the X direction may be greater than half the dimension of the finger memory region 504 in the Y direction. Additionally, the dimension of each finger memory region 504 in the Y direction may be approximately the same as the dimension of the wall structure region 506 in the Y direction. In other embodiments, the first isolation structure may have any other suitable shape.

[0093] In one embodiment, a portion of the first isolation structure 516 formed in the array region 503 may be significantly larger than the portion of the first isolation structure 516 formed in the intermediate region 501. For example, the entire first isolation structure 516 may be formed in the array region 503 with an edge overlapping the boundary between the array region 503 and the intermediate region 501, or the portion of the first isolation structure 516 formed in the array region 503 may be twice as large as the portion of the first isolation structure 516 formed in the intermediate region 501. In other embodiments, the portion of the first isolation structure formed in the array region may be equal to or smaller than the portion of the first isolation structure formed in the wall structure region.

[0094] The first isolation structure 516 may be made of an insulating material (e.g., silicon dioxide). It should be noted that when the second dielectric layer 522 is removed during a subsequent etching process, the etching rate of the material used to form the first isolation structure 516 may be significantly lower than the etching rate of the material used to form the second dielectric layer 522.

[0095] refer to Figure 25 In a stepped structure formed by multiple memory regions 502 that are in contact with each other, the region near the boundary between two memory regions 502 is called the second bundle structure 519. In a subsequent process, after partially replacing the second dielectric layer 522 in the stepped structure with an electrode layer, the second dielectric layer 522 (refer to...) Figure 27 A portion of this structure can be retained in the second bundle structure 519 to provide mechanical support for the material layer and electrical isolation for the two block storage areas 502. It should be noted that in... Figure 25In the diagram, the rectangular regions connecting the first isolation structures 516 formed on each side of the intermediate region 501 are used to schematically indicate the location of the second bundle structure 519. In practical applications, after partially removing multiple second dielectric layers 522 from the intermediate region, the remaining portion of the second dielectric layer in each sub-step structure 520 can have the same characteristics as... Figure 25 The rectangles shown have different shapes. Additionally, as in... Figure 27 As shown, because sub-steps are formed in each sub-step structure 520, the top layer of the first dielectric layer 521 located at the boundary between block storage areas 5021 and 5022, or between block storage areas 5023 and 5024, can be lower than the top surface of the initially formed stacked structure. Therefore, the top surface of the second bundle structure 519 can be lower than the top surface of the first bundle structure 518. Figure 25 In the schematic top view shown, since the first bundle structure 518 and the second bundle structure 519 have different heights, the second bundle structure 519 is shown as a discrete part cut by multiple first bundle structures 518.

[0096] Furthermore, returning to Figure 39 Multiple gate slots (GLS) extending in a first lateral direction can be formed perpendicularly through the stacked structure and at the boundary of each finger storage area and each wall structure area of ​​the block storage area. Each GLS formed between the multiple finger storage areas and adjacent block storage areas that are in contact with each other can be truncated in the intermediate area by two first isolation structures formed on both sides of the intermediate area. In addition, within the block storage area, each GLS formed between adjacent finger storage areas can be confined in the array area and does not extend into the intermediate area (S703). Figure 29-32 A schematic diagram illustrating an exemplary semiconductor structure according to various embodiments of the present disclosure is provided. Specifically, Figure 29 A schematic planar diagram illustrating the semiconductor structure is shown. Figure 30 This explains the process along line D-D'. Figure 29 The schematic cross-sectional view of the semiconductor structure shown in the figure is as follows. Figure 31 This explains the process along line C-C'. Figure 29 A schematic cross-sectional view of the semiconductor structure shown in the figure, and Figure 32 This explains the process along line B-B'. Figure 29 The diagram shows a schematic cross-sectional view of the semiconductor structure.

[0097] refer to Figure 29-32Multiple GLS 508s extending in the X direction can be formed perpendicularly through the stacked structure and at the boundaries of each finger storage area 504 and each wall structure area 506 of the multiple block storage areas 502. The GLS 508s formed between the wall structure areas 506 and adjacent block storage areas 502 that are in contact with each other can extend through the array area 503 and the intermediate area 501, and thus can electrically separate two adjacent block storage areas 502. For example, refer to... Figure 29 The GLS 508, formed between the second storage area 5022 and the third storage area 5023, can extend along the X direction through the entire stack structure.

[0098] The GLS 508 formed between the plurality of finger storage areas 504 and adjacent block storage areas 502 that are in contact with each other can be confined within two array regions 503. That is, at each side of the intermediate region 501, the GLS 508 formed between the plurality of finger storage areas 504 and two block storage areas 502 that are in contact with each other can be connected to a corresponding first isolation structure 516, and therefore, the GLS 508 may not extend into the intermediate region 501. For example, refer to Figure 29 Between the first storage area 5021 and the second storage area 5022 or between the third storage area 5023 and the fourth storage area 5024, each GLS 508 can only be formed in the array area 503 on one side of the intermediate area 501, and can be connected to (or terminated by) the first isolation structure 516 formed on the same side of the intermediate area 501.

[0099] Furthermore, within the array region 503 of each block storage area 502 (including the first block storage area 5021, the second block storage area 5022, the third block storage area 5023, and the fourth block storage area 5024), GLS 508 can be formed between adjacent finger storage areas 504 and between the wall structure area 506 and adjacent finger storage areas 504; and within the intermediate region 501 of each block storage area 502, GLS 508 can be formed between the wall structure area 506 and adjacent finger storage areas 504. It should be noted that within each block storage area 502, the GLS 508 formed in the intermediate region 501 may not be precisely located at the boundary between the wall structure area 506 and adjacent finger storage areas 504; additionally, the formed GLS 508 may not extend into the first bundle structure 518 in the X direction. For example, GLS 508 can be formed at the edge of the sub-step structure 520, and the length of GLS 508 can be less than the width of the sub-step structure 520 in the X direction. It should also be noted that within each block storage area 502, each GLS 508 formed in the array area 503 can extend along the X direction through the entire array area 503.

[0100] refer to Figures 29-30 Along the D-D' line in the array region 503 near the middle region 501, a GLS 508 can be formed at the boundary between the wall structure region 506 and the adjacent block storage regions 502 that are in contact with each other, passing through the stacked structure. (Reference) Figure 29 and 31 Along the C-C' line parallel to the Y direction and cutting off the sub-step structure 520, in addition to the GLS 508 formed at the boundary between the wall structure region 506 and the two block storage regions 502 that are in contact with each other, a GLS 508 can also be formed within each block storage region 502 to separate the wall structure region 506 from the adjacent finger storage region 504. It should be noted that in the intermediate region 501, the GLS 508 may not be formed at the boundary between adjacent finger storage regions 504. (See reference...) Figure 29 and 32 Along the B-B' line parallel to the Y direction and cutting off the first bundle of structures 518 between adjacent sub-step structures 520, a GLS 508 through the stacked structure can be formed at the boundary between the wall structure area 506 and the adjacent block storage areas 502 that are in contact with each other.

[0101] Multiple GLS 508s can serve as process references for replacing multiple second dielectric layers 522 in the array region 503 and the stepped structure during subsequent processes. In one embodiment, GLS 508s can be formed in only two array regions 503 at the boundary between multiple pointer memory regions 504 and adjacent block memory regions 502 that are in contact with each other (see reference). Figure 29 and Figure 31 Furthermore, during the subsequent removal of multiple second dielectric layers 522 from array region 503, the first isolation structure 516 formed on both sides of intermediate region 501 can provide protection for the central portion of the second dielectric layer 522 in intermediate region 501 adjacent to the boundary between the two block memory regions 502. Therefore, after the removal of the second dielectric layer 522 from array region 503, the central portion of the second dielectric layer 522 (located in the second bundle structure 519) can remain in intermediate region 501 between the two block memory regions 502 that bring multiple finger memory regions into contact with each other. Thus, the remaining central portion of the second dielectric layer 522 in intermediate region 501 between the two block memory regions 502 can provide necessary mechanical support and electrical isolation for subsequently formed memory devices. Alternatively, the etching process can also remove portions of the second dielectric layer 522 located longitudinally below the intended word line contacts 512 in finger memory regions 504 adjacent to wall structure region 506.

[0102] For example, refer to Figure 29The distance from point E, located in the intermediate region 501 and at the boundary between the plurality of finger memory areas 504 and two block memory areas 502 (e.g., a third block memory area 5023 and a fourth block memory area 5024) that are in contact with each other, to the nearest GLS 508 can be L1, while the distance from the location of the word line contact 512 to be formed to the nearest GLS 508 can be L3. To ensure that the central portion of the second dielectric layer 522 in the intermediate region 501 between the two block memory areas 502 is retained after removing a portion of the second dielectric layer 522 located longitudinally below the intended word line contact 512, L1 can always be greater than L3. That is, the shortest distance from the point located in the intermediate region 501 and at the boundary between the plurality of finger memory areas 504 and two block memory areas 502 that are in contact with each other to the nearest GLS 508 can be greater than the longest distance from the location of the word line contact 512 to the nearest GLS 508. Similarly, in order to ensure that the central portion of the second dielectric layer 522 in the intermediate region 501 between the two block storage regions 502 is retained after a portion of the second dielectric layer 522 in the array region 503 is removed, the shortest distance from the point located in the intermediate region 501 and at the boundary between the two block storage regions 502 that make the plurality of finger storage regions 504 contact each other to the nearest GLS 508 can be greater than the longest distance from the point located in the array region 503 to the nearest GLS 508.

[0103] Furthermore, after removing a portion of the second dielectric layer 522 located longitudinally below the intended word line contact 512, at least a portion of the second dielectric layer 522 in the first bundle structure 518 can be retained. Therefore, the removed portion of the second dielectric layer 522, along with the plurality of first dielectric layers 521, can provide mechanical support for the material structure in the intermediate region 501. For example, refer to... Figure 29The distance from point F in the first bundle structure 518 to the nearest GLS 508 can be L2, and to ensure that at least a portion of the second dielectric layer 522 in the first bundle structure 518 is retained after removing the portion of the second dielectric layer 522 located below the intended word line contact 512 in the longitudinal direction, the maximum value of L2 can be greater than the maximum value of L3. That is, the longest distance from a point in the first bundle structure 518 to the nearest GLS 508 can be longer than the longest distance from the location of the word line contact 512 to be formed to the nearest GLS 508. Therefore, by appropriately selecting the etching time, at least a portion of the second dielectric layer 522 in the first bundle structure 518 is retained after removing the portion of the second dielectric layer 522 located below the intended word line contact 512 in the longitudinal direction. Similarly, in order to ensure that at least a portion of the second dielectric layer 522 in the first bundle structure 518 is retained after a portion of the second dielectric layer 522 in the array region 503 is removed, the longest distance from a point in the first bundle structure 518 to the nearest GLS 508 can be longer than the longest distance from a point in the array region 503 to the nearest GLS 508.

[0104] Since GLS 508 can be not formed between adjacent pointer memory areas 504 within the intermediate region 501 of each block memory area 502, a large portion of the second dielectric layer 522 in the stepped structure can be left unremoved during the subsequent removal of the plurality of second dielectric layers 522, and the remaining portion of the second dielectric layer 522 and the plurality of first dielectric layers 521 can provide mechanical support for the material structure in the intermediate region 501.

[0105] Furthermore, returning to Figure 39 Multiple second dielectric layers can be removed from the array region and partially from the intermediate region. After removing multiple second dielectric layers from the array region and partially from the stepped structure, the central portion of the second dielectric layer located in the second bundle structure spanning the multiple pointer memory regions and adjacent block memory regions in contact with each other can be retained, and at least a portion of the second dielectric layer located in each first bundle structure can also be retained (S704). Figure 33-35 Schematic cross-sectional views illustrating semiconductor structures consistent with various embodiments of this disclosure are provided. Specifically, Figure 33 The cross-sectional view shown is from Figure 30 It is derived from the cross-sectional view shown in the figure. Figure 34 The cross-sectional view shown is from Figure 31 The cross-sectional view shown in the figure is derived from, and Figure 35 The cross-sectional view shown is from Figure 32The cross-sectional view shown is derived from this. It should be noted that, since the second dielectric layer is initially located between adjacent first dielectric layers, the planar view of the semiconductor structure remains consistent after the second dielectric layer is removed from the array region and partially from the intermediate region. Figure 29 The plane shown in Figure 1 That is, Figure 29 A schematic plan view of the semiconductor structure after removing the second dielectric layer from the array region and partially from the stepped structure is also provided.

[0106] refer to Figure 29 and 33 -35, multiple second dielectric layers 522 can be removed from array region 503 and partially from intermediate region 501. Because Figure 33 A schematic cross-sectional view of the semiconductor structure along the D-D' line located in array region 503 is shown, so that the multiple second dielectric layers 522 at the cross-sectional view are completely removed. (As shown in...) Figure 34 As shown, the central portion of a plurality of second dielectric layers 522 spanning the boundary between a plurality of finger memory regions 504 and two block memory regions 502 in contact with each other can be retained in the semiconductor structure. (As shown in...) Figure 35 As shown, portions of a plurality of second dielectric layers 522 may be retained in the first bundle structure 518, and each second dielectric layer 522 may continue to extend across two block memory areas 502 that make the plurality of pointer memory areas 504 contact each other.

[0107] Furthermore, returning to Figure 39 Multiple electrode layers can be formed in the blank space between adjacent first dielectric layers (S705). Figures 36-38 Schematic cross-sectional views illustrating semiconductor structures consistent with various embodiments of this disclosure are provided. Specifically, Figure 36 The cross-sectional view shown is from Figure 33 It is derived from the cross-sectional view shown in the figure. Figure 37 The cross-sectional view shown is from Figure 34 The cross-sectional view shown in the figure is derived from, and Figure 38 The cross-sectional view shown is from Figure 35 The cross-sectional view shown is derived from this. It should be noted that, since the electrode layers are formed between adjacent first dielectric layers, the planar view of the semiconductor structure remains consistent after multiple electrode layers are formed. Figure 29 The plane shown in Figure 1 That is, Figure 29 A schematic plan view of a semiconductor structure is also provided after multiple electrode layers are formed in the blank space between adjacent first dielectric layers.

[0108] refer to Figure 29 and 36-38, multiple electrode layers 531 can be formed in the blank space between adjacent first dielectric layers 521. Therefore, multiple second dielectric layers 522 formed in array region 503 can be replaced by multiple electrode layers 531 (see reference). Figure 30 ), and portions of the second dielectric layer 522 can be replaced by multiple electrode layers 531 (see reference). Figures 31-32 In one embodiment, the plurality of electrode layers 531 may be made of tungsten.

[0109] In one embodiment, for two block storage regions 502 (e.g., second block storage region 5022 and third block storage region 5023) that make the wall structure region 506 contact each other, a portion of the electrode layer 531 formed in one block storage region 502 (e.g., second block storage region 5022) can be isolated from a portion of the electrode layer 531 formed in the other block storage region 502 (e.g., third block storage region 5023) by passing through the GLS 508 formed by the stacked structure. For multiple memory regions 504 that are in contact with adjacent block memory regions 502 (e.g., first block memory region 5021 and second block memory region 5022, or third block memory region 5023 and fourth block memory region 5024), a first isolation structure 516 is formed on each side of the intermediate region 501. A GLS 508 is formed in the array region 503 and connected to the first isolation structure 516. The remaining central portion of the second dielectric layer 522 in the intermediate region 501 across the two block memory regions 502 can electrically isolate a portion of the electrode layer 531 formed in one block memory region 502 (e.g., first block memory region 5021 or third block memory region 5023) from a portion of the electrode layer 531 formed in the other block memory region 502 (e.g., second block memory region 5022 or fourth block memory region 5024).

[0110] Furthermore, after forming multiple electrode layers 531, multiple word line contacts 512 can be formed in the intermediate region 501 to electrically connect to the steps formed in the pointer storage region 504 adjacent to the wall structure region 506. Additionally, multiple channel structures (not shown) can be formed in the array region.

[0111] According to the disclosed method, the formed stepped structure includes multiple sub-stepped structures, and along the length of the wall structure, adjacent sub-stepped structures are separated from each other by a first bundle structure connected to the wall structure. The first bundle structure provides mechanical support to the wall structure, thus preventing the wall structure from collapsing during the formation of the GLS passing through the wall structure. Furthermore, for adjacent block memory areas where memory regions are configured between their wall structure regions, the GLS formed between the two block memory areas is truncated in the intermediate region by two first isolation structures formed on both sides of the intermediate region. In the intermediate region spanning the two block memory areas, a second bundle structure connects the first isolation structures formed on each side of the intermediate region. In the second bundle structure, after the second dielectric layer is removed from the array region, a portion of the second dielectric layer is retained between adjacent first dielectric layers. Therefore, the second dielectric layer and the first dielectric layer located in the second bundle structure not only provide mechanical support for subsequent manufacturing processes but also provide electrical isolation for the two block memory areas. Additionally, after the second dielectric layer is removed from the array region, at least a portion of the second dielectric layer is retained in each first bundle structure, which also provides mechanical support for subsequent manufacturing processes.

[0112] This disclosure also provides another method for forming storage devices. Figure 40 A schematic top view illustrating a semiconductor structure manufactured by an exemplary method according to various embodiments of this disclosure is provided. Compared to the semiconductor structure formed by the method described in the above embodiments, the method used to form... Figure 40 The method of the semiconductor structure shown may not include forming a first isolation structure along the Y direction on each side of the intermediate region 501 between the plurality of finger memory regions 504 and adjacent block memory regions 502 that are in contact with each other. Alternatively, when forming a plurality of GLS 508, the GLS 508 (also referred to as the first separator structure) formed between the plurality of finger memory regions 504 and adjacent block memory regions 502 that are in contact with each other may be located in the array region 503. After further replacing the plurality of second dielectric layers with a plurality of electrode layers, since a plurality of electrode layers are inevitably formed at the boundary between the two block memory regions in the region near the end of each first separator structure, the method may further include extending each first separator structure along the X direction to completely remove the plurality of electrode layers formed at the boundary between the two block memory regions. Thus, electrical isolation between two adjacent block memory regions can be achieved. In one embodiment, a first separation structure (e.g., a GLS 508 formed between multiple finger memory regions 504 and adjacent block memory regions 502 in contact with each other) can be extended toward the intermediate region 501 by a dry etching process, so that multiple electrode layers can be completely removed from the boundary between the two block memory regions 502.

[0113] This disclosure also provides another method for forming semiconductor structures. Figure 41 A schematic top view illustrating a semiconductor structure manufactured by an exemplary method according to various embodiments of this disclosure is provided. Compared to the semiconductor structure formed by the method described in the above embodiments, the method used to form... Figure 41 The method of constructing the semiconductor structure shown may include forming a plurality of discrete second isolation structures 530 along the Y direction at the boundary between a plurality of finger memory regions 504 and adjacent block memory regions 502 that are in contact with each other. These plurality of second isolation structures 530 may be formed together with a first isolation structure 516 and therefore may be made of the same material as the first isolation structure 516. For example, when a first isolation structure 516 is formed on each side of an intermediate region 501 and between two adjacent block memory regions 502, a plurality of discrete second isolation structures 530 may be formed simultaneously in the intermediate region 501 at the boundary between two adjacent block memory regions 502. Further, after removing the plurality of second dielectric layers, portions of the second dielectric layers 522 may remain in the stepped region 501. In the X direction, the remaining portions of the second dielectric layers may connect adjacent second isolation structures 530, and each first isolation structure 516 may also be connected to a second isolation structure 530. Therefore, the GLS 508 (e.g., the first partition structure), the plurality of first isolation structures 516, the plurality of second isolation structures 530, and the remainder of the second dielectric layer can together provide electrical isolation for two adjacent block storage areas 502.

[0114] This disclosure also provides a storage device. Figure 12 and Figure 20-23 A schematic diagram illustrating an exemplary storage device consistent with various embodiments of this disclosure is provided. Specifically, Figure 12 A schematic plan view of an exemplary storage device is shown. Figure 20 A schematic cross-sectional view of the storage device along line D-D' is shown. Figure 21 A schematic cross-sectional view of the storage device along line C-C' is shown, and Figure 22-23 Two schematic examples of cross-sectional views of storage devices along line B-B' are shown.

[0115] refer to Figure 12 and 20-23. X, Y, and Z are used to illustrate the spatial relationships of components in a memory device. The memory device may include a substrate 550 and a stacked structure formed on the substrate 550. In a first lateral direction (X direction) about the substrate 550, the memory device may include two array regions 503 and an intermediate region 501 disposed between the two array regions 503. In a second lateral direction (Y direction) about the substrate 550, the memory device may be divided into multiple block memory regions 502. Further, in the Y direction, each block memory region 502 may include multiple finger memory regions 504 and wall structure regions 506.

[0116] Furthermore, adjacent block storage areas 502 in the plurality of block storage areas 502 may have their wall structure areas 506 in contact with each other, or their plurality of finger storage areas 504 in contact with each other. For example, along the Y direction, the plurality of block storage areas 502 may include block storage areas 5021, 5022, 5023 and 5024 arranged sequentially along the Y direction. Block storage areas 5021 and 5022 can be connected to each other using multiple pointer storage areas 504 of block storage area 5021 adjacent to multiple pointer storage areas 504 of block storage area 5022; block storage areas 5022 and 5023 can be connected to each other using a wall structure area 506 of block storage area 5022 adjacent to a wall structure area 506 of block storage area 5023; and block storage areas 5023 and 5024 can be connected to each other using multiple pointer storage areas 504 of block storage area 5024 adjacent to multiple pointer storage areas 504 of block storage area 5024. It should be noted that, for illustrative purposes, in Figure 12 The diagram shows four block memory regions 502 (block memory region 5021, block memory region 5022, block memory region 5023, and block memory region 5024). However, in practical applications, the semiconductor structure may include at least two block memory regions that allow multiple memory regions to contact each other. It should also be noted that in... Figure 12 Only the portion of each array region 503 adjacent to the middle region 501 is shown.

[0117] The stacked structure may include a plurality of first dielectric layers 521 and a plurality of electrode layers 531. The plurality of first dielectric layers 521 and the plurality of electrode layers 531 may be alternately stacked on a substrate 550. In one embodiment, the substrate 550 may be made of silicon, germanium, silicon-germanium, or any other suitable semiconductor material. In other embodiments, the substrate may be made of SOI, GOI, or any other suitable semiconductor composite material. In one embodiment, the plurality of first dielectric layers 521 may be made of an oxide (e.g., silicon dioxide), and the plurality of electrode layers 531 may be made of a conductive material (e.g., tungsten).

[0118] In the intermediate area 501, the stacking structure may include a wall structure (not labeled) formed by wall structure areas 506 that make wall structure areas 506 contact each other with adjacent block storage areas 502.

[0119] Furthermore, the storage device may include a first isolation structure 516 formed through the stacked structure at each side of the intermediate region 501 between the plurality of pointer storage areas 504 and adjacent block storage areas 502 that are in contact with each other.

[0120] In one embodiment, the first isolation structure 516 may have a rectangular shape and may be made of an insulating material (e.g., silicon dioxide). The dimension of the first isolation structure 516 in the X direction may be larger than the dimension of the first isolation structure 516 in the Y direction. For example, the dimension of the first isolation structure 516 in the Y direction may be in the range of approximately 10 nm to 40 nm. Furthermore, the dimension of the first isolation structure 516 in the X direction may be greater than half the dimension of the memory region 504 in the Y direction. In other embodiments, the first isolation structure may have any other suitable shape.

[0121] In one embodiment, a portion of the first isolation structure 516 formed in the array region 503 may be significantly larger than the portion of the first isolation structure 516 formed in the intermediate region 501. For example, the entire first isolation structure 516 may be formed in the array region 503 with an edge overlapping the boundary between the array region 503 and the intermediate region 501, or the portion of the first isolation structure 516 formed in the array region 503 may be twice as large as the portion of the first isolation structure 516 formed in the intermediate region 501. In other embodiments, the portion of the first isolation structure formed in the array region may be equal to or smaller than the portion of the first isolation structure formed in the wall structure region.

[0122] Furthermore, in the intermediate region 501, the stacked structure may also include a stepped structure (not labeled) formed in a plurality of finger memory regions 504 that contact each other with adjacent block memory regions 502. Along the X direction, the stepped structure may include a plurality of sub-stepped structures 520, and adjacent sub-stepped structures 520 may be spaced apart from each other by a first bundle structure 518 extending along the Y direction. Along the Y direction, the first bundle structure 518 may be connected to the wall structure region 506 of each block memory region 502. In one embodiment, the width of each first bundle structure 518 may be L0 in the X direction, and within each block memory region 502, the sub-stepped structure 520 may include multiple rows of sub-steps (not shown) extending along the Y direction. Each sub-step may include multiple pairs of first dielectric layers 521 and electrode layers 531.

[0123] Furthermore, at least a portion of each first bundle structure 518 may include a stacked structure formed by a plurality of first dielectric layers 521 alternating with a plurality of second dielectric layers 522. That is, in each first bundle structure 518, the second dielectric layers 522 and the electrode layers 531 may be connected to each other and located between the same pair of first dielectric layers 521. The plurality of second dielectric layers 522 may be made of a nitride (e.g., silicon nitride). In one embodiment, reference... Figure 22 Along the Y direction, each second dielectric layer 522 may continue to extend across two block memory regions 502 that bring the plurality of pointer memory regions 504 into contact with each other. In other embodiments, refer to Figure 23 Along the Y direction, each second dielectric layer 522 may include multiple discrete sub-parts, and the multiple second dielectric layers 522 together with the multiple first dielectric layers 521 may form multiple vertical pillars, which may further provide mechanical support for the storage device.

[0124] Furthermore, in the intermediate region 501, the storage device may include a second bundle structure 519 located across adjacent block storage regions 502 that contact the plurality of finger storage regions 504. The second bundle structure 519 may connect a first isolation structure 516 located on one side of the intermediate region 501 to another first isolation structure 516 located on the other side of the intermediate region 501. Additionally, in the second bundle structure 519, the storage device may also include a plurality of second dielectric layers 522 alternating with the plurality of first dielectric layers 521. It should be noted that the boundary between the plurality of finger storage regions 504 and the adjacent block storage regions 502 that contact each other may be located in a stepped structure, and the top layer of the plurality of second dielectric layers 522 may be lower than the top layer of the plurality of electrode layers 531 located in the wall structure. The plurality of second dielectric layers 522 may be connected to the first isolation structures 516 formed on each side of the intermediate region 501.

[0125] The storage device may further include a plurality of GLS 508s that are vertically formed through the stacked structure and extend in the X direction. The plurality of GLS 508s may include GLS 508s formed between wall structure regions 506 and adjacent block storage regions 502 that are in contact with each other. The GLS 508s formed between wall structure regions 506 and adjacent block storage regions 502 that are in contact with each other may extend through two array regions 503 and an intermediate region 501 to electrically separate two adjacent block storage regions 502.

[0126] The plurality of GLS 508 may also include GLS 508 formed between the plurality of finger storage areas 504 and adjacent block storage areas 502 that are in contact with each other. Each GLS 508 formed between the plurality of finger storage areas 504 and adjacent block storage areas 502 that are in contact with each other may be confined in the array region 503 and may be connected to a corresponding first isolation structure located on the same side of the intermediate region 501. In one embodiment, the first isolation structure 516 formed on each side of the intermediate region 501, the GLS 508 formed in the array region 503 and connected to the first isolation structure 516, and the plurality of first dielectric layers 521 and the plurality of second dielectric layers 522 in the intermediate region 501 spanning the two block storage areas 502 may electrically isolate the plurality of finger storage areas 504 from the adjacent block storage areas 502 that are in contact with each other.

[0127] Within each block storage area 502, the plurality of GLS 508 may also include GLS 508 formed between adjacent finger storage areas 504 and between the wall structure area 506 and adjacent finger storage areas 504. It should be noted that within each block storage area 502, the GLS 508 formed in the intermediate area 501 may not be precisely located between adjacent finger storage areas 504 or at the boundary between the wall structure area 506 and adjacent finger storage areas 504; furthermore, the formed GLS 508 may not extend in the X direction into the first bundle structure 518. It should also be noted that within each block storage area 502, each GLS 508 formed in the array area 503 may extend along the X direction through the entire array area 503.

[0128] Further, refer to Figure 12 The distance from point E, located in the intermediate region 501 and at the boundary between the plurality of finger storage areas 504 and two block storage areas 502 (e.g., a third block storage area 5023 and a fourth block storage area 5024) that are in contact with each other, to the nearest GLS 508 can be L1, while the distance from the location of the word line contact 512 to be formed to the nearest GLS 508 can be L3. In one embodiment, L1 can always be greater than L3. That is, the shortest distance from the point located in the intermediate region 501 and at the boundary between the plurality of finger storage areas 504 and two block storage areas 502 that are in contact with each other to the nearest GLS 508 can be greater than the longest distance from the location of the word line contact 512 to the nearest GLS 508. Similarly, the shortest distance from a point located in the intermediate region 501 and at the boundary between the multiple pointer storage areas 504 and the two block storage areas 502 that are in contact with each other to the nearest GLS 508 can be greater than the longest distance from a point located in the array region 503 to the nearest GLS 508.

[0129] Further, refer to Figure 12 The distance from point F in the first bundle structure 518 to the nearest GLS 508 can be L2. In one embodiment, the maximum value of L2 can be greater than the maximum value of L3. That is, the longest distance from a point in the first bundle structure 518 to the nearest GLS 508 can be longer than the longest distance from the location of the word line contact 512 to be formed to the nearest GLS 508. Therefore, by appropriately selecting the etching time, at least a portion of the second dielectric layer 522 in the first bundle structure 518 is retained after removing a portion of the second dielectric layer 522 located below the intended word line contact 512 in the longitudinal direction. Similarly, to ensure that at least a portion of the second dielectric layer 522 in the first bundle structure 518 is retained after removing a portion of the second dielectric layer 522 in the array region 503, the longest distance from a point in the first bundle structure 518 to the nearest GLS 508 can be longer than the longest distance from a point in the array region 503 to the nearest GLS 508.

[0130] In one embodiment, reference Figure 12 In the X direction, the GLS 508 formed in each sub-step structure 520 between adjacent finger storage areas 504 or between wall structure area 506 and finger storage area 504 can be equal to or shorter than the size of the sub-step structure 520. Therefore, in the X direction, the distance L0' between GLS 508 can be equal to or greater than the distance L0 between sub-step structures 520. That is, the length of each GLS 508 formed in the sub-step structure 520 can be equal to or less than the width of the sub-step structure 520 in the X direction.

[0131] Furthermore, the storage device may include a plurality of word line contacts 512 formed in the intermediate region 501 for electrically connecting multiple rows of sub-steps. For example, word line contacts 512 may be formed in each finger storage region 504 to electrically connect to the sub-steps formed in the finger storage region 504.

[0132] According to the disclosed storage device, the formed stepped structure includes multiple sub-stepped structures, and along the length of the wall structure, adjacent sub-stepped structures are separated from each other by a first bundle structure connected to the wall structure. The first bundle structure provides mechanical support to the wall structure, thus preventing the wall structure from collapsing when forming the GLS that passes through the wall structure. Furthermore, for adjacent block storage areas where the memory region is configured between its wall structure regions, the GLS formed between the two block storage areas is truncated in the intermediate region by two first isolation structures formed on both sides of the intermediate region. In the intermediate region spanning the two block storage areas, a second bundle structure connects the first isolation structures formed on each side of the intermediate region. In the second bundle structure, after the second dielectric layer is removed from the array region, a portion of the second dielectric layer is retained between adjacent first dielectric layers. Therefore, the second dielectric layer and the first dielectric layer located in the second bundle structure not only provide mechanical support for subsequent manufacturing processes but also provide electrical isolation between the two block storage areas. In addition, after the second dielectric layer is removed from the array region, at least a portion of the second dielectric layer remains in each first bundle structure, which also provides mechanical support for the subsequent manufacturing process.

[0133] This disclosure also provides another storage device. Figure 29 and Figures 36-38 A schematic diagram illustrating an exemplary storage device consistent with various embodiments of this disclosure is provided. Specifically, Figure 29 A schematic plan view of an exemplary storage device is shown. Figure 36 A schematic cross-sectional view of the storage device along line D-D' is shown. Figure 37 A schematic cross-sectional view of the storage device along line C-C' is shown, and Figure 38 A schematic cross-sectional view of the storage device along line B-B' is shown.

[0134] Reference 29 and Figures 36-39 The storage devices are substantially the same as those described in the embodiments provided above. The following description will focus on the differences between these storage devices and similar components will not be described again herein. For details of similar components, please refer to the corresponding descriptions in the embodiments provided above.

[0135] refer to Figure 29Within each block memory region 502 of the memory device, the sub-step structure 520 may include a single row of sub-steps (not shown) extending along the Y direction. This single row of sub-steps may be formed in the pointer memory region 504 adjacent to the wall structure region 506. Each sub-step may include multiple pairs of first dielectric layers 521 and electrode layers 531. Accordingly, word line contacts 512 may be formed in the pointer memory region 504 adjacent to the wall structure region 506. Furthermore, within the intermediate region 501 of each block memory region 502, a GLS 508 may be formed only between the wall structure region 506 and the adjacent pointer memory region 504. (See reference...) Figures 37-38 In the case where a GLS 508 is not formed between adjacent pointer storage areas 504 in the intermediate region 501, the plurality of second dielectric layers 522 located in the intermediate region 501 spanning the adjacent block storage areas 502 that make the plurality of pointer storage areas contact each other can be wider in the Y direction, and the plurality of second dielectric layers 522 located in the first bundle structure 518 can also be continuous, and therefore can have a larger size in the Y direction.

[0136] According to the manufacturing method of the memory device, a plurality of second dielectric layers 522 may initially occupy the space between adjacent first dielectric layers 521. Further, portions of the second dielectric layers 522 may be removed, and then a plurality of electrode layers 531 may be formed to fill the space created by removing the second dielectric layers 522. Furthermore, since the etching process for removing portions of the second dielectric layers 522 may be an isotropic wet etching process, and etching may begin from a plurality of GLS 508s, the portions of the second dielectric layers 522 retained after the etching process can be controllable by designing the pattern of the plurality of GLS 508s and appropriately selecting the etching time. In one embodiment, since the sub-step structure 520 in each block memory region 502 may only include a single row of sub-steps formed in the finger memory region 504 adjacent to the wall structure region 506, it may not be necessary to remove portions of the second dielectric layers 522 initially formed in the intermediate region 501 of the finger memory region 504 that is not in contact with the wall structure region 506. Therefore, in the intermediate region 501, it may not be necessary to form a GLS 508 between adjacent pointer memory regions 504. Therefore, the plurality of second dielectric layers located in the intermediate region 501 spanning the plurality of pointer memory regions and adjacent block memory regions 502 that are in contact with each other can be wider in the Y direction, and the plurality of second dielectric layers 522 located in the first bundle structure 518 may not be disconnected in the Y direction.

[0137] According to the disclosed storage device, the formed stepped structure includes multiple sub-stepped structures, and adjacent sub-stepped structures are separated from each other by a first bundle structure connected to the wall structure along the length direction of the wall structure. The first bundle structure provides mechanical support to the wall structure, thus preventing the wall structure from collapsing when forming the GLS that passes through the wall structure. Furthermore, for adjacent block memory regions that bring multiple finger memory regions into contact with each other, the GLS formed between the two block memory regions is truncated in the intermediate region by two first isolation structures formed on both sides of the intermediate region. Additionally, multiple second dielectric layers are located in the second bundle structure spanning the block memory regions that bring multiple finger memory regions into contact with each other. In the second bundle structure, multiple second dielectric layers alternate with multiple first dielectric layers. The stacked structure of the first and second dielectric layers is connected to the first isolation structures formed on both sides of the intermediate region, and thus provides mechanical support for the material structure in the intermediate region. A first isolation structure, a GLS formed in the array region and connected to the first isolation structure, and a plurality of first dielectric layers and a plurality of second dielectric layers formed in a second bundle structure spanning adjacent block memory regions that bring the plurality of memory regions into contact with each other provide electrical isolation between the two block memory regions. Additionally, portions of the second dielectric layers arranged in each first bundle structure also provide mechanical support for the material structure in the intermediate region.

[0138] The above description illustrates specific exemplary embodiments of the present invention only and is not intended to limit the scope of the invention. Those skilled in the art can understand this specification as a whole and can combine technical features from various embodiments to create other embodiments understandable to them. Any equivalents or modifications fall within the scope of the invention without departing from its spirit and principles.

Claims

1. A storage device, comprising: A stacked structure comprising alternating first dielectric layers and multiple electrode layers, wherein: In the first lateral direction, the storage device includes an array region and an intermediate region disposed between the array regions, and In the second lateral direction, the stacked structure includes a first storage area and a second storage area, each including a wall structure area, wherein, in the intermediate area, the wall structure areas of the first storage area and the second storage area are separated by a stepped structure. A bundle structure located in the intermediate region, and a first bundle structure including a wall structure region extending along the second lateral direction and connecting the first storage area and the second storage area; and A plurality of second dielectric layers are located in the bundle structure, wherein, in the first bundle structure, the plurality of second dielectric layers alternate with the plurality of first dielectric layers.

2. The storage device according to claim 1, wherein: The number of the first bundle structure is one; or There are multiple first bundle structures, and the multiple first bundle structures are separately arranged in the first transverse direction.

3. The storage device according to claim 1 or 2, wherein: The bundle structure further includes a second bundle structure arranged to span the first storage area and the second storage area, and extending through the intermediate area in the first lateral direction, wherein: In the second bundle structure, the plurality of second dielectric layers alternate with the plurality of first dielectric layers.

4. The storage device according to claim 3, further comprising: A first isolation structure is formed perpendicularly through the stacked structure on each side of the intermediate area along the first lateral direction and between the first storage area and the second storage area along the second lateral direction.

5. The storage device according to claim 4, wherein: The first isolation structure is made of silicon dioxide.

6. The storage device according to claim 4, wherein: Along the first transverse direction, the stepped structure includes a plurality of sub-stepped structures, and at least two adjacent sub-stepped structures are separated by the first bundled structure.

7. The storage device according to claim 6, further comprising: A first separation structure is formed perpendicularly through the stacked structure and lies between the first and second storage blocks in each array region along the first lateral direction.

8. The storage device according to claim 7, wherein: The first storage area includes a first edge opposite to the second storage area, and the second storage area includes a second edge opposite to the first storage area; as well as The storage device further includes a second partition structure formed on each of the first and second edges and extending through the array region and the stepped structure.

9. The storage device according to claim 8, wherein, Each item in the first and second storage areas further includes: A plurality of pointer storage areas extending along the first lateral direction, wherein: In the second lateral direction, the first bundle structure extends through the plurality of finger storage areas of the first storage area and the plurality of finger storage areas of the second storage area, and connects to the wall structure area of ​​the first storage area and the second storage area.

10. The storage device according to claim 9, further comprising: A plurality of third partition structures are formed within each of the first and second storage areas and located between the wall structure area and the adjacent storage area, wherein: In each array region of the first or second storage region, a third partition structure extends through the array region; and In the middle area of ​​the first storage area or the second storage area, a third partition structure is arranged near the edge of each sub-step structure of the wall structure area, wherein the length of the third partition structure in the first lateral direction is shorter than or equal to the width of the sub-step structure in the first lateral direction.

11. The storage device according to claim 10, wherein: Within the first storage area or the second storage area, each of the sub-step structures includes multiple steps formed in a finger storage area adjacent to the wall structure area; as well as The storage device further includes a plurality of word line contacts formed in the finger storage area adjacent to the wall structure area for electrically connecting the plurality of steps.

12. The storage device according to claim 10, further comprising: Multiple fourth partition structures are formed within each item in the first and second memory areas and located between adjacent memory areas, wherein: In each array region of the first or second storage region, a fourth partition structure extends through the array region; and In the middle area of ​​the first storage area or the second storage area, and between adjacent storage areas, a fourth partition structure is arranged in each sub-step structure, wherein the length of the fourth partition structure in the first lateral direction is shorter than or equal to the width of the sub-step structure in the first lateral direction.

13. The storage device according to claim 1, wherein: Along the second transverse direction, each of the plurality of second dielectric layers in the first bundle structure comprises a plurality of discrete sub-parts.

14. The storage device according to claim 9, wherein: The first isolation structure has a dimension in the first lateral direction that is greater than half the dimension of each of the plurality of finger memory areas in the second lateral direction; and The dimensions of the first isolation structure in the second lateral direction are in the range of 10 nm to 40 nm.

15. The storage device according to claim 9, wherein: The dimension of the wall structure region in the second lateral direction is approximately the same as the dimension of each of the plurality of finger storage regions in the second lateral direction.

16. The storage device according to claim 4, further comprising: A plurality of second isolation structures are formed along the first lateral direction between the first storage area and the second storage area, wherein: The plurality of second dielectric layers connect adjacent second isolation structures, and each first isolation structure is connected to a second isolation structure.

17. The storage device according to claim 16, wherein: The plurality of second isolation structures are formed simultaneously with the first isolation structure; and The first isolation structure and the plurality of second isolation structures are made of insulating material.

18. The storage device according to claim 17, wherein: The plurality of second isolation structures are located in the intermediate region.

19. The storage device according to claim 1, wherein: The plurality of first dielectric layers are made of silicon dioxide; The plurality of second dielectric layers are made of silicon nitride; and The multiple electrode layers are made of tungsten.

20. A method for forming a storage device, comprising: A stacked structure is formed, the stacked structure comprising alternating arrangements of a plurality of first dielectric layers and a plurality of second dielectric layers, wherein: In the first lateral direction, the stacked structure is formed in the array region and the intermediate region arranged between the array region; A stepped structure and a first bundle structure are formed in the intermediate region along the second transverse direction; A plurality of gate slots (GLS) are formed that pass vertically through the stacked structure and extend along the first lateral direction, wherein: In the second lateral direction, the plurality of gate gaps at least define a first storage area and a second storage area, and The plurality of gate slots includes gate slots formed in each array region at the boundary between the first storage region and the second storage region; and The plurality of second dielectric layers are removed from the array region and partially from the intermediate region, wherein: After the plurality of second dielectric layers are removed from the array region and partially from the intermediate region, portions of the plurality of second dielectric layers remain in the first bundle structure.

21. The method of claim 20, wherein: The number of the first bundle structure is one; or There are multiple first bundle structures, and the multiple first bundle structures are separately arranged in the first transverse direction.

22. The method of claim 20, further comprising: A second bundle structure is formed spanning the first storage area and the second storage area, and extending through the intermediate area in the first lateral direction, wherein: After the plurality of second dielectric layers are removed from the array region and partially from the intermediate region, portions of the plurality of second dielectric layers remain in the second bundle structure.

23. The method of claim 22, further comprising: A first isolation structure is formed perpendicularly through the stacked structure between the first storage area and the second storage area, wherein: The first isolation structure is located at the boundary between each array region and the intermediate region; and The first isolation structure is connected to the gate gap formed on the side adjacent to the intermediate region in each array region, and the remaining portions of the plurality of second dielectric layers in the second bundle structure are connected to the first isolation structure on each side of the intermediate region.

24. The method according to claim 23, wherein: Along the first transverse direction, the stepped structure includes a plurality of sub-stepped structures, and at least two adjacent sub-stepped structures are separated by the first bundled structure.

25. The method according to claim 24, wherein, Each item in the first and second storage areas includes: A wall structure region and a plurality of finger storage regions extending along the first lateral direction, wherein: The plurality of pointer memory areas in the first memory area and the plurality of pointer memory areas in the second memory area are adjacent to each other. The stepped structure is located in the intermediate area between the wall structure areas of the first storage area and the second storage area. In the second lateral direction, the first bundle structure extends through the plurality of finger storage areas of the first storage area and the plurality of finger storage areas of the second storage area, and connects to the wall structure area of ​​the first storage area and the second storage area.

26. The method of claim 25, further comprising: After the plurality of second dielectric layers are removed from the array region and partially from the intermediate region, a plurality of electrode layers are formed between adjacent first dielectric layers.

27. The method according to claim 23, wherein: The first isolation structure is made of insulating material.

28. The method of claim 23, further comprising, when forming the first isolation structure perpendicularly through the stacked structure and located at the boundary between each array region and the intermediate region: Multiple second isolation structures are formed in the intermediate region, wherein: In the second lateral direction, each of the plurality of second isolation structures is aligned with the first isolation structure.

29. The method according to claim 28, wherein: The first isolation structure and the plurality of second isolation structures are made of insulating material; and After the plurality of second dielectric layers are removed from the array region and partially from the intermediate region, the remaining portions of the plurality of second dielectric layers in the second bundle structure are connected to adjacent second isolation structures, and each first isolation structure is also connected to a second isolation structure.

30. The method of claim 26, wherein: The first storage area includes a first edge opposite to the second storage area, and the second storage area includes a second edge opposite to the first storage area; as well as The plurality of gate slots further include: a gate slot formed on the first edge and extending through the array region and the intermediate region, and a gate slot formed on the second edge and extending through the array region and the intermediate region.

31. The method according to claim 30, wherein, Within each of the first and second storage areas, the plurality of gate slots extending along the first lateral direction further include: Located in each array region and between the wall structure region and the adjacent finger storage region; A gate gap is formed in each array region and located between adjacent finger storage regions, wherein: Along the first lateral direction, each gate slot formed in the array region and located between adjacent finger storage regions extends through the array region; and The grid gaps located in the intermediate region and at the edges of each sub-step structure near the wall structure region, wherein: The length of the grating gap located in the intermediate zone and at the edge of each sub-step structure near the wall structure zone in the first lateral direction is shorter than or equal to the width of the sub-step structure in the first lateral direction.

32. The method according to claim 31, wherein: Within the first or second storage area, each sub-step structure includes multiple steps formed in a finger storage area adjacent to the wall structure area; as well as The storage device further includes a plurality of word line contacts formed in the finger storage area adjacent to the wall structure area for electrically connecting the plurality of steps.

33. The method according to claim 32, wherein, Within each of the first and second storage areas, the plurality of gate slots extending along the first lateral direction further include: A gate gap is formed in each sub-intermediate region and located between adjacent finger storage regions, wherein: Along the first lateral direction, the length of the gate gap formed in the sub-intermediate area and located between adjacent finger storage areas is shorter than or equal to the width of the sub-step structure in the first lateral direction.

34. The method according to any one of claims 30-33, wherein: Along the second lateral direction, after the plurality of second dielectric layers are removed from the array region and partially from the intermediate region, the remaining portion of each second dielectric layer in the first bundle structure comprises a plurality of discrete sub-parts.

35. The method according to any one of claims 30-33, wherein: The longest distance from a point in one of the plurality of electrode layers to the nearest gate slot among the plurality of gate slots is less than the shortest distance from a point in one of the plurality of second dielectric layers to the nearest gate slot among the plurality of gate slots.

36. The method of claim 25, wherein: The first isolation structure has a dimension in the first lateral direction that is greater than half the dimension of each of the plurality of finger memory areas in the second lateral direction; and The dimensions of the first isolation structure in the second lateral direction are in the range of 10 nm to 40 nm.

37. The method of claim 36, wherein: The dimension of the wall structure region in the second lateral direction is approximately the same as the dimension of each of the plurality of finger storage regions in the second lateral direction.

38. The method according to any one of claims 30-33, wherein: The plurality of first dielectric layers are made of silicon dioxide; The plurality of second dielectric layers are made of silicon nitride; and The multiple electrode layers are made of tungsten.

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