An electrostatic discharge protection device, equivalent circuit and chip

Abstract

The application provides an electrostatic discharge protection device, an equivalent circuit and a chip. The electrostatic discharge protection device comprises a first deep well region and a second deep well region, a third deep well region and a fourth deep well region, a first injection region and a second injection region, a third injection region and a fourth injection region, a first well region and a second well region, a fifth injection region and a sixth injection region. The fifth injection region is used for being connected with a PAD port of the chip, and the sixth injection region is used for being grounded. The electrostatic discharge protection device can also play a good protection role when a negative ESD occurs.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to an electrostatic discharge protection device, an equivalent circuit and a chip. BACKGROUND

[0002] In the field of chip, excellent electrostatic discharge (ESD, Electro-Static discharge) device is very important for protecting the port safety. In the existing ESD structure protection design, the main purpose is to improve the requirement of ESD positive voltage input, and the negative voltage input is less considered. For high-voltage chips used in industry, due to the complexity of working conditions, the range of input negative voltage is wider, and the existing ESD structure cannot meet the use requirement. SUMMARY

[0003] Therefore, the purpose of the present application is to provide an electrostatic discharge protection device, an equivalent circuit and a chip, so as to meet the requirement of negative voltage input while meeting the requirement of ESD positive voltage input.

[0004] In the first aspect, the present application provides an electrostatic discharge protection device, which comprises a first deep well region and a second deep well region, the first deep well region and the second deep well region are formed in a semiconductor substrate, and the first deep well region and the second deep well region have a first conductivity type; a third deep well region and a fourth deep well region, the third deep well region is formed in the first deep well region, the third deep well region has a second conductivity type, the fourth deep well region is formed in the second deep well region, and the fourth deep well region has the second conductivity type; a first implant region and a second implant region, the first implant region and the second implant region are formed in the first deep well region, and the first implant region and the second implant region have different conductivity types; a third implant region and a fourth implant region, the third implant region and the fourth implant region are formed in the second deep well region, and the third implant region and the fourth implant region have different conductivity types, and the conductivity type of the third implant region is the same as that of the first implant region; a first well region and a second well region, the first well region is formed in the third deep well region, the first well region has the second conductivity type, the second well region is formed in the fourth deep well region, and the second well region has the second conductivity type; a fifth implant region and a sixth implant region, the fifth implant region is formed in the first well region, the fifth implant region has the second conductivity type, and the sixth implant region is formed in the second well region, and the sixth implant region has the second conductivity type; wherein the fifth implant region is used for connecting with a PAD port of a chip, and the sixth implant region is used for grounding.

[0005] Preferably, a fifth deep well region is further included, the fifth deep well region is formed in the semiconductor substrate, and the fifth deep well region is arranged between the first deep well region and the second deep well region, and the fifth deep well region has the second conductivity type.

[0006] Preferably, the third deep well region is disposed in the first deep well region away from the fifth deep well region, and the fourth deep well region is disposed in the second deep well region away from the fifth deep well region.

[0007] Preferably, the first implant region has the second conductivity type, the second implant region has the first conductivity type, the second implant region is disposed proximate to the fifth deep well region, the first implant region is adjacent to the second implant region, and the first implant region is between the second implant region and the third deep well region; the third implant region has the second conductivity type, the fourth implant region has the first conductivity type, the fourth implant region is disposed proximate to the fifth deep well region, the third implant region is adjacent to the fourth implant region, and the third implant region is between the fourth implant region and the fourth deep well region.

[0008] Preferably, the semiconductor substrate has the second conductivity type.

[0009] Preferably, the first conductivity type is N-type, and the second conductivity type is P-type.

[0010] In a second aspect, an equivalent circuit of an electrostatic discharge protection device is provided, the electrostatic discharge protection device being the electrostatic discharge protection device as described above, the equivalent circuit of the electrostatic discharge protection device comprising a first MOS tube and a second MOS tube, a gate of the first MOS tube being connected with a gate of the second MOS tube, a source of the first MOS tube being connected with a source of the second MOS tube, the source of the first MOS tube further being connected with a gate of the second MOS tube, a base of the first MOS tube being connected with a base of the second MOS tube, and the source of the first MOS tube further being connected with the base of the second MOS tube.

[0011] Preferably, a drain of the first MOS tube is connected with a PAD port of a chip, and a drain of the second MOS tube is grounded.

[0012] Preferably, the fifth implant region is a drain of the first MOS tube, the third deep well region and the first deep well region are a gate of the first MOS tube, the first implant region and the second implant region are a source of the first MOS tube; the sixth implant region is a drain of the second MOS tube, the second deep well region and the fourth deep well region are a gate of the second MOS tube, and the third implant region and the fourth implant region are a source of the second MOS tube.

[0013] In a third aspect, a chip is provided, the chip comprising the electrostatic discharge protection device as described above.

[0014] The electrostatic discharge protection device, the equivalent circuit and the chip provided by the application, the electrostatic discharge protection device comprises a first deep well region and a second deep well region, the first deep well region and the second deep well region are formed in a semiconductor substrate, and the first deep well region and the second deep well region have a first conductivity type; a third deep well region and a fourth deep well region, the third deep well region is formed in the first deep well region, the third deep well region has a second conductivity type, the fourth deep well region is formed in the second deep well region, and the fourth deep well region has the second conductivity type; a first implant region and a second implant region, the first implant region and the second implant region are formed in the first deep well region, and the first implant region and the second implant region have different conductivity types; a third implant region and a fourth implant region, the third implant region and the fourth implant region are formed in the second deep well region, the third implant region and the fourth implant region have different conductivity types, and the conductivity type of the third implant region is the same as that of the first implant region; a first well region and a second well region, the first well region is formed in the third deep well region, the first well region has the second conductivity type, the second well region is formed in the fourth deep well region, and the second well region has the second conductivity type; a fifth implant region and a sixth implant region, the fifth implant region is formed in the first well region, the fifth implant region has the second conductivity type, the sixth implant region is formed in the second well region, and the sixth implant region has the second conductivity type; wherein the fifth implant region is used to be connected with a PAD port of the chip, the sixth implant region is used to be grounded, a parasitic diode can be formed through the first deep well region and the third deep well region and turned on, the first implant region, the first deep well region and the third deep well region form a parasitic PNP triode, so that a large amount of negative charges input by the fifth implant region are released to the ground through the first implant region and the third implant region, and thus a good protection effect can be achieved when a negative ESD occurs.

[0015] In order to make the above objectives, characteristics and advantages of the application more apparent, the following will describe a preferred embodiment in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the application, the following will briefly introduce the drawings needed to be used in the embodiments. It should be understood that the following drawings only show some of the embodiments of the application, and therefore should not be regarded as a limitation to the scope. For those skilled in the art, other related drawings can also be obtained without creative labor.

[0017] Figure 1 A sectional view of an electrostatic discharge protection device provided by the embodiments of the application;

[0018] Figure 2 An equivalent circuit diagram of an electrostatic discharge protection device provided by the embodiments of the application.

[0019] Reference signs:

[0020] The first deep well region 10, the third deep well region 11, the first well region 12, the fifth injection region 13, the first injection region 14, the second injection region 15, the second deep well region 20, the fourth deep well region 21, the second well region 22, the sixth injection region 23, the fourth injection region 24, the third injection region 25, the semiconductor substrate 30, and the fifth deep well region 40. DETAILED DESCRIPTION

[0021] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the following will briefly describe the technical solutions in the embodiments of the present application with reference to the accompanying drawings. Obviously, the described embodiments are only a part instead of all of the embodiments of the present application. The components of the embodiments of the present application described and shown in the accompanying drawings can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. Based on the embodiments of the present application, every other embodiment obtained by a person skilled in the art without creative work falls within the scope of the present application.

[0022] First, the application scenarios applicable to the present application are introduced. The present application can be applied to electrostatic discharge protection (or ESD path) of a chip.

[0023] In the field of chips, an excellent electrostatic discharge (ESD) path is very important for protecting the safety of a port. Generally, the working voltage of the port is higher than the ground potential (0V) of the chip, that is, positive voltage input, and the ESD path between the port and the ground needs to ensure that there is no leakage current of the port under a certain positive voltage. However, in some power control chips, the port voltage can be higher or lower than the ground potential (0V), that is, both positive voltage input and negative voltage input exist. At this time, the ESD structure needs to withstand the positive or negative voltage input of the port and meet the ESD protection level requirements. In the general ESD protection design, the main requirement is for positive voltage resistance, and the design of a structure that can meet both positive and negative voltages is less common. The current general ESD design scheme focuses on positive voltage design, and the negative voltage is generally considered to be around (-0.7V) to (-2V). However, for high-voltage chips used in industry, due to the complexity of working conditions, the input negative voltage range is wider, and can even reach -40V. Therefore, the conventional ESD negative voltage range is too low and cannot meet the use requirements.

[0024] Based on this, the embodiments of the present application provide an electrostatic discharge protection device, an equivalent circuit, and a chip.

[0025] Please refer to Figure 1 , Figure 1A cross-sectional view of an electrostatic discharge protection device is provided in embodiments of the present application. Figure 1 As shown in the figure, the electrostatic discharge protection device provided by the embodiments of the present application includes a first deep well region 10 and a second deep well region 20, a third deep well region 11 and a fourth deep well region 21, a first implant region 14 and a second implant region 15, a third implant region 25 and a fourth implant region 24, a first well region 12 and a second well region 22, a fifth implant region 13 and a sixth implant region 23, a fifth deep well region 40 and a semiconductor substrate 30. The first deep well region 10 and the second deep well region 20 are formed in the semiconductor substrate 30, and the first deep well region 10 and the second deep well region 20 have a first conductivity type. The third deep well region 11 is formed in the first deep well region 10, and the third deep well region 11 has a second conductivity type. The fourth deep well region 21 is formed in the second deep well region 20, and the fourth deep well region 21 has a second conductivity type. The first implant region 14 and the second implant region 15 are formed in the first deep well region 10, and the first implant region 14 and the second implant region 15 have different conductivity types. The third implant region 25 and the fourth implant region 24 are formed in the second deep well region 20, and the third implant region 25 and the fourth implant region 24 have different conductivity types, and the conductivity type of the third implant region 25 is the same as that of the first implant region 14. The first well region 12 is formed in the third deep well region 11, and the first well region 12 has a second conductivity type. The second well region 22 is formed in the fourth deep well region 21, and the second well region 22 has a second conductivity type. The fifth implant region 13 is formed in the first well region 12, and the fifth implant region 13 has a second conductivity type. The sixth implant region 23 is formed in the second well region 22, and the sixth implant region 23 has a second conductivity type. The fifth deep well region 40 is formed in the semiconductor substrate 30, and the fifth deep well region 40 is arranged between the first deep well region 10 and the second deep well region 20, and the fifth deep well region 40 has a second conductivity type. The fifth implant region 13 is used to connect with a PAD port of a chip, and the sixth implant region 23 is used for grounding.

[0026] Specifically, the third deep well region 11 is arranged on a side of the first deep well region 10 away from the fifth deep well region 40, and the fourth deep well region 21 is arranged on a side of the second deep well region 20 away from the fifth deep well region 40. The first implant region 14 has a second conductivity type, and the second implant region 15 has a first conductivity type. The second implant region 15 is arranged on a side close to the fifth deep well region 40, the first implant region 14 is adjacent to the second implant region 15, and the first implant region 14 is located between the second implant region 15 and the third deep well region 11. The third implant region 25 has a second conductivity type, and the fourth implant region 24 has a first conductivity type. The fourth implant region 24 is arranged on a side close to the fifth deep well region 40, the third implant region 25 is adjacent to the fourth implant region 24, and the third implant region 25 is located between the fourth implant region 24 and the fourth deep well region 21. The semiconductor substrate 30 has a second conductivity type. The first conductivity type is N type, and the second conductivity type is P type.

[0027] like Figure 1 The electrostatic discharge protection device shown comprises the following: the first injection region 14, the fifth injection region 13, and the fourth injection region 24 are P-type injection regions (Pdiff); the second injection region 15, the third injection region 25, and the sixth injection region 23 are N-type injection regions (Ndiff); the first deep well region 10 and the second deep well region 20 are N-type deep well regions (DNwell); the third deep well region 11, the fourth deep well region 21, and the fifth deep well region 40 are P-type deep well regions (DPwell); and the first well region 12 and the second well region 22 are P-type well regions (Pwell). The semiconductor substrate 30 is a P-type substrate (PSUB).

[0028] When the electrostatic discharge protection device is working, the fifth injection region 13 (D1) is connected to the level input port, such as the PAD port of the chip, and the sixth injection region 23 (D2) is grounded. G1, G2, S1, and S2 are shorted together. Here, G represents the gate, S represents the source, and D represents the base. At this time, the fifth injection region 13, the first well region 12, and the third deep well region 11 are at the same potential; the sixth injection region 23, the second well region 22, and the fourth deep well region 21 are at the same potential; and because S1 and S2 are shorted, the first deep well region 10, the first injection region 14, the second injection region 15, the second deep well region 20, the fourth injection region 24, and the third injection region 25 are at the same potential.

[0029] When the input voltage at D1 is a normal operating positive voltage, the PN junction formed by the first deep well region 10 and the third deep well region 11 is conducting, and the potential of the first deep well region 10 is approximately equal to the potential of the third deep well region 11. The PN junction formed by the first deep well region 10 and the semiconductor substrate 30 is reverse-biased and cut off. The PN junction formed by the second deep well region 20 and the semiconductor substrate 30 is also reverse-biased and cut off. The PN junction formed by the second deep well region 20 and the fourth deep well region 21 is also reverse-biased and cut off. When the input voltage is less than the reverse breakdown voltage of the PN junction, there is no DC path from D1 to ground, and only a very small reverse leakage current exists.

[0030] When the input voltage at D1 is a negative voltage during normal operation, the PN junction formed by the first deep well region 10 and the third deep well region 11 is reverse-biased and cut off. The PN junctions formed by the semiconductor substrate 30 and the first deep well region 10, the semiconductor substrate 30 and the second deep well region 20, and the fourth deep well region 21 and the second deep well region 20 are sequentially turned on. The potentials of the first deep well region 10 and the second deep well region 20 are approximately equal to ground. When the input voltage is less than the reverse breakdown voltage of the PN junction, there is no DC path from D1 to ground, and only a very small reverse leakage current exists.

[0031] Understandably, the electrostatic discharge protection device here is a port ESD structure based on HVPMOS that can withstand both positive and negative high voltages. During normal operation, regardless of whether the input port is positive or negative, this ESD circuit has no DC path to ground, and only a very small diode reverse leakage current exists.

[0032] When a forward ESD occurs at the PAD port to ground, the parasitic diode formed by the second deep well region 20 and the fourth deep well region 21 breaks down in reverse, and current begins to flow. This causes the parasitic PNP transistor formed by the fourth injection region 24, the second deep well region 20, and the fourth deep well region 21 to conduct, and a large amount of positive charge is quickly released to ground through the channel via the second deep well region 20 and the fourth deep well region 21.

[0033] When a negative ESD occurs at the PAD port to ground, the parasitic diode formed by the first deep well region 10 and the third deep well region 11 breaks down in reverse, and current begins to flow. This causes the parasitic PNP transistor formed by the first injection region 14, the first deep well region 10, and the third deep well region 11 to conduct, and a large amount of negative charge is quickly released to ground through the channel via the first injection region 14 and the third deep well region 11.

[0034] Even in the event of positive or negative ESD, this electrostatic discharge protection device can still provide protection. The electrostatic discharge protection device provided in this application supports a port input voltage range of -40V to 100V. Compared with existing electrostatic discharge protection devices that support port input negative voltages concentrated between (-0.7V) and (-2V), this device can support both positive and negative port input voltages, thus meeting the operating conditions of high-voltage chips used in industry.

[0035] like Figure 2 As shown, Figure 2 This is an equivalent circuit diagram of an electrostatic discharge protection device provided in an embodiment of this application. The electrostatic discharge protection device is as described above. The equivalent circuit of the electrostatic discharge protection device includes a first MOSFET and a second MOSFET. The gate of the first MOSFET is connected to the gate of the second MOSFET, the source of the first MOSFET is connected to the source of the second MOSFET, the source of the first MOSFET is also connected to the gate of the second MOSFET, the base of the first MOSFET is connected to the base of the second MOSFET, and the source of the first MOSFET is also connected to the base of the second MOSFET.

[0036] Specifically, the drain of the first MOS tube is connected with the PAD port of the chip, and the drain of the second MOS tube is grounded. Wherein, the fifth implant region 13 is the drain of the first MOS tube, the third deep well region 11 and the first deep well region 10 are the gate of the first MOS tube, the first implant region 14 and the second implant region 15 are the source of the first MOS tube. The sixth implant region 23 is the drain of the second MOS tube, the second deep well region 20 and the fourth deep well region 21 are the gate of the second MOS tube, and the third implant region 25 and the fourth implant region 24 are the source of the second MOS tube.

[0037] Wherein, Figure 2 PM1 in the formula is the first MOS tube, PM2 is the second MOS tube, PAD is the PAD port of the chip, and GND is the ground.

[0038] The ESD structure realized based on the HVPMOS in the scheme can not only meet the functional requirements of positive and negative voltage inputs, but also far exceed the general ESD breakdown voltage value at the lower limit of negative voltage input and the upper limit of positive voltage input.

[0039] In an embodiment of the present application, a chip is also provided, and the PAD port of the chip is connected with the electrostatic discharge protection device according to any one of the embodiments.

[0040] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the system, device and unit described above can refer to the corresponding process in the foregoing method embodiments, which will not be repeated here.

[0041] In the several embodiments provided by the present application, it should be understood that the disclosed system, device and method can be implemented in other ways. The device embodiments described above are only schematic. For example, the division of the units is only a logical function division, and there can be another division manner in actual implementation. Also, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections between the units can be indirect couplings or communication connections through some interfaces, devices or units, and can be electrical, mechanical or in other forms.

[0042] The units described as separate components can or can not be physically separate, and the components displayed as units can or can not be physical units, that is, they can be located in one place, or can be distributed on a plurality of network units. According to actual needs, some or all of the units can be selected to achieve the purpose of the embodiment scheme.

[0043] In addition, each function unit in each embodiment of the present application can be integrated in one processing unit, or each unit can be physically present separately, or two or more units can be integrated in one unit.

[0044] If the functions are realized in the form of software function units and sold or used as independent products, they can be stored in a nonvolatile computer readable storage medium executable by a processor. Based on this understanding, the technical solutions of the present application or the part of the present application that essentially contributes to the prior art or the part of the technical solutions of the present application can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The foregoing storage medium includes a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various program code storage media.

[0045] Finally, it should be noted that the above-described embodiments are merely specific embodiments of the present application, which are used to illustrate the technical solutions of the present application, but not to limit the same. The protection scope of the present application is not limited thereto, although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any skilled person familiar with the technical field can modify or easily think of changes to the technical solutions recorded in the foregoing embodiments within the technical range disclosed by the present application, or replace some technical features with equivalent ones; and these modifications, changes or replacements do not make the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. An electrostatic discharge protection device, characterized by, The device comprises: a first deep well region and a second deep well region, the first deep well region and the second deep well region being formed in a semiconductor substrate, the first deep well region and the second deep well region having a first conductivity type; a third deep well region and a fourth deep well region, the third deep well region being formed in the first deep well region, the third deep well region having a second conductivity type, the fourth deep well region being formed in the second deep well region, the fourth deep well region having a second conductivity type; a first implant region and a second implant region, the first implant region and the second implant region being formed in the first deep well region, the first implant region and the second implant region having different conductivity types; a third implant region and a fourth implant region, the third implant region and the fourth implant region being formed in the second deep well region, the third implant region and the fourth implant region having different conductivity types, the third implant region having the same conductivity type as the first implant region; a first well region and a second well region, the first well region being formed in the third deep well region, the first well region having the second conductivity type, the second well region being formed in the fourth deep well region, the second well region having the second conductivity type; a fifth implant region and a sixth implant region, the fifth implant region being formed in the first well region, the fifth implant region having the second conductivity type, the sixth implant region being formed in the second well region, the sixth implant region having the second conductivity type; wherein the fifth implant region is configured to be connected to a PAD port of a chip, and the sixth implant region is configured to be grounded.

2. The apparatus of claim 1, wherein, Further comprising: a fifth deep well region, the fifth deep well region being formed in the semiconductor substrate, and the fifth deep well region being disposed between the first deep well region and the second deep well region, the fifth deep well region having the second conductivity type.

3. The apparatus of claim 2, wherein, The third deep well region is disposed on a side of the first deep well region away from the fifth deep well region, and the fourth deep well region is disposed on a side of the second deep well region away from the fifth deep well region.

4. The apparatus of claim 3, wherein, The first implant region has the second conductivity type, the second implant region has the first conductivity type, the second implant region is disposed on a side close to the fifth deep well region, the first implant region is adjacent to the second implant region, and the first implant region is located between the second implant region and the third deep well region. The third implant region has the second conductivity type, the fourth implant region has the first conductivity type, the fourth implant region is disposed on a side close to the fifth deep well region, the third implant region is adjacent to the fourth implant region, and the third implant region is located between the fourth implant region and the fourth deep well region.

5. The apparatus of claim 1, wherein, The semiconductor substrate has the second conductivity type.

6. The apparatus of claim 1, wherein, The first conductivity type is N-type, and the second conductivity type is P-type.

7. An equivalent circuit of an electrostatic discharge protection device, characterized by, The electrostatic discharge protection device is the electrostatic discharge protection device of any one of claims 1 to 6, and an equivalent circuit of the electrostatic discharge protection device comprises: a first MOS transistor and a second MOS transistor, a gate of the first MOS transistor is connected with a gate of the second MOS transistor, a source of the first MOS transistor is connected with a source of the second MOS transistor, and the source of the first MOS transistor is also connected with the gate of the second MOS transistor, a drain of the first MOS transistor is connected with a PAD port of the chip, and a drain of the second MOS transistor is grounded.

8. The equivalent circuit of claim 7, wherein, the fifth implantation region is used as a drain of the first MOS transistor, the third deep well region and the first deep well region are used as a gate of the first MOS transistor, and the first implantation region and the second implantation region are used as a source of the first MOS transistor; the sixth implantation region is used as a drain of the second MOS transistor, the second deep well region and the fourth deep well region are used as a gate of the second MOS transistor, and the third implantation region and the fourth implantation region are used as a source of the second MOS transistor.

9. A chip, characterized by The chip comprises the electrostatic discharge protection device according to any one of claims 1 to 6.

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