Adaptive on-time control circuit for DC-DC converter, and DC-DC converter

Abstract

Embodiments of the present disclosure provide an adaptive on-time control circuit for a DC-DC converter, which includes: a freewheeling diode exit current limiting detection circuit, a timing start control circuit, an adaptive timing circuit, and a conduction control signal generation circuit. The freewheeling diode exit current limiting detection circuit generates a first pulse signal according to the valley current limiting indication signal of the DC-DC converter and the power transistor conduction control signal of the DC-DC converter. The timing start control circuit generates a timing control signal according to the first pulse signal, the valley current limiting indication signal, and the timing arrival pulse signal output by the adaptive timing circuit. The adaptive timing circuit starts timing when the timing control signal indicates the start of timing, determines the timing duration according to the input voltage and output voltage of the DC-DC converter, and provides a timing arrival pulse signal when the timing duration is reached. The conduction control signal generation circuit generates a conduction control signal according to the timing arrival pulse signal, the first pulse signal, and the clock signal.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of integrated circuit technology, and more particularly, to an adaptive on-time control circuit for a DC-DC converter and a DC-DC converter. Background Art

[0002] With the rapid development of the integrated circuit industry and the increasing expansion of the analog integrated circuit market, DC-DC (direct current to direct current) converters have received extensive attention and rapid development. As a high-efficiency switching power supply technology, DC-DC converters have the advantages of fast dynamic response, simple control, and direct control of output current. In a DC-DC converter, a power transistor and a freewheeling diode conduct alternately to control the charging and discharging of an inductor in the DC-DC converter, thereby achieving a stable output of the DC-DC converter. A current detection circuit may be provided in the DC-DC converter. When the inductor current flowing through the inductor is too large, the charging of the inductor can be stopped by controlling the power transistor and the freewheeling diode. Charging of the inductor is allowed again when the inductor current drops to the valley current limit value. In this way, the function of overcurrent protection can be achieved. Summary of the Invention

[0003] Embodiments described herein provide an adaptive on-time control circuit for a DC-DC converter and a DC-DC converter.

[0004] According to a first aspect of the present disclosure, there is provided an adaptive on-time control circuit for a DC-DC converter. The adaptive on-time control circuit includes: a freewheeling diode exit current limit detection circuit, a timing start control circuit, an adaptive timing circuit, and a conduction control signal generation circuit. Among them, the freewheeling diode exit current limit detection circuit is configured to: generate a first pulse signal according to the valley current limit indication signal of the DC-DC converter and the power transistor conduction control signal of the DC-DC converter, and provide the first pulse signal to the timing start control circuit and the conduction control signal generation circuit via a first node. The timing start control circuit is configured to: generate a timing control signal according to the first pulse signal, the valley current limit indication signal, and the timing arrival pulse signal output by the adaptive timing circuit, and provide the timing control signal to the adaptive timing circuit via a second node. The adaptive timing circuit is configured to: start timing when the timing control signal indicates the start of timing, determine the timing duration according to the input voltage and output voltage of the DC-DC converter, and provide a timing arrival pulse signal to the timing start control circuit and the conduction control signal generation circuit via a third node when the timing duration is reached. The conduction control signal generation circuit is configured to: generate a conduction control signal according to the timing arrival pulse signal, the first pulse signal, and the clock signal from the clock signal terminal.

[0005] In some embodiments of the present disclosure, the clock signal has a fixed frequency.

[0006] In some embodiments of the present disclosure, the freewheeling diode current limiting detection circuit includes: a first monostable flip-flop and a NAND gate. The input terminal of the first monostable flip-flop is provided with a valley current limiting indication signal. The output terminal of the first monostable flip-flop is coupled to the first input terminal of the NAND gate. The second input terminal of the NAND gate is provided with a power transistor conduction control signal. The output terminal of the NAND gate is coupled to the first node. The first monostable flip-flop is triggered at the rising edge of the valley current limiting indication signal from the first level to the second level to generate a second pulse signal.

[0007] In some embodiments of the present disclosure, the pulse width of the second pulse signal is equal to the period of the clock signal.

[0008] In some embodiments of the present disclosure, the timing start control circuit includes: a first OR gate. The first input terminal of the first OR gate is coupled to the third node. The second input terminal of the first OR gate is coupled to the first node. The third input terminal of the first OR gate is provided with a valley current limiting indication signal. The output terminal of the first OR gate is coupled to the second node.

[0009] In some embodiments of the present disclosure, the adaptive timing circuit includes: a capacitor, a first transistor, a second transistor, a third transistor, a fourth transistor, a first error amplifier, a first resistor, a voltage comparator, and a second monostable flip-flop. The first end of the capacitor is coupled to the first input terminal of the voltage comparator and the second pole of the first transistor. The second end of the capacitor is coupled to the first pole of the first transistor and the second voltage terminal. The control pole of the first transistor is coupled to the second node. The control pole of the second transistor is coupled to the control pole and the second pole of the third transistor. The first pole of the second transistor is coupled to the first voltage terminal. The second pole of the second transistor is coupled to the first end of the capacitor. The first pole of the third transistor is coupled to the first voltage terminal. The second pole of the third transistor is coupled to the second pole of the fourth transistor. The control pole of the fourth transistor is coupled to the output terminal of the first error amplifier. The first pole of the fourth transistor is coupled to the first end of the first resistor. The second end of the first resistor is coupled to the second voltage terminal. The first input terminal of the first error amplifier EA1 is coupled to the output voltage terminal of the DC-DC converter. The second input terminal of the first error amplifier EA1 is coupled to the first pole of the fourth transistor. The second input terminal of the voltage comparator is provided with the voltage difference between the output voltage and the input voltage of the DC-DC converter. The output terminal of the voltage comparator is coupled to the input terminal of the second monostable flip-flop. The output terminal of the second monostable flip-flop is coupled to the third node. The second monostable flip-flop is triggered at the rising edge of the output signal of the voltage comparator from the second level to the first level to generate a timing arrival pulse signal.

[0010] In some embodiments of the present disclosure, the pulse width of the timing arrival pulse signal is determined according to the discharge speed of the capacitor.

[0011] In some embodiments of the present disclosure, the conduction control signal generation circuit includes: an AND gate and a second OR gate. Among them, the first input terminal of the AND gate is coupled to the first node. The second input terminal of the AND gate is coupled to the clock signal terminal. The output terminal of the AND gate is coupled to the first input terminal of the second OR gate. The second input terminal of the second OR gate is coupled to the third node.

[0012] According to a second aspect of the present disclosure, an adaptive on-time control circuit for a DC-DC converter is provided. The adaptive on-time control circuit includes: a first monostable flip-flop, a NAND gate, a first OR gate, a capacitor, a first transistor, a second transistor, a third transistor, a fourth transistor, a first error amplifier, a first resistor, a voltage comparator, a second monostable flip-flop, an AND gate, and a second OR gate. Among them, the input terminal of the first monostable flip-flop is provided with a valley current limit indication signal of the DC-DC converter. The output terminal of the first monostable flip-flop is coupled to the first input terminal of the NAND gate. The first monostable flip-flop is triggered at the rising edge of the valley current limit indication signal from the first level to the second level to generate a second pulse signal. The second input terminal of the NAND gate is provided with a power transistor conduction control signal of the DC-DC converter. The output terminal of the NAND gate is coupled to the second input terminal of the first OR gate. The first input terminal of the first OR gate is coupled to the output terminal of the second monostable flip-flop. The third input terminal of the first OR gate is provided with a valley current limit indication signal. The output terminal of the first OR gate is coupled to the control electrode of the first transistor. The first end of the capacitor is coupled to the first input terminal of the voltage comparator and the second electrode of the first transistor. The second end of the capacitor is coupled to the first electrode of the first transistor and the second voltage terminal. The control electrode of the second transistor is coupled to the control electrode and the second electrode of the third transistor. The first electrode of the second transistor is coupled to the first voltage terminal. The second electrode of the second transistor is coupled to the first end of the capacitor. The first electrode of the third transistor is coupled to the first voltage terminal. The second electrode of the third transistor is coupled to the second electrode of the fourth transistor. The control electrode of the fourth transistor is coupled to the output terminal of the first error amplifier. The first electrode of the fourth transistor is coupled to the first end of the first resistor. The second end of the first resistor is coupled to the second voltage terminal. The first input terminal of the first error amplifier is coupled to the output voltage terminal of the DC-DC converter. The second input terminal of the first error amplifier is coupled to the first electrode of the fourth transistor. The second input terminal of the voltage comparator is provided with a voltage difference between the output voltage and the input voltage of the DC-DC converter. The output terminal of the voltage comparator is coupled to the input terminal of the second monostable flip-flop. The output terminal of the second monostable flip-flop is coupled to the second input terminal of the second OR gate. The second monostable flip-flop is triggered at the rising edge of the output signal of the voltage comparator from the second level to the first level to generate a timing arrival pulse signal. The first input terminal of the AND gate is coupled to the output terminal of the NAND gate. The second input terminal of the AND gate is coupled to the clock signal terminal. The output terminal of the AND gate is coupled to the first input terminal of the second OR gate.

[0013] According to a third aspect of the present disclosure, a DC-DC converter is provided, including: the adaptive on-time control circuit according to the first aspect or the second aspect of the present disclosure.

[0014] In some embodiments of the present disclosure, the DC-DC converter is a boost converter. Description of the Drawings

[0015] To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the accompanying drawings of the embodiments will be briefly described below. It should be understood that the following-described accompanying drawings only relate to some embodiments of the present disclosure and do not limit the present disclosure, where:

[0016] Figure 1 is an exemplary circuit diagram of a DC-DC converter;

[0017] Figure 2 is for Figure 1 a timing diagram of some signals of the DC-DC converter shown;

[0018] Figure 3 is an exemplary circuit diagram of a DC-DC converter according to an embodiment of the present disclosure;

[0019] Figure 4 is a schematic block diagram of an adaptive on-time control circuit according to an embodiment of the present disclosure;

[0020] Figure 5 is an exemplary circuit diagram of an adaptive on-time control circuit according to an embodiment of the present disclosure; and

[0021] Figure 6 is for Figure 3 a timing diagram of some signals of the DC-DC converter shown.

[0022] In the accompanying drawings, labels with the same last two digits correspond to the same elements. It should be noted that the elements in the accompanying drawings are schematic and not drawn to scale. Detailed Embodiments

[0023] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of the present disclosure without creative efforts shall also fall within the scope of protection of the present disclosure.

[0024] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which the subject matter of this disclosure belongs. Further will be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the specification and the relevant art, and will not be interpreted in an idealized or overly formal form unless expressly defined otherwise herein. As used herein, a statement that two or more parts are "connected" or "coupled" together shall mean that these parts are directly joined together or joined through one or more intermediate components.

[0025] In all embodiments of the present disclosure, since the source and drain (emitter and collector) of a transistor are symmetric, and the conduction current directions between the source and drain (emitter and collector) of an N-type transistor and a P-type transistor are opposite, thus in the embodiments of the present disclosure, the controlled intermediate terminal of the transistor is referred to as the control electrode, and the remaining two terminals of the transistor are respectively referred to as the first electrode and the second electrode. The transistors employed in the embodiments of the present disclosure are mainly switching transistors. Additionally, terms such as "first" and "second" are only used to distinguish one component (or a part of a component) from another component (or another part of a component).

[0026] Figure 1 An exemplary circuit diagram of a DC-DC converter 100 is shown. The DC-DC converter 100 is a fixed-frequency valley current mode boost converter. The DC-DC converter 100 includes: an error amplifier EA, a PWM comparator CP1, a capacitor Cc, a resistor Rc, a resistor Rs, a transistor MN2, a current source I, an AND gate AND2, an inverter NG, a first RS flip-flop LH1, a second RS flip-flop LH2, a freewheeling diode MH, a power transistor ML, an inductor L, an output capacitor Cout, and a minimum on-time control circuit. Figure 1 A load resistor Rload is also shown.

[0027] In Figure 1In the example, the error amplifier EA generates an error signal eaout based on the output voltage Vout of the DC-DC converter 100 and the reference voltage VREF. The error signal eaout is provided to the inverting input terminal of the PWM comparator CP1. The non-inverting input terminal of the PWM comparator CP1 is coupled to the current source I and the resistor Rs via the node sum. The current value of the current source I is Idc - Isns, where Idc represents the constant current value and Isns represents the value of the inductor current flowing through the inductor L. When the power transistor conduction control signal LG is at a high level, the transistor MN2 conducts, and the voltage at the node sum is pulled down to ground. Therefore, the PWM signal output by the PWM comparator CP1 is at a low level. Thus, the output signal MAIN_TRIP of the AND gate AND2 is at a low level. After the minimum conduction time, when the clock signal CLK flips to a high level, both the freewheeling diode conduction control signal HG output by the first RS flip-flop LH1 and the power transistor conduction control signal LG output by the second RS flip-flop LH2 become low levels, thereby turning on the freewheeling diode MH and turning off the power transistor ML. The inductor L discharges, and the inductor current flowing through the inductor L gradually decreases. At this time, since the power transistor conduction control signal LG is at a low level, the transistor MN2 is cut off, and the current provided by the current source I flows through the resistor Rs, thereby forming a voltage at the node sum. The voltage at the node sum becomes (Idc - Isns) × Rs, where Rs represents the resistance value of the resistor Rs. When the voltage at the node sum is greater than the voltage value of the error signal eaout, the PWM signal output by the PWM comparator CP1 is at a high level.

[0028] In Figure 1 the example, the valley current limit indication signal is represented by LIM. When the inductor current drops and is equal to or lower than the valley current limit value, the valley current limit indication signal LIM is at a low level. In other cases, the valley current limit indication signal LIM is at a high level. When the valley current limit indication signal LIM is at a low level, the waveform of the output signal MAIN_TRIP of the AND gate AND2 follows the waveform of the PWM signal.

[0029] When the output signal MAIN_TRIP of the AND gate AND2 is at a high level, both the freewheeling diode conduction control signal HG output by the first RS flip-flop LH1 and the power transistor conduction control signal LG output by the second RS flip-flop LH2 become high levels, thereby turning on the power transistor ML and turning off the freewheeling diode MH, and the inductor L is charged, and the inductor current flowing through the inductor L gradually increases.

[0030] When the current of the freewheeling diode MH is higher than the valley current limit value (the valley current limit indication signal LIM is at a high level), even if the clock signal CLK flips to a high level, the on / off states of the freewheeling diode MH and the power transistor ML cannot be changed. The freewheeling diode MH can be turned off and the power transistor ML can be turned on only when the current of the freewheeling diode MH drops below the valley current limit value.

[0031] In Figure 1 's example, the clock signal CLK is supplied to the minimum on-time control circuit. The minimum on-time control circuit can control the power transistor ML to be turned off by the clock signal CLK at a high level only after experiencing the minimum on-time.

[0032] Figure 2 illustrates the Figure 1 timing diagram of some signals for the DC-DC converter 100 shown in Figure 2 . The following describes Figure 1 the operation process of the DC-DC converter 100 shown in

[0033] Starting from the moment t2, after experiencing the minimum on-time ton, at this time (i.e., at the moment t3), if the clock signal CLK just flips to a high level, the power transistor ML is immediately turned off. In this way, as Figure 2 shown, the waveform of the inductor current IL will exhibit a periodic large / small wave phenomenon.

[0034] By increasing the minimum on-time of the boost converter, the above-mentioned large and small wave problems can be alleviated, but this will affect the minimum duty cycle of the boost converter, so it is not a good solution. The above-mentioned large and small wave problems can be alleviated by setting a fixed on-time for the power transistor ML, and it will not affect the minimum duty cycle of the boost converter. However, the fixed on-time of the power transistor ML cannot change with the change of the application scenario after being set. For example, the input voltage of the DC-DC converter 100 may gradually decrease during use. When the input voltage of the DC-DC converter 100 decreases, the time for the inductor current to rise from the valley current limit value to the peak current limit value will become longer, that is, the normal rising slope of the inductor current will become smaller. However, the preset fixed on-time will make the rising time of the inductor current during the fixed on-time unchanged, that is, the inductor current will start to decrease before rising to the peak current limit value. Therefore, the large and small wave problems will appear again in the inductor current.

[0035] Embodiments of the present disclosure propose a DC-DC converter. Figure 3 An exemplary circuit diagram of a DC-DC converter 300 according to an embodiment of the present disclosure is shown. Relative to Figure 1 the shown DC-DC converter 100, Figure 3 the shown DC-DC converter 300 replaces the minimum on-time control circuit in Figure 1 with an adaptive on-time control circuit 310. The adaptive on-time control circuit 310 is configured to: start timing when the inductor current drops to the valley current limit value VY_LIM, and turn off the power transistor ML and turn on the freewheeling transistor MH when the timing reaches the adaptive on-time. The adaptive on-time can change with the change of the input voltage of the DC-DC converter 300. In this way, the waveform of the inductor current can be regular and there will be no large and small wave phenomena due to the clock signal CLK turning high or the input voltage changing.

[0036] Figure 4 A schematic block diagram of an adaptive on-time control circuit 410 according to an embodiment of the present disclosure is shown. The adaptive on-time control circuit 410 may include: a freewheeling transistor dropout current limit detection circuit 411, a timing start control circuit 412, an adaptive timing circuit 413, and a turn-on control signal generation circuit 414.

[0037] The output terminal of the freewheeling diode exit current limiting detection circuit 411 can be coupled to the first input terminal of the timing start control circuit 412 and the first input terminal of the conduction control signal generation circuit 414 via the first node N1. The freewheeling diode exit current limiting detection circuit 411 can also be provided with the valley current limiting indication signal LIM of the DC-DC converter 300 and the power transistor conduction control signal LG of the DC-DC converter 300. The freewheeling diode exit current limiting detection circuit 411 can be configured to: generate a first pulse signal LIM_SHOTB according to the valley current limiting indication signal LIM and the power transistor conduction control signal LG, and provide the first pulse signal LIM_SHOTB to the timing start control circuit 412 and the conduction control signal generation circuit 414 via the first node N1.

[0038] The first input terminal of the timing start control circuit 412 can be coupled to the output terminal of the freewheeling diode exit current limiting detection circuit 411 and the first input terminal of the conduction control signal generation circuit 414 via the first node N1. The second input terminal of the timing start control circuit 412 can be coupled to the output terminal of the adaptive timing circuit 413 and the second input terminal of the conduction control signal generation circuit 414 via the third node N3. The output terminal of the timing start control circuit 412 can be coupled to the input terminal of the adaptive timing circuit 413 via the second node N2. The timing start control circuit 412 can be provided with the valley current limiting indication signal LIM of the DC-DC converter 300. The timing start control circuit 412 can be configured to: generate a timing control signal according to the first pulse signal LIM_SHOTB, the valley current limiting indication signal LIM, and the timing arrival pulse signal Ton_SHOT output by the adaptive timing circuit 413, and provide the timing control signal to the adaptive timing circuit 413 via the second node N2.

[0039] The input terminal of the adaptive timing circuit 413 may be coupled to the output terminal of the timing start control circuit 412 via the second node N2. The output terminal of the adaptive timing circuit 413 may be coupled to the second input terminal of the timing start control circuit 412 and the second input terminal of the conduction control signal generation circuit 414 via the third node N3. The input terminal of the adaptive timing circuit 413 may also be coupled to the input voltage terminal Vin and the output voltage terminal Vout of the DC-DC converter 300. The adaptive timing circuit 413 may be configured to: start timing when the timing control signal indicates the start of timing, determine the timing duration according to the input voltage Vin and the output voltage Vout of the DC-DC converter 300, and provide a timing arrival pulse signal Ton_SHOT to the timing start control circuit 412 and the conduction control signal generation circuit 414 via the third node N3 when the timing duration is reached. In some embodiments of the present disclosure, the start of timing is indicated when the timing control signal flips from a high level to a low level. In some embodiments of the present disclosure, the timing duration may be determined according to the voltage difference between the input voltage Vin and the output voltage Vout of the DC-DC converter 300.

[0040] The first input terminal of the conduction control signal generation circuit 414 may be coupled to the output terminal of the freewheeling diode dropout current limiting detection circuit 411 via the first node N1. The second input terminal of the conduction control signal generation circuit 414 may be coupled to the output terminal of the adaptive timing circuit 413 and the second input terminal of the timing start control circuit 412 via the third node N3. The conduction control signal generation circuit 414 may also be coupled to the clock signal terminal CLK. The conduction control signal generation circuit 414 may be configured to: generate a conduction control signal CTL according to the timing arrival pulse signal Ton_SHOT, the first pulse signal LIM_SHOTB, and the clock signal CLK from the clock signal terminal CLK. The conduction control signal CTL may be output from the output terminal of the conduction control signal generation circuit 414.

[0041] In some embodiments of the present disclosure, the clock signal CLK has a fixed frequency. The pulse width of the first pulse signal LIM_SHOTB is equal to the period of the clock signal CLK.

[0042] Figure 6 Shows for Figure 3 The timing diagram of some signals of the DC-DC converter 300 shown below. In combination with Figure 3 , Figure 4 And Figure 6To describe the operating principle of the adaptive on-time control circuit 410. At time t2, the inductor current drops to the valley current limit value VY_LIM, and the valley current limit indication signal LIM becomes low. The output signal MAIN_TRIP of the AND gate AND2 becomes high, so that the power transistor conduction control signal LG becomes high. Therefore, the power transistor ML conducts, and the inductor current IL starts to rise. Since the power transistor conduction control signal LG becomes high, the transistor MN2 conducts, and the voltage of the node sum is pulled down to ground. At this time, the PWM signal becomes low. Therefore, the output signal MAIN_TRIP of the AND gate AND2 becomes low.

[0043] The freewheeling diode exit current limit detection circuit 411 generates a first pulse signal LIM_SHOTB according to the valley current limit indication signal LIM and the power transistor conduction control signal LG. The first pulse signal LIM_SHOTB may have a low-level pulse to indicate that the freewheeling diode MH exits the current limit state. The timing start control circuit 412 generates a low-level timing control signal according to the first pulse signal LIM_SHOTB with a low-level pulse, the valley current limit indication signal LIM in the low level, and the timing arrival pulse signal Ton_SHOT in the low level. The timing control signal triggers the adaptive timing circuit 413 to start timing. The first pulse signal LIM_SHOTB with a low-level pulse can control the conduction control signal generation circuit 414 not to be controlled by the clock signal CLK, so as to output a low-level conduction control signal CTL. Since the output signal MAIN_TRIP of the AND gate AND2 and the conduction control signal CTL are both in the low level, the freewheeling diode MH and the power transistor ML both maintain their previous states, and the inductor current IL continues to rise.

[0044] At time t4, when the timing duration ton_new is reached, the adaptive timing circuit 413 outputs a timing arrival pulse signal Ton_SHOT with a high-level pulse. The timing arrival pulse signal Ton_SHOT with a high-level pulse can cause the timing control signal output by the timing start control circuit 412 to flip to the high level, thereby controlling the reset of the adaptive timing circuit 413 and causing the conduction control signal CTL generated by the conduction control signal generation circuit 414 to flip to the high level. The conduction control signal CTL in the high level can cause the power transistor conduction control signal LG to become low, thereby turning off the power transistor ML and turning on the freewheeling diode MH.

[0045] The timing duration ton_new can be set to the normal on-time of the DC-DC converter 300, that is, ton_new = (1 - Vin / Vout) × Tsw. Wherein, Vin represents the voltage value of the input voltage of the DC-DC converter 300, Vout represents the voltage value of the output voltage of the DC-DC converter 300, and Tsw represents the period of the PWM signal.

[0046] In this way, the adaptive on-time control circuit 410 can control the inductor current of the DC-DC converter 300 to be regular, and the phenomenon of large and small waves will not occur.

[0047] Figure 5 An exemplary circuit diagram of an adaptive on-time control circuit according to an embodiment of the present disclosure is shown. The freewheeling diode dropout current limit detection circuit 511 may include: a first monostable flip-flop 5111 and a NAND gate NAND1. Among them, the input terminal of the first monostable flip-flop 5111 is provided with a valley current limit indication signal LIM. The output terminal of the first monostable flip-flop 5111 is coupled to the first input terminal of the NAND gate NAND1. The second input terminal of the NAND gate NAND1 is provided with a power transistor on-control signal LG. The output terminal of the NAND gate NAND1 is coupled to the first node N1. The first monostable flip-flop 5111 is triggered at the falling edge of the valley current limit indication signal LIM from the first level to the second level to generate a second pulse signal LIM_FD. In some embodiments of the present disclosure, the second pulse signal LIM_FD has a high-level pulse. The pulse width of the second pulse signal LIM_FD is equal to the period of the clock signal CLK. The first level is a high level, the second level is a low level, and the falling edge from the first level to the second level is a falling edge. The first monostable flip-flop 5111 is a falling-edge triggered monostable flip-flop.

[0048] The timing start control circuit 512 may include: a first OR gate OR1. Among them, the first input terminal of the first OR gate OR1 is coupled to the third node N3. The second input terminal of the first OR gate OR1 is coupled to the first node N1. The third input terminal of the first OR gate OR1 is provided with a valley current limit indication signal LIM. The output terminal of the first OR gate OR1 is coupled to the second node N2.

[0049] The adaptive timing circuit 513 may include: a capacitor Con, a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a first error amplifier EA1, a first resistor R1, a voltage comparator COMP, and a second monostable flip-flop 5131. Among them, the first end of the capacitor Con is coupled to the first input terminal of the voltage comparator COMP and the second pole of the first transistor M1. The second end of the capacitor Con is coupled to the first pole of the first transistor M1 and the second voltage terminal V2. The control pole of the first transistor M1 is coupled to the second node N2. The control pole of the second transistor M2 is coupled to the control pole and the second pole of the third transistor M3. The first pole of the second transistor M2 is coupled to the first voltage terminal V1. The second pole of the second transistor M2 is coupled to the first end of the capacitor Con. The first pole of the third transistor M3 is coupled to the first voltage terminal V1. The second pole of the third transistor M3 is coupled to the second pole of the fourth transistor M4. The control pole of the fourth transistor M4 is coupled to the output terminal of the first error amplifier EA1. The first pole of the fourth transistor M4 is coupled to the first end of the first resistor R1. The second end of the first resistor R1 is coupled to the second voltage terminal V2. The first input terminal of the first error amplifier EA1 is coupled to the output voltage terminal Vout of the DC-DC converter. The second input terminal of the first error amplifier EA1 is coupled to the first pole of the fourth transistor M4. The second input terminal of the voltage comparator COMP is provided with the voltage difference (Vout-Vin) between the output voltage Vout and the input voltage Vin of the DC-DC converter. In one example, the voltage difference (Vout-Vin) between the output voltage Vout and the input voltage Vin can be obtained by inputting the output voltage Vout and the input voltage Vin into a subtractor. The output terminal of the voltage comparator COMP is coupled to the input terminal of the second monostable flip-flop 5131. The output terminal of the second monostable flip-flop 5131 is coupled to the third node N3. The second monostable flip-flop 5131 is triggered at the rising edge of the output signal Ton_END of the voltage comparator COMP from the second level to the first level to generate a timing arrival pulse signal Ton_SHOT.

[0050] In some embodiments of the present disclosure, the timing arrival pulse signal Ton_SHOT has a high-level pulse. The pulse width of the timing arrival pulse signal Ton_SHOT is determined according to the discharge speed of the capacitor Con. It should be ensured that the conduction time of the first transistor M1 is sufficient to completely release the charge of the capacitor Con. The first level is the high level, the second level is the low level, and the rising edge from the second level to the first level is the rising edge. The second monostable flip-flop 5131 is a rising-edge-triggered monostable flip-flop.

[0051] The conduction control signal generation circuit 514 may include: an AND gate AND1 and a second OR gate OR2. Among them, the first input terminal of the AND gate AND1 is coupled to the first node N1. The second input terminal of the AND gate AND1 is coupled to the clock signal CLK terminal. The output terminal of the AND gate AND1 is coupled to the first input terminal of the second OR gate OR2. The second input terminal of the second OR gate OR2 is coupled to the third node N3. The output terminal of the second OR gate OR2 is coupled to the reset terminal R of the first RS flip-flop LH1 and the second RS flip-flop LH2.

[0052] In Figure 5 the example, a high voltage is input from the first voltage terminal V1, and the second voltage terminal V2 is grounded. The first input terminal of the voltage comparator COMP is the non-inverting input terminal. The second input terminal of the voltage comparator COMP is the inverting input terminal. The first input terminal of the first error amplifier EA1 is the non-inverting input terminal. The second input terminal of the first error amplifier EA1 is the inverting input terminal. The first transistor M1 and the fourth transistor M4 are N-type transistors. The second transistor M2 and the third transistor M3 are P-type transistors. Those skilled in the art should understand that based on the above inventive concept, the Figure 5 circuit shown in Figure 5 should also fall within the protection scope of the present disclosure. In this variant, the above transistors and voltage terminals may also have settings different from those in the

[0053] example shown in Figure 3 、 Figure 5 and Figure 6 The working principle of the adaptive conduction time control circuit 510 will be described below in conjunction with

[0054] The falling edge of the valley current limit indication signal LIM triggers the first monostable flip-flop 5111 to generate a second pulse signal LIM_FD with a high-level pulse. At this time, the power transistor conduction control signal LG is at a high level. Therefore, the NAND gate NAND1 generates a first pulse signal LIM_SHOTB with a low-level pulse. When all three inputs of the first OR gate OR1 are at a low level, the first OR gate OR1 outputs a timing control signal at a low level. The timing control signal causes the first transistor M1 to turn off, and the current flowing through the second transistor M2 starts to charge the capacitor Con. The current flowing through the second transistor M2 is equal to the current converted from the output voltage Vout by the first error amplifier EA1, the fourth transistor M4, and the first resistor R1, that is, Vout / R1. Here, R1 represents the resistance value of the first resistor R1. A ramp signal RAMP is generated at the first end of the capacitor Con. At the same time, the first pulse signal LIM_SHOTB with a low-level pulse enables the AND gate AND1 to maintain a low-level output within the pulse width of the first pulse signal LIM_SHOTB. In this way, during this period, the conduction control signal generation circuit 514 is not controlled by the clock signal CLK and can output a low-level conduction control signal CTL. Since both the output signal MAIN_TRIP of the AND gate AND2 and the conduction control signal CTL are at a low level, the freewheeling diode MH and the power transistor ML both maintain their previous states, and the inductor current IL continues to rise.

[0055] At time t4, the timing duration ton_new is reached, and the voltage value of the ramp signal RAMP rises to (Vout - Vin), and the output signal Ton_END of the voltage comparator COMP flips to a high level. The rising edge of the output signal Ton_END triggers the second monostable flip-flop 5131 to output a timing arrival pulse signal Ton_SHOT with a high-level pulse. The timing arrival pulse signal Ton_SHOT with a high-level pulse enables the first OR gate OR1 to output a high-level timing control signal to turn on the first transistor M1, and enables the conduction control signal CTL output by the second OR gate OR2 to flip to a high level. After the first transistor M1 is turned on, the capacitor Con starts to discharge, and the ramp signal RAMP drops below (Vout - Vin). Therefore, the output signal Ton_END of the voltage comparator COMP flips to a low level. Since the timing arrival pulse signal Ton_SHOT output by the second monostable flip-flop 5131 will remain at a high level for a period of time, it can control the first transistor M1 to remain turned on for a period of time, so that the capacitor Con can be fully discharged. The conduction control signal CTL at a high level enables the power transistor conduction control signal LG to become a low level, thereby turning off the power transistor ML and turning on the freewheeling diode MH.

[0056] The timing duration ton_new can be set as the normal conduction time of the DC-DC converter 300, i.e., ton_new = (1 - Vin / Vout) × Tsw. Wherein, Vin represents the voltage value of the input voltage of the DC-DC converter 300, Vout represents the voltage value of the output voltage of the DC-DC converter 300, and Tsw represents the period of the PWM signal.

[0057] According to the internal structure of the adaptive timing circuit 513, it can be obtained that:

[0058]

[0059] Wherein, Con represents the capacitance value of the capacitor Con, and R1 represents the resistance value of the first resistor R1. Therefore, by setting Con×R1 = Tsw, it can be made that

[0060]

[0061] In this way, the adaptive conduction time control circuit 510 can control the inductor current of the DC-DC converter 300 to be regular without the phenomenon of large and small waves.

[0062] In summary, the adaptive conduction time control circuit for a DC-DC converter according to an embodiment of the present disclosure can generate a conduction control signal, and the conduction control signal can force the power transistor of the DC-DC converter to turn off the power transistor and turn on the freewheeling diode only after the adaptive conduction time. The adaptive conduction time can change with the change of the input voltage, so it can be applied to more application scenarios. Due to the adoption of the adaptive conduction time control circuit according to an embodiment of the present disclosure, the waveform of the inductor current of the DC-DC converter according to an embodiment of the present disclosure is regular and will not have the phenomenon of large and small waves due to the change of the input voltage.

[0063] Unless otherwise clearly indicated in the context, the singular forms of the words used in this text and the appended claims include the plural, and vice versa. Thus, when referring to the singular, the corresponding plural of the term is usually included. Similarly, the terms "comprising" and "including" will be interpreted as inclusive rather than exclusive. Likewise, the terms "including" and "or" should be interpreted as inclusive, unless such an interpretation is explicitly prohibited in this text. Where the term "example" is used in this text, especially when it is located after a group of terms, the "example" is merely exemplary and illustrative and should not be considered exclusive or extensive.

[0064] Further aspects and scope of adaptability will become apparent from the description provided herein. It should be understood that the various aspects of the present application can be implemented alone or in combination with one or more other aspects. It should also be understood that the description and specific embodiments herein are for illustrative purposes only and are not intended to limit the scope of the present application.

[0065] The above has described several embodiments of the present disclosure in detail. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The protection scope of the present disclosure is defined by the appended claims.

Claims

1. An adaptive on-time control circuit for a DC-DC converter, comprising: A freewheeling diode dropout current limiting detection circuit, a timing start control circuit, an adaptive timing circuit, and a conduction control signal generation circuit, wherein the freewheeling diode dropout current limiting detection circuit is configured to: generate a first pulse signal according to the valley current limiting indication signal of the DC-DC converter and the power transistor conduction control signal of the DC-DC converter, and provide the first pulse signal to the timing start control circuit and the conduction control signal generation circuit via a first node; the timing start control circuit is configured to: generate a timing control signal according to the first pulse signal, the valley current limiting indication signal, and the timing arrival pulse signal output by the adaptive timing circuit, and provide the timing control signal to the adaptive timing circuit via a second node; the adaptive timing circuit is configured to: start timing when the timing control signal indicates the start of timing, determine the timing duration according to the input voltage and output voltage of the DC-DC converter, and provide the timing arrival pulse signal to the timing start control circuit and the conduction control signal generation circuit via a third node when the timing duration is reached; the conduction control signal generation circuit is configured to: generate a conduction control signal according to the timing arrival pulse signal, the first pulse signal, and the clock signal from the clock signal terminal.

2. The adaptive turn-on time control circuit according to claim 1, wherein The clock signal has a fixed frequency.

3. The adaptive turn-on time control circuit according to claim 2, wherein The freewheeling diode dropout current limiting detection circuit includes: a first monostable flip-flop and a NAND gate, wherein the input terminal of the first monostable flip-flop is provided with the valley current limiting indication signal, and the output terminal of the first monostable flip-flop is coupled to the first input terminal of the NAND gate; the second input terminal of the NAND gate is provided with the power transistor conduction control signal, and the output terminal of the NAND gate is coupled to the first node; The first monostable flip-flop is triggered at the rising edge of the valley current limiting indication signal from the first level to the second level to generate a second pulse signal.

4. The adaptive turn-on time control circuit according to claim 3, wherein, The pulse width of the second pulse signal is equal to the period of the clock signal.

5. The adaptive turn-on time control circuit according to any one of claims 1 to 4, wherein, The timing start control circuit includes: a first OR gate, wherein the first input terminal of the first OR gate is coupled to the third node, the second input terminal of the first OR gate is coupled to the first node, the third input terminal of the first OR gate is provided with the valley current limiting indication signal, and the output terminal of the first OR gate is coupled to the second node.

6. The adaptive turn-on time control circuit according to any one of claims 1 to 4, wherein, The adaptive timing circuit includes: a capacitor, a first transistor, a second transistor, a third transistor, a fourth transistor, a first error amplifier, a first resistor, a voltage comparator, and a second monostable flip-flop, wherein the first end of the capacitor is coupled to the first input terminal of the voltage comparator and the second pole of the first transistor, and the second end of the capacitor is coupled to the first pole of the first transistor and a second voltage terminal; The control pole of the first transistor is coupled to the second node; The control pole of the second transistor is coupled to the control pole and the second pole of the third transistor, the first pole of the second transistor is coupled to a first voltage terminal, and the second pole of the second transistor is coupled to the first end of the capacitor; The first pole of the third transistor is coupled to the first voltage terminal, and the second pole of the third transistor is coupled to the second pole of the fourth transistor; The control pole of the fourth transistor is coupled to the output terminal of the first error amplifier, and the first pole of the fourth transistor is coupled to the first end of the first resistor; The second end of the first resistor is coupled to the second voltage terminal; The first input terminal of the first error amplifier is coupled to the output voltage terminal of the DC-DC converter, and the second input terminal of the first error amplifier is coupled to the first pole of the fourth transistor; The second input terminal of the voltage comparator is provided with the voltage difference between the output voltage of the DC-DC converter and the input voltage, and the output terminal of the voltage comparator is coupled to the input terminal of the second monostable flip-flop; The output terminal of the second monostable flip-flop is coupled to the third node; The second monostable flip-flop is triggered at the rising edge of the output signal of the voltage comparator from the second level to the first level to generate the timing arrival pulse signal.

7. The adaptive turn-on time control circuit according to claim 6, wherein, The pulse width of the timing arrival pulse signal is determined according to the discharge speed of the capacitor.

8. The adaptive turn-on time control circuit according to any one of claims 1 to 4, wherein, The turn-on control signal generation circuit includes: an AND gate and a second OR gate, wherein, the first input terminal of the AND gate is coupled to the first node, the second input terminal of the AND gate is coupled to the clock signal terminal, and the output terminal of the AND gate is coupled to the first input terminal of the second OR gate; The second input terminal of the second OR gate is coupled to the third node.

9. An adaptive on-time control circuit for a DC-DC converter, comprising: A first monostable flip-flop, a NAND gate, a first OR gate, a capacitor, a first transistor, a second transistor, a third transistor, a fourth transistor, a first error amplifier, a first resistor, a voltage comparator, a second monostable flip-flop, an AND gate, and a second OR gate, wherein, the input terminal of the first monostable flip-flop is provided with the valley current limit indication signal of the DC-DC converter, the output terminal of the first monostable flip-flop is coupled to the first input terminal of the NAND gate, and the first monostable flip-flop is triggered at the rising edge of the valley current limit indication signal from the first level to the second level to generate a second pulse signal; The second input terminal of the NAND gate is provided with the power transistor turn-on control signal of the DC-DC converter, and the output terminal of the NAND gate is coupled to the second input terminal of the first OR gate; The first input terminal of the first OR gate is coupled to the output terminal of the second monostable flip-flop, the third input terminal of the first OR gate is provided with the valley current limit indication signal, and the output terminal of the first OR gate is coupled to the control pole of the first transistor; The first end of the capacitor is coupled to the first input terminal of the voltage comparator and the second pole of the first transistor, and the second end of the capacitor is coupled to the first pole of the first transistor and the second voltage terminal; The control pole of the second transistor is coupled to the control pole and the second pole of the third transistor, the first pole of the second transistor is coupled to the first voltage terminal, and the second pole of the second transistor is coupled to the first end of the capacitor; The first pole of the third transistor is coupled to the first voltage terminal, and the second pole of the third transistor is coupled to the second pole of the fourth transistor; The control pole of the fourth transistor is coupled to the output terminal of the first error amplifier, and the first pole of the fourth transistor is coupled to the first end of the first resistor; The second end of the first resistor is coupled to the second voltage terminal; The first input terminal of the first error amplifier is coupled to the output voltage terminal of the DC-DC converter, and the second input terminal of the first error amplifier is coupled to the first pole of the fourth transistor; The second input terminal of the voltage comparator is provided with the voltage difference between the output voltage and the input voltage of the DC-DC converter, and the output terminal of the voltage comparator is coupled to the input terminal of the second monostable flip-flop; The output terminal of the second monostable flip-flop is coupled to the second input terminal of the second OR gate; The second monostable flip-flop is triggered at the rising edge of the output signal of the voltage comparator from the second level to the first level to generate a timing arrival pulse signal; The first input terminal of the AND gate is coupled to the output terminal of the NAND gate, the second input terminal of the AND gate is coupled to the clock signal terminal, and the output terminal of the AND gate is coupled to the first input terminal of the second OR gate.

10. A DC-DC converter, comprising: The adaptive on-time control circuit according to any one of claims 1 to 9.

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