MMC submodule topology for DC fault current blocking and its working method

Abstract

The invention belongs to the technical field of MMC submodules, and proposes an MMC submodule topology for blocking direct current fault current and a working method thereof, comprising a first insulated gate bipolar transistor, a second insulated gate bipolar transistor connected to the first insulated gate bipolar transistor, a third diode connected to the second insulated gate bipolar transistor, and a fourth insulated gate bipolar transistor connected to the third diode; a capacitor is arranged between the first insulated gate bipolar transistor and the fourth insulated gate bipolar transistor; on the basis of a proposed novel submodule topology structure, the third insulated gate bipolar transistor T3 is removed to obtain an improved novel topology, compared with the proposed novel submodule topology and other topologies with direct current short-circuit current absorption capability, one power switch device is reduced, and the cost is reduced; at the same time, considering that the switching frequency of the MMC is low, the added diode does not need to have a fast recovery time, and the withstand voltage level of the improved novel topology can be the same as that of the proposed novel submodule topology and the like.

Description

Technical Field

[0001] The invention belongs to the technical field of MMC submodules, and in particular relates to an MMC submodule topology for DC fault current blocking and a working method thereof. Background Art

[0002] Existing modular multilevel converter (MMC) submodule topologies include half-bridge submodules, half-bridge derivative submodules, and typical full-bridge submodules with DC side bipolar short-circuit fault current blocking capability.

[0003] The inventors found that if Figure 1 As shown, a novel submodule topology structure with DC short-circuit fault current blocking capability proposed in the prior art includes a first insulated gate bipolar transistor (IGBT) T1, a second insulated gate bipolar transistor T2, a third insulated gate bipolar transistor T3 and a fourth insulated gate bipolar transistor T4; wherein the third insulated gate bipolar transistor T3 is mainly used to provide a bypass path by the diode D3 when in a cut-off state, and to force current to flow through the capacitor when a DC side fault occurs. Therefore, during the operation of the submodule topology, the third insulated gate bipolar transistor T3 of the anti-parallel third diode D3 is idle and wasted. Summary of the invention

[0004] In order to solve the above problems, the present invention proposes an MMC submodule topology for DC fault current blocking and a working method thereof, wherein the insulated gate bipolar transistor T3 is removed to obtain an improved new topology, which reduces one power switching device and reduces the cost compared with the proposed new submodule topology and other topologies with DC short-circuit current absorption capability, and considering that the MMC switching frequency is low, the added diode does not need to have a fast recovery time, and the withstand voltage level of the improved new topology can be the same as that of the proposed new submodule topology and the like.

[0005] In order to achieve the above objectives, in a first aspect, the present invention provides an MMC submodule topology for DC fault current blocking, which adopts the following technical solution:

[0006] An MMC submodule topology for DC fault current blocking, comprising a first insulated gate bipolar transistor, a second insulated gate bipolar transistor connected to the first insulated gate bipolar transistor, a third diode connected to the second insulated gate bipolar transistor, and a fourth insulated gate bipolar transistor connected to the third diode; a capacitor is provided between the first insulated gate bipolar transistor and the fourth insulated gate bipolar transistor;

[0007] An emitter of the second insulated gate bipolar transistor is connected to an anode of the third diode, and an emitter of the third diode is connected to a collector of the fourth insulated gate bipolar transistor.

[0008] Further, the emitter of the first insulated gate bipolar transistor is connected to the collector of the second insulated gate bipolar transistor.

[0009] Furthermore, a first diode, a second diode and a fourth diode are respectively connected in anti-parallel to the first insulated gate bipolar transistor, the second insulated gate bipolar transistor and the fourth insulated gate bipolar transistor.

[0010] Furthermore, a fifth diode is connected in parallel to a series branch between the capacitor and the first insulated gate bipolar transistor, and a sixth diode is connected in parallel to a series branch between the capacitor and the fourth insulated gate bipolar transistor.

[0011] Furthermore, the anode of the fifth diode is connected to the negative electrode of the capacitor, and the cathode is connected to the emitter of the first insulated gate bipolar transistor; the anode of the sixth diode is connected to the collector of the fourth insulated gate bipolar transistor, and the cathode is connected to the anode of the capacitor.

[0012] In order to achieve the above object, in a second aspect, the present invention further provides an MMC submodule topology working method for DC fault current blocking, which adopts the following technical solution:

[0013] A MMC submodule topology working method for DC fault current blocking adopts the MMC submodule topology for DC fault current blocking as described in any one of claims 1-5, including: when the DC side bipolar short circuit occurs, the current flows through a path from a sixth diode to a capacitor and then to a fifth diode, providing reverse voltage to the circuit and absorbing the short-circuit current into the capacitor.

[0014] Furthermore, if the first insulated gate bipolar transistor and the fourth insulated gate bipolar transistor remain in the on state, and the second insulated gate bipolar transistor remains in the off state, the current flows through the first diode in the forward direction and flows through the first insulated gate bipolar transistor in the reverse direction, and the sub-module provides a capacitor voltage to the bridge arm where it is located. At this time, the sub-module is in the on state.

[0015] Further, if the second insulated gate bipolar transistor and the fourth insulated gate bipolar transistor remain in the on state, and the first insulated gate bipolar transistor remains in the off state, the current flows through the second insulated gate bipolar transistor and the third diode in the forward direction, and flows through the fourth insulated gate bipolar transistor and the fifth diode in the reverse direction, the sub-module provides zero voltage to the bridge arm where it is located, and the sub-module is in the cut-off state at this time.

[0016] Furthermore, if the fourth insulated gate bipolar transistor remains in the on state, the first insulated gate bipolar transistor and the second insulated gate bipolar transistor remain in the off state, the current flows through the first diode and the fourth diode in the forward direction, and flows through the fourth insulated gate bipolar transistor and the fifth diode in the reverse direction; when the current is forward, the sub-module provides a capacitor voltage to the bridge arm where it is located, and provides zero voltage in the reverse direction. At this time, the sub-module state is a redundant state.

[0017] Furthermore, if the first insulated gate bipolar transistor, the second insulated gate bipolar transistor and the fourth insulated gate bipolar transistor are all kept in the disconnected state, the current flows through the first diode and the fourth diode in the forward direction, and flows through the sixth diode and the fifth diode in the reverse direction; when the current is forward, the sub-module provides a capacitor voltage to the bridge arm where it is located, and provides a negative capacitor voltage in the reverse direction, and at this time the sub-module state is a locked state.

[0018] Compared with the prior art, the present invention has the following beneficial effects:

[0019] 1. In the present invention, based on the proposed new submodule topology structure, the third insulated gate bipolar transistor T3 is removed to obtain an improved new topology. Compared with the proposed new submodule topology and other topologies with DC short-circuit current absorption capability, one power switch device is reduced, and the cost is reduced. Meanwhile, considering that the MMC switching frequency is low, the added diode does not need to have a fast recovery time, and the withstand voltage level of the improved new topology can be the same as that of the proposed new submodule topology;

[0020] 2. The present invention models a new improved submodule converter station (ESM-MMC) and a conventional submodule converter station (H-MMC), and performs simulation verification under normal operation and DC bipolar short-circuit faults; through simulation experiment comparison, it can be verified that the performance of the proposed new ESM submodule topology under normal operating conditions is effective. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The drawings in the specification that constitute a part of this embodiment are used to provide a further understanding of this embodiment. The schematic embodiments of this embodiment and their descriptions are used to explain this embodiment and do not constitute improper limitations on this embodiment.

[0022] Figure 1 This is a schematic diagram of the topology of a novel submodule proposed in Embodiment 1 of the present invention;

[0023] Figure 2 This is a schematic diagram of the improved submodule structure of Example 1 of the present invention;

[0024] Figure 3 The AC and DC current flow paths after full-pole locking of the H converter station in embodiment 1 of the present invention;

[0025] Figure 4 The HD submodule of Embodiment 1 of the present invention;

[0026] Figure 5 It is a DC fault current flow path after the HD submodule is locked in embodiment 1 of the present invention;

[0027] Figure 6 The AC and DC current flow paths after full-pole locking of the F converter station in Example 1 of the present invention;

[0028] Figure 7 It is the forward flow path of the submodule current when the embodiment 1 of the present invention is in the input state;

[0029] Figure 8 It is a reverse flow path of the submodule current when in the input state of embodiment 1 of the present invention;

[0030] Fig. 9 It is the forward flow path of the submodule current in the cut-off state of the embodiment 1 of the present invention;

[0031] Fig.10 It is a reverse flow path of the submodule current in the cut-off state of the first embodiment of the present invention;

[0032] Fig.11 The forward flow path of the submodule current in the redundant state of the first embodiment of the present invention;

[0033] Fig.12 The forward flow path of the submodule current in the redundant state of the first embodiment of the present invention;

[0034] Fig.13 It is the forward flow path of the submodule current in the locked state of the first embodiment of the present invention;

[0035] Fig.14 It is the forward flow path of the submodule current in the locked state of the first embodiment of the present invention;

[0036] Fig.15 It is the simulation model of embodiment 1 of the present invention;

[0037] Fig.16 Schematic diagram of coordinates of Example 1 of the present invention;

[0038] Fig.17 This is a block diagram of the inner loop control of Embodiment 1 of the present invention;

[0039] Fig.18 This is a block diagram of an outer loop controller according to Embodiment 1 of the present invention;

[0040] Fig.19 is the H-MMC differential mode voltage of embodiment 1 of the present invention;

[0041] Fig. 20is the ESM-MMC differential mode voltage of embodiment 1 of the present invention;

[0042] Fig.21 For Example 1 of the present invention Fig.19 The dotted line enlarges the waveform;

[0043] Fig. 22 For Example 1 of the present invention Fig. 20 The dotted line enlarges the waveform;

[0044] Fig.23 is the H-MMC three-phase alternating current of Example 1 of the present invention;

[0045] Fig.24 is the ESM-MMC three-phase alternating current of Example 1 of the present invention;

[0046] Fig.25 For Example 1 of the present invention Fig.23 The dotted line enlarges the waveform;

[0047] Fig.26 For Example 1 of the present invention Fig.24 The dotted line enlarges the waveform;

[0048] Fig. 27 The H-MMC A-phase AC voltage and current of Example 1 of the present invention;

[0049] Fig.28 The ESM-MMC A-phase AC voltage and current of Example 1 of the present invention;

[0050] Fig.29 is the capacitor voltage of the upper bridge arm submodule of the H-MMC in Embodiment 1 of the present invention;

[0051] Fig.30 is the capacitor voltage of the upper bridge arm submodule of the ESM-MMC in Example 1 of the present invention;

[0052] Fig.31 is the DC side voltage of the H-MMC in Example 1 of the present invention;

[0053] Fig.32 is the DC side voltage of the ESM-MMC in Example 1 of the present invention;

[0054] Fig.33 The H-MMC DC current waveform during a DC bipolar short circuit fault in Example 1 of the present invention;

[0055] Fig.34 The ESM-MMC DC current waveform during a DC bipolar short circuit fault in Example 1 of the present invention;

[0056] Fig.35 For Example 1 of the present invention Fig.33The dotted part is the enlarged waveform;

[0057] Fig.36 For Example 1 of the present invention Fig.34 The dotted part is the enlarged waveform;

[0058] Fig.37 For Example 1 of the present invention Fig.33 The dotted line part is the enlarged waveform;

[0059] Fig.38 For Example 1 of the present invention Fig.34 The dotted line part is the enlarged waveform;

[0060] Fig.39 The waveform of the H-MMC three-phase AC current when a DC bipolar short circuit fault occurs in Example 1 of the present invention;

[0061] Fig.40 The waveform of the three-phase AC current of the ESM-MMC during a DC bipolar short circuit fault in Example 1 of the present invention;

[0062] Fig.41 is the capacitor voltage of the H-MMC submodule in Example 1 of the present invention;

[0063] Fig.42 It is the capacitor voltage of the ESM-MMC submodule in Example 1 of the present invention. DETAILED DESCRIPTION

[0064] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0065] It should be noted that the following detailed descriptions are exemplary and are intended to provide further explanation of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same meanings as those commonly understood by those skilled in the art to which the present application belongs.

[0066] The converter station with a half-bridge submodule (Half Bridge SM) is an H converter station, the converter station with a half-bridge derived submodule (Half Bridge Derived SM) is an HD converter station, and the converter station with a full-bridge submodule (Full Bridge SM) is an F converter station.

[0067] Embodiment 1:

[0068] like Figure 2As shown, this embodiment provides an MMC submodule topology for DC fault current blocking, including a first insulated gate bipolar transistor T1, a second insulated gate bipolar transistor T2 connected to the first insulated gate bipolar transistor T1, a third diode D3 connected to the second insulated gate bipolar transistor T2, and a fourth insulated gate bipolar transistor T4 connected to the third diode D3; a capacitor C is provided between the first insulated gate bipolar transistor T1 and the fourth insulated gate bipolar transistor T4;

[0069] Specifically, the emitter of the first insulated gate bipolar transistor T1 is connected to the collector of the second insulated gate bipolar transistor T2; the emitter of the second insulated gate bipolar transistor T2 is connected to the anode of the third diode D3, and the emitter of the third diode D3 is connected to the collector of the fourth insulated gate bipolar transistor T4; the first insulated gate bipolar transistor T1, the second insulated gate bipolar transistor T2 and the fourth insulated gate bipolar transistor T4 are respectively anti-parallel-connected with a first diode D1, a second diode D2 and a fourth diode D4.

[0070] A fifth diode D5 is connected in parallel to the series branch between the capacitor C and the first insulated gate bipolar transistor T1, and a sixth diode D6 is connected in parallel to the series branch between the capacitor C and the fourth insulated gate bipolar transistor T4. Specifically, the anode of the fifth diode D5 is connected to the negative electrode of the capacitor C, and the cathode is connected to the emitter of the first insulated gate bipolar transistor T1; the anode of the sixth diode D6 is connected to the collector of the fourth insulated gate bipolar transistor T4, and the cathode is connected to the anode of the capacitor C.

[0071] After a bipolar short-circuit fault occurs on the DC side, due to the inherent detection and judgment time and protection action time of the system, the operating status of the entire system can be divided into two stages: the stage from the occurrence of the fault to the lockout stage of the converter station and the post-lockout stage. The period from the occurrence of the fault to the lockout stage of the converter station is a process in which the system continues to operate according to the original normal operating conditions. Since the sub-modules of the HD converter station and the F converter station operate according to the half-bridge sub-module operation principles during normal operation, there is no difference in this stage. In essence, a bipolar short-circuit fault on the DC side is equivalent to an instantaneous surge in load. The converter station control system faces a large deviation from the static operating point in a very short time, causing the original controller parameters to no longer meet the stability requirements, resulting in the system losing stability. The sub-module capacitor discharges through the short-circuit point on the DC side to generate a fault current, causing the sub-module capacitor voltage to continue to decrease until the start of the lockout stage; such as Figure 3As shown, after the lockout, all submodule control signals of the converter station disappear, causing the converter station to be locked as a whole. For the H converter station, at this time, the DC fault current only flows through the diode D2 in the upper and lower bridge arms of each phase. Therefore, for the AC side, it is equivalent to being grounded through two parallel bridge arm inductors L0. The AC side current changes to a short-circuit current in a short time, so that the DC fault is transmitted to the AC side. At the same time, after the converter station is locked, it evolves into a diode uncontrolled rectifier circuit, which will continuously provide feed energy to the short-circuit point. There is no natural arc extinction point for the DC side fault current, so there will be no time node for the converter station to change its working condition, that is, the DC side bipolar short-circuit fault cannot be automatically cleared. In the existing fault handling method, the short-circuit energy source is often cleared by disconnecting the AC circuit breaker, but the mechanical breaking mechanism of the AC circuit breaker makes the action time too long, making it difficult to effectively deal with such faults.

[0072] like Figure 4 and Figure 5 As shown in the figure, similar to the half-bridge sub-module, the half-bridge derivative sub-module does not essentially change the fault development process of the converter station in the post-blocking stage. It only shares the fault current flowing through the diode D2 by triggering the bypass thyristor (SCR) during the fault. Therefore, it does not have the DC bipolar short-circuit fault current blocking capability.

[0073] Unlike the H and HB converter stations, the fault current of the F converter station will flow through the submodule capacitor after blocking, which provides a physical mechanism for the submodule to naturally block the fault current. Figure 5 As shown in the figure, when the F converter station enters the locked state, the DC side fault current flow path is the diode D3, capacitor C and diode D2 of the full-bridge sub-module. Therefore, the sub-module capacitor voltage will gradually increase and provide a reverse voltage to the AC energy feeding circuit. When it increases to a certain value, the fault current path will be completely blocked.

[0074] like Figure 1 As shown, this embodiment uses the mechanism of blocking the bipolar short-circuit fault current on the DC side to propose a new sub-module topology, and provides a normal operation mechanism and a bipolar short-circuit fault current blocking mechanism on the DC side, and makes a certain degree of improvement in combination with actual needs, so that it has better economy and practicality; the proposed topology is composed of three N-channel IGBTs with anti-parallel diodes and one P-channel IGBT with anti-parallel diodes plus two discrete diode devices and a capacitor, which does not have an economic advantage over the sub-module. The working principle and all possible operating states of the proposed new sub-module topology are as follows:

[0075] like Figure 7 and Figure 8As shown, if the first insulated gate bipolar transistor T1 and the fourth insulated gate bipolar transistor T4 remain in the ON state, the second insulated gate bipolar transistor T2 and the third insulated gate bipolar transistor T3 remain in the OFF state, the current flows through the first diode D1 in the forward direction and flows through the first insulated gate bipolar transistor T1 in the reverse direction, and the sub-module provides a capacitor voltage to the bridge arm where it is located, then the sub-module state at this time can be defined as the input state.

[0076] like Fig. 9 and Fig.10 As shown, if the second insulated gate bipolar transistor T2 and the fourth insulated gate bipolar transistor T4 remain in the on state, the first insulated gate bipolar transistor T4 and the third insulated gate bipolar transistor T3 remain in the off state, the current flows through the second insulated gate bipolar transistor T2 and the third diode D3 in the forward direction, and flows through the fourth insulated gate bipolar transistor T4 and the fifth diode D5 in the reverse direction, and the sub-module provides zero voltage to the bridge arm where it is located, then the sub-module state at this time can be defined as a cut-off state.

[0077] If the third insulated gate bipolar transistor T3 and the fourth insulated gate bipolar transistor T4 remain in the on state, and the first insulated gate bipolar transistor T1 and the second insulated gate bipolar transistor T2 remain in the off state, the current flows through the first diode D1 and the fourth diode D4 in the forward direction, and there are two parallel branches in the reverse direction, one flows through the fourth insulated gate bipolar transistor T4 switch tube and the fifth diode D5 diode, and the other flows through the third insulated gate bipolar transistor T3 and the second diode D2 diode; when the current is forward, the sub-module provides a capacitor voltage to the bridge arm where it is located, and provides zero voltage in the reverse direction. This state is not needed during normal operation, so the sub-module state can be defined as a redundant state at this time.

[0078] If all the insulated gate bipolar transistors remain in the off state, the current flows through the first diode D1 and the fourth diode D4 in the forward direction, and flows through the sixth diode D6 and the fifth diode D5 in the reverse direction; when the current is forward, the sub-module provides a capacitor voltage to the bridge arm where it is located, and provides a negative capacitor voltage in the reverse direction. At this time, the state of the sub-module can be defined as a locked state.

[0079] In summary, the third insulated gate bipolar transistor T3 is mainly used to provide a bypass path for D3 in the cut-off state, and to force the current to flow through the capacitor when a DC side fault occurs; thus, the third insulated gate bipolar transistor T3 can be removed to obtain an improved new topology, such as Figure 2 shown.

[0080] When the bipolar short circuit occurs on the DC side, the new submodule improved topology (Enhanced Half Bridge SM, ESM) flows through the sixth diode D6-capacitor C-fifth diode D5, thereby providing reverse voltage to the circuit and absorbing the short circuit current into the submodule capacitor, accelerating the arc extinction of the DC fault current. Compared with the proposed new submodule topology and other topologies with the ability to absorb DC short circuit current, one power switch device is reduced, reducing the cost. At the same time, considering the low switching frequency of MMC, the added diode does not need to have a fast recovery time, and its withstand voltage level can be the same as that of the proposed new submodule topology.

[0081] In other embodiments, a new improved submodule converter station (ESM-MMC) is modeled, and simulation verification is performed under normal operation and DC bipolar short circuit fault; the simulation model is as follows: Fig.15 shown.

[0082] To facilitate subsequent processing, Fig.15 The names of the variables used in the model and their physical meanings are summarized in Table 1. The switching cycle average mathematical model after carrier phase shift modulation modeling is obtained, and the controller design and control parameter selection are carried out on this basis.

[0083] Table 1 Simulation model parameters

[0084]

[0085]

[0086]

[0087]

[0088]

[0089]

[0090] It should be noted that formulas 1 to 3 describe the mathematical model that considers the external characteristics of the MMC converter and the dynamic characteristics of the total capacitance voltage of the bridge arm under the carrier phase shift modulation strategy, and have been averaged over the switching cycle, that is, each physical quantity in the formula represents its average value in a switching cycle. Under the carrier phase shift modulation strategy, all submodules of the same bridge arm use the same modulation wave. jx , j+1 represents the next phase obtained by phase j in the positive sequence direction, and the positive sequence directions are a, b and c. The average value of the differential mode voltage switching cycle in formula (2) is obtained by eliminating the voltage between OU and the voltage between OL from the original equation under the condition of three-phase symmetry on the AC side, which will not be repeated here.

[0091] The approximate analytical solution of the above mathematical model obtained by the principle of successive approximation of the pickup truck can prove that there is no DC component in the steady state formula (3) and company (4), that is, the MMC converter using the carrier phase shift modulation strategy has the ability of self-balancing the bridge arm energy and the sub-module voltage, so no additional voltage control strategy is adopted for it. If the sub-module capacitor voltage fluctuation is ignored (taking the zero-order approximate analytical solution), there is:

[0092]

[0093] Substituting formula (5) into formula (2) yields

[0094]

[0095] Performing constant power Park transformation on company (6) yields:

[0096]

[0097] like Fig.16 As mentioned above, the relationship between the stationary coordinate system and the synchronous coordinate system is:

[0098]

[0099]

[0100] Park transformation matrix and, the synchronous reference coordinate system is that the q axis (reactive axis) lags the d axis (active axis) by 90°, θ s Indicates the lag of the q-axis behind the a-axis angle. In the model, v is locked by a three-phase PLL. sa The sinusoidal phase is obtained.

[0101] By s du =-s dl ,s qu =-s ql , substituting into formula (7) we can get:

[0102]

[0103] The inner loop controller is designed according to the inner loop controlled object shown in formula (8). For the sake of simplicity, feedforward decoupling control is not considered, and the control block diagram is obtained as follows: Fig.17 shown.

[0104] The outer loop controller is designed based on the inner loop controller. The outer loop controlled object adopts the small signal model obtained by formula (4) and formula (5), and is obtained as Fig.18 The outer loop controller block diagram is shown.

[0105] The main circuit and control circuit parameters used in the simulation model are organized into Table 2.

[0106] Table 2 Main circuit, control parameters and static operating point

[0107]

[0108]

[0109] Comparison of simulation waveforms under normal operating conditions:

[0110] The comparison under normal working conditions is divided into transient, steady state and load change waveform comparison. The entire simulation process lasts for 4 seconds. At 3 seconds, the DC side voltage given value is added with Δv dc_ref =100V, the A-phase differential mode voltage, three-phase AC current, power factor, A-phase upper bridge arm submodule capacitor voltage, and DC side voltage waveforms are as follows: Fig.19 — Fig.32 .

[0111] Fig.19 and Fig. 22 This is the comparison of the differential mode voltage of phase A under normal operating conditions; Figure 23 to Figure 26 Comparison of three-phase AC current under normal operating conditions; Fig. 27 and Fig.28 is the power factor under normal operating conditions, which are the A-phase AC voltage and current of H-MMC and the A-phase AC voltage and current of ESM-MMC; Fig.29 and Fig.30 is the capacitor voltage of the upper bridge arm submodule of phase A under normal operating conditions, which are the capacitor voltage of the upper bridge arm submodule of H-MMC and the capacitor voltage of the upper bridge arm submodule of ESM-MMC respectively; Figure 31 to Figure 32 are the DC side voltages under normal operating conditions, namely the H-MMC DC side voltage and the SM-MMC DC side voltage; through the comparison of the above simulation waveforms, it can be verified that the performance of the proposed ESM sub-module topology under normal operating conditions is effective.

[0112] Comparison of simulation waveforms under bipolar short-circuit conditions on the DC side: In order to verify the fault current blocking capability of the ESM submodule topology under bipolar short-circuit conditions on the DC side, the simulation model is operated as follows: at 1.5s, a sudden bipolar short circuit occurs on the DC side, with a short-circuit resistance of 1 ohm. The converter station is then locked after a delay of 10ms to simulate the inherent delay time of the system protection action, and the complete DC side current, three-phase AC current, and capacitor voltage waveforms of the A-phase upper bridge arm submodule are obtained in phase 1 (from the occurrence of the fault to the converter station locking phase) and phase 2 (after the locking phase). Fig.33 — Fig.42 shown.

[0113] in, Figure 33-Figure 38Comparison of DC side current under bipolar short circuit conditions. After the DC bipolar short circuit fault occurs at 1.5s, the system deviates greatly from the static operating point in a short time and loses stability. In the first stage, the submodule capacitor injects energy into the short circuit point through the bridge arm inductance, so the DC side current oscillates greatly in the form of resonance. The oscillation period depends on the bridge arm inductance and the equivalent total capacitance of the submodule. At 1.51s, the converter station is fully blocked and enters the second stage. For H-MMC, the fault current does not flow through the submodule capacitor after the whole station is blocked, and there is no mechanism to block the fault. Therefore, the system enters the three-phase uncontrolled rectification state in steady state, and the DC side current has a six-pulse envelope waveform. For ESM-MMC, the fault current flows through the submodule capacitor after the whole station is blocked, and there is a mechanism to block the fault, so the system is naturally blocked after a short time.

[0114] Fig.39 and Fig.40 The three-phase current of the AC side is compared under the bipolar short-circuit condition. For H-MMC, since the short-circuit resistance is very small, the AC side is approximately equivalent to a three-phase short circuit after the whole station is locked, and the current on the AC side is approximately a three-phase symmetrical short-circuit current; for ESM-MMC, the AC side is equivalent to an open circuit after the fault is naturally blocked, so the fault will not affect the AC system.

[0115] Fig.41 and Fig.42 Comparison of the capacitor voltage of the upper bridge arm submodule of phase A under bipolar short-circuit conditions shows that the submodule voltage no longer changes after the H-MMC is locked, while the submodule voltage will be charged for a period of time after the ESM-MMC is locked until the fault is naturally blocked.

[0116] Embodiment 2:

[0117] A MMC submodule topology working method for DC fault current blocking adopts the MMC submodule topology for DC fault current blocking as described in Example 2, including: when the DC side bipolar short circuit occurs, the current flows through a path from a sixth diode to a capacitor and then to a fifth diode, providing reverse voltage to the circuit and absorbing the short-circuit current into the capacitor.

[0118] Furthermore, if the first insulated gate bipolar transistor and the fourth insulated gate bipolar transistor remain in the on state, and the second insulated gate bipolar transistor remains in the off state, the current flows through the first diode in the forward direction and flows through the first insulated gate bipolar transistor in the reverse direction, and the sub-module provides a capacitor voltage to the bridge arm where it is located. At this time, the sub-module is in the on state.

[0119] Further, if the second insulated gate bipolar transistor and the fourth insulated gate bipolar transistor remain in the on state, and the first insulated gate bipolar transistor remains in the off state, the current flows through the second insulated gate bipolar transistor and the third diode in the forward direction, and flows through the fourth insulated gate bipolar transistor and the fifth diode in the reverse direction, the sub-module provides zero voltage to the bridge arm where it is located, and the sub-module is in the cut-off state at this time.

[0120] Furthermore, if the fourth insulated gate bipolar transistor remains in the on state, the first insulated gate bipolar transistor and the second insulated gate bipolar transistor remain in the off state, the current flows through the first diode and the fourth diode in the forward direction, and flows through the fourth insulated gate bipolar transistor and the fifth diode in the reverse direction; when the current is forward, the sub-module provides a capacitor voltage to the bridge arm where it is located, and provides zero voltage in the reverse direction. At this time, the sub-module state is a redundant state.

[0121] Furthermore, if the first insulated gate bipolar transistor, the second insulated gate bipolar transistor and the fourth insulated gate bipolar transistor are all kept in the disconnected state, the current flows through the first diode and the fourth diode in the forward direction, and flows through the sixth diode and the fifth diode in the reverse direction; when the current is forward, the sub-module provides a capacitor voltage to the bridge arm where it is located, and provides a negative capacitor voltage in the reverse direction, and at this time the sub-module state is a locked state.

[0122] The above description is only a preferred embodiment of the present embodiment and is not intended to limit the present embodiment. For those skilled in the art, the present embodiment may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present embodiment shall be included in the protection scope of the present embodiment.

Claims

1. MMC submodule topology for DC fault current blocking, characterized in that: It includes a first insulated gate bipolar transistor, a second insulated gate bipolar transistor connected to the first insulated gate bipolar transistor, a third diode connected to the second insulated gate bipolar transistor, and a fourth insulated gate bipolar transistor connected to the third diode; a capacitor is provided between the first insulated gate bipolar transistor and the fourth insulated gate bipolar transistor; The emitter of the second insulated gate bipolar transistor is connected to the anode of the third diode, and the emitter of the third diode is connected to the collector of the fourth insulated gate bipolar transistor; The first insulated gate bipolar transistor, the second insulated gate bipolar transistor and the fourth insulated gate bipolar transistor are respectively connected in anti-parallel with a first diode, a second diode and a fourth diode; the series branch between the capacitor and the first insulated gate bipolar transistor is connected in parallel with a fifth diode, and the series branch between the capacitor and the fourth insulated gate bipolar transistor is connected in parallel with a sixth diode; When the DC side bipolar short circuit occurs, the current flows through the sixth diode to the capacitor and then to the fifth diode, providing reverse voltage to the circuit and absorbing the short-circuit current into the capacitor at the same time; if the fourth insulated gate bipolar transistor remains in the on state, the first insulated gate bipolar transistor and the second insulated gate bipolar transistor remain in the off state, the current flows through the first diode and the fourth diode in the forward direction, and flows through the fourth insulated gate bipolar transistor and the fifth diode in the reverse direction; when the current is forward, the sub-module provides the capacitor voltage to the bridge arm where it is located, and provides zero voltage in the reverse direction, and the sub-module state is redundant at this time.

2. The MMC submodule topology for DC fault current blocking according to claim 1, characterized in that: An emitter of the first insulated gate bipolar transistor is connected to a collector of the second insulated gate bipolar transistor.

3. The MMC submodule topology for DC fault current blocking according to claim 1, characterized in that: The anode of the fifth diode is connected to the negative electrode of the capacitor, and the cathode is connected to the emitter of the first insulated gate bipolar transistor; the anode of the sixth diode is connected to the collector of the fourth insulated gate bipolar transistor, and the cathode is connected to the anode of the capacitor.

4. An MMC submodule topology working method for DC fault current blocking, characterized in that: The MMC submodule topology for DC fault current blocking as described in any one of claims 1 to 3 is adopted, including: when the DC side bipolar is short-circuited, the current flows through the sixth diode to the capacitor and then to the fifth diode, providing reverse voltage to the circuit and absorbing the short-circuit current into the capacitor.

5. The MMC submodule topology working method for DC fault current blocking according to claim 4, characterized in that: If the first insulated gate bipolar transistor and the fourth insulated gate bipolar transistor remain in the on state, and the second insulated gate bipolar transistor remains in the off state, the current flows through the first diode in the forward direction and flows through the first insulated gate bipolar transistor in the reverse direction, and the sub-module provides a capacitor voltage to the bridge arm where it is located. At this time, the sub-module is in the on state.

6. The MMC submodule topology working method for DC fault current blocking according to claim 4, characterized in that: If the second insulated gate bipolar transistor and the fourth insulated gate bipolar transistor remain in the on state, and the first insulated gate bipolar transistor remains in the off state, the current flows through the second insulated gate bipolar transistor and the third diode in the forward direction, and flows through the fourth insulated gate bipolar transistor and the fifth diode in the reverse direction, and the sub-module provides zero voltage to the bridge arm where it is located. At this time, the sub-module is in the cut-off state.

7. The MMC submodule topology working method for DC fault current blocking according to claim 4, characterized in that: If the fourth insulated gate bipolar transistor remains in the on state, the first insulated gate bipolar transistor and the second insulated gate bipolar transistor remain in the off state, the current flows through the first diode and the fourth diode in the forward direction, and flows through the fourth insulated gate bipolar transistor and the fifth diode in the reverse direction; when the current is forward, the sub-module provides a capacitor voltage to the bridge arm where it is located, and provides zero voltage in the reverse direction. At this time, the sub-module state is a redundant state.

8. The MMC submodule topology working method for DC fault current blocking according to claim 4, characterized in that: If the first insulated gate bipolar transistor, the second insulated gate bipolar transistor and the fourth insulated gate bipolar transistor are all kept in the disconnected state, the current flows through the first diode and the fourth diode in the forward direction, and flows through the sixth diode and the fifth diode in the reverse direction; when the current is forward, the sub-module provides a capacitor voltage to the bridge arm where it is located, and provides a negative capacitor voltage in the reverse direction. At this time, the sub-module is in a locked state.

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