Digital signal driving circuit and driving method with multi-channel input and single-channel output

Abstract

The application belongs to the signal reading part in the circuit system, and relates to a digital signal driving circuit and a driving method with multi-channel input and single-channel output. The driving circuit comprises an enabling pulse generating circuit, a time sequence generating circuit and m signal transmission circuits. The enabling pulse generating circuit has one clock signal input end, one enabling pulse signal input end and n column-level circuit output switch control signal output ends. The time sequence generating circuit has k column-level circuit output switch control signal input ends and k signal transmission control time sequence output ends. Each signal transmission circuit has n column-level circuit signal input ends, n column-level circuit output switch control signal input ends, k signal transmission control time sequence input ends and one single-tap data output end. In one signal transmission circuit, n columns of signals are divided into k sections for driving respectively, and each section has j columns of reading circuits, so that multi-channel input and single-channel output of single-tap signal transmission from the column-level circuit are realized.

Description

Technical Field

[0001] This invention relates to the signal readout section of a circuit system, and more particularly to a digital signal driving circuit and driving method with multi-channel input and single-channel output. Background Technology

[0002] For column-level signal readout circuit systems used in focal plane array sensor signal readout, where the basic unit is a readout circuit with a physical size within one or several pixels of column width, a subsystem is typically required to centralize the output signals of multiple column readout circuits to a single tap circuit, and then uniformly output the signals to the outside of the readout circuit from the tap circuit. In this subsystem, multiple column-level circuits corresponding to a tap output signals to the tap sequentially, for example, column 0, column 1 to (n-1)th columns; when a column-level circuit outputs a signal, the other column-level circuits disconnect from the tap; the tap receives the signal and sequentially outputs the data content of column 0, column 1 to (n-1)th columns. This type of readout method reduces the number of input / output ports (physical contacts) required for the circuit system from thousands to tens of thousands, greatly improving the system integration.

[0003] To reduce the number of taps in a circuit system and improve system integration, it is desirable for a single tap to correspond to as many column-level circuits as possible, provided the tap processing speed allows. A common approach is to directly connect the output of a column-level circuit to the input of a tap circuit, and the outputs (switching mechanisms) of the other corresponding column-level circuits, establishing a physical connection to the same wire network. However, this approach requires considering the parasitic loads from the conductors themselves and the outputs of each column-level circuit: the more column-level circuits a tap corresponds to, the greater the load from the conductors and the other column-level circuits, placing higher demands on the output driving capability of the column-level circuits. Furthermore, considering RC network theory, the output driving capability of column-level circuits has an objective upper limit, making it unsuitable for driving large-scale readout circuits—the network of tap-connected conductors. This results in a trade-off between signal speed and integrity.

[0004] Controlling the load of the output drive for each column-level circuit is one approach to solving the aforementioned problems. One method is to reduce the number of column-level circuits corresponding to the taps. However, when the total number of column-level circuits in the readout circuit system is fixed, this method is not conducive to controlling the number of taps in the system, thus affecting the system integration. For circuit systems with large pixel sizes and long horizontal dimensions of the focal plane array, the load of the readout circuit-tap connection wire network will inevitably be too large, failing to fundamentally solve the problem. A more suitable method is to add multi-level drives to the "direct physical connection method" wire network. By adjusting the load of each level of the multi-level drive circuit, the load at the output of the column-level circuit can be controlled. However, the original "direct physical connection method" wire network contains a part where digital signals need to propagate bidirectionally, while the digital signal drive circuit required by this method usually only supports unidirectional signal propagation. If the design is not proper, it will lead to signal conflicts within the system. Therefore, careful design of the architecture and timing is required to ensure that the signal is transmitted in the correct direction. Summary of the Invention

[0005] This invention provides a digital signal driving circuit with multi-channel input and single-channel output, which is particularly suitable for applications where column-level readout circuits transmit signals to single-channel taps. Its feature is that it realizes multi-level driving of large-area digital signal wire networks, effectively overcoming the large parasitic load problem caused by such networks.

[0006] In a first aspect, the present invention provides a multi-channel input single-channel output digital signal driving circuit, comprising an enable pulse generation circuit, a timing generation circuit, and m signal transmission circuits; the enable pulse generation circuit has a clock signal input terminal, an enable pulse signal input terminal, and n column-level circuit output switch control signal output terminals; the timing generation circuit has k column-level circuit output switch control signal input terminals and k signal transmission control timing output terminals; each of the signal transmission circuits has n column-level circuit signal input terminals, n column-level circuit output switch control signal input terminals, k signal transmission control timing input terminals, and a single-tap data output terminal; n / k=j; n, k, j, and m are all positive integers, and n and k are even numbers;

[0007] In this circuit, the n column-level circuit signal input terminals of each signal transmission circuit correspond one-to-one as the n column-level circuit signal input terminal bus of the digital signal driving circuit; the single-tap data output terminals of the m signal transmission circuits correspond one-to-one as the m single-tap data output terminals of the digital signal driving circuit; the k signal transmission control timing output terminals of the timing generation circuit correspond one-to-one as the k signal transmission control timing input terminals of each signal transmission circuit; the clock signal input terminal and the enable pulse signal input terminal of the enable pulse generation circuit correspond one-to-one as the clock signal input terminal and the enable pulse signal input terminal of the digital signal driving circuit, respectively; the n column-level circuit output switch control signal output terminals of the enable pulse generation circuit correspond one-to-one as the n column-level circuit output switch control signal input terminals of the m signal transmission circuits; and the k column-level circuit output switch control signal output terminals of the enable pulse generation circuit correspond one-to-one as the k column-level circuit output switch control signal input terminals of the timing generation circuit.

[0008] In a second aspect, the present invention also provides a digital signal driving method with multi-channel input and single-channel output, used to implement a digital signal driving circuit with multi-channel input and single-channel output as described in the first aspect of the present invention, the method comprising:

[0009] Input a clock signal at the clock signal input terminal of the enable pulse generation circuit, and input a high-level pulse with a length of one clock cycle that can be recognized by the clock trigger edge at the enable pulse signal input terminal;

[0010] In the column-level circuit of the enable pulse generation circuit, the output switch control signal output terminal outputs high-level pulses with a length of one clock cycle in the order of the 0th to (n-1)th ports.

[0011] The n column-level circuit output switch control signals are used to sequentially close and open all the column-level circuit output switches in the m signal transmission circuits, so that the signals on the bus at the data input terminal of each column-level circuit sequentially enter each signal transmission circuit for transmission.

[0012] k column-level circuit output switch control signals are output to the timing generation circuit to generate timing sequences that control the opening and closing of k driver-related switches in each signal transmission circuit. The generated timing sequences are output from the k signal transmission control timing output terminals of the timing generation circuit to the signal transmission control timing input terminals of each signal transmission circuit.

[0013] The signals collected by the signal transmission circuit from the corresponding column-level circuits are sequentially output from the single-tap data output terminals of each signal transmission circuit.

[0014] When a clock cycle ends, the input clock of the enable pulse generation circuit remains unchanged, and a high-level pulse with a length of one clock cycle that can be recognized by the clock trigger edge is sent to its enable pulse signal input terminal again, that is, the above process is repeated; the pulse width of each column-level circuit data is one clock cycle, and it takes one large cycle, i.e., n clock cycles, to complete the data output of all columns.

[0015] The beneficial effects of this invention are:

[0016] 1. In the traditional multi-channel input and single-channel output digital signal driving circuit, which is particularly suitable for column-level circuits to single-tap signal transmission, the present invention achieves multi-level driving of digital signal wires by arranging several timing-controlled driving circuits on the signal transmission path, effectively overcoming the problem of large parasitic load caused by large area and long distance wires in such circuits.

[0017] 2. The timing required for the newly added circuit in this invention, compared to the traditional driving circuit, is entirely generated internally by the circuit itself. It can operate normally using only the timing (clock, enable pulse) used by the traditional driving circuit, without the need to add new timing, making it simple to use.

[0018] 3. The present invention makes minor changes to the main signal transmission circuit in the traditional driving circuit. Apart from the driving circuit with buffer as the main component, no other components are added. In addition, the added timing generation circuit supports providing timing to multiple signal transmission circuits (for merging bus outputs), which is beneficial to the layout area of ​​the control circuit and facilitates physical implementation. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of a digital signal driving circuit with multi-channel input and single-channel output according to an embodiment of the present invention;

[0020] Figure 2 This is a schematic diagram of the enable pulse generation circuit according to an embodiment of the present invention;

[0021] Figure 3 This is a schematic diagram of the timing generation circuit according to an embodiment of the present invention;

[0022] Figure 4 This is a schematic diagram of a usable timing generation sub-circuit in an embodiment of the present invention;

[0023] Figure 5 This is a schematic diagram of the signal transmission circuit in an embodiment of the present invention;

[0024] Figure 6 This is a schematic diagram of the digital signal driving circuit used in a preferred embodiment of the present invention;

[0025] Figure 7 This is a schematic diagram of the input and output timing signals in a preferred embodiment of the present invention;

[0026] In the diagram: (wherein:)

[0027] 101: Enable pulse generation circuit; 102: Timing generation circuit; 103~105: Signal transmission circuit; 106~108: Column-level circuit signal input bus; 109~111: Single-tap data output terminal; 112: Clock signal input terminal; 113: Enable pulse signal input terminal.

[0028] 201~205: D flip-flops; 206~210: Output terminals of column circuit output switch control signals; 211: Input terminal of enable pulse signal; 212: Input terminal of clock signal.

[0029] 301~305: Timing generation sub-circuit; 306~311: Signal transmission control timing output terminal; 312~317: Column-level circuit output switch control signal input terminal;

[0030] 401: Start switch pulse input terminal, 402: End switch pulse input terminal, 403: Switch pulse transmission output terminal, 404: Switch pulse transmission inverted output terminal, 405: First inverter, 411: Second inverter, 406: First OR gate, 408: Second OR gate, 410: Third OR gate, 407: First AND gate, 409: First latch;

[0031] 501~507: Tri-state gate driver; 508~527: Column-level circuit signal input terminal; 528~534: Signal transmission control timing input terminal; 535~554: Column-level circuit output switch; 555: Single-tap data output terminal.

[0032] 601~603: Pulse counter; 604: Enable pulse generation circuit; 605: Timing generation circuit; 606~609: Signal transmission circuit; 610~612: Counting pulse input terminal of digital signal driving circuit; 613: Pulse counter reset signal input terminal of digital signal driving circuit; 614~617: Single tap data output terminal of digital signal driving circuit; 618: Clock signal input terminal of digital signal driving circuit; 619: Enable pulse signal input terminal of digital signal driving circuit. Detailed Implementation

[0033] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0034] This invention provides a digital signal driving circuit with multi-channel input and single-channel output. The top-level circuit of this driving circuit system (referred to as circuit 1) is as follows: Figure 1 As shown, it includes an enable pulse generation circuit 101 (referred to as circuit 2), a timing generation circuit 102 (referred to as circuit 3), and m signal transmission circuits 103, 104, and 105 (referred to as circuit 4) of the 0th, 1st, ..., (m-1)th generation.

[0035] The enable pulse generation circuit 101 has a clock signal input terminal 112 (clk), an enable pulse signal input terminal 113 (en_pulse), and n column-level circuit output switch control signal output terminals 109, 110, and 111 (col_data_out). <m-1>);

[0036] The timing generation circuit 102 has k column-level circuit output switch control signal input terminals (col_sw_en<0,j-1,2j-1,…,nj-1>) and k signal transmission control timing output terminals (int_sw_ctrl<0:k-1>);

[0037] Each of the signal transmission circuits 103, 104, and 105 has n column-level circuit signal input terminals (col_data_in<0:n-1>), n column-level circuit output switch control signal input terminals (col_sw_en<0:n-1>), k signal transmission control timing input terminals (int_sw_ctrl<0:k-1>), and a single-tap data output terminal 109, 110, and 111 (col_data_out);

[0038] In the above circuit ports, n, j, and k follow the relationship n / k=j; n, j, k, and m must all be positive integers, n and k must be even numbers, j is not less than 2, and k is not less than 4.

[0039] In this circuit, each of the n column-level circuit signal input terminals col_data_in<0:n-1> of the signal transmission circuit corresponds one-to-one with the n column-level circuit signal input bus 106, 107, and 108 of the digital signal driving circuit; that is, all the column-level circuit signal input terminals col_data_in<0:n-1> of the 0th circuit 4 serve as the 0th group of column-level circuit signal input bus col_data_in_0<0:n-1> of the circuit 1, all the column-level circuit signal input terminals col_data_in<0:n-1> of the 1st circuit 4 serve as the 1st group of column-level circuit signal input bus col_data_in_1<0:n-1> of the circuit 1, and so on, until all the column-level circuit signal input terminals col_data_in<0:n-1> of the (m-1)th circuit 4 serve as the (m-1)th group of column-level circuit signal input bus 106, 107, and 108 of the circuit 1 (col_data_in_(m-1)<0:n-1>).

[0040] The single-tap data output terminals of m signal transmission circuits are used as the m single-tap data output terminals of the digital signal driving circuit; that is, in sequence, the single-tap data output terminals col_data_out of circuit 4 (0, 1, ..., (m-1)) are used as the single-tap data output terminals 109, 110, 111 of circuit 1 (col_data_out<0:m-1>).

[0041] The k signal transmission control timing output terminals of the timing generation circuit, int_sw_ctrl<0:k-1>, are connected one-to-one by name to the k signal transmission control timing input terminals of the m signal transmission circuits, int_sw_ctrl<0:k-1>.

[0042] The clock signal input terminal 112 and the enable pulse signal input terminal 113 of the enable pulse generation circuit are respectively used as the clock signal input terminal 112 and the enable pulse signal input terminal 113 of the digital signal driving circuit.

[0043] The output terminals of the n column-level circuits that enable the pulse generation circuit, col_sw_en<0:n-1>, are connected one-to-one by name to the input terminals of the n column-level circuits that enable the pulse generation circuits, col_sw_en<0:n-1>.

[0044] The output terminals of the k column-level circuit output switch control signals of the enable pulse generation circuit, col_sw_en<0,j-1,2j-1,…,nj-1>, are connected one-to-one to the input terminals of the k column-level circuit output switch control signals of the timing generation circuit, col_sw_en<0,j-1,2j-1,…,nj-1>.

[0045] In this embodiment of the invention, the driving method corresponding to the digital signal driving circuit includes:

[0046] Input a clock signal at the clock signal input terminal of the enable pulse generation circuit, and input a high-level pulse with a length of one clock cycle that can be recognized by the clock trigger edge at the enable pulse signal input terminal;

[0047] In the column-level circuit of the enable pulse generation circuit, the output terminal col_sw_en<0:n-1> of the switch control signal output terminal outputs high-level pulses with a length of one clock cycle in the order of the 0th to (n-1)th ports;

[0048] The n column-level circuit output switch control signals are used to sequentially close and open all the column-level circuit output switches in the m signal transmission circuits, so that the signals on the bus at the data input terminal of each column-level circuit sequentially enter each signal transmission circuit for transmission.

[0049] k column-level circuit output switch control signals col_sw_en<0,j-1,2j-1,…,nj-1> are output to the timing generation circuit 102 to generate the timing sequence for controlling the opening and closing of the k driver-related switches in each signal transmission circuit. The generated timing sequence is output from the k signal transmission control timing output terminals int_sw_ctrl<0:k-1> of the timing generation circuit to the signal transmission control timing input terminals int_sw_ctrl<0:k-1> of each signal transmission circuit.

[0050] The signals collected by the signal transmission circuit from the corresponding column-level circuits are sequentially output from the single-tap data output terminals of each signal transmission circuit.

[0051] When a clock cycle ends, the input clock of the enable pulse generation circuit remains unchanged, and a high-level pulse with a length of one clock cycle that can be recognized by the clock trigger edge is sent to its enable pulse signal input terminal again, that is, the above process is repeated; the pulse width of each column-level circuit data is one clock cycle, and it takes one large cycle, i.e., n clock cycles, to complete the data output of all columns.

[0052] In the above process, circuit 1 acts as a single-tap output system. The signals collected from the corresponding column-level circuits are sequentially output from the single-tap data output terminals of each circuit 4. The pulse width of each column-level circuit data is one clock cycle, and n clock cycles are required to complete the data output of all columns. After the above process is completed, keeping the input clock of circuit 2 unchanged, the signal with the above characteristics is sent to its enable pulse signal input terminal again to repeat the above process.

[0053] This digital signal driving circuit and its corresponding driving method can be understood as follows: For a single tap corresponding to a total of n columns of readout circuits, in a signal transmission circuit, the combined output signal wires of these columns are divided into k segments and driven separately. Each segment contains the output structure of j columns of readout circuits, and the system can support n columns of m bits of bus output. Therefore, in the above circuit ports, n, j, k, and m must all be positive integers, n and k must be even numbers, j is not less than 2, k is not less than 4, and n, j, and k follow the relationship n / k = j.

[0054] Enable pulse generation circuit (circuit 2) as follows Figure 2 As shown, the enable pulse generation circuit includes n cascaded D flip-flops 201, 202, 203, 204, 205, ordered as number 0, 1, ..., (n-1), with the Q output of the previous D flip-flop connected to the D input of the next D flip-flop; the clock inputs of the n D flip-flops are connected to the same clock signal input, wherein the D input of the first D flip-flop is connected to the enable pulse signal input, and the Q outputs of the n D flip-flops serve as the output switch control signals for the n column-level circuits, respectively.

[0055] Specifically, the D input of the 0th flip-flop serves as the enable pulse signal input 211 of circuit 2, and its clock input CK serves as the clock signal input 212 of circuit 2; the Q output of the 0th flip-flop is connected to the D input of the 1st flip-flop, the Q output of the 1st flip-flop is connected to the D input of the 2nd flip-flop, and so on, until the Q output of the (n-2)th flip-flop is connected to the D input of the (n-1)th flip-flop. Simultaneously, the connections between the aforementioned Q outputs and adjacent D inputs serve as the (n-1)th (column-level circuit output switch control signal outputs 206, 207, 208, 209 (col_sw_en<0:n-2>)) of circuit 2; the Q output of the (n-1)th flip-flop serves as the column-level circuit output switch control signal output 210 (col_sw_en) of circuit 2. <n-1>The clock input terminals of the first, second to (n-1) flip-flops are all connected to the clock signal input terminal 212 of circuit 2.

[0056] In this embodiment of the invention, under the above-described enable pulse generation circuit, the driving method corresponding to the digital signal driving circuit includes:

[0057] A clock signal is input to the clock signal input terminal of the enable pulse generation circuit, and a high-level pulse with a length of one clock cycle and recognizable by the clock trigger edge is input to the enable pulse signal input terminal. After a certain time delay after the occurrence of the clock trigger edge, the 0th flip-flop of the enable pulse generation circuit outputs a high-level pulse with a length of one clock cycle at the Q output terminal. This pulse is output as the signal of the column circuit output switch control signal output terminal, and at the same time, the pulse is input to the D input terminal of the 1st flip-flop, repeating the above clock triggering process. The pulse is transmitted through the flip-flops in the enable pulse generation circuit until the column circuit output switch control signal output terminal outputs a pulse in the nth clock cycle, ending the operation of one large cycle.

[0058] Specifically, a clock signal is input to its clock signal input terminal, and a high-level pulse of one clock cycle length is input to its enable pulse signal input terminal, which can be recognized by the clock trigger edge (for example, a clock trigger edge is located at the middle of the high level of the enable pulse signal). The 0th flip-flop will output a high-level pulse of one clock cycle length at its Q output terminal after a certain time delay after the occurrence of the clock trigger edge. This pulse serves as the output signal col_sw_en of the column-level circuit output switch control terminal. <0> The signal is output externally, and simultaneously the pulse is input to the D input of the first flip-flop, repeating the above clock triggering process. In the second clock cycle, a high-level pulse with a length of one clock cycle is output to its Q output, serving as the output signal col_sw_en of the column circuit output switch control terminal. <1> The signal is output externally, and so on. This pulse is "transmitted" through the trigger in circuit 2 until the final column circuit outputs the switch control signal output terminal col_sw_en. <n-1>In the nth clock cycle, a pulse is output to end the operation of one large cycle. To repeat the above process, the clock signal input is maintained, and a high-level pulse with a length of one clock cycle that can be recognized by the clock trigger edge is input again at the enable pulse signal input terminal.

[0059] Timing generation circuit (Circuit 3) as follows Figure 3 As shown, there are (k-1) timing generation sub-circuits 301, 302, 303, 304, and 305 (hereinafter referred to as circuit 5), including the 0th, 1st, 2nd, ..., (k-2)th timing generation sub-circuits. Circuit 5 has a start switch pulse input terminal pulse_start_prev, an end switch pulse input terminal pulse_end, a switch pulse transmission output terminal level_next, and a switch pulse transmission inverted output terminal level_next_b. The switch pulse transmission output terminal of the previous timing generation sub-circuit is connected to the start switch pulse input terminal of the next timing generation sub-circuit, forming a cascaded circuit. Among them, the 0th to (k / 2-)th timing generation sub-circuits have a total of (k-1)th timing generation sub-circuits 301, 302, 303, 304, and 305. 1) The switch pulse transmission output terminals of the timing generation sub-circuit are connected sequentially to the first k / 2 signal transmission control timing output terminals 306, 307, and 308. The switch pulse transmission inverted output terminals of the (k / 2-1) to (k-2)th timing generation sub-circuit are connected sequentially to the last k / 2 signal transmission control timing output terminals 309, 310, and 311. The start switch pulse input terminal of the 0th timing generation sub-circuit and the end switch pulse input terminals of the 0th to (k-2)th timing generation sub-circuit are connected sequentially to the k column-level circuit output switch control signal input terminals 312, 313, 314, 315, 316, and 317 (intermediate ports omitted).

[0060] Specifically, the starting switch pulse input terminal of the (k / 2-1)th circuit 5 in circuit 3 is connected to the switch pulse transmission output terminal of the (k / 2-2)th circuit 5. This connection line also serves as the signal transmission control timing output terminal int_sw_ctrl of circuit 3. <k 2-2>The end switch pulse input terminal of the (k / 2-1)th circuit 5 serves as the output switch control signal input terminal col_sw_en of the column-level circuit of circuit 3. <n 2-1>The switch pulse transmission output terminal of the (k / 2-1)th circuit 5 is connected to the start switch pulse input terminal of the (k / 2)th circuit 5, and serves as the signal transmission control timing output terminal int_sw_ctrl of circuit 3. <k 2-1>The inverted output terminal of the switching pulse transmission of the (k / 2-1)th circuit 5 serves as the signal transmission control timing output terminal of circuit 3, int_sw_ctrl. <k 2>The starting switch pulse input terminal of the (k / 2-2)th circuit 5 is connected to the switch pulse transmission output terminal of the (k / 2-3)th circuit 5, and serves as the signal transmission control timing output terminal int_sw_ctrl of circuit 3. <k 2-3>The starting switch pulse input terminal of the (k / 2-3)th circuit 5 is connected to the switch pulse transmission output terminal of the (k / 2-4)th circuit 5, and serves as the signal transmission control timing output terminal int_sw_ctrl of circuit 3. <k 2-4>This process continues until the starting switch pulse input terminal of the first circuit 5 is connected to the switch pulse transmission output terminal of the 0th circuit 5, and serves as the signal transmission control timing output terminal int_sw_ctrl of circuit 3. <0> The inverted output terminals of the switching pulse transmission of circuits 5 (0th, 1st, ..., (k / 2-3), (k / 2-2) are not connected externally. Their end-of-phase switching pulse input terminals serve as the column-level circuit output switch control signal input terminals (col_sw_en) of circuit 3.<j-1,2j-1,…,n / 2-2j-1,n / 2-j-1> The starting switch pulse input terminal of circuit 5 (number 0) serves as the input terminal of the column-level circuit output switch control signal col_sw_en for circuit 3. <0> The switch pulse transmission output terminal of the k / 2th circuit 5 is connected to the starting switch pulse input terminal of the (k / 2+1)th circuit 5, the switch pulse transmission output terminal of the (k / 2+1)th circuit 5 is connected to the starting switch pulse input terminal of the (k / 2+2)th circuit 5, and so on, until the switch pulse transmission output terminal of the (k-3)th circuit 5 is connected to the starting switch pulse input terminal of the (k-2)th circuit 5; the switch pulse transmission inverted output terminals of the k / 2th, (k / 2+1), ..., (k-3), and (k-2)th circuits 5 are respectively used as the signal transmission control timing output terminals int_sw_ctrl of circuit 5.<k / 2+1, k / 2+2,…,k-2,k-1> Their end switch pulse input terminals serve as the column-level circuit output switch control signal input terminals col_sw_en< n / 2+j-1,n / 2+2j-1,…,n-2j-1,nj-1> of circuit 3, respectively; the switch pulse transmission output terminal of the (k-2)th circuit 5 is not connected to the outside.

[0061] In this embodiment of the invention, under the above-described timing generation circuit, the driving method corresponding to the digital signal driving circuit includes:

[0062] A high-level pulse with a duration of one clock cycle is input to the output switch control signal input terminals of the 0th and (j-1)th column-level circuits, respectively. After processing by the 0th timing generation sub-circuit, a pulse with a rising edge coinciding with the rising edge of the pulse input to the 0th column-level circuit and a falling edge coinciding with the falling edge of the pulse input to the (j-1)th column-level circuit is generated at the switch pulse transmission output terminal of the 0th timing generation sub-circuit. This pulse has a high-level width of j clock cycles and is output from the signal transmission control timing output terminal of the timing generation circuit for control. The corresponding switches in the signal transmission circuit are simultaneously input to the start switch pulse input terminal of the first timing generation sub-circuit; repeating the above process, a high-level pulse with a duration of one clock cycle is input to the end switch pulse input terminal of the first to (k / 2-1) timing generation sub-circuits in sequence. The switch pulse transmission output terminals of the first to (k / 2-1) timing generation sub-circuits in the timing generation circuit will serve as the first to (k / 2-1) signal transmission control timing output terminals of the timing generation circuit, respectively outputting pulses with rising edges coinciding with the rising edge of the input pulse of the 0th column-level circuit output switch control signal input terminal, falling edges coinciding with the falling edge of the input pulse of the (2j-1), (3j-1), ..., (n / 2-1)th column-level circuit output switch control signal input terminal, and high-level pulses with widths of 2j, 3j, ..., n / 2 clock cycles;

[0063] The inverting output terminal of the switching pulse transmission of the (k / 2-1)th timing generation sub-circuit outputs a signal that is inverted from its switching pulse transmission output terminal. Its rising edge coincides with the falling edge of the (k / 2-1)th transmission control timing output terminal of the timing generation circuit, and its falling edge coincides with the rising edge of the pulse received at the input terminal of the column-level circuit output switching control signal for the next large cycle. Its high-level width is at least n / 2 clock cycles. This signal is output as the (k / 2)th signal transmission control timing output terminal of the timing generation circuit. This process is repeated, sequentially inputting the switching control signals from the (k / 2)th to (k-2)th column-level circuits of the timing generation circuit. Each input pulse has a high-level duration of one clock cycle. After being processed by the k / 2 to (k-2)th timing generation sub-circuits, the rising edge of the output of the inverted output terminal of the timing generation circuit, which is the output switch control signal input terminal of the column circuit, overlaps with the falling edge of the pulse received by the output switch control signal input terminal of the column circuit. The falling edge of the pulse overlaps with the rising edge of the pulse received by the output switch control signal input terminal of the 0th column circuit of the next large cycle. The high-level pulse width is at least (n / 2-j), (n / 2-2j), ..., j clock cycles. This completes the operation of one large cycle.

[0064] Specifically, firstly, at the column-level circuit output switch control signal input terminal col_sw_en of circuit 3. <0> and col_sw_en <j-1>Input pulses with a high-level duration of one clock cycle. Considering the working principle of circuit 2 that generates these two pulses, col_sw_en <j-1>The time when the pulse is received will be earlier than col_sw_en <0> The received pulse is (j-1) clock cycles late. Through the processing of circuit 5 (0th circuit), a rising edge is generated at the output of the switching pulse transmission of circuit 5, coinciding with col_sw_en. <0> The rising edge of the input pulse coincides with the falling edge of col_sw_en. <j-1>The input pulse has a falling edge that coincides with the input pulse and a high-level width of j clock cycles. This pulse is transmitted from the signal transmission control timing output terminal int_sw_ctrl of circuit 3. <0> The output is used to control the corresponding switch in circuit 4, and is also input to the start switch pulse input terminal of the first circuit 5 in circuit 3; a high-level pulse with a duration of one cycle is input to the end switch pulse input terminal of the first circuit 5 (i.e., the column-level circuit output switch control signal input terminal col_sw_en <2j-1> of circuit 3). Considering the working principle of circuit 2 that generates this pulse, the time when col_sw_en<2j-1> receives the pulse will be earlier than col_sw_en <0> The received pulse is (2j-1) clock cycles late. Through processing by the first circuit 5, a rising edge is generated at the output of the switching pulse transmission of circuit 5, coinciding with col_sw_en. <0> The input pulse has a rising edge that coincides with the falling edge of the col_sw_en<2j-1> input pulse, and a high-level width of 2j clock cycles. This pulse is transmitted from the signal transmission control timing output terminal int_sw_ctrl of circuit 3. <1> The output is simultaneously input to the starting switch pulse input terminal of the first circuit 5 in circuit 3; and so on, following the above process, the switch pulse transmission output terminals of the second, third, ..., (k / 2-1)th circuits 5 in circuit 3 will serve as the signal transmission control timing output terminals of circuit 3, int_sw_ctrl<2,3,...,k / 2-1>, respectively outputting the rising edge and col_sw_en. <0> The input pulse has a rising edge that coincides with the falling edge of the col_sw_en<3j-1,4j-1,…,n / 2-1> input pulse, and a high-level pulse width of 3j, 4j,…,n / 2 clock cycles. The switching pulse transmission inverting output terminal of the (k / 2-1)th circuit 5 in circuit 3 outputs a signal inverted from its switching pulse transmission output terminal, and its rising edge coincides with the transmission control timing output terminal int_sw_ctrl of circuit 3. <k 2-1>The falling edge coincides with the falling edge of the column-level circuit output switch control signal input terminal col_sw_en of the next large cycle. <0> If the rising edges of the received pulses coincide, then the high-level width is at least n / 2 clock cycles. This signal serves as the signal transmission control timing output terminal int_sw_ctrl of circuit 3. <k 2>Output; then, in circuit 3, the end switch pulse input terminals of the k / 2, (k / 2+1), ..., (k-2)th circuits 5 (i.e., the column-level circuit output switch control signal input terminals col_sw_en< n / 2+j-1,n / 2+2j-1,…,nj-1>) are respectively input with a high-level pulse duration of one clock cycle. The timing of the pulse received at these input terminals will be different from that at col_sw_en. <0> The received pulses are received at times that are (n / 2+j-1), (n / 2+2j-1), ..., (nj-1) clock cycles later, respectively. After processing by circuit 5, their switching pulses are transmitted to the inverted output terminal (i.e., the column-level circuit output switch control signal input terminal int_sw_ctrl of circuit 3).<k / 2+1, k / 2+2,…, k-1> The rising edge of the output is respectively connected to the input terminal col_sw_en of the column circuit output switch control signal.<n / 2+j-1,n / 2+2j-1,…,n-j-1> The falling edges of the received pulse overlap and coincide with the falling edges of the next large cycle are input to the column-level circuit output switch control signal col_sw_en. <0> The rising edges of the received pulses overlap, and the high-level widths of each pulse are at least (n / 2-j), (n / 2-2j), ..., j clock cycles, thus ending the operation of one large cycle. The operation circuit 2 inputs pulses to the output switch control signal input terminal of the column circuit of the circuit 3 again, and the above process can be repeated.

[0065] A usable circuit 5 such as Figure 4 As shown, the circuit includes two inverters (numbers 1 and 2), three OR gates (numbers 1, 2, and 3), an AND gate 407, and a latch 409 (which latches data when the latch pulse level is high). The input of the first inverter 405 is connected to the end switch pulse input 402 of circuit 5, and its output is connected to the first input of the first AND gate. The second input of the first AND gate is connected to the data output (Q terminal) of the first latch, and its output is connected to the second input of the second OR gate 408. The first input of the second OR gate 408 is connected to the start switch pulse input 401 of circuit 5, and its output is connected to the data output of the first latch. Input terminal (D terminal); The latch pulse input terminal (L terminal) of the first latch is connected to the output terminal of the first OR gate 406; The first input terminal of the first OR gate 406 is connected to the start switch pulse input terminal of circuit 5, and its second input terminal is connected to the end switch pulse input terminal of circuit 5; The first input terminal of the third OR gate 410 is connected to the end switch pulse input terminal of circuit 5, its second input terminal is connected to the data output terminal of the first latch, and its output terminal is connected to the switch pulse transmission output terminal 403 of circuit 5 and the input terminal of the second inverter 411; The output terminal of the second inverter 411 is connected to the switch pulse transmission inverted output terminal 404 of circuit 5.

[0066] In this embodiment of the invention, under the above-described timing generation sub-circuit, the driving method corresponding to the digital signal driving circuit includes:

[0067] The circuit 5 is used as follows: First, pulses with a certain high-level duration are input to its start switch pulse input terminal and end switch pulse input terminal respectively. The high-level portions of the two pulses should not overlap, and the pulse input to the end switch pulse input terminal should arrive at circuit 5 later than the pulse input to the start switch pulse input terminal. Then, two pulses are generated in the first OR gate, which are used to latch the relevant data of the first latch. The first inverter, the first AND gate, the second OR gate, and the first register constitute a sample-and-hold device. When a pulse is input to the start switch pulse input terminal, the first register samples, and its data output terminal starts to output a high level. When a high-level pulse is input to the start switch pulse input terminal, the first latch changes from the sampling state to the latching state, and its data output terminal remains at a high level until the end switch pulse input terminal receives a high level. The first latch then enters the sampling state again. When a low-level sample is received at the first input of the first AND gate, the data output of the first latch outputs a low level. When a high-level pulse is input to the end switch pulse input, the first latch returns to the latched state, and the data output remains low. Then, the high-level pulse output from the data output of the first register is concatenated with the pulse output from the end switch pulse input in the time domain using the third OR gate. Finally, a long pulse is obtained at the output of the OR gate (i.e., the switch pulse transmission output of circuit 3). The rising edge of the pulse coincides with the rising edge of the pulse input to the start switch pulse input, the falling edge coincides with the falling edge of the pulse input to the end switch pulse input, and the high-level time is the sum of the mutual delay time of the rising edges of the two input pulses and the high-level time of the pulse input to the end switch pulse input. The inverted signal of the long pulse is obtained at the switch pulse transmission inverting output.

[0068] Signal transmission circuit (circuit 4) as follows Figure 5 As shown, the signal transmission circuit includes k digital signal drivers 501, 502, 503, 504, 505, 506, 507 with tri-state gates (0, 1, ..., (k-1)), and n column-level circuit output switches 535, 536, 537, 538, 539, 540, 541, 542, 543, 544, 545, 546, 547, 548, 549, 550, 551, 552, 553, 554. In the 0th to (k / 2-1)th drivers, the output terminal of the previous driver is connected to the input terminal of the next driver, and in the (k / 2-1)th to (k-1)th drivers, the input terminal of the previous driver is connected to the output terminal of the next driver. The input terminals of each driver are connected sequentially to... The output terminals of the j-th column-level circuit output switches are connected to the output terminals of the j-th column-level circuit output switches. The state control terminals of the 0th to (k-1)th drivers are connected to the k signal transmission control timing input terminals 528, 529, 530, 531, 532, 533, and 534 of the signal transmission circuit in sequence. The signal input terminals of the 0th to (n-1)th column-level circuit output switches 508, 509, 510, 511, 512, 513, 514, 515, 516, 517, 518, 519, 520, 521, 522, 523, 524, 525, 526, and 527 are connected to the input terminals of the 0th to (n-1)th column-level circuit output switches in sequence. The output terminal of the (k / 2-1)th driver is connected to the single-tap data output terminal 555 of the signal transmission circuit.

[0069] Specifically, the output of the (k / 2-1)th driver is connected to the output of the (k / 2)th driver, and is also connected to the single-tap data output terminal col_data_out of circuit 4; the input of the (k / 2-1)th driver is connected to the output of the (n / 2-j), (n / 2-j+1), ..., (n / 2-2), (n / 2-1)th column-level circuit output switches of circuit 4, and is also connected to the output of the (k / 2-2)th driver. The input of the (k / 2-2)th driver is connected to the circuit... The output terminals of the (n / 2-2j), (n / 2-2j+1), ..., (n / 2-j-2), (n / 2-j-1)th column-level circuit output switches of circuit 4 are connected to the output terminal of the (k / 2-3)th driver, and so on, until the input terminal of the 0th driver is connected to the output terminals of the 0th, 1st, ..., (j-2), (j-1)th column-level circuit output switches of circuit 4; the input terminal of the k / 2th driver is connected to the n / 2th, (n / 2+1), ..., (n / 2+j-2)th drivers of circuit 4. The output terminals of the (n / 2+j-1)th column-level circuit output switches are connected to the output terminals of the (k / 2+1)th driver. The input terminals of the (k / 2+1)th driver are connected to the output terminals of the (n / 2+j), (n / 2+j+1), ..., (n / 2+2j-2), (n / 2+2j-1)th column-level circuit output switches of circuit 4, and connected to the output terminals of the (k / 2+2)th driver, and so on, until the input terminal of the (k-1)th driver is connected to the (nj), (nj-1)th driver, ..., (nj-2)th driver of circuit 4. The output terminals of the n-j+1), ..., (n-2), (n-1) column-level circuit output switches are connected in sequence to the column-level circuit signal input terminals col_data_in<0:n-1> of the 0, 1, ..., (n-1) circuit 4, respectively; the state control terminals of the 0, 1, ..., (k-1) drivers are connected in sequence to the signal transmission control timing input terminals int_sw_ctrl<0:k-1> of the circuit 4.

[0070] In this embodiment of the invention, under the above-described signal transmission circuit, the driving method corresponding to the digital signal driving circuit includes:

[0071] Assume that the buffer output remains normal when the state control terminal of the three-state gate receives a high level, and the output terminal is in a high-impedance state when it receives a low level.

[0072] Pulses with a certain high-level duration are input to the start switch pulse input terminal and the end switch pulse input terminal of the timing generation sub-circuit, respectively. The high-level portions of the two pulses should not overlap, and the pulse input to the end switch pulse input terminal should arrive at the timing generation sub-circuit later than the pulse input to the start switch pulse input terminal. Then, two pulses are generated before and after the first OR gate, respectively, for latching the relevant data of the first latch. A sample-and-hold device is constructed from the first inverter, the first AND gate, the second OR gate, and the first register. When a pulse is input to the start switch pulse input terminal, the first register samples, and its data output terminal starts outputting a high level. When the high-level pulse input to the start switch pulse input terminal ends, the first latch changes from the sampling state to the latching state, and its data output terminal remains at a high level until the end switch pulse input terminal receives a high level, at which point the first latch re-enters the sampling state. When a low-level sample is received at the first input of the first AND gate, the data output of the first latch outputs a low level. When a high-level pulse is input to the end switch pulse input, the first latch returns to the latched state, and the data output remains low. Then, the high-level pulse output from the data output of the first register and the pulse output from the end switch pulse input are concatenated in the time domain using the third OR gate. Finally, a long pulse is obtained at the output of the OR gate, i.e., the switch pulse transmission output of circuit 3. The rising edge of the pulse coincides with the rising edge of the pulse input to the start switch pulse input, the falling edge coincides with the falling edge of the pulse input to the end switch pulse input, and the high-level time is the sum of the mutual delay time of the rising edges of the two input pulses and the high-level time of the pulse input to the end switch pulse input. The inverted signal of the long pulse is obtained at the switch pulse transmission inverting output.

[0073] Specifically, firstly, a high level is input to the timing input terminal int_sw_ctrl<0:k / 2-1> via control circuit 2, which in turn controls circuit 3 to transmit the signal to circuit 4. When the input k / 2:k-1> is low, drivers 0 to (k / 2-1) maintain normal buffer output, while drivers k / 2 to (k-1) enter a high-impedance state. This can be considered as the output of driver k / 2 being disconnected from the single-tap data output of circuit 4. Simultaneously, under the control of circuit 2, the output switches of the 0th, 1st, ..., (j-1th) column-level circuits in circuit 4 are sequentially closed and then opened, with the closing process not overlapping. The data input to the signal input terminals col_data_in<0:j-1> of the 0th, 1st, ..., (j-1th) column-level circuits in circuit 4 sequentially enters the tri-state gate driver chain of circuit 4, passes through its 0th to (k / 2-1th) drivers, and finally reaches its single-tap data output, completing the data output. Afterwards, control circuit 2 causes the signal transmission control timing input terminal int_sw_ctrl of circuit 4 to be activated. <0> When the input goes low, `int_sw_ctrl<1:k / 2-1>` remains high, and `int_sw_ctrl<k / 2:k-1>` remains low. At this time, the 0th driver is in a high-impedance state, which can be considered as its output being disconnected. The 1st to (k / 2-1)th drivers maintain normal buffer output, and the k / 2nd to (k-1)th drivers maintain a high-impedance state. Simultaneously, under the control of circuit 2, the input is sent to the signal input terminals `col_data_in` of the j-th, (j+1), ..., (2j-1)th column-level circuits in circuit 4.<j,j+1,…,2j-1> The data sequentially enters the tri-state gate driver chain of circuit 4, passes through its first to (k / 2-1) drivers, and finally reaches its single-tap data output terminal to complete the data output; then, control circuit 2 controls the signal transmission timing input terminal int_sw_ctrl of circuit 4. <1> The input goes low, int_sw_ctrl <0> Keep low level, int_sw_ctrl<2:k / 2-1> keep high level, int_sw_ctrl <k 2:k-1>Keep it low... and so on, until control circuit 2 causes the signal transmission control timing input terminal int_sw_ctrl of circuit 4 to be activated. <k 2-2>When the input goes low, int_sw_ctrl<0,1,…, k / 2-2> remains low, and int_sw_ctrl... <k 2-1>Keep it high, int_sw_ctrl <k 2:k-1>Keep it low to complete the signal input terminal col_data_in of the 4-column stage circuit.<n / 2-j, n / 2-j+1,…, n / 2-1> The process of sequentially outputting data from the single-tap data output terminal; then keeping int_sw_ctrl<0:k / 2-1> low, int_sw_ctrl <k 2>to go high, int_sw_ctrl<k / 2+1:k-1> Keeping the level low can be considered as the output of the (k / 2-1)th driver disconnecting from the single-tap data output, the output of the k / 2th driver reconnecting to the single-tap data output, and the output of the (k / 2+1)th driver disconnecting from the external connection. This completes the signal input of the 4th column-level circuit, col_data_in.<n / 2, n / 2+1,…, n / 2+j-1> The process of sequentially outputting data from the single-tap data output terminal; then keeping int_sw_ctrl<0:k / 2-1> low, int_sw_ctrl <k 2>Keep it high, int_sw_ctrl<k / 2+1> to go high, int_sw_ctrl<k / 2+2:k-1> Keep it low to complete the signal input terminal col_data_in of the 4-column stage circuit.<n / 2+j, n / 2+j+1,…, n / 2+2j-1> The data is output sequentially from the single-tap data output terminal; this process continues until int_sw_ctrl<0:k / 2-1> is kept low, and int_sw_ctrl... <k 2:k-2>Keep it high, int_sw_ctrl <k-1>The signal level changes to high, completing the signal input of the 4-column stage circuit col_data_in.<n-j, n-j+1,…, n-1> The data is output sequentially from the single-tap data output terminal, thereby completing the process of all column-level circuit signal input terminal data being output from their single-tap data output terminals in circuit 4. The relevant timing is then input to circuit 2 again to repeat this process.

[0074] In a preferred embodiment of the present invention, this embodiment is intended to illustrate the operation of circuit 1 in conjunction with a practical working scenario, wherein m=4, n=32, k=8, then j=4, which means that circuit 1 in this embodiment supports 4-bit width output and contains 4 circuits 4; each circuit 4 has 32 column-level circuit signal input terminals, and a driver is set every 4 column-level circuit signal input terminals, for a total of 8 drivers; then circuit 2 has a total of 32 flip-flops, and circuit 3 has 7 circuits 5.

[0075] The circuit diagram used in the preferred embodiment is as follows: Figure 6 As shown, the timing diagram used in circuit 6 is as follows: Figure 7 As shown. Circuit 6, in addition to the various circuits contained in Circuit 1, also includes 32 four-bit pulse counters 601, 602, and 603 (numbered 0, 1, ..., 31). These counters count the number of pulses of the input clock pulse signal and output the count result. This process is usually the final step in the operation of certain types of analog-to-digital converters. Each pulse counter has a counting pulse input terminal (count_in), a reset signal input terminal (count_rst), and a counting result output bus (count_out<3:0>). In Circuit 6, the counting pulse input terminals of the 0th to 31st pulse counters are connected to the 0th to 31st counting pulse input terminals 610, 611, and 612 of Circuit 6, respectively. The reset signal input terminals of all counters are connected to the pulse counter reset signal input terminal 613 of Circuit 6. The counting result output terminal (count_out) of the 0th to 31st pulse counters... <0> A total of 32 wires are used as buses to connect one-to-one with the column-level circuit signal input terminal col_data_in<0:31> of the 0th signal transmission circuit 606, and the counting result output terminal count_out of the 0th to 31st pulse counters. <1> A total of 32 wires are used as buses to connect one-to-one with the column-level circuit signal input terminals col_data_in<0:31> of the first signal transmission circuit 607, and so on, completing the connection of the pulse counter's counting result output terminal to each circuit 4. The single-tap data output terminals of the 0th to 3rd signal transmission circuits 606, 607, 608, and 609 serve as the 0th to 3rd single-tap data output terminals 614, 615, 616, and 617 of circuit 6. The clock signal input terminal of the enable pulse generation circuit 604 (i.e., circuit 2) serves as the clock signal input terminal 618 of circuit 6. The enable pulse signal input terminal of the enable pulse generation circuit 604 (i.e., circuit 2) serves as the enable pulse signal input terminal 619 of circuit 6. The timing generation circuit 605 serves as a bridge between the enable pulse generation circuit 604 and the signal transmission circuits 606, 607, 608, and 609.

[0076] The driving method corresponding to the digital driving circuit based on the above preferred embodiment includes the following:

[0077] First, a low-level reset pulse is input to the reset signal input terminal of circuit 6 to clear the counter output. Then, clock pulse signals with pairwise equal or unequal pulse counts are input to the counting pulse input terminals of each counter. The pulse count is immediately reflected on the counting result output terminal bus of each counter. When no more pulses are input, the final counting result will be retained on the counting result output terminal bus of each counter. Inputting a low-level reset pulse to the clock signal input terminal and enable pulse signal input terminal of circuit 6 is as follows: Figure 7 The signal shown in the waveform can be successively obtained according to the principle described above. Figure 7 The waveforms of the column-level circuit output switch control signal col_sw_en and the signal transmission control timing signal int_sw_ctrl are shown in the diagram. col_sw_en controls the output switches of each column-level circuit in circuit 4, sequentially allowing data from the signal input terminals of each column-level circuit to the signal transmission driver chain in circuit 4. int_sw_ctrl synchronously controls the output state of each tri-state gate driver in circuit 4 to be either high impedance or not, ensuring no signal transmission conflicts. Data from the output bus of each counter can be successively obtained from the single-tap data terminal col_data_out<3:0> of circuit 6, with each data segment lasting for one clock cycle. Figure 7 As shown, if the final numbers obtained by the 0th, 1st, and 31st counters are 6 (binary 0110), 9 (binary 1001), and 12 (binary 1100) respectively, then in col_sw_en <0> When the level is high, the binary data 0110 is obtained in col_data_out<3:0>, and col_sw_en <1> When the level is high, the binary data 1001 is obtained in col_data_out<3:0>, and col_sw_en <31> When the level is high, the binary data 1100 is obtained in col_data_out<3:0>.

[0078] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents. < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / n> < / k>

Claims

1. A digital signal driving circuit with multi-channel input and single-channel output, comprising an enable pulse generation circuit, a timing generation circuit, and m signal transmission circuits; characterized in that, The enable pulse generation circuit has one clock signal input terminal, one enable pulse signal input terminal, and n column-level circuit output switch control signal output terminals; the timing generation circuit has k column-level circuit output switch control signal input terminals and k signal transmission control timing output terminals; each signal transmission circuit has n column-level circuit signal input terminals, n column-level circuit output switch control signal input terminals, k signal transmission control timing input terminals, and one single-tap data output terminal; n / k=j; n, k, j, and m are all positive integers, and n and k are even numbers; j is not less than 2, and k is not less than 4; In this circuit, the n column-level circuit signal input terminals of each signal transmission circuit correspond one-to-one as the n column-level circuit signal input terminal bus of the digital signal driving circuit; the single-tap data output terminals of the m signal transmission circuits correspond one-to-one as the m single-tap data output terminals of the digital signal driving circuit; the k signal transmission control timing output terminals of the timing generation circuit are connected one-to-one to the k signal transmission control timing input terminals of each signal transmission circuit; the clock signal input terminal and the enable pulse signal input terminal of the enable pulse generation circuit are respectively the clock signal input terminal and the enable pulse signal input terminal of the digital signal driving circuit; the n column-level circuit output switch control signal output terminals of the enable pulse generation circuit are connected one-to-one to the n column-level circuit output switch control signal input terminals of the m signal transmission circuits; and the k column-level circuit output switch control signal output terminals of the enable pulse generation circuit are connected one-to-one to the k column-level circuit output switch control signal input terminals of the timing generation circuit. The signal transmission circuit includes k digital signal drivers with tri-state gates and n column-level circuit output switches. In the 0th to (k / 2-1)th drivers, the output terminal of the previous driver is connected to the input terminal of the next driver, and in the (k / 2-1)th to (k-1)th drivers, the input terminal of the previous driver is connected to the output terminal of the next driver. The input terminal of each driver is sequentially connected to the output terminal of j column-level circuit output switches. The state control terminals of the 0th to (k-1)th drivers are sequentially connected to k signal transmission control timing input terminals of the signal transmission circuit. The signal input terminals of the 0th to (n-1)th column-level circuits of the signal transmission circuit are sequentially connected to the input terminals of the 0th to (n-1)th column-level circuit output switches. The output terminal of the (k / 2-1)th driver is connected to the single-tap data output terminal of the signal transmission circuit.

2. The digital signal driving circuit with multi-channel input and single-channel output according to claim 1, characterized in that, The enable pulse generation circuit includes n cascaded D flip-flops, with the Q output of the previous D flip-flop connected to the D input of the next D flip-flop; the clock inputs of the n D flip-flops are connected to the same clock signal input, wherein the D input of the first D flip-flop is connected to the enable pulse signal input, and the Q outputs of the n D flip-flops serve as the outputs of the n column-level circuit output switch control signals.

3. The digital signal driving circuit with multi-channel input and single-channel output according to claim 1, characterized in that, The timing generation circuit includes (k-1) cascaded timing generation sub-circuits; each timing sub-circuit has a start switch pulse input terminal, an end switch pulse input terminal, a switch pulse transmission output terminal, and a switch pulse transmission inverted output terminal; the switch pulse transmission output terminal of the previous timing generation sub-circuit is connected to the start switch pulse input terminal of the next timing generation sub-circuit, forming a cascaded circuit; wherein, the switch pulse transmission output terminals of the 0th to (k / 2-1)th timing generation sub-circuit are sequentially connected to the first k / 2 signal transmission control timing output terminals, and the switch pulse transmission inverted output terminals of the (k / 2-1)th to (k-2)th timing generation sub-circuit are sequentially connected to the last k / 2 signal transmission control timing output terminals; the start switch pulse input terminal of the 0th timing generation sub-circuit and the end switch pulse input terminals of the 0th to (k-2)th timing generation sub-circuit are sequentially connected to the output switch control signal input terminals of k column-level circuits.

4. The digital signal driving circuit with multi-channel input and single-channel output according to claim 3, characterized in that, The timing generation subcircuit includes two inverters, three OR gates, one AND gate, and one latch. The input of the first inverter is connected to the end switch pulse input of the timing generation subcircuit, and its output is connected to the first input of the first AND gate. The second input of the first AND gate is connected to the data output of the first latch, and its output is connected to the second input of the second OR gate. The first input of the second OR gate is connected to the start switch pulse input of the timing generation subcircuit, and its output is connected to the data input of the first latch. The latch pulse output of the first latch... The input terminal is connected to the output terminal of the first OR gate; the first input terminal of the first OR gate is connected to the start switch pulse input terminal of the timing generation sub-circuit, and its second input terminal is connected to the end switch pulse input terminal of the timing generation sub-circuit; the first input terminal of the third OR gate is connected to the end switch pulse input terminal of the timing generation sub-circuit, its second input terminal is connected to the data output terminal of the first latch, and its output terminal is connected to the switch pulse transmission output terminal of the timing generation sub-circuit and the input terminal of the second inverter; the output terminal of the second inverter is connected to the switch pulse transmission inverted output terminal of the timing generation sub-circuit.

5. A method for driving digital signals with multiple inputs and a single output, used to implement a digital signal driving circuit with multiple inputs and a single output as described in any one of claims 1 to 4, characterized in that, The method includes: Input a clock signal at the clock signal input terminal of the enable pulse generation circuit, and input a high-level pulse with a length of one clock cycle that can be recognized by the clock trigger edge at the enable pulse signal input terminal; In the column-level circuit of the enable pulse generation circuit, the output switch control signal output terminal outputs high-level pulses with a length of one clock cycle in the order of the 0th to (n-1)th ports. The n column-level circuit output switch control signals are used to sequentially close and open all the column-level circuit output switches in the m signal transmission circuits, so that the signals on the bus at the data input terminal of each column-level circuit sequentially enter each signal transmission circuit for transmission. k column-level circuit output switch control signals are output to the timing generation circuit to generate timing sequences that control the opening and closing of k driver-related switches in each signal transmission circuit. The generated timing sequences are output from the k signal transmission control timing output terminals of the timing generation circuit to the signal transmission control timing input terminals of each signal transmission circuit. The signals collected by the signal transmission circuit from the corresponding column-level circuits are sequentially output from the single-tap data output terminals of each signal transmission circuit. When a clock cycle ends, the input clock of the enable pulse generation circuit remains unchanged, and a high-level pulse with a length of one clock cycle that can be recognized by the clock trigger edge is sent to its enable pulse signal input terminal again, that is, the above process is repeated; the pulse width of each column-level circuit data is one clock cycle, and it takes one large cycle, i.e., n clock cycles, to complete the data output of all columns.

6. The digital signal driving method with multi-channel input and single-channel output according to claim 5, characterized in that, The operation of the enable pulse generation circuit includes: A clock signal is input to the clock signal input terminal of the enable pulse generation circuit. A high-level pulse with a length of one clock cycle and recognizable by the clock trigger edge is input to the enable pulse signal input terminal. After a certain time delay following the occurrence of the clock trigger edge, the 0th flip-flop of the enable pulse generation circuit outputs a high-level pulse with a length of one clock cycle at the Q output terminal. The pulse output at the Q output terminal is used as the signal output terminal of the column circuit output switch control signal output terminal. At the same time, the pulse output by the Q output terminal of the 0th flip-flop is input to the D input terminal of the 1st flip-flop, and the above clock triggering process is repeated. The pulse input at the enable pulse signal input terminal is transmitted through the flip-flops in the enable pulse generation circuit until the column circuit output switch control signal output terminal outputs a pulse in the nth clock cycle, ending the operation of one large cycle.

7. A digital signal driving method with multi-channel input and single-channel output according to claim 5, characterized in that, The operation of the timing generation circuit includes: The timing generation circuit includes k-1 cascaded timing generation sub-circuits; A high-level pulse with a duration of one clock cycle is input to the output switch control signal input terminals of the 0th and (j-1)th column-level circuits, respectively. After processing by the 0th timing generation sub-circuit, a pulse with a rising edge coinciding with the rising edge of the pulse input to the 0th column-level circuit and a falling edge coinciding with the falling edge of the pulse input to the (j-1)th column-level circuit is generated at the switch pulse transmission output terminal of the 0th timing generation sub-circuit. This pulse has a high-level width of j clock cycles. The pulse generated at the output terminal of the 0th timing generation sub-circuit is then used to control the timing output from the signal transmission of the timing generation circuit. The output is used to control the corresponding switch in the signal transmission circuit, and is simultaneously input to the start switch pulse input terminal of the first timing generation sub-circuit. Repeat the above process, and input a high-level pulse with a duration of one clock cycle to the end switch pulse input terminal of the first to (k / 2-1) timing generation sub-circuits in sequence. The switch pulse transmission output terminal of the first to (k / 2-1) timing generation sub-circuits in the timing generation circuit will serve as the first to (k / 2-1) signal transmission control timing output terminal of the timing generation circuit. The output pulses will have rising edges that coincide with the rising edge of the input pulse of the 0th column circuit output switch control signal input terminal, falling edges that coincide with the falling edge of the input pulse of the (2j-1), (3j-1), ..., (n / 2-1)th column circuit output switch control signal input terminal, and high-level pulses with a width of 2j, 3j, ..., n / 2 clock cycles, respectively. The inverting output terminal of the switching pulse transmission of the (k / 2-1)th timing generation sub-circuit outputs a signal inverted from its switching pulse transmission output terminal. Its rising edge coincides with the falling edge of the (k / 2-1)th transmission control timing output terminal of the timing generation circuit, and its falling edge coincides with the rising edge of the pulse received by the input terminal of the column-level circuit output switching control signal for the next large cycle. Its high-level width is at least n / 2 clock cycles. The inverting output terminal of the switching pulse transmission of the (k / 2-1)th timing generation sub-circuit outputs a signal inverted from its switching pulse transmission output terminal as the (k / 2)th signal transmission control timing output terminal of the timing generation circuit. This process is repeated sequentially at the k / th... The output switch control signal input terminals of the 2~(k-2) column-level circuits are respectively input with a high-level pulse duration of one clock cycle. After being processed by the k / 2~(k-2)th timing generation sub-circuit, the rising edge of the output switch control signal input terminal of the column-level circuit of the timing generation circuit is transmitted from their switching pulses to the inverted output terminal. The falling edge of the output switch control signal input terminal of the column-level circuit overlaps with the falling edge of the pulse received by the output switch control signal input terminal of the column-level circuit, and the falling edge is uniformly overlapped with the rising edge of the pulse received by the 0th column-level circuit output switch control signal input terminal of the next large cycle. The high-level pulse width is at least (n / 2-j), (n / 2-2j), ..., j clock cycles. This completes the operation of one large cycle.

8. A digital signal driving method with multi-channel input and single-channel output according to claim 7, characterized in that, The operation of the timing generation sub-circuit includes: Pulses with a certain high-level duration are input to the start switch pulse input terminal and the end switch pulse input terminal of the timing generation sub-circuit, respectively. The high-level portions of the start switch pulse and the end switch pulse should not overlap, and the pulse input to the end switch pulse input terminal should arrive at the timing generation sub-circuit later than the pulse input to the start switch pulse input terminal. Then, two pulses are generated before and after the first OR gate, respectively used for data latching of the first latch. A sample-and-hold device is constructed from the first inverter, the first AND gate, the second OR gate, and the first register. When a pulse is input to the start switch pulse input terminal, the first register samples, and its data output terminal starts outputting a high level. When the high-level pulse input to the start switch pulse input terminal ends, the first latch changes from the sampling state to the latching state, and its data output terminal remains at a high level until the end switch pulse input terminal receives a high level, at which point the first latch re-enters the sampling state. When a low-level sample is received at the first input of the first AND gate, the data output of the first latch outputs a low level. When a high-level pulse is input to the end switch pulse input, the first latch returns to the latched state, and the data output remains low. Then, the high-level pulse output from the data output of the first register is concatenated with the pulse output from the end switch pulse input in the time domain using the third OR gate. Finally, a long pulse is obtained at the output of the third OR gate, i.e., the switch pulse transmission output of the sequential generation circuit. The rising edge of the pulse coincides with the rising edge of the pulse input to the start switch pulse input, the falling edge coincides with the falling edge of the pulse input to the end switch pulse input, and the high-level time is the sum of the mutual delay time of the rising edges of the start switch pulse and the high-level time of the pulse input to the end switch pulse input. The inverted signal of the long pulse is obtained at the switch pulse transmission inverting output.

9. A digital signal driving method with multi-channel input and single-channel output according to claim 5, characterized in that, The operation of the signal transmission circuit includes: The state control terminal of the tri-state gate in the signal transmission circuit maintains normal buffer output when it receives a high level, and the output terminal is in a high-impedance state when it receives a low level. By controlling the enable pulse generation circuit, the timing generation circuit is controlled to input a high level to the 0th to (k / 2-1th)th signal transmission control timing input terminals of the signal transmission circuit, and a low level to the k / 2th to (k-1th)th signal transmission control timing input terminals. At this time, the 0th to (k / 2-1th)th drivers maintain normal buffer output, while the k / 2th to (k-1th)th drivers enter a high-impedance state, which is regarded as the output terminal of the k / 2th driver being disconnected from the single-tap data output terminal of the signal transmission circuit. At the same time, under the control of the enable pulse generation circuit, the output switches of the 0th to (j-1th)th column circuits in the signal transmission circuit are closed and opened in sequence, and the closing process does not overlap. The data input to the signal input terminals of the 0th to (j-1th)th column circuits in the signal transmission circuit enters the digital signal driver of the tri-state gate of the signal transmission circuit in sequence, and finally reaches its single-tap data output terminal through its 0th to (k / 2-1th)th drivers to complete the data output. By sequentially controlling the enable pulse generation circuit to make the 0th to (k-1)th signal transmission control timing input terminals of the signal transmission circuit high or low level, the process of outputting data from the single tap data output terminals of all column-level circuit signal input terminals in the signal transmission circuit is completed.

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