Three-dimensional ferroelectric memory and electronic device

Abstract

The embodiment of the application belongs to the technical field of storage devices, and particularly relates to a three-dimensional ferroelectric memory and an electronic device. The embodiment of the application aims to solve the problem that the size of the three-dimensional ferroelectric memory is large in the related art, and miniaturization of the three-dimensional ferroelectric memory is difficult to realize. The three-dimensional ferroelectric memory and the electronic device of the embodiment of the application, the storage layer comprises a reference layer, a first dielectric layer is arranged on the side of the reference layer away from the substrate, the first dielectric layer comprises a plurality of first storage blocks arranged at intervals, a second dielectric layer is arranged on the side of the reference layer toward the substrate, and the second dielectric layer comprises a plurality of second storage blocks arranged at intervals; the first dielectric layer and the second dielectric layer share one reference layer, compared with one dielectric layer corresponding to one reference layer, the number of the reference layers is reduced, and then the size of the three-dimensional ferroelectric memory in the direction perpendicular to the substrate is reduced, and then the volume of the three-dimensional ferroelectric memory is reduced, and miniaturization of the three-dimensional ferroelectric memory is realized.

Description

Technical Field

[0001] This application relates to the field of storage device technology, and in particular to a three-dimensional ferroelectric memory and electronic device. Background Technology

[0002] With the gradual development of storage device technology, three-dimensional ferroelectric memory has broad application prospects due to its fast read and write speed and high storage capacity.

[0003] In related technologies, a three-dimensional ferroelectric memory includes a substrate and multiple storage layers, which are stacked sequentially along a direction perpendicular to the substrate. Each storage layer includes a reference layer and a dielectric layer located on the side of the reference layer facing away from the substrate. The dielectric layer includes multiple storage blocks arranged in an array on the reference layer. Each storage block, together with the reference layer, constitutes a storage cell, and both the storage blocks and the reference layer are made of ferroelectric material. Each storage block is connected to a bit line and a word line, which enable information reading and writing.

[0004] However, in related technologies, the dielectric layer and the reference layer correspond one-to-one, which makes the size of the three-dimensional ferroelectric memory large in the direction perpendicular to the substrate, making it difficult to miniaturize the three-dimensional ferroelectric memory. Summary of the Invention

[0005] The purpose of this application is to provide a three-dimensional ferroelectric memory and electronic device. By providing a first dielectric layer on the side of each reference layer away from the substrate and a second dielectric layer on the side of the reference layer facing the substrate, and by having the two dielectric layers share a single reference layer, the number of reference layers in the three-dimensional ferroelectric memory is reduced, thereby reducing the volume of the three-dimensional ferroelectric memory and achieving miniaturization of the three-dimensional ferroelectric memory.

[0006] This application discloses a three-dimensional ferroelectric memory, including: a substrate and a plurality of storage layers stacked on the substrate; each of the plurality of storage layers includes a reference layer, a first dielectric layer disposed on the side of the reference layer away from the substrate, and a second dielectric layer disposed on the side of the reference layer facing the substrate. The first dielectric layer includes a plurality of first storage blocks spaced apart, and the second dielectric layer includes a plurality of second storage blocks spaced apart. Each of the plurality of first storage blocks and each of the plurality of second storage blocks is attached to the reference layer. Each first storage block and the reference layer are combined to form a first storage cell, and each second storage block and the reference layer are combined to form a second storage cell.

[0007] Based on the above technical content, the first dielectric layer and the second dielectric layer share a reference layer, which means that the number of reference layers is half the number of each dielectric layer. Compared with setting one dielectric layer for each reference layer, the number of reference layers is reduced, thereby reducing the size of the three-dimensional ferroelectric memory in the direction perpendicular to the substrate, and thus reducing the volume of the three-dimensional ferroelectric memory, realizing the miniaturization of the three-dimensional ferroelectric memory.

[0008] In one implementation, a plurality of first memory blocks and a plurality of second memory blocks are arrayed, and the plurality of first memory blocks and the plurality of second memory blocks correspond one-to-one in a direction perpendicular to the reference layer; the first dielectric layer further includes a first electrode bonded to one side of the first memory block and a second electrode bonded to the other side of the first memory block; the second dielectric layer further includes a third electrode bonded to one side of the second memory block and a fourth electrode bonded to the other side of the second memory block.

[0009] With this configuration, data writing and reading of the first storage cell formed between the first storage block and the reference layer can be achieved through the first electrode and the second electrode. Similarly, data writing and reading of the second storage cell formed between the second storage block and the reference layer can be achieved through the third electrode and the fourth electrode.

[0010] In one implementation, the three-dimensional ferroelectric memory further includes a first connecting layer located on the side of the first memory block away from the substrate and a second connecting layer located on the side of the second memory block facing the substrate. The first connecting layer includes a plurality of parallel and spaced first connecting lines, each of which is connected to a first electrode corresponding to a column of the first memory blocks. The second connecting layer includes a plurality of parallel and spaced second connecting lines, each of which is connected to a third electrode corresponding to a column of the second memory blocks.

[0011] With this configuration, power can be supplied to the corresponding first electrode via the first connection line and to the corresponding third electrode via the second connection line, so as to facilitate the reading of data in the first storage unit and the second storage unit, or the writing of data into the first storage unit and the second storage unit.

[0012] In one implementation, the three-dimensional ferroelectric memory further includes a third connecting layer located on the side of the first memory block away from the substrate and a fourth connecting layer located on the side of the second memory block facing the substrate. The third connecting layer includes a plurality of parallel and spaced third connecting lines, each of which is connected to a second electrode corresponding to a row of the first memory block. The fourth connecting layer includes a plurality of parallel and spaced fourth connecting lines, each of which is connected to a fourth electrode corresponding to a row of the second memory block.

[0013] With this configuration, a first storage block can be uniquely identified by a first connection line and a third connection line, so as to accurately read data from or write data into the first storage cell composed of the first storage block and the reference layer; similarly, a second storage block can be uniquely identified by a second connection line and a fourth connection line, so as to accurately read data from or write data into the second storage cell composed of the second storage block and the reference layer.

[0014] In one implementation, the first connection layer is located between the first storage block and the third connection layer, and the second connection layer is located between the second storage block and the fourth connection layer.

[0015] With this setup, the planes where the first connecting lines are located are parallel and spaced apart from the planes where the third connecting lines are located, and the planes where the second connecting lines are located are parallel and spaced apart from the planes where the fourth connecting lines are located. The wiring is more reasonable, avoiding mutual interference between the first and third connecting lines, as well as between the second and fourth connecting lines.

[0016] In one implementation, a second electrode connected to the first storage block and a fourth electrode connected to the second storage block are connected in opposite first and second storage blocks.

[0017] With this configuration, the second electrode corresponding to the first storage block in each row and the fourth electrode corresponding to the second storage block can share a common connection line, thereby reducing the number of conductive layers in the three-dimensional ferroelectric memory and further reducing the volume of the three-dimensional ferroelectric memory.

[0018] In one implementation, a through-hole is provided on the reference layer, and in the first and second memory blocks disposed opposite to each other, a second electrode coupled to the first memory block and a fourth electrode coupled to the second memory block are connected by a conductive block disposed in the through-hole.

[0019] The connection between the second electrode, which is bonded to the first memory block, and the fourth electrode, which is bonded to the second memory block, is achieved by a conductive block located inside the through hole. This eliminates the need for wiring outside the reference layer to connect the second electrode and the fourth electrode, resulting in a simple structure that is easy to manufacture.

[0020] In one implementation, the conductive block, the corresponding second electrode, and the fourth electrode are integrated into a single structure.

[0021] This setup simplifies the fabrication of three-dimensional ferroelectric memory by allowing the conductive block, corresponding second electrode, and fourth electrode to be formed in a single process.

[0022] In one implementation, the three-dimensional ferroelectric memory includes a third connection layer, which includes a plurality of parallel and spaced third connection lines, each of which is connected to a second electrode corresponding to a row of first memory blocks.

[0023] With this configuration, within the same storage layer, a third connection line can be used to connect the second electrodes in a row of the first storage block and the fourth electrodes in a row of the second storage block opposite to the first storage block.

[0024] In one implementation, the three-dimensional ferroelectric memory includes a third connection layer, which includes a plurality of parallel and spaced third connection lines, each of which is connected to a fourth electrode corresponding to a row of second memory blocks.

[0025] In one implementation, a plurality of first conductive lines are provided between adjacent memory layers. One end of each of the plurality of first conductive lines is connected to a third electrode in a memory layer away from the substrate, and the other end of each of the plurality of first conductive lines is connected to a corresponding first electrode in a memory layer close to the substrate.

[0026] With this configuration, the first electrode in the storage layer near the substrate and the third electrode in the storage layer far from the substrate are connected by a first conductive line between adjacent storage layers. This allows each of the first electrode in the storage layer near the substrate and the third electrode in the storage layer far from the substrate to have a corresponding line for connection to external devices. Compared to having separate conductive layers for each of the first electrode in the storage layer near the substrate and the third electrode in the storage layer far from the substrate, this configuration reduces the number of conductive layers in the three-dimensional ferroelectric memory, thereby reducing the volume of the three-dimensional ferroelectric memory.

[0027] In one implementation, a plurality of second conductive lines are disposed between two adjacent storage layers. One end of each of the plurality of second conductive lines is connected to a fourth electrode in the storage layer away from the substrate, and the other end of each of the plurality of second conductive lines is connected to a corresponding second electrode in the storage layer close to the substrate. The three-dimensional ferroelectric memory also includes a fourth connection layer, which includes a plurality of fourth connection lines arranged in parallel and spaced apart. Each of the plurality of fourth connection lines is connected to a row of second conductive lines.

[0028] With this configuration, the fourth electrode in the storage layer furthest from the substrate and the second electrode in the storage layer closest to the substrate can be connected via the second conductive line. Since the second and fourth electrodes are connected in the opposing first and second storage blocks in each storage layer, the second conductive line also connects the second and fourth electrodes in the first and second storage blocks perpendicular to the substrate in the entire three-dimensional ferroelectric memory. In the entire three-dimensional ferroelectric memory, the second and fourth electrodes in the first and second storage blocks perpendicular to the substrate can be connected to external devices via a connecting line. Compared to setting a connecting line for the second electrode in each storage layer, the number of conductive layers in the three-dimensional ferroelectric memory can be further reduced, thereby reducing the volume of the three-dimensional ferroelectric memory.

[0029] In one implementation, a fourth connection layer is disposed between the substrate and a storage layer adjacent to the substrate, and each of the plurality of fourth connection lines is connected to a fourth electrode corresponding to a row of second storage blocks in the storage layer adjacent to the substrate.

[0030] The second electrode of the first storage block in the same row and the fourth electrode of the second storage block in the corresponding row are led out through the fourth connection line of the storage layer located near the substrate and facing the substrate. There is no need to set the fourth connection line between each storage layer, which further reduces the volume of the three-dimensional ferroelectric memory.

[0031] In one implementation, a fourth connection layer is disposed on the side of the storage layer away from the substrate, and each of the plurality of fourth connection lines is connected to a second electrode corresponding to a row of first storage blocks in the storage layer away from the substrate.

[0032] The second electrode of the first storage block in the same row and the fourth electrode of the second storage block in the corresponding row are led out through the fourth connection line located on the side of the storage layer facing the substrate away from the substrate. There is no need to set the fourth connection line between each storage layer, which further reduces the volume of the three-dimensional ferroelectric memory.

[0033] In one implementation, an insulating dielectric layer is provided between adjacent storage layers.

[0034] Insulating layers can be used to isolate adjacent reference layers. Insulating dielectric layers can separate two memory layers, providing an insulating connection between them to prevent interference.

[0035] In one implementation, the reference layer, the first memory block, and the second memory block all include resistive switching materials, phase change materials, and resistive switching structures.

[0036] In one implementation, the reference layer, the first storage block, and the second storage block all include ferroelectric materials.

[0037] This application also discloses an electronic device, including a circuit board and a three-dimensional ferroelectric memory connected to the circuit board, wherein the three-dimensional ferroelectric memory is the three-dimensional ferroelectric memory as described above.

[0038] The electronic device provided in this application embodiment has multiple storage layers stacked on a substrate in a three-dimensional ferroelectric memory. Each storage layer includes a reference layer. A first dielectric layer is disposed on the side of the reference layer away from the substrate. The first dielectric layer includes multiple spaced-apart first storage blocks. A second dielectric layer is disposed on the side of the reference layer facing the substrate. The second dielectric layer includes multiple spaced-apart second storage blocks. Both the first and second storage blocks are attached to the reference layer so that the first storage blocks and the reference layer are combined to form a first storage unit, and the second storage blocks and the reference layer are combined to form a second storage unit. Data is stored in each of the first and second storage units. The first and second dielectric layers share a single reference layer, meaning that the number of reference layers is half the number of dielectric layers. Compared to a single dielectric layer corresponding to a single reference layer, this reduces the number of reference layers, thereby reducing the size of the three-dimensional ferroelectric memory in the direction perpendicular to the substrate, and thus reducing the volume of the three-dimensional ferroelectric memory, achieving miniaturization of the three-dimensional ferroelectric memory. Attached Figure Description

[0039] Figure 1 Schematic diagram of the structure of the three-dimensional ferroelectric memory provided for the implementation of this application Figure 1 ;

[0040] Figure 2 for Figure 1 A three-dimensional structural diagram of a ferroelectric memory.

[0041] Figure 3 A top view of a three-dimensional ferroelectric memory provided for implementation of this application;

[0042] Figure 4 A schematic diagram showing that the first polarization direction and the second polarization direction are opposite in the three-dimensional ferroelectric memory provided for the implementation of this application;

[0043] Figure 5 A schematic diagram showing that the first polarization direction and the second polarization direction are the same in the three-dimensional ferroelectric memory provided for the implementation of this application;

[0044] Figure 6 Schematic diagram of the structure of the three-dimensional ferroelectric memory provided for the implementation of this application Figure 2 ;

[0045] Figure 7 Schematic diagram of the structure of the three-dimensional ferroelectric memory provided for the implementation of this application Figure 3 ;

[0046] Figure 8 for Figure 7 A three-dimensional structural diagram of a ferroelectric memory.

[0047] Figure 9 Schematic diagram of the structure of the three-dimensional ferroelectric memory provided for the implementation of this application Figure 4 ;

[0048] Figure 10 Schematic diagram of the structure of the three-dimensional ferroelectric memory provided for the implementation of this application Figure 5 ;

[0049] Figure 11 for Figure 10 A three-dimensional structural diagram of a ferroelectric memory.

[0050] Explanation of reference numerals in the attached figures:

[0051] 1: Base;

[0052] 2: Storage layer;

[0053] 3: First conductive line;

[0054] 4: Second conductive wire;

[0055] 5: Insulating dielectric layer;

[0056] 20: Reference layer;

[0057] 30: First storage block;

[0058] 40: Second storage block;

[0059] 50: First connecting line;

[0060] 60: Second connecting line;

[0061] 70: Third connecting line;

[0062] 80: Fourth connecting line;

[0063] 201: Conductive block;

[0064] 301: First electrode;

[0065] 302: Second electrode;

[0066] 401: Third electrode;

[0067] 402: Fourth electrode;

[0068] L: Pre-determined distance. Detailed Implementation

[0069] The terminology used in the implementation section of this application is only for explaining specific embodiments of this application and is not intended to limit this application. The implementation of the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0070] With the gradual development of storage device technology, three-dimensional ferroelectric memories have become a research hotspot due to their high storage capacity and fast read / write speeds. Among them, ferroelectric memories that realize data reading and writing by utilizing the ferroelectric polarization characteristics of ferroelectric materials have been widely used.

[0071] In related technologies, a three-dimensional ferroelectric memory includes a substrate and multiple storage layers stacked on the substrate. Each storage layer includes a reference layer and a dielectric layer disposed on the side of the reference layer away from the substrate. The dielectric layer includes multiple storage blocks arrayed on the reference layer. Both the storage blocks and the reference layer are made of ferroelectric material, and the storage blocks and the reference layer constitute a storage cell. Each storage block is connected to a bit line and a word line. The word line and the bit line are arranged perpendicularly, and the data in the storage cell can be read or written through the word line and the bit line.

[0072] However, in related technologies, each dielectric layer is provided with a corresponding reference layer, which makes the size of the three-dimensional ferroelectric memory larger along the direction perpendicular to the substrate, resulting in a large volume of the three-dimensional ferroelectric memory and making it difficult to miniaturize the three-dimensional ferroelectric memory.

[0073] This application provides a three-dimensional ferroelectric memory. By having two adjacent dielectric layers share a single reference layer, the number of reference layers in the three-dimensional ferroelectric memory is reduced, thereby reducing the size of the three-dimensional ferroelectric memory along the direction perpendicular to the substrate and achieving miniaturization of the three-dimensional ferroelectric memory.

[0074] Figure 1 Schematic diagram of the structure of the three-dimensional ferroelectric memory provided for the implementation of this application Figure 1 , Figure 2 for Figure 1 A three-dimensional structural diagram of a ferroelectric memory, as shown below. Figure 1 and Figure 2 As shown. The three-dimensional storage provided in this application embodiment includes a substrate 1 and a plurality of storage layers 2 stacked on the substrate 1, wherein the substrate 1 is used to support each storage layer 2, and the material of the substrate 1 can be one or more of single crystal silicon, silicon germanium or germanium.

[0075] Data is stored in each storage layer 2. The storage layer 2 includes a reference layer 20, a first medium layer disposed on the side of the reference layer 20 away from the substrate 1, and a second medium layer disposed on the side of the reference layer 20 facing the substrate 1. The first medium layer includes a plurality of first storage blocks 30 spaced apart, and the second medium layer includes a plurality of second storage blocks 40 spaced apart. Both the first storage blocks 30 and the second storage blocks 40 are attached to the reference layer 20, such that the first storage blocks 30 and the reference layer 20 are combined to form a first storage cell, and the second storage blocks 40 and the reference layer 20 are combined to form a second storage cell. Data can be read and written on the first storage cell and the second storage cell.

[0076] In the above implementation, multiple first storage blocks 30 can be arrayed on the side of the reference layer 20 away from the substrate 1, and similarly, multiple second storage blocks 40 can be arrayed on the side of the reference layer 20 facing the substrate 1, making the arrangement of the first storage blocks 30 and the second storage blocks 40 relatively regular. Furthermore, the number of first storage blocks 30 and second storage blocks 40 can be the same, and the first storage blocks 30 and second storage blocks 40 correspond one-to-one in the direction perpendicular to the reference layer 20, that is, the projection of the first storage block 30 onto the reference layer 20 coincides with the projection of the second storage block 40 onto the reference layer 20.

[0077] In this embodiment, the first storage block 30 and the reference layer 20 are combined to form a first storage cell, and the second storage block 40 and the reference layer 20 are combined to form a second storage cell. For example, Figure 4 A schematic diagram showing that the first polarization direction and the second polarization direction are opposite in the three-dimensional ferroelectric memory provided for the implementation of this application. Figure 5 A schematic diagram showing the first and second polarization directions being the same in the three-dimensional ferroelectric memory provided for the implementation of this application is shown below. Figure 4 and Figure 5A domain wall channel can be formed between the first storage block 30 and the reference layer 20. The reference layer 20 has a first polarization direction, and the first storage block 30 has a second polarization direction. During data reading, when the first polarization direction and the second polarization direction are the same, no domain wall channel is formed between the first storage block 30 and the reference layer 20, and the first storage block 30 is in a high-resistance state. At this time, the data read from the first storage cell can be "0". Conversely, when the first polarization direction and the second polarization direction are opposite, a domain wall channel is formed between the first storage block 30 and the reference layer 20, and the data read from the first storage cell can be "0". In a low-resistivity state, the data read from the first storage cell can be "1". However, in this embodiment, when the first polarization direction is the same as the second polarization direction, no domain wall channel is formed between the first storage block 30 and the reference layer 20, and the first storage block 30 is in a high-resistivity state. In this case, the data read from the first storage cell can be "1". Conversely, when the first polarization direction is opposite to the second polarization direction, a domain wall channel is formed between the first storage block 30 and the reference layer 20, and the first storage block 30 is in a low-resistivity state. In this case, the data read from the first storage cell can be "0". In this embodiment, the second storage block 40 and the reference layer 20 form a second storage cell. The data reading principle of the second storage cell can be the same as that of the first storage cell, and will not be described further here.

[0078] During data writing, a preset voltage is applied to the first storage block 30. When the voltage reaches the preset voltage, the second polarization direction of the first storage block 30 is reversed. Due to the reversal of the second polarization direction, the first storage block 30 changes from a high-resistance state to a low-resistance state, and the data "1" is written to the first storage cell. Conversely, when the first storage block 30 changes from a low-resistance state to a high-resistance state, the data "0" is written to the first storage cell. Alternatively, when the voltage reaches the preset voltage, the second polarization direction of the first storage block 30 is reversed. Due to the reversal of the second polarization direction, the first storage block 30 changes from a high-resistance state to a low-resistance state, and the data "0" is written to the first storage cell. Conversely, when the first storage block 30 changes from a low-resistance state to a high-resistance state, the data "1" is written to the first storage cell. The data writing process for the second storage cell is largely the same as that for the first storage cell, and will not be described in detail here.

[0079] It is worth noting that this embodiment does not limit the preset voltage. As long as the second polarization direction of the first storage block 30 is reversed when the voltage on the first storage block 30 rises to the preset voltage, it is acceptable.

[0080] This embodiment does not limit the materials of the first memory block 30, the second memory block 40, and the reference layer 20, as long as it ensures that domain wall channels can be formed between the first memory block 30, the second memory block 40, and the reference layer 20, or that similar resistive switching characteristics can be formed between the first memory block 30, the second memory block 40, and the reference layer 20. For example, the reference layer 20, the first memory block 30, and the second memory block 40 can all include a resistive switching material, a phase change material, and a resistive switching structure; wherein, the resistive switching material can be nickel oxide (NiO), titanium oxide (TiOx), hafnium oxide (HfOx), etc., and the phase change material can be mGeTe. nSb₂Te₃(GST), vanadium dioxide ( The resistive switching structure can be a PN junction, a magnetic tunnel junction, a ferroelectric tunnel junction, etc. Furthermore, in this embodiment, the reference layer 20, the first memory block 30, and the second memory block 40 are all made of ferroelectric materials.

[0081] In the above implementation, in order to obtain or write data into the first and second storage units, a connection line is provided outside the reference layer 20 to connect to the first storage block 30 and the second storage block 40. During data reading, the current flowing through the first and second storage blocks 30 and 40 can be obtained through the connection line to determine the resistance state of the first and second storage blocks 30 and 40, thereby enabling the reading of data from the first and second storage units. During data writing, a voltage can be applied to the first and second storage units through the connection line. When the voltage reaches a preset voltage, the polarization direction of the first and second storage blocks 30 and 40 is changed to achieve data writing.

[0082] The three-dimensional ferroelectric memory provided in this embodiment has multiple storage layers 2 stacked on a substrate 1. Each storage layer 2 includes a reference layer 20. A first dielectric layer is disposed on the side of the reference layer 20 away from the substrate 1. The first dielectric layer includes multiple spaced first storage blocks 30. A second dielectric layer is disposed on the side of the reference layer 20 facing the substrate 1. The second dielectric layer includes multiple spaced second storage blocks 40. Both the first storage blocks 30 and the second storage blocks 40 are attached to the reference layer 20 so that the first storage blocks 30 and the reference layer 20 are combined to form a first storage cell, and the second storage blocks 40 and the reference layer 20 are combined to form a second storage cell. Data is stored in each of the first and second storage cells. The first dielectric layer and the second dielectric layer share a single reference layer 20. In other words, the number of reference layers 20 is half the number of dielectric layers. Compared with a single dielectric layer corresponding to each reference layer 20, the number of reference layers 20 is reduced, thereby reducing the size of the three-dimensional ferroelectric memory in the direction perpendicular to the substrate 1, and thus reducing the volume of the three-dimensional ferroelectric memory, achieving miniaturization of the three-dimensional ferroelectric memory.

[0083] Continue to refer to Figure 1 and Figure 2 In this embodiment, to facilitate connection with the first storage block 30, the first dielectric layer further includes a first electrode 301 disposed on one side of the first storage block 30 and a second electrode 302 disposed on the other side of the first storage block 30. Both the first electrode 301 and the second electrode 302 are connected to the first storage block 30, thereby allowing data in the first storage unit to be read through the first electrode 301 and the second electrode 302. Of course, data can also be written to the first storage unit through the first electrode 301 and the second electrode 302. Similarly, the second dielectric layer further includes a third electrode 401 disposed on one side of the second storage block 40 and a fourth electrode 402 disposed on the other side of the second storage block 40. Both the third electrode 401 and the fourth electrode 402 are connected to the second storage block 40, thereby allowing data in the second storage unit to be read through the third electrode 401 and the fourth electrode 402. Of course, data can also be written to the second storage unit through the third electrode 401 and the fourth electrode 402.

[0084] For example, the first electrode 301 and the second electrode 302 can both be made of metal materials such as copper and silver. Of course, the first electrode 301 and the second electrode 302 can also be made of other non-metallic conductive materials. Similarly, the third electrode 401 and the fourth electrode 402 can both be made of metal materials such as copper and silver. Of course, the third electrode 401 and the fourth electrode 402 can also be made of other non-metallic conductive materials.

[0085] In this embodiment, the three-dimensional ferroelectric memory can be a bipolar memory, meaning that the read direction of the three-dimensional ferroelectric memory does not depend on the polarization direction of the reference layer 20. That is, data can be read whether the polarization direction of the reference layer 20 is the same as or opposite to the current direction flowing through the first storage block 30. Similarly, data can be read whether the polarization direction of the reference layer 20 is the same as or opposite to the current direction flowing through the second storage block 40. Accordingly, when the voltage of the first electrode 301 is higher than the voltage of the second electrode 302, or when the voltage of the first electrode 301 is lower than the voltage of the second electrode 302, the first storage unit corresponding to the first storage block 30 can read data. Similarly, when the voltage of the third electrode 401 is higher than the voltage of the fourth electrode 402, or when the voltage of the third electrode 401 is lower than the voltage of the fourth electrode 402, the second storage unit corresponding to the second storage block 40 can read data.

[0086] Of course, the three-dimensional ferroelectric memory in this embodiment can also be a unipolar memory, that is, the read direction of the three-dimensional ferroelectric memory depends on the polarization direction of the reference layer 20. In other words, data can only be read when the polarization direction of the reference layer 20 is opposite to the current direction flowing through the first storage block 30. Similarly, data can only be read when the polarization direction of the reference layer 20 is opposite to the current direction flowing through the second storage block 40. Accordingly, the polarization direction of the reference layer 20 is from the first electrode 301 to the second electrode 302. Data can only be read from the first storage cell corresponding to the first storage block 30 when the voltage of the first electrode 301 is lower than the voltage of the second electrode 302. When the second electrode 302 points to the first electrode 301, the first storage cell corresponding to the first storage block 30 can only read data when the voltage of the first electrode 301 is higher than the voltage of the second electrode 302. Similarly, when the polarization direction of the reference layer 20 is the third electrode 401 pointing to the fourth electrode 402, the first storage cell corresponding to the first storage block 30 can only read data when the voltage of the third electrode 401 is lower than the voltage of the fourth electrode 402; and when the polarization direction of the reference layer 20 is the fourth electrode 402 pointing to the third electrode 401, the first storage cell corresponding to the first storage block 30 can only read data when the voltage of the third electrode 401 is higher than the voltage of the fourth electrode 402. This configuration allows the three-dimensional ferroelectric memory to be adapted to a wider range of applications.

[0087] In an implementation where multiple first storage blocks 30 and multiple second storage blocks 40 are arrayed and the first storage blocks 30 and second storage blocks 40 correspond one-to-one within the same storage layer 2, in the corresponding first storage blocks 30 and second storage blocks 40, the first electrode 301 can be directly opposite the third electrode 401, and the corresponding second electrode 302 can be directly opposite the fourth electrode 402.

[0088] Continue to refer to Figure 1 and Figure 2 In this embodiment, an insulating dielectric layer 5 is provided between adjacent storage layers 2. The insulating dielectric layer 5 can separate the two storage layers 2 and realize the insulating connection between the two storage layers 2 so as to prevent the two storage layers 2 from interfering with each other.

[0089] Figure 3 A top view of the three-dimensional ferroelectric memory provided for the implementation of this application, continuing to refer to... Figures 1-3In some embodiments, the three-dimensional ferroelectric memory includes a first connecting layer disposed on the side of the first storage block 30 facing away from the substrate 1 and a second connecting layer disposed on the side of the second storage block 40 facing the substrate 1. The first connecting layer includes a plurality of parallel and spaced first connecting lines 50, each of which is connected to a first electrode 301 corresponding to a column of the first storage block 30. The second connecting layer includes a plurality of parallel and spaced second connecting lines 60, each of which is electrically connected to a third electrode 401 of a column of the second storage block 40. This configuration allows power to be supplied to the corresponding first electrode 301 via the first connecting lines 50 and to the corresponding third electrode 401 via the second connecting lines 60, facilitating the reading of data from the first and second storage units or the writing of data to the first and second storage units.

[0090] Furthermore, the three-dimensional ferroelectric memory also includes a third connecting layer disposed on the side of the first storage block 30 away from the substrate 1 and a fourth connecting layer disposed on the side of the second storage block 40 facing the substrate 1. The third connecting layer includes a plurality of parallel and spaced third connecting lines 70, each of the plurality of third connecting lines 70 being connected to a second electrode 302 corresponding to a row of the first storage block 30. The fourth connecting layer includes a plurality of parallel and spaced fourth connecting lines 80, each of the plurality of fourth connecting lines 80 being connected to a fourth electrode 402 corresponding to a row of the second storage block 40.

[0091] With this configuration, data reading or writing of the corresponding first storage unit can be achieved through the first connection line 50 and the third connection line 70. Similarly, data reading or writing of the corresponding second storage unit can be achieved through the second connection line 60 and the fourth connection line 80.

[0092] In the above implementation, the first connecting line 50, the second connecting line 60, the third connecting line 70 and the fourth connecting line 80 can all be metal wires mainly made of metal materials such as copper and silver. Of course, the first connecting line 50, the second connecting line 60, the third connecting line 70 and the fourth connecting line 80 can also be mainly made of other non-metallic conductive materials.

[0093] The extension directions of the first connection line 50 and the second connection line 60 can be parallel to the column direction of the first storage block 30 and the second storage block 40, and the third connection line 70 and the fourth connection line 80 can be parallel to the row direction of the first storage block 30 and the second storage block 40. The first connection line 50 and the second connection line 60 can be word lines, and correspondingly, the third connection line 70 and the fourth connection line 80 are bit lines; conversely, the first connection line 50 and the second connection line 60 can be bit lines, and correspondingly, the third connection line 70 and the fourth connection line 80 are word lines. A first storage block 30 can be uniquely selected from multiple first storage blocks 30 arranged in the array using a first connection line 50 and a third connection line 70. That is, the intersection of any first connection line 50 and third connection line 70 is the selected first storage block 30. The first electrode 301 of the selected first storage block 30 is connected to the first connection line 50, and the second electrode 302 of the selected first storage block 30 is connected to the third connection line 70. Data reading and writing of the first storage cell corresponding to the selected first storage block 30 can be achieved through these first and third connection lines. Similarly, a second storage block 40 can be uniquely selected from multiple second storage blocks 40 arranged in the array using a second connection line 60 and a fourth connection line 80. Data reading and writing of the second storage cell corresponding to the selected second storage block 40 can be achieved through these second and fourth connection lines.

[0094] Continue to refer to Figure 1 and Figure 2 Furthermore, the first connecting line 50 can be disposed on the side of a corresponding column of first storage blocks 30 facing away from the substrate 1, and the first connecting line 50 is attached to the side of each first electrode 301 of the corresponding column of first storage blocks 30 facing away from the substrate 1, so that the first connecting line 50 can make good contact with each first electrode 301 of the corresponding column of first storage blocks 30. Similarly, the second connecting line 60 can be disposed on the side of a corresponding column of second storage blocks 40 facing the substrate 1, and the second connecting line 60 is attached to the side of each third electrode 401 of the corresponding column of second storage blocks 40 facing the substrate 1, so that the second connecting line 60 can make good contact with each third electrode 401 of the corresponding column of second storage blocks 40. The third connecting line 70 can be disposed on the side of each corresponding first storage block 30 facing away from the substrate 1, and the third connecting line 70 is attached to the side of each second electrode 302 of the corresponding row of first storage blocks 30 facing away from the substrate. The fourth connection line 80 can be disposed on the side of the corresponding row of second storage block 40 facing the substrate 1, and the fourth connection line 80 is attached to the side of the corresponding row of second storage block 40 facing the substrate 1, so that the fourth connection line 80 and the fourth electrode 402 of the corresponding row of second storage block 40 have good contact.

[0095] Furthermore, the first connection layer can be located between the first storage block 30 and the third connection layer, and the second connection layer can be located between the second storage block 40 and the fourth connection layer. With this configuration, the planes where the first connection lines 50 and the third connection lines 70 are located are parallel and spaced apart, and the planes where the second connection lines 60 and the fourth connection lines 80 are parallel and spaced apart. This makes the wiring more reasonable, avoiding mutual interference between the first connection lines 50 and the third connection lines 70, as well as between the second connection lines 60 and the fourth connection lines 80. It is worth noting that, since the distance between the third connection layer and the first storage block 30 is relatively large, a first contact block extending towards the corresponding first storage block 30 can be provided on each third connection line 70, and the third connection line 70 is connected to each third electrode 401 through the first contact block; similarly, since the distance between the fourth connection layer and the second storage block 40 is relatively large, a second contact block extending towards the second storage block 40 can be provided on the fourth connection line 80, and the connection between the fourth connection line 80 and the fourth electrode 402 can be achieved through the second contact block; wherein the first contact block and the third connection line 70 are integral structures formed in one process, and the fourth connection line 80 and the second contact block can also be integral structures formed in one process.

[0096] In the above implementation, the three-dimensional ferroelectric memory includes multiple stacked storage layers 2, and the structure of each storage layer 2 can be the same as that of the storage layer 2 in the above implementation; or some storage layers 2 in the three-dimensional ferroelectric memory of this embodiment have the same structure as the storage layer 2 in the above implementation.

[0097] In some embodiments, the first connection line 50 and the second connection line 60 can be word lines, and the corresponding third connection line 70 and the fourth connection line 80 are bit lines; or the first connection line 50 and the second connection line 60 can be bit lines, and the corresponding third connection line 70 and the fourth connection line 80 are word lines. The corresponding voltage configurations can include: floating mode, ground mode, 1 / 2 bias voltage mode, and 1 / 3 bias voltage mode. In floating mode, no voltage is configured for unselected word lines and bit lines, and a certain voltage is configured for selected word lines. In ground mode, unselected word lines and bit lines are grounded, and a certain voltage is configured for selected word lines. In 1 / 2 bias voltage mode, the voltage configured for unselected word lines and bit lines is half that of the selected word lines. In 1 / 3 bias voltage mode, the voltage configured for unselected word lines is one-third that of the selected word lines, and the voltage configured for unselected bit lines is two-thirds that of the selected word lines.

[0098] Figure 6 Schematic diagram of the structure of the three-dimensional ferroelectric memory provided for the implementation of this application Figure 2 Continue to refer to Figure 6Since electrodes are provided on both sides of the reference layer 20, to prevent current in one electrode of the reference layer 20 from reaching the electrode on the other side of the reference layer 20, i.e., to prevent leakage between the electrodes on both sides of the reference layer 20, the opposing first memory block 30 and second memory block 40 can be spaced at a predetermined distance L in a direction parallel to the reference layer 20. A reasonable setting of the predetermined distance L can reduce leakage between the electrodes on both sides of the reference layer 20, thereby reducing leakage current and crosstalk between the electrodes on both sides of the reference layer 20.

[0099] Figure 7 Schematic diagram of the structure of the three-dimensional ferroelectric memory provided for the implementation of this application Figure 3 , Figure 8 for Figure 7 A three-dimensional structural diagram of a ferroelectric memory, as shown below. Figure 7 and Figure 8 As shown, in an implementation where multiple first storage blocks 30 and multiple second storage blocks 40 are arrayed, the multiple first storage blocks 30 and multiple second storage blocks 40 correspond one-to-one. Each first storage block 30 has a first electrode 301 on one side and a second electrode 302 on the other side. Correspondingly, each second storage block 40 has a third electrode 401 on one side and a fourth electrode 402 on the other side. The second electrode 302 connected to the first storage block 30 and the fourth electrode 402 connected to the second storage block 40 are connected to each other.

[0100] With this configuration, in the corresponding first storage block 30 and second storage block 40, data reading and writing of the first storage unit and the second storage unit can be realized through the connecting lines connected to the second electrode 302 and the fourth electrode 402, as well as the connecting lines connected to the first electrode 301 and the second electrode 302. In other words, the second electrode 302 and the fourth electrode 402 can share a connecting line, thereby reducing the number of conductive layers in the three-dimensional ferroelectric memory and further reducing the volume of the three-dimensional ferroelectric memory.

[0101] Furthermore, in the opposing first storage block 30 and second storage block 40, the first electrode 301 can be positioned directly opposite the second electrode 302, and the corresponding third electrode 401 can be positioned directly opposite the fourth electrode 402. In this case, a through-hole can be provided on the reference layer 20. In the opposing first storage block 30 and second storage block 40, the second electrode 302, which is coupled to the first storage block 30, and the fourth electrode 402, which is coupled to the second storage block 40, are connected by a conductive block 201 disposed within the through-hole. With this configuration, the connection between the second electrode 302, which is coupled to the first storage block 30, and the fourth electrode 402, which is coupled to the second storage block 40, is achieved through the conductive block 201 located within the through-hole, eliminating the need for additional wiring, resulting in a simple structure and ease of fabrication.

[0102] In the above implementation, the conductive block 201, and the corresponding second electrode 302 and fourth electrode 402 can be an integral structure. This configuration simplifies the fabrication of the three-dimensional ferroelectric memory by forming the conductive block 201, the corresponding second electrode 302 and fourth electrode 402 in a single process. For example, the conductive block 201, and the corresponding second electrode 302 and fourth electrode 402 can be formed by vapor deposition, deposition, or electroplating. Of course, in other implementations, the conductive block 201, and the corresponding second electrode 302 and fourth electrode 402 can also be separate structures, in which case the conductive block 201 needs to be in contact with the corresponding second electrode 302 and fourth electrode 402.

[0103] In this embodiment, the three-dimensional ferroelectric memory includes a first connecting layer disposed on the side of the first storage block 30 facing away from the substrate 1, and a second connecting layer disposed on the side of the second storage block 40 facing away from the substrate 1. The first connecting layer includes a plurality of parallel and spaced first connecting lines 50, the extension direction of the first connecting lines 50 being parallel to the column direction of the arrayed first storage blocks 30, and the first connecting lines 50 being connected to each first electrode 301 corresponding to a column of first storage blocks 30. The second connecting layer includes a plurality of parallel and spaced second connecting lines 60, the extension direction of the second connecting lines 60 being parallel to the column direction of the arrayed second storage blocks 40, and each second connecting line 60 being connected to each third electrode 401 of a column of second storage blocks 40.

[0104] Furthermore, the three-dimensional ferroelectric memory also includes a third connection layer, which comprises a plurality of parallel and spaced third connection lines 70. Each of the plurality of third connection lines 70 is connected to a second electrode 302 corresponding to a row of first storage blocks 30. With this configuration, the second electrode 302 and the fourth electrode 402 of the corresponding first storage block 30 and second storage block 40 can be connected to the outside world through the third connection lines 70 connected to the second electrode 302 of the first storage block 30. At this time, a first storage block 30 can be uniquely selected through the first connection line 50 and the third connection line 70, and data can be read or written to the first storage cell corresponding to the selected first storage block 30 through the first connection line 50 and the third connection line 70. Similarly, a second storage block 40 can be uniquely selected through the second connection line 60 and the third connection line 70, and data can be read or written to the second storage cell corresponding to the selected second storage block 40 through the second connection line 60 and the third connection line 70.

[0105] The third connecting line 70 may be disposed on the side of the first storage block 30 away from the substrate 1, and the first connecting line 50 is located between the first storage block 30 and the third connecting line 70.

[0106] Of course, in other implementations, the third connection layer can also be set on the side of the second storage block 40 facing the substrate 1, and the second connection layer is located between the third connection layer and the second storage block 40; correspondingly, the third connection layer can include a plurality of parallel and spaced third connection lines 70, the extension direction of the third connection lines 70 can be parallel to the row direction of the plurality of second storage blocks 40 arranged in the array, and each third connection line 70 is connected to the fourth electrode 402 corresponding to a row of second storage blocks 40.

[0107] In the above implementation, the three-dimensional ferroelectric memory includes multiple stacked storage layers 2, and the structure of each storage layer 2 may be the same as that of the storage layer 2 in the above implementation; or, some storage layers 2 may be the same as the storage layer 2 in the above implementation.

[0108] Figure 9 Schematic diagram of the structure of the three-dimensional ferroelectric memory provided for the implementation of this application Figure 4 Continue to refer to Figure 9 .

[0109] In an implementation where multiple first storage blocks 30 and multiple second storage blocks 40 are arrayed, the multiple first storage blocks 30 and multiple second storage blocks 40 correspond one-to-one. Each first storage block 30 has a first electrode 301 on one side and a second electrode 302 on the other side. Correspondingly, each second storage block 40 has a third electrode 401 on one side and a fourth electrode 402 on the other side. The second electrode 302 connected to the first storage block 30 and the fourth electrode 402 connected to the second storage block 40 are connected. Further, multiple first conductive lines 3 are provided between adjacent storage layers 2. One end of each first conductive line 3 is connected to a third electrode 401 in a storage layer 2 away from the substrate 1, and the other end of each first conductive line 3 is connected to a corresponding first electrode 301 in a storage layer 2 close to the substrate 1.

[0110] With this configuration, the first electrode 301 in the storage layer 2 closest to the substrate 1 and the third electrode 401 in the storage layer 2 furthest from the substrate 1 are connected by the first conductive line 3. This allows each of the first electrode 301 in the storage layer 2 closest to the substrate 1 and the third electrode 401 in the storage layer 2 furthest from the substrate 1 to be connected to an external device via a corresponding line. Compared to having separate conductive layers for each of the first electrode 301 in the storage layer 2 closest to the substrate 1 and the third electrode 401 in the storage layer 2 furthest from the substrate 1, this configuration reduces the number of conductive layers in the three-dimensional ferroelectric memory, thereby reducing the volume of the three-dimensional ferroelectric memory.

[0111] In the above implementation, each of the first conductive lines 3 is arranged in an array between two adjacent storage layers 2, and an intermediate conductive layer can be arranged between two adjacent storage layers 2. The intermediate conductive layer includes a plurality of intermediate connecting lines arranged in parallel and at intervals, and each intermediate connecting line is connected to a column of first conductive lines 3.

[0112] Furthermore, the storage layer 2 is provided with a first connection layer and a second connection layer. The first connection layer is located on the side of the first storage block 30 facing away from the substrate 1. The first connection layer includes a plurality of parallel and spaced first connection lines 50, the extension direction of which is the same as the column direction of the first storage block 30, and the first connection lines 50 are connected to the first electrodes 301 corresponding to a column of first storage blocks 30. The second connection layer is located on the side of the second storage block 40 facing the substrate 1 in the storage layer 2. The second connection layer includes a plurality of parallel and spaced second connection lines 60. The extension direction of the second connection line 60 is parallel to the column direction of the corresponding second storage block 40, and each second connection line 60 is connected to the third electrode 401 of a column of second storage blocks 40; a third connection layer is also provided in each storage layer 2, and each third connection layer is provided on the side of the first storage block 30 of the storage layer 2 away from the substrate 1. The third connection layer includes a plurality of third connection lines 70 arranged in parallel and at intervals. The extension direction of the third connection line 70 is parallel to the row direction of the corresponding first storage block 30, and each third connection line 70 is connected to the second electrode 302 corresponding to a row of first storage blocks 30.

[0113] In use, in two adjacent storage layers, a first storage block 30 closer to the substrate 1 and a second storage block 40 farther from the substrate 1 can be selected via an intermediate connection line and a third connection line 70 in the two storage layers 2 connected by the intermediate connection line, thereby enabling the reading or writing of data in the corresponding storage units. In the storage layer 2 closer to the substrate 1, a second storage block 40 can be uniquely selected via the third connection line 70 and the second connection line 60, thereby enabling the reading or writing of data in the second storage unit corresponding to the second storage block 40. In the storage layer 2 farther from the substrate 1, a first storage block 30 can be uniquely selected via the first connection line 50 and the third connection line 70, thereby enabling the reading or writing of data in the first storage unit corresponding to the first storage block 30.

[0114] Of course, in the above implementation, each storage layer 2 may not have a third connection layer. Instead, a fourth connection layer is provided on the side of the second storage block 40 facing the substrate 1 in each storage layer 2. The fourth connection layer includes a plurality of parallel and spaced fourth connection lines 80. The extension direction of the fourth connection lines 80 is parallel to the row direction of the second storage block 40. Each fourth connection line 80 is connected to the fourth electrode 402 corresponding to a row of second storage blocks 40. Since the second electrode 302 and the fourth electrode 402 are connected in the relative first storage block 30 and second storage block 40, the fourth connection line 80 has the same function as the third connection line 70.

[0115] Figure 10Schematic diagram of the structure of the three-dimensional ferroelectric memory provided for the implementation of this application Figure 5 , Figure 11 for Figure 10 The three-dimensional structure diagram of the ferroelectric memory is shown below. Figure 10 and Figure 11 .

[0116] In an implementation where multiple first storage blocks 30 and multiple second storage blocks 40 are arrayed, the multiple first storage blocks 30 and multiple second storage blocks 40 correspond one-to-one. Each first storage block 30 has a first electrode 301 on one side and a second electrode 302 on the other side. Correspondingly, each second storage block 40 has a third electrode 401 on one side and a fourth electrode 402 on the other side. The second electrode 302 connected to the first storage block 30 and the fourth electrode 402 connected to the second storage block 40 are connected to each other. Furthermore, a plurality of second conductive lines 4 are provided between two adjacent storage layers 2. One end of each of the plurality of second conductive lines 4 is connected to a fourth electrode 402 in the storage layer 2 away from the substrate 1, and the other end of each of the plurality of second conductive lines 4 is connected to a corresponding second electrode 302 in the storage layer 2 close to the substrate 1. The three-dimensional ferroelectric memory includes a fourth connection layer, which includes a plurality of fourth connection lines 80 arranged in parallel and at intervals. Each of the plurality of fourth connection lines 80 is connected to a row of second conductive lines 4.

[0117] With this configuration, the fourth electrode 402 in the storage layer 2 away from the substrate 1 and the second electrode 302 in the storage layer 2 close to the substrate 1 can be connected through the second conductive line 4. Since the second electrode 302 and the fourth electrode 402 are connected in the opposite first storage block 30 and second storage block 40 in each storage layer 2, the second conductive line 4 also realizes the connection between the second electrode 302 and the fourth electrode 402 in the first storage block 30 and the second storage block 40 facing each other in the direction perpendicular to the substrate 1 in the entire three-dimensional ferroelectric memory. In the entire three-dimensional ferroelectric memory, the second electrode 302 and the fourth electrode 402 in the first storage block 30 and the second storage block 40 facing each other in the direction perpendicular to the substrate 1 can be connected to external devices through a connecting line. Compared with setting a connecting line to the second electrode 302 in each storage layer 2, the number of conductive layers in the three-dimensional ferroelectric memory can be further reduced, thereby reducing the volume of the three-dimensional ferroelectric memory.

[0118] In the above implementation, each storage layer 2 may also have a first connection layer and a second connection layer. The first connection layer may be disposed on the side of the first storage block 30 facing away from the substrate 1 in the storage layer 2. The first connection layer includes a plurality of parallel and spaced first connection lines 50. The extension direction of the first connection lines 50 is parallel to the column direction of the first storage block 30. Each first connection line 50 is connected to a first electrode 301 corresponding to a column of first storage blocks 30. The second connection layer may be disposed on the side of the second storage block 40 facing the substrate 1 in the storage layer 2. The second connection layer includes a plurality of parallel and spaced second connection lines 60. The extension direction of the second connection lines 60 is parallel to the column direction of the second storage block 40. Each second connection line 60 is connected to a third electrode 401 corresponding to a column of second storage blocks 40.

[0119] The three-dimensional ferroelectric memory includes a fourth connection layer, which comprises a plurality of parallel and spaced fourth connection lines 80. Each of the plurality of fourth connection lines 80 is connected to a row of second conductive lines 4. With this configuration, a first storage block 30 can be uniquely selected based on the fourth connection lines 80 and the first connection lines 50, enabling the reading and writing of data in the first storage cell corresponding to that first storage block 30; similarly, a second storage block 40 can be uniquely selected based on the fourth connection lines 80 and the second connection lines 60, enabling the reading and writing of data in the second storage cell corresponding to that second storage block 40.

[0120] For example, the fourth connection layer can be disposed between the substrate 1 and the storage layer 2 near the substrate 1. Each of the plurality of fourth connection lines 80 is connected to the fourth electrode 402 corresponding to a row of second storage blocks 40 in the storage layer 2 near the substrate 1. With this configuration, the second electrode 302 of the first storage block 30 in the same row and the fourth electrode 402 of the second storage block 40 in the corresponding row are led out through the fourth connection lines 80 located on the side of the storage layer 2 near the substrate 1 toward the substrate 1. There is no need to set fourth connection lines 80 between the storage layers 2, further reducing the volume of the three-dimensional ferroelectric memory.

[0121] In some embodiments, the fourth connection layer may also be disposed on the side of the storage layer 2 away from the substrate 1, and each of the plurality of fourth connection lines 80 is connected to the second electrode 302 corresponding to a row of first storage blocks 30 in the storage layer 2 away from the substrate 1. With this configuration, the second electrode 302 of the first storage block 30 in the same row and the fourth electrode 402 of the second storage block 40 in the corresponding row are led out through the fourth connection lines 80 located on the side of the storage layer 2 away from the substrate 1 facing the substrate 1, eliminating the need for fourth connection lines 80 between the storage layers 2, and further reducing the volume of the three-dimensional ferroelectric memory.

[0122] Continue to refer to Figures 1-11This application also provides an electronic device, including a circuit board and a three-dimensional ferroelectric memory connected to the circuit board. The three-dimensional ferroelectric memory can be the three-dimensional ferroelectric memory described in the above embodiments. The circuit board can be a printed circuit board (PCB), but it can also be a flexible circuit board (FPC), etc. This embodiment does not limit the type of circuit board.

[0123] The electronic device provided in this application embodiment includes a three-dimensional ferroelectric memory with multiple storage layers 2 stacked on a substrate 1. Each storage layer 2 includes a reference layer 20. A first dielectric layer is disposed on the side of the reference layer 20 away from the substrate 1. The first dielectric layer includes multiple spaced first storage blocks 30. A second dielectric layer is disposed on the side of the reference layer 20 facing the substrate 1. The second dielectric layer includes multiple spaced second storage blocks 40. Both the first storage blocks 30 and the second storage blocks 40 are attached to the reference layer 20, so that the first storage blocks 30 and the reference layer 20 are combined to form a first storage unit, and the second storage blocks 40 and the reference layer 20 are combined to form a second storage unit. Data is stored in each of the first and second storage units. The first dielectric layer and the second dielectric layer share a single reference layer 20. In other words, the number of reference layers 20 is half the number of dielectric layers. Compared with one dielectric layer corresponding to one reference layer 20, the number of reference layers 20 is reduced, thereby reducing the size of the three-dimensional ferroelectric memory in the direction perpendicular to the substrate 1, and thus reducing the volume of the three-dimensional ferroelectric memory, achieving miniaturization of the three-dimensional ferroelectric memory.

[0124] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A three-dimensional ferroelectric memory, characterized in that, include: A substrate and multiple storage layers stacked on the substrate; Each of the plurality of storage layers includes a reference layer, a first dielectric layer disposed on the side of the reference layer facing away from the substrate, and a second dielectric layer disposed on the side of the reference layer facing the substrate. The first dielectric layer includes a plurality of first storage blocks spaced apart, and the second dielectric layer includes a plurality of second storage blocks spaced apart. Each of the plurality of first storage blocks and each of the plurality of second storage blocks is attached to the reference layer. Each first storage block and the reference layer are combined to form a first storage cell, and each second storage block and the reference layer are combined to form a second storage cell. The plurality of first storage blocks and the plurality of second storage blocks are arranged in an array, and the plurality of first storage blocks and the plurality of second storage blocks correspond one-to-one in the direction perpendicular to the reference layer; The first dielectric layer further includes a first electrode bonded to one side of the first memory block and a second electrode bonded to the other side of the first memory block; The second dielectric layer further includes a third electrode bonded to one side of the second memory block and a fourth electrode bonded to the other side of the second memory block; The three-dimensional ferroelectric memory further includes a first connecting layer located on the side of the first memory block away from the substrate and a second connecting layer located on the side of the second memory block facing the substrate. The first connecting layer includes a plurality of parallel and spaced first connecting lines, each of the plurality of first connecting lines being connected to a first electrode corresponding to a column of the first memory blocks. The second connecting layer includes a plurality of parallel and spaced second connecting lines, each of the plurality of second connecting lines being connected to a third electrode corresponding to a column of the second memory blocks. The three-dimensional ferroelectric memory further includes a third connecting layer located on the side of the first memory block away from the substrate and a fourth connecting layer located on the side of the second memory block facing the substrate. The third connecting layer includes a plurality of parallel and spaced third connecting lines, each of which is connected to a second electrode corresponding to a row of the first memory block. The fourth connecting layer includes a plurality of parallel and spaced fourth connecting lines, each of which is connected to a fourth electrode corresponding to a row of the second memory block.

2. The three-dimensional ferroelectric memory according to claim 1, characterized in that, The first connection layer is located between the first storage block and the third connection layer, and the second connection layer is located between the second storage block and the fourth connection layer.

3. The three-dimensional ferroelectric memory according to claim 1, characterized in that, In the first and second memory blocks respectively, the second electrode connected to the first memory block and the fourth electrode connected to the second memory block are connected.

4. The three-dimensional ferroelectric memory according to claim 3, characterized in that, A through hole is provided on the reference layer. In the first storage block and the second storage block arranged opposite to each other, the second electrode that is connected to the first storage block and the fourth electrode that is connected to the second storage block are connected by a conductive block provided in the through hole.

5. The three-dimensional ferroelectric memory according to claim 4, characterized in that, The conductive block, the second electrode corresponding to the conductive block, and the fourth electrode are an integral structure.

6. The three-dimensional ferroelectric memory according to any one of claims 3-5, characterized in that, The three-dimensional ferroelectric memory includes a third connection layer, which includes a plurality of parallel and spaced third connection lines. Each of the plurality of third connection lines is connected to a second electrode corresponding to a row of the first memory block.

7. The three-dimensional ferroelectric memory according to any one of claims 3-5, characterized in that, The three-dimensional ferroelectric memory includes a third connection layer, which includes a plurality of parallel and spaced third connection lines. Each of the plurality of third connection lines is connected to a fourth electrode corresponding to a row of the second memory block.

8. The three-dimensional ferroelectric memory according to claim 6, characterized in that, A plurality of first conductive lines are provided between adjacent storage layers. One end of each of the plurality of first conductive lines is connected to a third electrode in the storage layer away from the substrate, and the other end of each of the plurality of first conductive lines is connected to a corresponding first electrode in the storage layer close to the substrate.

9. The three-dimensional ferroelectric memory according to claim 7, characterized in that, A plurality of first conductive lines are provided between adjacent storage layers. One end of each of the plurality of first conductive lines is connected to a third electrode in the storage layer away from the substrate, and the other end of each of the plurality of first conductive lines is connected to a corresponding first electrode in the storage layer close to the substrate.

10. The three-dimensional ferroelectric memory according to any one of claims 3-5, characterized in that, A plurality of second conductive lines are provided between two adjacent storage layers. One end of each of the plurality of second conductive lines is connected to the fourth electrode in the storage layer away from the substrate, and the other end of each of the plurality of second conductive lines is connected to the corresponding second electrode in the storage layer close to the substrate. The three-dimensional ferroelectric memory further includes a fourth connection layer, which includes a plurality of parallel and spaced fourth connection lines, each of which is connected to a row of second conductive lines.

11. The three-dimensional ferroelectric memory according to claim 10, characterized in that, The fourth connection layer is disposed between the substrate and the storage layer adjacent to the substrate, and each of the plurality of fourth connection lines is connected to the fourth electrode corresponding to a row of the second storage block in the storage layer adjacent to the substrate.

12. The three-dimensional ferroelectric memory according to claim 10, characterized in that, The fourth connection layer is disposed on the side of the storage layer away from the substrate, and each of the plurality of fourth connection lines is connected to the second electrode corresponding to a row of the first storage block in the storage layer away from the substrate.

13. The three-dimensional ferroelectric memory according to any one of claims 1-5, 8-9, 11-12, characterized in that, An insulating dielectric layer is provided between adjacent storage layers.

14. The three-dimensional ferroelectric memory according to any one of claims 1-5, 8-9, 11-12, characterized in that, The reference layer, the first memory block, and the second memory block all include resistive switching materials, phase change materials, or resistive switching structures.

15. The three-dimensional ferroelectric memory according to claim 14, characterized in that, The reference layer, the first storage block, and the second storage block all comprise ferroelectric materials.

16. An electronic device, comprising a circuit board and a three-dimensional ferroelectric memory connected to the circuit board, wherein the three-dimensional ferroelectric memory is the three-dimensional ferroelectric memory as described in any one of claims 1-15.

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