A memory operation method, a memory and a storage system

Abstract

Embodiments of the present application provide a memory operation method, a memory and a storage system. The memory comprises a plurality of storage surfaces and a peripheral circuit coupled with the storage surfaces. The peripheral circuit comprises a buffer device coupled between a first storage surface and a second storage surface. The buffer device is configured to read first data from the first storage surface and transmit the first data to the second storage surface, or read second data from the second storage surface and transmit the second data to the first storage surface. The first storage surface and the second storage surface are any two storage surfaces of the plurality of storage surfaces.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of memory, and in particular to a memory operating method, a memory and a storage system. BACKGROUND

[0002] Recently, with the development of memory, the memory can be volatile or non-volatile. The non-volatile memory can keep data even in the case of no power supply, and has been widely used in cellular phones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices and other devices. According to the configuration of the structure of the storage array contained in the memory, the memory can be classified into single storage plane type and multi-storage plane type. The single plane type memory includes a storage array arranged in a single plane, and the multi-plane type memory includes a storage array arranged in multiple planes. At present, the data transmission between the planes in the memory needs to be realized by means of a memory control coupled with the memory, and the existing circuit design cannot support the data transmission between the storage planes within the memory. SUMMARY

[0003] Therefore, the present application provides a memory operating method, a memory and a storage system, a buffer device is added in the peripheral circuit of the memory, the buffer device is coupled between a first storage plane and a second storage plane of the memory, so that the buffer device can be used to read data from the first storage plane and transmit the data to the second storage plane, or read data from the second storage plane and transmit the data to the first storage plane.

[0004] To achieve the above-mentioned purpose, the technical scheme of the present application is as follows:

[0005] In a first aspect, an embodiment of the present application provides a memory, comprising:

[0006] comprising: a plurality of storage planes; and a peripheral circuit coupled with the storage planes, wherein:

[0007] the peripheral circuit comprises: a buffer device coupled between a first storage plane and a second storage plane, wherein the buffer device is configured to read first data from the first storage plane and transmit the first data to the second storage plane, or read second data from the second storage plane and transmit the second data to the first storage plane;

[0008] wherein the first storage plane and the second storage plane are any two storage planes of the plurality of storage planes.

[0009] In the above scheme, the buffer device comprises a clock buffer component, a first buffer component corresponding to the first storage surface, a second buffer component corresponding to the second storage surface, and a conversion buffer component, wherein;

[0010] The clock buffer component is configured to receive an original clock signal and a first read enable signal of the first storage surface; generate a first sub-input clock signal of the first storage surface based on the original clock signal when the first read enable signal is valid; and send the first sub-input clock signal to the first buffer component;

[0011] The first buffer component is coupled to the clock buffer component and configured to receive the first read enable signal and the first sub-input clock signal; output a first output signal based on the first sub-input clock signal when the first read enable signal is valid; and transmit the first output signal to the conversion buffer; the first output signal comprises a first output clock signal, a first data signal for representing first data, and a first address signal.

[0012] The conversion buffer component is configured to receive the first output signal, the first read enable signal, and a first write enable signal of the second storage surface; convert the first output clock signal, the first data signal, and the first address signal contained in the first output signal into a first input signal of the second storage surface when the first read enable signal and the first write enable signal are valid; the first input signal comprises a first input clock signal, a second data signal for representing the first data, and a second address signal; and transmit the first input signal to the second buffer component.

[0013] The second buffer component is configured to receive the first input signal and the first write enable signal; generate a first write clock signal based on the first input clock signal when the first write enable signal is valid; generate a first write address based on the second address signal; generate the first data based on the second data signal; and write the first data into the first write address of the second storage surface based on the first write clock signal.

[0014] In the above scheme, the clock buffer is further coupled to the second buffer component and configured to receive the original clock signal and a second read enable signal of the second storage surface; generate a second sub-input clock signal based on the original clock signal when the second read enable signal is valid; and send the second sub-input clock signal to the second buffer component.

[0015] The second buffer component is configured to receive the second read enable signal and the second sub-input clock signal, output a second output signal based on the second sub-input clock signal when the second read enable signal is valid, and transmit the second output signal to the conversion buffer; the second output signal comprises a second output clock signal, a third data signal for representing the second data, and a third address signal;

[0016] The conversion buffer component is configured to receive the second output signal, the second read enable signal, and a second write enable signal of the first storage surface, and convert the second output clock signal, the second data signal, and the third address signal contained in the second output signal into a second input signal of the first storage surface when the second read enable signal and the second write enable signal are valid; the second input signal comprises a second input clock signal, a fourth data signal for representing the second data, and a fourth address signal; and the second input signal is transmitted to the first buffer component.

[0017] The first buffer component is configured to receive the second input signal and the second write enable signal, generate a second write clock signal based on the second input clock signal when the second write enable signal is valid, generate a second write address based on the fourth address signal, generate the second data based on the fourth data signal, and write the second data into the second write address of the first storage surface based on the second write clock signal.

[0018] In the above scheme, the clock buffer component comprises a first tri-state buffer and a second tri-state buffer, wherein:

[0019] The input end of the first tri-state buffer and the input end of the second tri-state buffer are connected to the original clock signal;

[0020] The enable end of the first tri-state buffer is connected to the first read enable signal, and the output end outputs the first sub-input clock signal;

[0021] The enable end of the second tri-state buffer is connected to the second read enable signal, and the output end outputs the second sub-input clock signal.

[0022] In the above scheme, the first buffer component comprises a first buffer group, a second buffer group, and a third buffer group, wherein:

[0023] The first buffer group comprises a first clock buffer; the first clock buffer is configured to access the first sub-input clock signal and a first read enable signal; when the first read enable signal is valid, a first output clock signal is generated based on the first sub-input clock signal; and the first output clock signal is transmitted to the conversion buffer assembly;

[0024] The second buffer group comprises a first data buffer; the first data buffer is configured to access the first read enable signal and first data; when the first read enable signal is valid, the first data signal is generated based on the first data; and the first data signal is transmitted to the conversion buffer assembly; the first data is read from a first read address of the first storage surface based on the first sub-input clock signal;

[0025] The third buffer group comprises a first address buffer; the first address buffer is configured to access the first read enable signal and a first read address; when the first read enable signal is valid, the first address signal is generated based on the first read address; and the first address signal is transmitted to the conversion buffer assembly.

[0026] In the above scheme, the first buffer group further comprises a second clock buffer; the second clock buffer is configured to receive the second write enable signal and a second input clock signal; when the second write enable signal is valid, the second write clock signal is generated based on the second input clock signal;

[0027] The third buffer group further comprises a second address buffer; the second address buffer is configured to receive the second write enable signal and the fourth address signal; when the second write enable signal is valid, a second write address is generated based on the fourth address signal;

[0028] The second buffer group further comprises a second data buffer; the second data buffer is configured to receive the fourth data signal and the second write enable signal; when the second write enable signal is valid, the second data is generated based on the fourth data signal; and the second data is written to the second write address of the first storage surface based on the second write clock signal.

[0029] In the above scheme, the structure of the second buffer assembly is the same as that of the first buffer assembly.

[0030] In the above scheme, the conversion buffer assembly comprises a clock conversion group, an address conversion group and a data conversion group, wherein;

[0031] The clock conversion group is configured to receive the first output clock signal, the first read enable signal and the first write enable signal, generate the first input clock signal based on the first output clock signal when both the first read enable signal and the first write enable signal are valid, and transmit the first input clock signal to the second buffer assembly.

[0032] The address conversion group is configured to receive the first address signal, the first read enable signal and the first write enable signal, generate the second address signal based on the first address signal when both the first read enable signal and the first write enable signal are valid, and transmit the second address signal to the second buffer assembly.

[0033] The data conversion group is configured to receive the first data signal, the first read enable signal and the first write enable signal, generate the second data signal based on the first data signal when both the first read enable signal and the first write enable signal are valid, and transmit the second data signal to the second buffer assembly.

[0034] In the above solution, the clock conversion group is further configured to receive the second output clock signal, the second read enable signal and the second write enable signal, generate the second input clock signal based on the second output clock signal when both the second read enable signal and the second write enable signal are valid, and transmit the second input clock signal to the first buffer assembly.

[0035] The address conversion group is configured to receive the third address signal, the second read enable signal and the second write enable signal, generate the fourth address signal based on the third address signal when both the second read enable signal and the second write enable signal are valid, and transmit the fourth address signal to the first buffer assembly.

[0036] The data conversion group is configured to receive the third data signal, the second read enable signal and the second write enable signal, generate the fourth data signal based on the third data signal when both the second read enable signal and the second write enable signal are valid, and transmit the fourth data signal to the first buffer assembly.

[0037] In the above solution, the clock conversion group comprises a first group of buffers and a second group of buffers, the first group of buffers comprises a third tri-state buffer and a fourth tri-state buffer, and the second group of buffers comprises a fifth tri-state buffer and a sixth tri-state buffer.

[0038] The input end of the third tri-state buffer is connected with the output end of the fourth tri-state buffer; the output end of the third tri-state buffer is connected with the input end of the fourth tri-state buffer; the enable end of the third tri-state buffer is connected with the first read enable signal; and the enable end of the fourth tri-state buffer is connected with the second write enable signal.

[0039] The input end of the third tri-state buffer, the output end of the fourth tri-state buffer, the input end of the fifth tri-state buffer and the output end of the sixth tri-state buffer are connected.

[0040] The output end of the fifth tri-state buffer is connected with the input end of the sixth tri-state buffer; the enable end of the fifth tri-state buffer is connected with the second read enable signal; and the enable end of the sixth tri-state buffer is connected with the first write enable signal.

[0041] In the above scheme, the structure of the address conversion group and the structure of the data conversion group are the same as the structure of the clock conversion group.

[0042] In the above scheme, the peripheral circuit further comprises an I / O interface and a control logic unit, wherein,

[0043] The control logic unit is configured to receive a first command through the I / O interface; control the buffer device to read first data from the first storage surface, transmit the first data to the second storage surface, or read second data from the second storage surface, and transmit the second data to the first storage surface based on the first command.

[0044] In a second aspect, an embodiment of the present application provides an operation method of a memory, applied to the memory comprising a peripheral circuit, and the operation method comprises:

[0045] receiving a first command;

[0046] reading first data from a first storage surface, transmitting the first data to a second storage surface, or reading second data from the second storage surface, and transmitting the second data to the first storage surface based on the first command;

[0047] The first storage surface and the second storage surface are any two storage surfaces in a plurality of storage surfaces contained in the memory.

[0048] In the above scheme, the reading first data from the first storage surface, transmitting the first data to the second storage surface based on the first command comprises:

[0049] obtaining a first read enable signal based on the first command; and receiving an original clock signal;

[0050] The first sub-input clock signal is generated based on the original clock signal when the first read enable signal is valid; the first output signal is generated based on the first sub-input clock signal; the first output signal comprises a first output clock signal, a first data signal for representing first data, and a first address signal;

[0051] The first output clock signal, the first data signal, and the first address signal contained in the first output signal are converted into a first input signal of the second storage surface when the first read enable signal and a first write enable signal of the second storage surface are valid; the first input signal comprises a first input clock signal, a second data signal for representing the first data, and a second address signal; the first write enable signal is obtained based on the first command;

[0052] The first write clock signal is generated based on the first input clock signal when the first write enable signal is valid; the first write address is generated based on the second address signal; the first data is generated based on the second data signal; and the first data is written into the first write address of the second storage surface based on the first write clock signal.

[0053] In the above scheme,

[0054] The second data is read from the second storage surface based on the first command, and the second data is transmitted to the first storage surface, comprising:

[0055] The second read enable signal is obtained based on the first command; and an original clock signal is received;

[0056] The second sub-input clock signal is generated based on the original clock signal when the second read enable signal is valid;

[0057] The second output signal is outputted based on the second sub-input clock signal; the second output signal comprises a second output clock signal, a third data signal for representing the second data, and a third address signal;

[0058] The second output clock signal, the second data signal, and the third address signal contained in the second output signal are converted into a second input signal of the first storage surface when the second read enable signal and a second write enable signal of the first storage surface are valid; the second input signal comprises a second input clock signal, a fourth data signal for representing the second data, and a fourth address signal; the second write enable signal is obtained based on the first command;

[0059] generate a second write clock signal based on the second input clock signal; generate a second write address based on the fourth address signal; generate the second data based on the fourth data signal; and write the second data into the second write address of the first storage surface based on the second write clock signal.

[0060] In a third aspect, an embodiment of the present application further provides a storage system, comprising: one or more storage devices as described above; and a memory controller coupled to the storage devices; the memory controller is configured to send various operation commands to the storage devices.

[0061] In the above solution, the storage system is a solid state disk or a memory card.

[0062] Embodiments of the present application provide a storage device operation method, a storage device and a storage system. The storage device comprises a plurality of storage surfaces and a peripheral circuit coupled to the storage surfaces. The peripheral circuit comprises a buffer device coupled between a first storage surface and a second storage surface. The buffer device is configured to read first data from the first storage surface and transmit the first data to the second storage surface, or read second data from the second storage surface and transmit the second data to the first storage surface. The first storage surface and the second storage surface are any two storage surfaces of the plurality of storage surfaces. The storage device provided by the embodiments of the present application transmits data of one storage surface to another storage surface by the buffer device arranged between the storage surfaces, without the aid of a coupled memory controller, thereby realizing direct data transmission between the storage surfaces in the storage device, which is convenient and fast. BRIEF DESCRIPTION OF DRAWINGS

[0063] Aspects of the application are best understood from the following detailed description when read in conjunction with the accompanying drawings. It is noted that the various features are not drawn to scale. In fact, the dimensions can be arbitrarily increased or decreased for the sake of discussion. It is understood that the drawings are not limiting of the aspects of the application.

[0064] Figure 1 A block diagram illustrating an example system having a storage device in the related art is shown;

[0065] Figure 2 A schematic diagram illustrating an example memory card having a storage device is shown;

[0066] Figure 3 A schematic diagram illustrating an example solid state disk (SSD) having a storage device is shown;

[0067] Figure 4 A schematic diagram illustrating an example storage device having a peripheral circuit is shown;

[0068] Figure 5 A diagram illustrating an organization of a memory array included in a memory;

[0069] Figure 6 A side view illustrating a cross-section of an exemplary memory array including NAND memory strings;

[0070] Figure 7 A block diagram illustrating an exemplary memory including a memory array and peripheral circuitry;

[0071] Figure 8 A diagram illustrating an organization of a memory provided by an embodiment of the present invention;

[0072] Figure 9 A diagram illustrating an organization of a buffer provided by an embodiment of the present invention;

[0073] Figure 10 A diagram illustrating an organization of a clock buffer provided by an embodiment of the present invention;

[0074] Figure 11 A diagram illustrating an organization of a first buffer provided by an embodiment of the present invention;

[0075] Figure 12 A diagram illustrating an organization of a conversion buffer provided by an embodiment of the present invention;

[0076] Figure 13 A diagram illustrating an organization of a clock conversion provided by an embodiment of the present invention;

[0077] Figure 14 A diagram illustrating an organization of a principle provided by an embodiment of the present invention;

[0078] Figure 15 A diagram illustrating an organization of a clock buffer provided by an embodiment of the present invention;

[0079] Figure 16 A diagram illustrating an organization of a buffer associated with a memory plane provided by an embodiment of the present invention;

[0080] Figure 17 A diagram illustrating an organization of a conversion buffer provided by an embodiment of the present invention;

[0081] Figure 18 A diagram illustrating a flow of an operation method of a memory provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0082] The following disclosure provides many different embodiments, or examples, for implementing different characteristics of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the making of a first feature on or over a second feature in the following description can include embodiments in which the first and second features are formed in direct contact, and can also include embodiments in which additional features can be formed between the first and second features such that the first and second features can not be in direct contact. Additionally, the present disclosure can repeat reference data and / or letters in various examples. This repetition of reference data and / or letters is for the purpose of simplicity and clarity and does not indicate a relationship between the various embodiments and / or arrangements discussed.

[0083] Moreover, spatial or directional terms, such as "below," "lower," "bottom," "above," "upper," and the like, can be used herein for ease of describing the aspects of the present disclosure. The spatial and directional terms should be interpreted in the context of the present disclosure on the drawing figures. Spatial and directional terms are used for purposes of explanation and should not be considered as limiting. For example, a spatial or directional term can be used in connection with one or more components or features in a specific embodiment, and such term can be interpreted as extending to other components or features in other embodiments.

[0084] The technical solutions of the present application are described in detail below with reference to the accompanying drawings.

[0085] Figure 1 A block diagram of an exemplary system having a memory in the related art is shown. In Figure 1 In an embodiment, the system 100 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory. As Figure 1As shown, the system 100 can include a host 108 and a memory system 102, where the memory system 102 has one or more memories 104 and a memory controller 106; the host 108 can be a processor of an electronic device, such as a central processing unit (CPU) or a system on chip (SoC), which can be an application processor (AP) for example. The host 108 can be configured to send data to or receive data from the memory 104. Specifically, the memory 104 can be any memory disclosed in the present application. For example, a phase change random access memory (PCRAM), a three-dimensional NAND flash, and the like.

[0086] According to some embodiments, a memory controller 106 is coupled to the memory 104 and the host 108. And is configured to control the memory 104. The memory controller 106 can manage data stored in the memory 104 and communicate with the host 108. In some embodiments, the memory controller 106 is designed for operation in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices in low duty cycle environments such as personal computers, digital cameras, mobile telephones, etc. In some embodiments, the memory controller 106 is designed for operation in a high duty cycle environment, such as a Solid State Drive (SSD) or an embedded Multi Media Card (eMMC), where the SSD or eMMC is used as a data storage for mobile devices in high duty cycle environments such as smartphones, tablet computers, laptop computers, etc. as well as enterprise storage arrays. The memory controller 106 can be configured to control operations of the memory 104, such as read, erase, and program operations. The memory controller 106 can also be configured to manage various functions with respect to data stored in or to be stored in the memory 104, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to handle Error Correction Codes (ECC) with respect to data read from or written to the memory 104. The memory controller 106 can also perform any other suitable functions, for example, formatting the memory 104. The memory controller 106 can communicate with external devices (e.g., the host 108) according to a particular communication protocol.For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a Peripheral Component Interconnection (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachmnet (ATA) protocol, a Serial ATA protocol, a Parallel ATA protocol, a Small Computer Small Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a Firewire protocol, etc.

[0087] The memory controller 106 and the one or more memories 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the storage system 102 can be implemented and packaged into different types of end electronic products. In the case of a memory card 202 as shown in FIG. 2A, the memory controller 106 and the single memory 104 can be integrated into the memory card 202. The memory card can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc. The memory card can also include a memory card connector 204 that couples the memory card with a host (e.g., the host 108 in FIG. 1). In the case of a solid state drive (SSD) 302 as shown in FIG. 2B, the memory controller 106 and the multiple memories 104 can be integrated into the SSD 302. The SSD can also include an SSD connector 304 that couples the SSD with a host (e.g., the host 108 in FIG. 1). In some embodiments, the storage capacity and / or operating speed of the SSD is greater than that of the memory card. In addition, the memory controller 106 can also be configured to control the erase, read, write operations of the memories 104. Figure 2 Figure 1 Figure 3 Figure 1

[0088] Figure 4 A schematic diagram showing an exemplary memory including a peripheral circuit. In Figure 4 ​​​​As shown, memory 104 can include a storage array 401 and a peripheral circuit 402 coupled at the periphery of the storage array 401, where the storage array 401 can be a NAND flash storage array in which storage cells 406 are provided in an array of NAND memory strings 408, each of which extends vertically over a substrate (not shown). In some embodiments, each NAND memory string 408 includes a plurality of storage cells 406 coupled in series and stacked vertically. Each storage cell 406 can hold a continuous analog value, e.g., a voltage or charge, that depends on the number of electrons captured within a storage region of the storage cell 406. Each storage cell 406 can be a floating gate type of storage cell that includes a floating gate transistor, or a charge trap type of storage cell that includes a charge trap transistor.

[0089] In some embodiments, each storage cell 406 is a single level cell (SLC) that has two possible memory states and thus can store one bit of data, e.g., a first memory state "0" can correspond to a first voltage range and a second memory state "1" can correspond to a second voltage range. In some embodiments, each storage cell 406 is a multi-level cell (MLC) that has multiple memory states and thus can store multiple bits of data, e.g., an MLC can store two bits per cell, three bits per cell (also referred to as a trinary level cell (TLC)), or four bits per cell (also referred to as a quadruple level cell (QLC)). Each MLC can be programmed to assume a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to assume one of three possible programmed levels by writing one of three possible nominal storage values to the storage cell from an erased state. A fourth nominal storage value can be used for the erased state.

[0090] As Figure 4As shown, each NAND memory string 408 can include a source select gate (SSG) 410 at its source end and a drain select gate (DSG) 412 at its drain end. The SSG 410 and the DSG 412 can be configured to activate a selected NAND memory string 408 (column of the array) during read and program (or write) operations. In some embodiments, the sources of the NAND memory strings 408 in the same block 404 are coupled through the same source line (SL) 414 (e.g., a common SL). In other words, according to some implementations, all NAND memory strings 408 in the same block 404 have an array common source (ACS). According to some implementations, the DSG 412 of each NAND memory string 408 is coupled to a respective bit line 416 from which data can be read and written via an output bus (not shown). In some embodiments, each NAND memory string 408 is configured to be selected or deselected by applying a select voltage (e.g., higher than a threshold voltage of a transistor having the DSG 412) or a deselect voltage (e.g., 0 volts (V)) to the respective DSG 412 via one or more DSG lines 413 and / or a select voltage (e.g., higher than a threshold voltage of a transistor having the SSG 410) or a deselect voltage (e.g., 0 V) to the respective SSG 410 via one or more SSG lines 415.

[0091] As Figure 4As shown, NAND memory strings 408 can be organized into multiple blocks 404, each of which can have a common source line 414 (e.g., coupled to ground). In some embodiments, each block 404 is a basic data unit with an erase operation, i.e., all memory cells 406 on the same block 404 are erased simultaneously. To erase memory cells 406 in a selected block 404, a source line 414 biased to the selected block 404 and unselected blocks 404 on the same plane as the selected block 404 can be used. It should be understood that in some examples, the erase operation can be performed at the half-block level, at the quarter-block level, or at any suitable number of blocks or any suitable fraction of blocks. Memory cells 406 of adjacent NAND memory strings 408 can be coupled via word lines 418, which select which row of memory cells 406 receives read and program operations. In some embodiments, memory cells 406 coupled to the same word line 418 are referred to as pages 420. A page 420 is a basic unit of data used for programming or reading operations, and the size of a page 420, measured in bits, can be related to the number of NAND memory strings 408 coupled by word lines 418 in a block 404. Each word line 418 may include multiple control gates (gate electrodes) at each memory cell 406 within the corresponding page 420, as well as gate lines coupling the control gates.

[0092] The organization structure of the memory array 401 inside the memory is as follows: Figure 5 As shown. The storage array 401 can be divided into several DIEs (or LUNs), each DIE has several planes, each plane has several blocks, each block has several pages, and each page corresponds to a wordline. Wordlines connect thousands upon thousands of storage units 406. The DIE / LUN is the basic unit for receiving and executing operation commands. For example... Figure 5As shown, LUN0 and LUN1 can receive and execute different commands at the same time (but still with certain limitations, which vary from one manufacturer to another). But within one LUN, only one command can be executed independently at a time, and a read access cannot be performed on one Page while a write access is being performed on another Page. A LUN is further divided into Planes, and there are usually 1 or 2 Planes in the market, and there are also 4 Planes of flash memory. Each Plane has its own Cache Register and Page Register, and the size of each is equal to the size of a Page. When writing a Page, the memory controller first transfers data from the memory controller to the Cache Register of the Plane corresponding to the Page, and then writes the data in the entire Cache Register to the memory cell. When reading, the data of the Page is first read from the memory cell to the Cache Register, and then transferred to the memory controller as needed. The "as needed" means that when we read data, there is no need to transfer the entire Page of data to the memory controller, but to select data for transfer as needed. But remember that both reading data from the memory cell to the Cache Register and writing data from the Cache Register to the memory cell are in units of Pages.

[0093] Figure 6 A side view showing a cross-section of an exemplary memory array including NAND memory strings. As Figure 6 As shown in FIG. 4A, the NAND memory strings 408 can extend vertically through the memory stack 604 over the substrate 602. The substrate 602 can include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0094] The memory stack 604 can include alternating gate conductive layers 606 and gate-to-gate dielectric layers 508. The number of pairs of gate conductive layers 606 and gate-to-gate dielectric layers 508 in the memory stack 604 can determine the number of memory cells 406 in the memory array 401. The gate conductive layers 606 can include a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate conductive layer 606 includes a metal layer, e.g., a tungsten layer. In some embodiments, each gate conductive layer 606 includes a doped polysilicon layer. Each gate conductive layer 606 can include a control gate that surrounds a memory cell 406 and can extend laterally at a top of the memory stack 604 as a DSG line 413, at a bottom of the memory stack 604 as a SSG line 415, or between the DSG line 413 and the SSG line 415 as a word line 418.

[0095] As shown in Figure 6 The NAND memory string 408 includes a channel structure 612 that extends vertically through the memory stack 604, as shown in FIG. 6B. In some embodiments, the channel structure 612 includes a channel hole that is filled with a semiconductor material(s) (e.g., as a semiconductor channel 620) and a dielectric material(s) (e.g., as a memory film 618). In some embodiments, the semiconductor channel 620 includes silicon, e.g., polysilicon. In some embodiments, the memory film 618 is a composite dielectric layer that includes a tunneling layer 626, a storage layer 624 (also referred to as a “charge-trapping / storage layer”), and a blocking layer 622. The channel structure 612 can have a cylindrical shape (e.g., a column shape). According to some embodiments, the semiconductor channel 620, the tunneling layer 626, the storage layer 624, and the blocking layer 622 are arranged radially from a center of the column toward an outer surface of the column in this order. The tunneling layer 626 can include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer 624 can include silicon nitride, silicon oxynitride, or any combination thereof. The blocking layer 622 can include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film 618 can include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0096] According to some embodiments, as shown in Figure 6As shown, well 614 (e.g., a P-well and / or an N-well) is formed in substrate 602, and the source terminal of NAND memory string 408 is in contact with well 614. For example, source line 414 may be coupled to well 614 to apply an erase voltage to well 614 (i.e., the source of NAND memory string 408) during an erase operation. In some embodiments, NAND memory string 408 also includes a channel plug 616 at the drain terminal of NAND memory string 408. It should be understood that, although in Figure 6 Although not shown, these may form additional components for the memory array 401. These additional components include, but are not limited to, gate line gaps / source contacts, local contacts, interconnect layers, etc. It should be noted that in some embodiments, Figure 6 The semiconductor channel 620 shown extends directly to the well 614, without requiring Figure 6 The gray plug on top of the 614-type sink. That is to say, Figure 6 The memory structure described is merely exemplary, and the data transmission device provided in this embodiment of the invention is applicable to memory structures of any kind.

[0097] Return to reference Figure 4 Peripheral circuitry 402 can be coupled to memory array 401 via bit line 416, word line 418, source line 414, SSG line 415, and DSG line 413. Peripheral circuitry 402 can include any suitable analog, digital, and mixed-signal circuitry to facilitate operation of memory array 401 by applying voltage and / or current signals to each target memory cell 406 via bit line 416, word line 418, source line 414, SSG line 415, and DSG line 413, and by sensing voltage and / or current signals from each target memory cell 406. Peripheral circuitry 402 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 7 Some exemplary peripheral circuitry is shown. Peripheral circuitry 402 includes a page buffer / sensor amplifier 704, a column decoder / bit line driver 706, a row decoder / word line driver 708, a voltage generator 710, a control logic unit 712, a register 714, an interface 716, and a data bus 718. It should be understood that in some examples, additional peripheral circuitry may be included. Figure 7 Additional peripheral circuitry not shown.

[0098] The page buffer / sense amplifier 704 can be configured to read data from and program (write) data to the memory array 401 according to control signals from the control logic unit 712. In one example, the page buffer / sense amplifier 704 can store a page of program data (write data) to be programmed into one page 420 of the memory array 401. In another example, the page buffer / sense amplifier 704 can perform a program verify operation to ensure that data has been correctly programmed into the memory cells 406 coupled to the selected word line 418. In yet another example, the page buffer / sense amplifier 704 can also sense low power signals from the bit lines 416 representing data bits stored in the memory cells 406 and amplify the small voltage swings to identifiable logic levels in read operations. The column decoder / bit line driver 706 can be configured to be controlled by the control logic unit 712 and select one or more NAND memory strings 408 by applying bit line voltages generated from the voltage generator 710.

[0099] The row decoder / word line driver 708 can be configured to be controlled by the control logic unit 712 and select / deselect blocks 404 of the memory array 401 and select / deselect word lines 418 of the blocks 404. The row decoder / word line driver 708 can also be configured to drive the word lines 418 using word line voltages generated from the voltage generator 710. In some implementations, the row decoder / word line driver 708 can also select / deselect and drive the SSG lines 415 and the DSG lines 413. As described in detail below, the row decoder / word line driver 708 is configured to perform erase operations on the memory cells 406 coupled to the selected word line(s) 418. The voltage generator 710 can be configured to be controlled by the control logic unit 712 and generate word line voltages (e.g., read voltages, program voltages, pass voltages, local voltages, verify voltages, etc.), bit line voltages, and source line voltages to be supplied to the memory array 401.

[0100] The control logic unit 712 can be coupled to each of the peripheral circuits described above and configured to control the operation of each of the peripheral circuits. The registers 714 can be coupled to the control logic unit 712 and include status registers, command registers, and address registers for storing status information, command operation codes (OP codes), and command addresses used to control the operation of each of the peripheral circuits. The interface 716 can be coupled to the control logic unit 712 and act as a control buffer to buffer control commands received from a host (not shown) and relay them to the control logic unit 712, and to buffer status information received from the control logic unit 712 and relay them to the host. The interface 716 can also be coupled to the column decoder / bit line driver 706 via the data bus 718 and act as a data I / O interface and data buffer to buffer data and relay them to or from the memory array 401.

[0101] Based on the above-described storage system and memory, the current data transmission between the Planes in the memory needs to be realized by means of the memory control coupled with the memory (specifically, the user reads the data of a certain Plane through the I / O interface, and then transmits the pre-read data to another Plane through the I / O interface), and the existing circuit design cannot support the data transmission between the storage surfaces (Planes) within the memory. In order to solve the above technical problems, as shown in the description, the embodiment of the present application provides a memory 104, which can include: a memory array 401; the memory array includes a plurality of storage surfaces; and a peripheral circuit 402 coupled with the storage surfaces, wherein; Figure 8

[0102] The peripheral circuit 402 includes: a buffering device 80 coupled between a first storage surface and a second storage surface, wherein the buffering device is used to read first data from the first storage surface and transmit the first data to the second storage surface, or read second data from the second storage surface and transmit the second data to the first storage surface;

[0103] Wherein the first storage surface and the second storage surface are any two storage surfaces of the plurality of storage surfaces.

[0104] It should be noted that the basic structure of the memory 104 here is also as described above Figures 1 to 7 ​The described, including a storage array, peripheral circuit, control logic unit contained in the peripheral circuit, etc. In the embodiment of the application, the buffer device 80 is added between the Plane, so that the Plane can directly transmit data without the help of the memory controller to indirectly realize the data transmission between the Plane. The first storage surface and the second storage surface described herein are any two storage surfaces of the plurality of storage surfaces. That is, in the memory, a buffer device can be coupled between any two storage surfaces. The buffer device is used to read data from the first storage surface and transmit to the second storage surface; or read data from the second storage surface and transmit to the first storage surface. The first data and the second data are used only to facilitate the distinction between the working processes of the two buffer devices, and do not limit the present application.

[0105] In some embodiments, as Figure 9 The buffer device 80 can include a clock buffer component 901, a first buffer component 902 corresponding to the first storage surface, a second buffer component 903 corresponding to the second storage surface, and a conversion buffer component 904, as shown.

[0106] The clock buffer component is used to receive an original clock signal and a first read enable signal of the first storage surface; when the first read enable signal is valid, generate a first sub-input clock signal of the first storage surface based on the original clock signal; and send the first sub-input clock signal to the first buffer component;

[0107] The first buffer component is coupled to the clock buffer component and is used to receive the first read enable signal and the first sub-input clock signal; when the first read enable signal is valid, output a first output signal based on the first sub-input clock signal; transmit the first output signal to the conversion buffer; and the first output signal includes a first output clock signal, a first data signal for indicating first data, and a first address signal.

[0108] The conversion buffer component is used to receive the first output signal, the first read enable signal, and a first write enable signal of the second storage surface; when the first read enable signal and the first write enable signal are valid, convert the first output clock signal, the first data signal, and the first address signal contained in the first output signal into a first input signal of the second storage surface; the first input signal includes a first input clock signal, a second data signal for indicating the first data, and a second address signal; and transmit the first input signal to the second buffer component.

[0109] The second buffer component is configured to receive the first input signal and the first write enable signal, generate a first write clock signal based on the first input clock signal when the first write enable signal is valid, generate a first write address based on the second address signal, generate the first data based on the second data signal, and write the first data into the first write address of the second storage surface based on the first write clock signal.

[0110] The structure of the buffer device and how it reads the first data from the first storage surface and transmits it to the second storage surface are described herein.

[0111] The original clock signal can be an externally input clock signal or generated by a memory internal control logic unit, and functions as a basic clock signal for data transmission between storage surfaces. The first read enable signal of the first storage surface is an enable signal for reading the first storage surface. The clock buffer component receives the first read enable signal and the original clock signal, and generates a first sub-input clock signal of the first storage surface based on the original clock signal when the first read enable signal is valid. The first sub-input clock signal is an input clock signal of the first storage surface. It should be noted that the first read enable signal can be active low or active high, and the specific form is determined according to the specific circuit design.

[0112] The first sub-input clock signal is sent to the first buffer component coupled to the clock buffer component. The first buffer component receives the first sub-input clock signal and the first read enable signal, and outputs a first output signal based on the first sub-input clock signal when the first read enable signal is valid, and sends the first output signal to the conversion buffer component. The first output signal includes a first output clock signal, a first data signal for representing first data, and a first address signal. That is, the first buffer component outputs the first output clock signal, the first data signal, and the first address signal, wherein the first data is data read from the first storage surface based on the first sub-input clock signal, the first address signal is a signal generated based on the address of the first data in the first storage surface, and the first output clock signal is a clock signal for outputting the first address signal and the first data signal from the first buffer component.

[0113] The conversion buffer component is configured to convert the first output signal into a first input signal of a second storage surface when the first read enable signal and the first write enable signal are active, wherein the first input signal comprises a first input clock signal, a second data signal for representing first data, and a second address signal; the first input clock signal is a clock signal for generating data written to the second storage surface; the second data signal is a converted signal of the first data signal, and represents the first data; and the second address signal is a converted address signal of the first address signal, and represents a write address of the second data written to the second storage surface.

[0114] The second buffer component is associated with the second storage surface, and is configured to receive the first write enable signal and the first input signal, and generate a first write clock signal based on the first input clock signal when the first write enable signal is active; generate a first write address based on the second address signal; generate first data based on the second data signal; and write the first data to the first write address of the second storage surface based on the first write clock signal.

[0115] Through the above process, the first data in the first storage surface can be written to the second storage surface.

[0116] In some embodiments, second data in the second storage surface can also be written to the first storage surface. Specifically, the components in the buffer device can work as follows:

[0117] The clock buffer is further coupled to the second buffer component, and is configured to receive the original clock signal and a second read enable signal of the second storage surface; generate a second sub-input clock signal based on the original clock signal when the second read enable signal is active; and send the second sub-input clock signal to the second buffer component.

[0118] The second buffer component is configured to receive the second read enable signal and the second sub-input clock signal; output a second output signal based on the second sub-input clock signal when the second read enable signal is active; and transmit the second output signal to the conversion buffer; the second output signal comprises a second output clock signal, a third data signal for representing the second data, and a third address signal.

[0119] The conversion buffer component is configured to receive the second output signal, the second read enable signal and a second write enable signal of the first storage surface; when the second read enable signal and the second write enable signal are valid, convert the second output clock signal, the second data signal and the third address signal contained in the second output signal into a second input signal of the first storage surface; the second input signal comprises a second input clock signal, a fourth data signal for representing the second data and a fourth address signal; and transmit the second input signal to the first buffer component.

[0120] The first buffer component is configured to receive the second input signal and the second write enable signal; when the second write enable signal is valid, generate a second write clock signal based on the second input clock signal; generate a second write address based on the fourth address signal; generate the second data based on the fourth data signal; and write the second data into the second write address of the first storage surface based on the second write clock signal.

[0121] It should be noted that the process described herein is the reverse of the process of reading data from the first storage surface and writing the data to the second storage surface described above, and how to implement the process is similar to the process described above, and can be understood by referring to the process described above, which will not be described herein.

[0122] Based on the foregoing description of the buffer device, for the clock buffer component, as shown in Figure 10 The clock buffer component 901 comprises a first tri-state buffer 1001 and a second tri-state buffer 1002, wherein

[0123] The input end of the first tri-state buffer and the input end of the second tri-state buffer are connected to the original clock signal;

[0124] The enable end of the first tri-state buffer is connected to the first read enable signal, and the output end outputs the first sub-input clock signal;

[0125] The enable end of the second tri-state buffer is connected to the second read enable signal, and the output end outputs the second sub-input clock signal.

[0126] It should be noted that the clock buffer component described herein is only an example, which includes two tri-state buffers: a first tri-state buffer and a second tri-state buffer, wherein the first tri-state buffer outputs a first sub-input clock signal related to the first storage surface based on the original clock signal when the first read enable signal is valid, for later use; the second tri-state buffer outputs a second sub-input clock signal related to the second storage surface based on the original clock signal when the second read enable signal is valid, for later use. In actual application, the first read enable signal and the second read enable signal are not valid at the same time.

[0127] It can be understood that the clock buffer component described herein is only an example of including two tri-state buffers. In fact, the clock buffer component can include tri-state buffers connected to N input terminals, connected to the original clock signal, and connected to the read enable signal of each storage surface; wherein N is an integer greater than 2.

[0128] For the first buffer component, as shown in Figure 11 The first buffer component 902 includes a first buffer group 1101, a second buffer group 1102, and a third buffer group 1103, wherein

[0129] The first buffer group includes a first clock buffer; the first clock buffer is used to connect to the first sub-input clock signal and the first read enable signal; when the first read enable signal is valid, the first output clock signal is generated based on the first sub-input clock signal; the first output clock signal is transmitted to the conversion buffer component;

[0130] The second buffer group includes a first data buffer; the first data buffer is used to connect to the first read enable signal and the first data; when the first read enable signal is valid, the first data signal is generated based on the first data; the first data signal is transmitted to the conversion buffer component; the first data is read from the first read address of the first storage surface based on the first sub-input clock signal;

[0131] The third buffer group includes a first address buffer; the first address buffer is used to connect to the first read enable signal and the first read address; when the first read enable signal is valid, the first address signal is generated based on the first read address; the first address signal is transmitted to the conversion buffer component.

[0132] It should be noted that the first buffer assembly corresponds to the first storage surface. Here, the process of the first buffer assembly generating the first output signal is described. Here, the first read enable signal is used as the enable signal of the first clock buffer included in the first buffer group, the first data buffer included in the second buffer group, and the first address buffer included in the third buffer group. When the first read enable signal is valid, the first clock buffer generates a first output clock signal based on the first sub-input clock signal and transmits the first output clock signal to the conversion buffer assembly; the first data buffer generates a first data signal based on first data and transmits the first data signal to the conversion buffer assembly, wherein the first data is read from the first read address of the first storage surface by the control logic unit of the memory based on the first sub-input clock signal; and the first address buffer generates a first address signal based on the first read address and transmits the first address signal to the conversion buffer assembly.

[0133] The foregoing is the logic of the first buffer assembly reading first data from the first storage surface, and the first buffer assembly can also write data to the first storage surface, so in some embodiments, the first buffer group further includes a second clock buffer; the second clock buffer is configured to receive the second write enable signal and a second input clock signal; and when the second write enable signal is valid, the second clock buffer generates a second write clock signal based on the second input clock signal.

[0134] The third buffer group further includes a second address buffer; the second address buffer is configured to receive the second write enable signal and the fourth address signal; and when the second write enable signal is valid, the second address buffer generates a second write address based on the fourth address signal.

[0135] The second buffer group further includes a second data buffer; the second data buffer is configured to receive the fourth data signal and the second write enable signal; and when the second write enable signal is valid, the second data buffer generates the second data based on the fourth data signal and writes the second data to the first storage surface at the second write address based on the second write clock signal.

[0136] It should be noted that the process of writing data to the first storage surface described here is the reverse of the process of reading data from the first storage surface described above. Here, the write enable signal, i.e., the second write enable signal, is effective, and data is written to the first storage surface.

[0137] Since the second storage surface has a similar structure to the first storage surface, in some embodiments, the structure of the second buffer assembly is the same as that of the first buffer assembly.

[0138] For the conversion buffer component, as shown in Figure 12 The conversion buffer component 904 includes a clock conversion group 1201, an address conversion group 1202, and a data conversion group 1203.

[0139] The clock conversion group is configured to receive the first output clock signal, the first read enable signal, and the first write enable signal; generate the first input clock signal based on the first output clock signal when both the first read enable signal and the first write enable signal are valid; and transmit the first input clock signal to the second buffer component.

[0140] The address conversion group is configured to receive the first address signal, the first read enable signal, and the first write enable signal; generate the second address signal based on the first address signal when both the first read enable signal and the first write enable signal are valid; and transmit the second address signal to the second buffer component.

[0141] The data conversion group is configured to receive the first data signal, the first read enable signal, and the first write enable signal; generate the second data signal based on the first data signal when both the first read enable signal and the first write enable signal are valid; and transmit the second data signal to the second buffer component.

[0142] Here, the conversion buffer component converts the first output signal into the first input signal, which implements the process of transmitting the first data of the first storage surface to the second storage surface. The first output signal output from the first buffer component is converted into the first input signal to be input into the second buffer component when both the first read enable signal of the first storage surface and the first write enable signal of the second storage surface are valid.

[0143] In some embodiments, the clock conversion group is further configured to receive the second output clock signal, the second read enable signal, and the second write enable signal; generate the second input clock signal based on the second output clock signal when both the second read enable signal and the second write enable signal are valid; and transmit the second input clock signal to the first buffer component.

[0144] The address conversion group is configured to receive the third address signal, the second read enable signal, and the second write enable signal; generate the fourth address signal based on the third address signal when both the second read enable signal and the second write enable signal are valid; and transmit the fourth address signal to the first buffer component.

[0145] The data conversion group is configured to receive the third data signal, the second read enable signal and the second write enable signal, generate the fourth data signal based on the third data signal when both the second read enable signal and the second write enable signal are active, and transmit the fourth data signal to the first buffer component.

[0146] Here, the conversion buffer component converts the second output signal into the second input signal, and the second data of the second storage surface is transmitted to the first storage surface. The second output signal output by the second buffer component is converted into the second input signal to be input into the first buffer component when both the second write enable signal of the first storage surface and the second read enable signal of the second storage surface are active.

[0147] For the clock conversion group, referring to Figure 13 As shown in the figure, the clock conversion group 1201 can include a first group of buffers 1301 and a second group of buffers 1302. The first group of buffers 1301 includes a third tri-state buffer 1301-1 and a fourth tri-state buffer 1301-2. The second group of buffers 1302 includes a fifth tri-state buffer 1302-1 and a sixth tri-state buffer 1302-2.

[0148] The input end of the third tri-state buffer is connected to the output end of the fourth tri-state buffer. The output end of the third tri-state buffer is connected to the input end of the fourth tri-state buffer. The enable end of the third tri-state buffer is connected to the first read enable signal. The enable end of the fourth tri-state buffer is connected to the second write enable signal.

[0149] The input end of the third tri-state buffer, the output end of the fourth tri-state buffer, the input end of the fifth tri-state buffer and the output end of the sixth tri-state buffer are connected.

[0150] The output end of the fifth tri-state buffer is connected to the input end of the sixth tri-state buffer. The enable end of the fifth tri-state buffer is connected to the second read enable signal. The enable end of the sixth tri-state buffer is connected to the first write enable signal.

[0151] It should be noted that only how the clock conversion group uses two groups of buffers to realize the conversion of the output clock signal of the first storage surface to the input clock signal of the second storage surface and the conversion of the output clock signal of the second storage surface to the input clock signal of the first storage surface is described here. It can be understood that in fact, the clock conversion group can include N groups of buffers, which can realize the conversion of the clock signal in any two storage surfaces. Figure 13The first output clock signal / second input clock signal, the first input clock signal / second output clock signal in the above-mentioned have been described, and will not be described here again.

[0152] In some embodiments, the structure of the address conversion group and the structure of the data conversion group are the same as the structure of the clock conversion group.

[0153] In some embodiments, the structure of the data conversion group is the same as the structure of the clock conversion group; the structure of the address conversion group further comprises elements for realizing address offset function, so as to realize writing data in one storage surface to a specified address in another storage surface.

[0154] In some embodiments, the peripheral circuit further comprises an I / O interface and a control logic unit, wherein,

[0155] The control logic unit is configured to receive a first command through the I / O interface; control the buffer device to read first data from the first storage surface, transmit the first data to the second storage surface, or read second data from the second storage surface, and transmit the second data to the first storage surface based on the first command.

[0156] It should be noted that the storage surfaces in the above-mentioned memory can directly transmit data between each other, but the control of which two storage surfaces transmit data, which storage surface reads data, which storage surface stores data, and the transmission timing, etc. are all controlled by the memory controller. That is, the memory controller sends a first command to the control logic unit of the memory through the I / O interface, and then the control logic unit parses the necessary information of which storage surface reads data, which storage surface stores data, etc. based on the first command, so as to realize the data transmission between the storage surfaces. That is, the sending of the first command can be transmitted by the memory controller contained in the storage system to the control logic unit through the I / O interface contained in the peripheral circuit, and the control logic unit parses the necessary information of which storage surface reads data, which storage surface stores data, etc. based on the first command, so as to realize the data transmission between the storage surfaces.

[0157] In order to understand the present application, the embodiments of the present application are described below Figures 14 to 17 for illustration. Figure 14 A schematic diagram of a principle structure provided by an embodiment of the present application is shown; Figure 15 A schematic diagram of a structure of a clock buffer assembly provided by an embodiment of the present application is shown; Figure 16 A schematic diagram of a structure of a buffer assembly associated with a storage surface provided by an embodiment of the present application is shown; Figure 17 A schematic diagram of a structure of a conversion buffer assembly provided by an embodiment of the present application is shown.

[0158] InFigure 14 The implementation principle of the method provided in this embodiment of the invention can be as follows: the original clock signal is input to the clock buffer component to generate a sub-input clock signal clk_in_x that enters the storage plane Plane(x); then, the clk_in_x is transmitted to the buffer component corresponding to Plane(x), and the buffer component generates an output signal including an output clock signal clk_plane_x, an address signal addr_plane_x, and a data signal data_plane_x based on the clk_in_x and the read enable signal, so as to complete the reading of Plane(x). Then, this output signal is input to the conversion buffer component. The conversion buffer component converts the output signal of Plane(x) into an input signal of Plane(y) containing the clock signal clk_plane_y, the address signal addr_plane_y, and the data signal data_plane_y. This input signal is then input to the buffer component corresponding to Plane(y). Based on these input signals and the write enable signal, the buffer component corresponding to Plane(y) writes the data read from Plane(x) into Plane(y), thus completing the direct data transfer from Plane(x) to Plane(y). It should be noted that... Figure 14 The arrows in the intermediate conversion buffer component are bidirectional, meaning that direct data transfer from Plane(y) to Plane(x) can also be accomplished. The specific process is similar to that described above and will not be repeated here. It should be noted that Plane(x) can be, for example... Figure 14 The diagram shows any one of the storage planes from PLANE0 to PLANEEN corresponding to each buffer component; Plane(y) can be any one of the storage planes from PLANE0 to PLANE except Plane(x). clk_in_x can be any one of clk_in_0 to clk_in_n. Figure 14 The storage plane corresponding to the cache component is not shown in the diagram. There is a one-to-one correspondence between the storage plane and the corresponding cache component. For details on the relationship between the two, please refer to the previous section. Figure 9 As shown.

[0159] for Figure 14 One structure of the clock buffer component in the middle is as follows Figure 15 As shown. The inputs of N tri-state buffers are connected together and connected to the original clock signal. The enable terminal of each tri-state buffer is connected to the read enable signal of the corresponding memory plane, and the output terminal is connected to the sub-input clock signal of the corresponding memory plane. For example, the enable terminal of the tri-state buffer corresponding to Plane(0) is connected to the read enable signal en_read_plane_0 corresponding to Plane(0), and the output terminal is connected to the sub-input clock signal clk_in_0 corresponding to Plane(0). And so on.

[0160] for Figure 14 The structure of the buffer component corresponding to the storage surface in the middle is as follows: Figure 16 As shown. Because the structure of the buffer components corresponding to each storage surface is the same. Figure 16 The explanation will focus on the buffer component corresponding to Plane(0).

[0161] Specifically, the buffer assembly includes: a first buffer group, a second buffer group, and a third buffer group, wherein;

[0162] The first buffer group includes a first clock buffer and a second clock buffer; wherein, the input terminal of the first clock buffer is connected to the sub-input clock signal clk_in_0 corresponding to Plane(0), the enable terminal is connected to the read enable signal en_read_plane_0 corresponding to Plane(0), and the output terminal outputs the output clock signal clk_plane_0; the input terminal of the second clock buffer is connected to the input clock signal clk_plane_0, the enable terminal is connected to the write enable signal en_write_plane_0 corresponding to Plane(0), and the output terminal outputs the write clock signal corresponding to Plane(0);

[0163] The second buffer group includes a first data buffer and a second data buffer; wherein, the input terminal of the first data buffer is connected to data read from Plane(0) based on the sub-input clock signal, the enable terminal is connected to en_read_plane_0, and the output terminal outputs the data signal data_plane_0 corresponding to the data read from Plane(0); the input terminal of the second data buffer is connected to the data signal generated by data read from other storage planes, the enable terminal is connected to en_write_plane_0, and the output terminal outputs the data read from other storage planes;

[0164] The third buffer group includes a first address buffer and a second address buffer; wherein, the input terminal of the first address buffer is connected to the read address (the position of the data read in Plane(0) in Plane(0)), the enable terminal is connected to en_read_plane_0, and the output terminal outputs the address signal addr_plane_0 corresponding to Plane(0); the input terminal of the second address buffer is connected to the address signal addr_plane_0 corresponding to Plane(0), the enable terminal is connected to en_write_plane_0, and the output terminal outputs the write address corresponding to Plane(0).

[0165] One optional embodiment is that when reading Plane(0), en_write_plane_0=0; en_read_plane_0=1; when writing Plane(0), en_write_plane_0=1; en_read_plane_0=0.

[0166] For Figure 14 , a structure of a conversion buffer component is shown in Figure 17 . The conversion buffer component comprises a clock conversion group, an address conversion group and a data conversion group, wherein, according to a structure shown in Figure 17 , the address conversion group and the data conversion group have the same structure as the clock conversion group.

[0167] Hereinafter, only the structure of the clock conversion group is described.

[0168] The clock conversion group comprises N groups of buffers connected with each other, each group of buffers comprises two tri-state buffers, wherein one tri-state buffer is controlled by a read enable signal of a corresponding storage surface, and the other tri-state buffer is controlled by a write enable signal of the corresponding storage surface. In this way, the conversion of the clock signals between different storage surfaces is realized.

[0169] It should be noted that, based on the structure of the conversion buffer component, Figure 17 , the address division of Plane(x) is the same as that of Plane(y), in other words, the position of the data read from Plane(x) in Plane(x) is the same as the position of the data stored in Plane(y). It should be understood that, for the storage address, an offset can also be performed to store in a specified position in Plane(y), and how to design is added according to actual requirements, to obtain the required address.

[0170] Here, when reading PLANE(X), en_read_plane_x=1, en_write_plane_x=0, and other buffer enable signals are 0. When writing PLANE(X), en_read_plane_x=0, en_write_plane_x=1, and other buffer enable signals are 0.

[0171] The memory provided by the embodiment of the present application realizes the direct data transmission between the storage surfaces in the memory by setting the buffer device between the storage surfaces and transmitting the data of one storage surface to another storage surface by the buffer device, without the help of the coupled memory controller, which is convenient and fast.

[0172] Based on the same inventive concept, as Figure 18As shown, the embodiment of the present application also provides an operation method of a memory, applied to a peripheral circuit included in the memory, and the operation method comprises:

[0173] S1801: receiving a first command;

[0174] S1802: reading first data from a first storage surface based on the first command, and transmitting the first data to a second storage surface; or reading second data from the second storage surface, and transmitting the second data to the first storage surface;

[0175] Wherein, the first storage surface and the second storage surface are any two storage surfaces in a plurality of storage surfaces included in the memory.

[0176] In some embodiments, the reading first data from a first storage surface based on the first command, and transmitting the first data to a second storage surface comprises:

[0177] obtaining a first read enable signal based on the first command; and receiving an original clock signal;

[0178] generating a first sub-input clock signal based on the original clock signal when the first read enable signal is valid; generating a first output signal based on the first sub-input clock signal; the first output signal comprises a first output clock signal, a first data signal for representing first data, and a first address signal;

[0179] converting the first output clock signal, the first data signal, and the first address signal included in the first output signal into a first input signal of the second storage surface when the first read enable signal and a first write enable signal of the second storage surface are valid; the first input signal comprises a first input clock signal, a second data signal for representing the first data, and a second address signal; the first write enable signal is obtained based on the first command;

[0180] generating a first write clock signal based on the first input clock signal when the first write enable signal is valid; generating a first write address based on the second address signal; generating the first data based on the second data signal; and writing the first data into the first write address of the second storage surface based on the first write clock signal.

[0181] In some embodiments, the reading second data from the second storage surface based on the first command, and transmitting the second data to the first storage surface comprises:

[0182] obtaining a second read enable signal based on the first command; and receiving an original clock signal;

[0183] generate a second sub-input clock signal based on the original clock signal when the second read enable signal is active;

[0184] output a second output signal based on the second sub-input clock signal; the second output signal comprises a second output clock signal, a third data signal for representing the second data, and a third address signal;

[0185] convert the second output clock signal, the second data signal, and the third address signal contained in the second output signal into a second input signal of the first storage surface when the second read enable signal and a second write enable signal of the first storage surface are active; the second input signal comprises a second input clock signal, a fourth data signal for representing the second data, and a fourth address signal; the second write enable signal is obtained based on the first command;

[0186] generate a second write clock signal based on the second input clock signal when the second write enable signal is active; generate a second write address based on the fourth address signal; generate the second data based on the fourth data signal; and write the second data into the second write address of the first storage surface based on the second write clock signal.

[0187] It should be noted that the technical solutions described in the operation method and the technical solutions of the memory belong to the same inventive concept, and both have the same technical features. The terms appearing in the structure of the memory and the technical solutions of the present application have been described in detail above, so the terms appearing here can be understood according to the meaning described above, and will not be described again.

[0188] The embodiment of the present application also provides a storage system, comprising: one or more memories described in any of the preceding embodiments;

[0189] and a memory controller coupled to the memory; the memory controller is configured to send various operation commands to the memory; wherein the various operation commands can comprise the first command.

[0190] It should be noted that the storage system herein comprises the memory described above, and both have the same technical features. The structure of the memory and the terms appearing in the technical solutions of the present application have been described in detail above, so the terms appearing here can be understood according to the meaning described above, and will not be described again.

[0191] The above only describes the preferred embodiments of the present application, and is not used to limit the protection scope of the present application.

Claims

1. A memory, characterized in that, include: Multiple storage planes; and peripheral circuitry coupled to the storage surface, wherein; The peripheral circuit includes: a buffer device coupled between a first storage surface and a second storage surface, wherein the buffer device is used to read first data from the first storage surface and transmit the first data to the second storage surface; or, to read second data from the second storage surface and transmit the second data to the first storage surface; Wherein, the first storage surface and the second storage surface are any two storage surfaces among the plurality of storage surfaces; The buffer device includes: a clock buffer component, a first buffer component corresponding to the first storage surface, a second buffer component corresponding to the second storage surface, and a conversion buffer component, wherein: The clock buffer component is configured to receive the original clock signal and the first read enable signal of the first storage surface; when the first read enable signal is valid, generate the first sub-input clock signal of the first storage surface based on the original clock signal; and send the first sub-input clock signal to the first buffer component. A first buffer component, coupled to the clock buffer component, is used to receive the first read enable signal and the first sub-input clock signal; when the first read enable signal is valid, it outputs a first output signal based on the first sub-input clock signal; and transmits the first output signal to the conversion buffer component; the first output signal includes a first output clock signal, a first data signal representing first data, and a first address signal; The conversion buffer component is configured to receive the first output signal, the first read enable signal, and the first write enable signal of the second storage surface; when the first read enable signal and the first write enable signal are valid, convert the first output clock signal, the first data signal, and the first address signal contained in the first output signal into a first input signal of the second storage surface; the first input signal includes: a first input clock signal, a second data signal representing the first data, and a second address signal; and transmit the first input signal to the second buffer component; The second buffer component is configured to receive the first input signal and the first write enable signal; when the first write enable signal is valid, generate a first write clock signal based on the first input clock signal; generate a first write address based on the second address signal; generate the first data based on the second data signal; and write the first data to the first write address of the second storage surface based on the first write clock signal.

2. The memory according to claim 1, characterized in that, The clock buffer component is also coupled to the second buffer component for receiving the original clock signal and the second read enable signal of the second storage surface; when the second read enable signal is valid, a second sub-input clock signal is generated based on the original clock signal. Send the second sub-input clock signal to the second buffer component; The second buffer component is configured to receive the second read enable signal and the second sub-input clock signal; when the second read enable signal is valid, it outputs a second output signal based on the second sub-input clock signal. The second output signal is transmitted to the conversion buffer component; the second output signal includes a second output clock signal, a third data signal representing the second data, and a third address signal. The conversion buffer component is configured to receive the second output signal, the second read enable signal, and the second write enable signal of the first storage surface; when the second read enable signal and the second write enable signal are valid, it converts the second output clock signal, the second data signal, and the third address signal contained in the second output signal into a second input signal of the first storage surface; the second input signal includes a second input clock signal, a fourth data signal representing the second data, and a fourth address signal; and transmits the second input signal to the first buffer component. The first buffer component is configured to receive the second input signal and the second write enable signal; when the second write enable signal is valid, it generates a second write clock signal based on the second input clock signal. A second write address is generated based on the fourth address signal; The second data is generated based on the fourth data signal; the second data is written to the second write address of the first storage surface based on the second write clock signal.

3. The memory according to claim 2, characterized in that, The clock buffer component includes: a first tri-state buffer and a second tri-state buffer, wherein; The input terminals of the first tri-state buffer and the second tri-state buffer are connected to the original clock signal; The enable terminal of the first tri-state buffer is connected to the first read enable signal, and the output terminal outputs the first sub-input clock signal; The enable terminal of the second tri-state buffer is connected to the second read enable signal, and the output terminal outputs the second sub-input clock signal.

4. The memory according to claim 2, characterized in that, The first buffer component includes: a first buffer group, a second buffer group, and a third buffer group, wherein; The first buffer group includes a first clock buffer; the first clock buffer is used to receive the first sub-input clock signal and the first read enable signal; when the first read enable signal is valid, a first output clock signal is generated based on the first sub-input clock signal; and the first output clock signal is transmitted to the conversion buffer component. The second buffer group includes a first data buffer; the first data buffer is used to receive the first read enable signal and first data; when the first read enable signal is valid, the first data signal is generated based on the first data; the first data signal is transmitted to the conversion buffer component; the first data is read from the first read address of the first storage surface based on the first sub-input clock signal; The third buffer group includes a first address buffer; the first address buffer is used to receive the first read enable signal and the first read address; when the first read enable signal is valid, the first address signal is generated based on the first read address; and the first address signal is transmitted to the conversion buffer component.

5. The memory according to claim 4, characterized in that, The first buffer group further includes a second clock buffer; the second clock buffer is used to receive the second write enable signal and the second input clock signal; when the second write enable signal is valid, the second write clock signal is generated based on the second input clock signal; The third buffer group further includes a second address buffer; the second address buffer is used to receive the second write enable signal and the fourth address signal; when the second write enable signal is valid, a second write address is generated based on the fourth address signal; The second buffer group further includes a second data buffer; the second data buffer is used to receive the fourth data signal and the second write enable signal; when the second write enable signal is valid, the second data is generated based on the fourth data signal; and the second data is written to the second write address of the first storage surface based on the second write clock signal.

6. The memory according to claim 5, characterized in that, The structure of the second buffer component is the same as that of the first buffer component.

7. The memory according to claim 2, characterized in that, The conversion buffer component includes: a clock conversion group, an address conversion group, and a data conversion group, wherein; The clock conversion group is used to receive the first output clock signal, the first read enable signal, and the first write enable signal; when both the first read enable signal and the first write enable signal are valid, it generates the first input clock signal based on the first output clock signal; and transmits the first input clock signal to the second buffer component. The address translation group is configured to receive the first address signal, the first read enable signal, and the first write enable signal; when both the first read enable signal and the first write enable signal are valid, generate the second address signal based on the first address signal; and transmit the second address signal to the second buffer component. The data conversion group is configured to receive the first data signal, the first read enable signal, and the first write enable signal; when both the first read enable signal and the first write enable signal are valid, generate the second data signal based on the first data signal; and transmit the second data signal to the second buffer component.

8. The memory according to claim 7, characterized in that, The clock conversion group is further configured to receive the second output clock signal, the second read enable signal, and the second write enable signal; when both the second read enable signal and the second write enable signal are valid, generate the second input clock signal based on the second output clock signal; and transmit the second input clock signal to the first buffer component. The address translation group is configured to receive the third address signal, the second read enable signal, and the second write enable signal; when both the second read enable signal and the second write enable signal are valid, generate the fourth address signal based on the third address signal; and transmit the fourth address signal to the first buffer component. The data conversion group is configured to receive the third data signal, the second read enable signal, and the second write enable signal; when both the second read enable signal and the second write enable signal are valid, generate the fourth data signal based on the third data signal; and transmit the fourth data signal to the first buffer component.

9. The memory according to claim 8, characterized in that, The clock conversion group includes: a first group of buffers and a second group of buffers; the first group of buffers includes a third tri-state buffer and a fourth tri-state buffer; the second group of buffers includes a fifth tri-state buffer and a sixth tri-state buffer; Wherein, the input terminal of the third tri-state buffer is connected to the output terminal of the fourth tri-state buffer; the output terminal of the third tri-state buffer is connected to the input terminal of the fourth tri-state buffer; the enable terminal of the third tri-state buffer is connected to the first read enable signal; and the enable terminal of the fourth tri-state buffer is connected to the second write enable signal. The input terminal of the third tri-state buffer, the output terminal of the fourth tri-state buffer, the input terminal of the fifth tri-state buffer, and the output terminal of the sixth tri-state buffer are connected; The output terminal of the fifth tri-state buffer is connected to the input terminal of the sixth tri-state buffer; the enable terminal of the fifth tri-state buffer is connected to the second read enable signal; and the enable terminal of the sixth tri-state buffer is connected to the first write enable signal.

10. The memory according to any one of claims 7 to 9, characterized in that, The structure of the address translation group and the structure of the data translation group are the same as the structure of the clock translation group.

11. The memory according to claim 1, characterized in that, The peripheral circuitry also includes I / O interfaces and control logic units, wherein, The control logic unit is configured to receive a first command through the I / O interface; and based on the first command, control the buffer device to read first data from the first storage surface and transmit the first data to the second storage surface; or, read second data from the second storage surface and transmit the second data to the first storage surface.

12. A method for operating a memory, characterized in that, The operation method, applied to the peripheral circuitry included in the memory, comprises: Receive the first command; Based on the first command, first data is read from the first storage surface and transmitted to the second storage surface; or, second data is read from the second storage surface and transmitted to the first storage surface. Wherein, the first storage surface and the second storage surface are any two storage surfaces among the plurality of storage surfaces included in the memory; The step of reading first data from the first storage surface based on the first command and transmitting the first data to the second storage surface includes: The first read enable signal is obtained based on the first command; the original clock signal is received. When the first read enable signal is valid, a first sub-input clock signal is generated based on the original clock signal; a first output signal is output based on the first sub-input clock signal; the first output signal includes a first output clock signal, a first data signal for representing first data, and a first address signal. When the first read enable signal and the first write enable signal of the second storage surface are valid, the first output clock signal, the first data signal, and the first address signal contained in the first output signal are converted into the first input signal of the second storage surface; the first input signal includes: a first input clock signal, a second data signal for representing the first data, and a second address signal; the first write enable signal is obtained based on the first command; When the first write enable signal is valid, a first write clock signal is generated based on the first input clock signal; a first write address is generated based on the second address signal; the first data is generated based on the second data signal; and the first data is written to the first write address of the second storage surface based on the first write clock signal. The step of reading second data from the second storage surface based on the first command and transmitting the second data back to the first storage surface includes: Based on the first command, a second read enable signal is obtained; and the original clock signal is received; When the second read enable signal is valid, a second sub-input clock signal is generated based on the original clock signal; A second output signal is output based on the second sub-input clock signal; the second output signal includes a second output clock signal, a third data signal for representing the second data, and a third address signal; When the second read enable signal and the second write enable signal of the first storage surface are valid, the second output clock signal, the second data signal, and the third address signal contained in the second output signal are converted into the second input signal of the first storage surface; the second input signal includes a second input clock signal, a fourth data signal for representing the second data, and a fourth address signal; the second write enable signal is obtained based on the first command; When the second write enable signal is valid, a second write clock signal is generated based on the second input clock signal; a second write address is generated based on the fourth address signal; the second data is generated based on the fourth data signal; and the second data is written to the second write address of the first storage surface based on the second write clock signal.

13. A storage system, characterized in that, include: One or more memories according to any one of claims 1 to 11; and the memory controller coupled to the memory; The memory controller is used to send various operation commands to the memory.

14. The storage system according to claim 13, characterized in that, The storage system is a solid-state drive (SSD) or a memory card.

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