A single-node based multi-channel server device

Abstract

The present invention provides a multi-channel server device based on a single node. The interconnection board is respectively communicatively connected to the FIT signal interfaces of the QSFP boards in multiple nodes; the FIT signal interfaces of multiple CPUs inside the main board are respectively communicatively connected to the FIT signal interfaces of the QSFP boards. The first CPLD inside the main board is communicatively connected to the first CPLDs inside other nodes through the second CPLD in the CPLD board, and is used for synchronously starting the timers of all CPUs inside the main board; the second CTM signal interfaces of the last CPUs inside the main boards in multiple nodes are sequentially communicatively connected to the first CTM signal interfaces of the first CPUs inside the main boards in the next node, so as to realize multi-channel CPU interconnection communication, effectively solving the problem that in the prior art, servers with more than 8 channels cannot be realized due to the number of CPUs in the main board, and can be applicable to various application scenarios with relatively high performance requirements.

Description

Technical Field

[0001] The present invention relates to the field of node servers, and in particular to a multi-channel server device based on a single node. Background Art

[0002] In recent years, the demand for servers has been growing. The functional requirements for servers have also become higher and higher. Under the condition that the CPU performance remains unchanged, multi-way servers are an effective way to improve server performance. Therefore, based on the traditional two-way servers, 4-way, 8-way and even more-way servers have appeared.

[0003] Feiteng is a leading domestic CPU manufacturer in China. Its main CPU: S2500 is also the most commonly used ARM architecture CPU in the information and innovation industry, but it is mostly used in 2-way and 4-way servers. Some manufacturers have achieved 8-way, but servers with higher numbers of ways have not been achieved.

[0004] The commonly used S2500 multi-way server currently places multiple CPUs on one motherboard. Although they can share one motherboard, due to the size limitation of the motherboard, more CPUs cannot be placed. At most, it can only develop a maximum of 8-way servers, and cannot develop more-way servers. This is not conducive to enhancing the system performance of the server and cannot be applied to a variety of application scenarios with high performance requirements. Summary of the invention

[0005] In order to solve the problems existing in the prior art, the present invention innovatively proposes a multi-way server device based on a single node, which effectively solves the problem that more than 8 servers cannot be realized due to the prior art, effectively enhances the system performance of the server, and can be applied to a variety of application scenarios with relatively high performance requirements.

[0006] The first aspect of the present invention provides a multi-way server device based on a single node, comprising: an interconnection board and multiple nodes, each node comprising a mainboard, a QSFP board and a CPLD board, the interconnection board is respectively communicated and connected with the FIT signal interface of the QSFP board in the multiple nodes, and is used to realize the aggregation of multi-way CPU computing power through direct interconnection between multiple processors; the mainboard comprises a CPU and a first CPLD, the CPLD board comprises a second CPLD, the FIT signal interfaces of the multiple CPUs inside the mainboard are respectively communicated and connected with the FIT signal interface of the QSFP board, the first CPLD inside the mainboard is communicated and connected with the first CPLD inside other nodes through the second CPLD in the CPLD board, and is used to synchronously start the timers of the CPUs inside all the mainboards; the second CTM signal interface of the last CPU inside the mainboard in the multiple nodes is communicated and connected with the first CTM signal interface of the first CPU inside the mainboard in the next node in sequence, and is used to realize the interconnection communication of the multiple CPUs.

[0007] Optionally, the QSFP board includes a first QSFP optical cage and a second QSFP optical cage. One end of the first QSFP optical cage is communicatively connected to the interconnection board, and the other end is communicatively connected to the FIT signal interfaces of some CPUs in the main board in the node where the QSFP board is located. One end of the second QSFP optical cage is communicatively connected to the interconnection board, and the other end is communicatively connected to the FIT signal interfaces of the remaining CPUs in the main board in the node where the QSFP board is located.

[0008] Further, the QSFP board further includes a first FIT signal connection status indicator module and a second FIT signal connection status indicator module. The first FIT signal connection status indicator module is disposed inside the first QSFP optical cage, and the second FIT signal connection status indicator module is disposed inside the second QSFP optical cage. Both the first FIT signal connection status indicator module and the second FIT signal connection status indicator module are communicatively connected to the main board in the node where the QSFP board is located.

[0009] Further, the main board in each node includes a baseboard management controller. The status reading ends of the baseboard management controller are communicatively connected to all CPUs inside the main board respectively, and the status output ends of the baseboard management controller are communicatively connected to the first FIT signal connection status indicator module and the second FIT signal connection status indicator module respectively.

[0010] Optionally, the node includes a main node and multiple slave nodes. After the first CPLD inside the main board in the slave node determines that all CPUs inside the main board in this node are ready, it sends a node ready signal to the second CPLD in the CPLD board of the main node through the second CPLD in the CPLD board of the slave node. After receiving the node ready signals of this node and all slave nodes, the second CPLD in the CPLD board of the main node sends node start signals to the first CPLDs inside the main boards of the main node and each slave node respectively. The first CPLDs in the main node and each slave node then send start commands respectively to ensure that the timers of all CPUs start synchronously.

[0011] Optionally, the first CTM signal interface of the first CPU inside the main board in the first node is grounded, and the second CTM signal interface of the last CPU inside the main board in the last node is grounded.

[0012] Optionally, the node includes a master node and multiple slave nodes. The CPLD board in the master node further includes a crystal oscillator and a clock chip. The crystal oscillator is used to provide a clock signal. The clock input terminal of the clock chip is communicatively connected to the clock output terminal of the crystal oscillator. One path of the clock output terminal of the clock chip in the CPLD board of the master node outputs to the CPU inside the main board in the master node, and the other path outputs to the CPLD boards of other slave nodes. The received clock signal is sent by the CPLD board of the slave node to the CPU inside the main board of this node.

[0013] Further, the CPLD board in the master node and the CPLD boards in the slave nodes both further include a switching chip. One path of the clock output terminal of the clock chip in the CPLD board of the master node outputs to the CPU inside the main board in the master node through the switching chip in the CPLD board of the master node, and the other path outputs to the switching chip in the CPLD boards of other slave nodes. The received clock signal is sent by the switching chip in the CPLD board of the slave node to the CPU inside the main board of this node; the first input terminal of the switching chip in the CPLD board of the slave node is communicatively connected to the clock output terminal of the clock chip in the CPLD board of the master node, and the output terminal of the switching chip in the CPLD board of the slave node is communicatively connected to the clock input terminal of the CPU of the main board in the slave node where the switching chip is located.

[0014] Further, the clock signals output by the clock chip in the CPLD board of the master node are all homologous clock signals.

[0015] Optionally, each CPLD board in the slave node further includes a crystal oscillator and a clock chip. The crystal oscillator is used to provide a clock signal. The clock input terminal of the clock chip is communicatively connected to the clock output terminal of the crystal oscillator. When the master node fails or is abnormal, any one of the slave nodes replaces the faulty or abnormal master node and becomes the new master node, which is used to make the clock sources of all CPUs in different nodes homologous.

[0016] The technical solution adopted by the present invention includes the following technical effects:

[0017] 1. In the technical solution of the present invention, the interconnection board is respectively communicatively connected to the FIT signal interfaces of the QSFP boards in multiple nodes, and is used to aggregate the computing capabilities of multiple CPUs through direct interconnection between multiple processors; the FIT signal interfaces of multiple CPUs inside the main board are respectively communicatively connected to the FIT signal interfaces of the QSFP board, and the first CPLD inside the main board is communicatively connected to the first CPLDs inside other nodes through the CPLD board, and is used to synchronously start the timers of all CPUs inside the main board; the second CTM signal interface of the last CPU inside the main board in multiple nodes is sequentially communicatively connected to the first CTM signal interface of the first CPU inside the main board in the next node, and is used to realize multi-way CPU interconnection communication, effectively solving the problem that servers with more than 8 channels cannot be realized due to the number of CPUs in the main board in the prior art, effectively enhancing the system performance of the server, and can be applied to various application scenarios with relatively high performance requirements.

[0018] 2. In the technical solution of the present invention, the QSFP board further includes a first FIT signal connection status indicator module and a second FIT signal connection status indicator module, which can visually determine the FIT signal connection status in the main board where it is located.

[0019] 3. In the technical solution of the present invention, after the CPLD board of the main node receives the node preparation completion signals of this node and all slave nodes, it respectively sends node start signals to the first CPLDs inside the main board of the main node and each slave node, and the first CPLDs of the main board in the main node and each slave node then respectively send start commands, ensuring that the timers of all CPUs are synchronously started.

[0020] 4. In the technical solution of the present invention, the CPLD board in the main node further includes a crystal oscillator and a clock chip. One path of the clock output of the clock chip in the CPLD board of the main node is output to the CPU inside the main board in the main node, and the other path is output to the CPLD boards of other slave nodes. The CPLD boards of the slave nodes send the received clock signals to the CPUs inside the main boards of their own nodes, ensuring the synchronization of the clock signals of the CPUs in all nodes.

[0021] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, for those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0023] Figure 1Schematic diagram of the structure of a single node in the device of Embodiment 1 in the solution of the present invention;

[0024] Figure 2 Schematic diagram of the communication between four nodes and the interconnection board in the device of Embodiment 1 in the solution of the present invention;

[0025] Figure 3 Schematic diagram of the CPU startup timing in the device of Embodiment 1 in the solution of the present invention;

[0026] Figure 4 Schematic diagram of the CTM signal interconnection between CPLD boards among four nodes in the device of Embodiment 1 in the solution of the present invention;

[0027] Figure 5 Schematic diagram of the CTM signal interconnection between CPUs inside the main board among four nodes in the device of Embodiment 1 in the solution of the present invention. Detailed implementation manners

[0028] To clearly illustrate the technical features of this solution, the present invention will be elaborated in detail below through specific implementation manners and in conjunction with its accompanying drawings. The following disclosure provides many different embodiments or examples for implementing different structures of the present invention. To simplify the disclosure of the present invention, the components and settings of specific examples are described below. In addition, the present invention may repeat reference numerals and / or letters in different examples. This repetition is for the purpose of simplification and clarity, and does not itself indicate the relationship between the various embodiments and / or settings discussed. It should be noted that the components illustrated in the drawings are not necessarily drawn to scale. The present invention omits the description of well-known components and processing technologies and processes to avoid unnecessarily limiting the present invention.

[0029] Embodiment 1

[0030] As Figure 1 - Figure 2As shown in the figure, to describe the embodiments of the present invention more clearly, a 16-way server is taken as an example for illustration, but it is not limited to 16-way servers. The present invention provides a multi-way server device based on a single node, including: an interconnect board (NCboard) and four nodes (NODE0-NODE3). Each node includes a main board (MB), a QSFP board (two QSFP_Risers, that is, QSFP optical mouse cages), and a CPLD board (CPLD_Riser card). The interconnect board is respectively communicatively connected to the FIT signal interfaces of the QSFP boards in multiple nodes, and is used to achieve the aggregation of multi-way CPU computing capabilities through direct interconnection between multiple processors; the main board includes a CPU and a first CPLD, the CPLD board includes a second CPLD, the FIT signal interfaces of multiple CPUs inside the main board are respectively communicatively connected to the FIT signal interfaces of the QSFP board, and the first CPLD inside the main board is communicatively connected to the first CPLDs inside other nodes through the second CPLD in the CPLD board, and is used to synchronously start the timers of all CPUs inside the main board (TIMER_FORCE-START); the second CTM signal interface (PANEL6) of the last CPU inside the main board in multiple nodes is sequentially communicatively connected to the first CTM signal interface (PANEL4) of the first CPU inside the main board in the next node, and is used to achieve multi-way CPU interconnection communication.

[0031] Among them, the core of the multi-way server design is the interconnection between multiple CPUs. The main difficulties in the Feiteng S2500 interconnection are the processing of the following signals: FIT signal, synchronization signal, CTM signal, and clock signal.

[0032] Among them, the FIT signal is Fast Interconnect Transport, that is, a fast interconnection transport interface, a direct connection interface customized by Feiteng between processor chips. Each path contains 4 Lanes (channels), and the single Lane rate is 25 Gbps; the synchronization signal is a signal to ensure that the timers of multiple CPUs can start simultaneously; the CTM signal is a multi-way CPU interconnection communication signal, and the purpose is to wake up the slave core; the clock signal is the clock signal required for the normal operation of the CPU.

[0033] The whole system is divided into two parts. The first part consists of 4 nodes, including a main board, a QSFP board, and a CPLD board. The main board is the center of the node operation, including resources such as a CPU, memory, and expansion slots. The QSFP board is responsible for leading out the FIT signal, and the CPLD board is responsible for processing the CTM signal, synchronization signal, and clock signal. The second part is the interconnection board, whose function is to access the FIT signals of 16 CPUs, implement protocol message processing and high-speed switching between multiple processors, support shared access to all system resources, maintain cache coherence, implement a tightly coupled shared memory multi-processor system structure, and aggregate the computing power of multiple CPUs through high-speed interconnection between processors.

[0034] FIT signal

[0035] Specifically, the FIT signal is the direct interconnection signal of the CPU. In normal dual-way and four-way main boards, the CPUs are directly interconnected within the board. However, in a 16-way device, direct interconnection between CPUs cannot be achieved, and the FIT must be connected to a dedicated interconnection board to complete data processing between multiple CPUs.

[0036] The specific implementation solution is as follows: Lead out the FIT signal of the CPU on each node main board and connect it to the QSFP board. Each QSFP board includes 2 QSFP optical mouse cages (the first QSFP optical mouse cage and the second QSFP optical mouse cage, and the optical mouse cage is the optical module mouse cage), and then transmit the FIT signal to the interconnection board through the optical modules and optical fibers in the QSFP optical mouse cages for processing.

[0037] The QSFP board includes the first QSFP optical mouse cage (QSFP_Riser card, that is, QSFP0, used to connect CPU0 and CPU1 inside the main board as shown in Figure 1 ), and the second QSFP optical mouse cage (QSFP_Riser card, that is, QSFP1, used to connect CPU2 and CPU3 inside the main board as shown in Figure 1 and can be adjusted flexibly). One end of the first QSFP optical mouse cage is communicatively connected to the interconnection board, and the other end is communicatively connected to the FIT signal interfaces of some CPUs (such as CPU0 and CPU1 inside the main board as shown in Figure 1 ) in the main board of the node where the QSFP board is located; One end of the second QSFP optical mouse cage is communicatively connected to the interconnection board, and the other end is communicatively connected to the FIT signal interfaces of the remaining CPUs (such as CPU2 and CPU3 inside the main board as shown in Figure 1 ) in the main board of the node where the QSFP board is located.

[0038] Specifically, the QSFP board also includes the first FIT signal connection status indicator module (such as Figure 1The first FIT signal connection status indicator module (LED0 / 1 as shown in the figure) and the second FIT signal connection status indicator module (LED2 / 3 as shown in Figure 1). The first FIT signal connection status indicator module is arranged inside the first QSFP optical cage (QSFP0), and the second FIT signal connection status indicator is arranged inside the second QSFP optical cage (QSFP1). Both the first FIT signal connection status indicator module and the second FIT signal connection status indicator module are respectively communicatively connected to the main board in the node where the QSFP board is located.

[0039] The main board in each node includes a baseboard management controller (BMC). The status reading ends of the baseboard management controller are respectively communicatively connected to all CPUs inside the main board, read the corresponding registers of the CPUs, and determine the Link status of the FIT signal in each CPU. The status output ends of the baseboard management controller are respectively communicatively connected to the first FIT signal connection status indicator module and the second FIT signal connection status indicator module, and are used to drive the FIT signal connection status indicator signals in the corresponding first FIT signal connection status indicator module and the second FIT signal connection status indicator module. Correspondingly, the first FIT signal connection status indicator module is used to indicate the FIT signal connection status of CPU0 and CPU1 in the main board, and the second FIT signal connection status indicator module is used to indicate the FIT signal connection status of CPU02 and CPU3 in the main board.

[0040] Synchronization signal

[0041] As Figure 3 - Figure 4 shown, in order to ensure that the timers of 16 CPUs can start timing simultaneously, it is necessary to send start signals to all CPUs at the same time. The specific implementation scheme is that the first CPLD of the 4-node main board sends a Node_Ready signal to the second CPLD in the CPLD board of Node0 (the main node) after determining that the CPU of this node is ready. After receiving the Node_Ready signals of this node and the other 3 nodes (Node1, Node2, Node3), the second CPLD in the CPLD board of Node0 sends a Node_Start signal to the first CPLD of the main board of each node. The first CPLD of the main board then sends a start command to ensure that the timers of 16 CPUs can start simultaneously. The timing is as Figure 3 shown:

[0042] The nodes include a master node (Node0) and multiple slave nodes (Node1, Node2, Node3). After the first CPLD inside the main board of a slave node determines that all CPUs inside the main board of this node are ready, it sends a node ready signal Node_Ready to the second CPLD in the CPLD board of the master node through the second CPLD in the CPLD board of the slave node. After receiving the node ready signals of this node and all slave nodes, the second CPLD in the CPLD board of the master node respectively sends node start signals to the first CPLD inside the main boards of the master node and each slave node. The first CPLDs of the main boards in the master node and each slave node then respectively send start commands Node_Start to ensure that the timers of all CPUs are started synchronously. The mutual communication between the CPLD boards in different nodes is realized through a connector located on the CPLD board.

[0043] CTM signal

[0044] The second CTM signal interface of the last CPU inside the main board in multiple nodes is sequentially communicatively connected to the first CTM signal interface of the first CPU inside the main board in the next node, for realizing multi-channel CPU interconnection communication. The first CTM signal interface of the first CPU inside the main board in the first node is grounded, and the second CTM signal interface of the last CPU inside the main board in the last node is grounded.

[0045] Specifically, each CPU of S2500 has two groups of CTM signals, namely PANEL4 (the first CTM signal interface) and PANLE6 (the second CTM signal interface). When Phytium requires multi-CPU interconnection, the PANEL6 of the previous CPU is connected to the PANEL4 of the next CPU, and the PANEL4 of the first CPU and the PANEL6 of the last CPU need to be grounded. Each node includes 4 CPUs, namely CPU0 - CPU3. In the main board, the PANEL4 of CPU0 and the PANEL6 of CPU3 need to be grounded, but for a system with 16 CPUs interconnected.

[0046] Such as Figure 5 As shown, the first CTM signal interface PANEL4 of the first CPU (CPU0) inside the main board in each node needs to be connected to the PANEL6 of the second CTM signal interface of the last CPU (CPU3) inside the main board in the previous node (connected through the CPLD board in the node). The PANEL4 of the first CPU (CPU0) inside the main board in the first node (Node0) and the PANEL6 of the last (CPU3) inside the main board in the last node (Node3) need to be grounded.

[0047] Connect the first CTM signal interface PANEL4 of the first CPU (CPU0) inside the main board and the second CTM signal interface PANEL6 of the last CPU (CPU3) in each node to the double-row pin header and the connector on the CPLD board respectively. For those that need to be interconnected, use cables for interconnection, and for those that need to be grounded, use a shorting block for grounding to meet the requirements of different nodes.

[0048] Clock signal

[0049] The node includes a master node (Node0) and multiple slave nodes (Node1, Node2, Node3). The CPLD board in the master node (Node0) also includes a crystal oscillator (Crystal) and a clock chip (ClockBuffer chip). The crystal oscillator is used to provide a clock signal. The clock input terminal of the clock chip is communicatively connected to the clock output terminal of the crystal oscillator. One path of the clock output terminal of the clock chip in the CPLD board of the master node outputs to the CPU inside the main board in the master node, and the other path outputs to the CPLD boards of other slave nodes. The CPLD board of the slave node sends the received clock signal to the CPU inside the main board of this node.

[0050] Both the CPLD board in the master node and the CPLD boards in the slave nodes also include switching chips. One path of the clock output terminal of the clock chip in the CPLD board of the master node outputs to the CPU inside the main board in the master node through the switching chip in the CPLD board of the master node, and the other path outputs to the switching chips in the CPLD boards of other slave nodes. The switching chips in the CPLD boards of the slave nodes send the received clock signal to the CPU inside the main board of this node; the first input terminal of the switching chip in the CPLD board of the slave node is communicatively connected to the clock output terminal of the clock chip in the CPLD board of the master node, and the output terminal of the switching chip in the CPLD board of the slave node is communicatively connected to the clock input terminal of the main board CPU in the slave node where the switching chip is located.

[0051] To ensure that the clock sources of the 16 CPUs are of the same origin, the ClockBuffer chip in the CPLD board of Node0 can output 4 paths of 50M clock signals of the same origin. Then, the clock signal of Node0 is sent to the Node0 main board through the connector on the CPLD board and sent to the switching chips on the CPLD boards of other nodes through the connector on the CPLD board. The switching chips on the CPLD boards of the slave nodes send the clock signal to the CPU inside the main board of the corresponding slave node. The mutual communication between the CPLD boards in different nodes is realized through the connectors (connectors) located on the CPLD board.

[0052] Preferably, the CPLD boards in the slave nodes (Node1, Node2, Node3) may also include a crystal oscillator (Crystal) and a clock chip (Clock Buffer chip). The crystal oscillator is used to provide a clock signal, and the clock input terminal of the clock chip is communicatively connected to the clock output terminal of the crystal oscillator. When the master node (Node1) fails or malfunctions, each slave node can replace the faulty or abnormal master node and become the new master node (after the slave node replaces the master node and becomes the new master node, the CPLD board in the new master node is responsible for processing the CTM signals, synchronization signals, and clock signals of other slave nodes), thus ensuring communication between different nodes in the multi-channel server, achieving the same clock source for all CPUs in different nodes, and improving the reliability of communication and signal synchronization such as clock among different nodes in the multi-channel server.

[0053] Further, the first input terminal of the switching chip in the CPLD board of the master node is communicatively connected to the clock output terminal of the clock chip in the CPLD board of other slave nodes through a connector located in the CPLD board (not conducting when the master node is normal). The second input terminal of the switching chip in the CPLD board of the master node is communicatively connected to the clock output terminal of the clock chip in the CPLD board of the master node. The output terminal of the switching chip in the CPLD board of the master node is communicatively connected to the clock input terminal of the CPU in the main board of the master node (conducting when the master node is normal). The switching control terminal of the switching chip in the CPLD board of the master node is communicatively connected to the control output terminal of the second CPLD in the CPLD board of the master node.

[0054] The first input terminal of the switching chip in the CPLD board of the slave node is communicatively connected to the clock output terminal of the clock chip in the CPLD board of the master node through a connector located in the CPLD board (conducting when the master node is normal). The second input terminal of the switching chip in the CPLD board of the slave node is communicatively connected to the clock output terminal of the clock chip in the CPLD board of the master node (not conducting when the master node is normal). The output terminal of the switching chip in the CPLD board of the slave node is communicatively connected to the clock input terminal of the CPU in the main board of the slave node. The switching control terminal of the switching chip in the CPLD board of the slave node is communicatively connected to the control output terminal of the second CPLD in the CPLD board of the slave node.

[0055] In the technical solution of the present invention, the interconnection board is respectively communicatively connected to the FIT signal interfaces of the QSFP boards in multiple nodes, and is used to aggregate the computing capabilities of multiple CPUs through direct interconnection between multiple processors; the FIT signal interfaces of multiple CPUs inside the main board are respectively communicatively connected to the FIT signal interfaces of the QSFP boards, and the CPLD inside the main board is communicatively connected to the CPLDs inside other nodes through the CPLD board, and is used to synchronously start the timers of all CPUs inside the main board; the second CTM signal interfaces of the last CPUs inside the main boards in multiple nodes are sequentially communicatively connected to the first CTM signal interfaces of the first CPUs inside the main boards in the next node, and are used to realize multi-way CPU interconnection communication, effectively solving the problem that servers with more than 8 channels cannot be realized due to the number of CPUs in the main board in the prior art, effectively enhancing the system performance of the server, and can be applicable to various application scenarios with relatively high performance requirements.

[0056] In the technical solution of the present invention, the QSFP board further includes a first FIT signal connection status indicator light and a second FIT signal connection status indicator light, which can visually determine the FIT signal connection status in the corresponding main board.

[0057] In the technical solution of the present invention, after the CPLD board of the master node receives the node ready completion signals of the present node and all slave nodes, it respectively sends node start signals to the CPLDs inside the main boards of the master node and each slave node, and the main board CPLDs in the master node and each slave node then respectively send start commands, ensuring the synchronous start of the timers of all CPUs.

[0058] In the technical solution of the present invention, the CPLD board in the master node further includes a crystal oscillator and a clock chip. One path of the clock output of the clock chip in the CPLD board of the master node is output to the CPU inside the main board in the master node, and the other path is output to the CPLD boards in other slave nodes. The CPLD board of the slave node sends the received clock signal to the CPU inside the main board in the present node, ensuring the synchronization of the clock signals of the CPUs in all nodes.

[0059] Although the specific implementation manners of the present invention are described above in conjunction with the drawings, it is not a limitation to the protection scope of the present invention. Those skilled in the art should understand that based on the technical solution of the present invention, various modifications or deformations that can be made by those skilled in the art without creative efforts are still within the protection scope of the present invention.

Claims

1. A multi-channel server device based on a single node, characterized in that, Including: An interconnection board and multiple nodes. Each node includes a main board, a QSFP board, and a CPLD board. The interconnection board is respectively communicatively connected to the FIT signal interfaces of the QSFP boards in multiple nodes, and is used to achieve the aggregation of multi-CPU computing capabilities through direct interconnection between multiple processors. The main board includes a CPU and a first CPLD. The CPLD board includes a second CPLD. The FIT signal interfaces of multiple CPUs inside the main board are respectively communicatively connected to the FIT signal interfaces of the QSFP board. The first CPLD inside the main board is communicatively connected to the first CPLDs inside other nodes through the second CPLD in the CPLD board, and is used to synchronously start the timers of all CPUs inside the main board. The second CTM signal interface of the last CPU inside the main board in multiple nodes is sequentially communicatively connected to the first CTM signal interface of the first CPU inside the main board in the next node, and is used to achieve multi-CPU interconnection communication. The QSFP board includes a first QSFP optical cage and a second QSFP optical cage. One end of the first QSFP optical cage is communicatively connected to the interconnection board, and the other end is communicatively connected to the FIT signal interfaces of some CPUs in the main board of the node where the QSFP board is located. One end of the second QSFP optical cage is communicatively connected to the interconnection board, and the other end is communicatively connected to the FIT signal interfaces of the remaining CPUs in the main board of the node where the QSFP board is located.

2. The multi-channel server device based on a single node according to claim 1, characterized in that, The QSFP board further includes a first FIT signal connection status indicator module and a second FIT signal connection status indicator module. The first FIT signal connection status indicator module is arranged inside the first QSFP optical cage, and the second FIT signal connection status indicator module is arranged inside the second QSFP optical cage. Both the first FIT signal connection status indicator module and the second FIT signal connection status indicator module are respectively communicatively connected to the main board of the node where the QSFP board is located.

3. The multi-channel server device based on a single node according to claim 2, characterized in that, The main board in each node includes a baseboard management controller. The status reading ends of the baseboard management controller are respectively communicatively connected to all CPUs inside the main board, and the status output ends of the baseboard management controller are respectively communicatively connected to the first FIT signal connection status indicator module and the second FIT signal connection status indicator module.

4. The multi-channel server device based on a single node according to claim 1, characterized in that, The node includes a main node and multiple slave nodes. After the first CPLD inside the main board in the slave node determines that all CPUs inside the main board in this node are ready, it sends a node ready signal to the second CPLD in the CPLD board of the main node through the second CPLD in the CPLD board of the slave node. After receiving the node ready signals of this node and all slave nodes, the second CPLD in the CPLD board of the main node respectively sends node start signals to the first CPLDs inside the main board of the main node and each slave node. The first CPLDs in the main node and each slave node then respectively send start commands to ensure that the timers of all CPUs are synchronously started.

5. The multi-channel server device based on a single node according to claim 1, characterized in that, The first CTM signal interface of the first CPU inside the main board in the first node is grounded, and the second CTM signal interface of the last CPU inside the main board in the last node is grounded.

6. The multi-channel server device based on a single node according to claim 1, characterized in that The node includes a main node and multiple slave nodes. The CPLD board in the main node further includes a crystal oscillator and a clock chip. The crystal oscillator is used to provide a clock signal. The clock input terminal of the clock chip is communicatively connected to the clock output terminal of the crystal oscillator. One path of the clock output terminal of the clock chip in the CPLD board of the main node outputs to the CPU inside the main board in the main node, and the other path outputs to the CPLD boards of other slave nodes. The received clock signal is sent by the CPLD board of the slave node to the CPU inside the main board of this node.

7. The multi-channel server device based on a single node according to claim 6, characterized in that, Both the CPLD board in the main node and the CPLD boards in the slave nodes further include switching chips. One path of the clock output terminal of the clock chip in the CPLD board of the main node outputs to the CPU inside the main board in the main node through the switching chip in the CPLD board of the main node, and the other path outputs to the switching chips in the CPLD boards of other slave nodes. The received clock signal is sent by the switching chip in the CPLD board of the slave node to the CPU inside the main board of this node. The first input terminal of the switching chip in the CPLD board of the slave node is communicatively connected to the clock output terminal of the clock chip in the CPLD board of the main node, and the output terminal of the switching chip in the CPLD board of the slave node is communicatively connected to the clock input terminal of the main board CPU in the slave node where the switching chip is located.

8. The multi-channel server device based on a single node according to claim 7, characterized in that, The clock signals output by the clock chip in the CPLD board of the main node are all homologous clock signals.

9. The multi-channel server device based on a single node according to claim 7, characterized in that, Each CPLD board in the slave node further includes a crystal oscillator and a clock chip. The crystal oscillator is used to provide a clock signal. The clock input terminal of the clock chip is communicatively connected to the clock output terminal of the crystal oscillator. When the main node fails or is abnormal, any one of the slave nodes replaces the faulty or abnormal main node and becomes the new main node, which is used to make the clock sources of all CPUs in different nodes homologous.

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