Semiconductor device and method of operating the same

Abstract

A semiconductor device and an operating method thereof are provided, including a physically unclonable function unit array. The physically unclonable function unit array includes a plurality of bit cells and generates a physically unclonable function response output in response to a challenge input and based on a data state of one of the plurality of bit cells. Each of the bit cells stores a bit of data and includes a transistor having a control terminal coupled to a word line and a first terminal coupled to a source line, a first memory cell having a first terminal coupled to a first data line and a second terminal coupled to a second terminal of the transistor, and a second memory cell having a first terminal coupled to a second data line different from the first data line and a second terminal coupled to the second terminal of the transistor and the second terminal of the first memory cell.

Description

TECHNICAL FIELD

[0001] One embodiment of the present disclosure relates to a semiconductor device, and more particularly, to a semiconductor device having a physically unclonable function unit. BACKGROUND

[0002] As the use of electronic devices utilizing integrated circuits to provide different forms of information for various applications increases, the need for protecting sensitive and / or important information stored in the electronic devices by allowing only authorized devices to access the data also increases. As manufacturing variations and / or misalignment tolerances occurring in semiconductor production processes can cause integrated circuits produced by the semiconductor production processes to differ from one another, a physically unclonable function (PUF) uses such physical uniqueness to distinguish the integrated circuits from one another. A PUF represents a challenge-response mechanism that maps a challenge and its corresponding response based on complex and variable natural phenomena of the physical materials used to produce the integrated circuits. SUMMARY

[0003] One embodiment of the present disclosure provides a semiconductor device. The device includes a physically unclonable function (PUF) unit array, the PUF unit array including a plurality of bitcell units and generating a physically unclonable function response output in response to a challenge input and based on a data state of one of the bitcell units. Each of the bitcell units stores a bit of data and includes a transistor, a first memory cell, and a second memory cell. The transistor has a control terminal coupled to a wordline and a first terminal coupled to a source line. The first memory cell has a first terminal coupled to a first data line and a second terminal coupled to the second terminal of the transistor. The second memory cell has a first terminal coupled to a second data line, the second data line being different from the first data line, and a second terminal, the second terminal of the second memory cell being coupled to the second terminal of the transistor and the second terminal of the first memory cell.

[0004] One embodiment of the present application provides a semiconductor operation method and includes the following operations: receiving a challenge input by a physically unclonable function generator; accessing a first bitcell in a physically unclonable function cell array in response to a wordline address associated with the challenge input, wherein the first bitcell is accessed; and outputting, by the physically unclonable function generator, a physically unclonable function response output according to an output signal, the physically unclonable function response output having a high logic state when a first voltage is greater than a second voltage, or the physically unclonable function response output having a low logic state when the first voltage is less than the second voltage. Accessing the first bitcell includes comparing, by a sense amplifier, the first voltage and the second voltage to generate the output signal in a read operation, the first voltage being at a first terminal of a first memory cell in the first bitcell, the first voltage being at a first terminal of a second memory cell in the first bitcell, a second terminal of the first memory cell and a second terminal of the second memory cell being coupled to each other to receive a read voltage.

[0005] One embodiment of the present application provides a semiconductor device including a sense amplifier and a first bitcell in a physically unclonable function cell array. The first bitcell stores first bit data associated with a first challenge input. The first bitcell has a first terminal coupled to a first terminal of the sense amplifier, a second terminal coupled to a second terminal of the sense amplifier different from the first terminal, and a third terminal coupled to a source line. In response to a read operation of the first bitcell performed in response to an activation operation of a word source line coupled to the first bitcell, the sense amplifier compares a first voltage at the first terminal of the first bitcell and a second voltage at the second terminal of the first bitcell to generate an output signal as a physically unclonable function response output, the output signal representing a first data state of the first bit data. BRIEF DESCRIPTION OF DRAWINGS

[0006] The aspects of the present application will best be understood from the following detailed description when read with reference to the accompanying drawings. It is noted that, in accordance with the standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features can be arbitrarily increased or decreased for the sake of discussion.

[0007] Figure 1 is one schematic diagram of a physically unclonable function (PUF) generator according to some embodiments;

[0008] Figure 2 is one schematic diagram of a portion of the PUF generator according to some embodiments and corresponding to Figure 1

[0009] Figure 3 is one schematic diagram of a portion of the PUF generator according to some embodiments and corresponding to​Figures 1-2 One schematic diagram of the portion of the PUF generator in the Enrollment operation;

[0010] Figures 4A-4B is a schematic diagram of the magnetic tunnel junction memory of the PUF generator corresponding to Figures 1-2

[0011] Figure 5 is a schematic diagram of the portion of the PUF generator in the Extraction operation corresponding to Figures 1-2

[0012] Figure 6 is a schematic diagram of the waveforms of the signals in the PUF generator corresponding to Figure 5

[0013] Figure 7 is a layout diagram of the portion of the PUF generator in a planar perspective corresponding to Figures 1-5

[0014] Figure 8 is a flowchart of the operation of the PUF generator corresponding to Figures 1-7

[0015] Figure 9 is a block diagram of a system for designing an integrated circuit layout design according to some embodiments of the present application;

[0016] Figure 10 is a block diagram of an integrated circuit manufacturing system and an integrated circuit manufacturing flow associated therewith according to some embodiments.

[0017]

Symbol Explanation

[0018] 100: Physical unclonable function generator

[0019] 101: Challenge input

[0020] 102: Response output

[0021] 110: Array of physical unclonable function cells

[0022] 120: Row decoder

[0023] 130: Column decoder

[0024] 140: Sense amplification circuit

[0025] 150: Input / output circuit

[0026] 160: Physical unclonable function control circuit​​​​​

[0027] 141: sense amplifier

[0028] BC: bit cell

[0029] BL11-BL1n, BL21-BL2n: data line

[0030] WL1-WLm: word line

[0031] SL: source line

[0032] V SL : source line voltage

[0033] 310, 320: memory cell

[0034] I L, I R : current

[0035] n1, n2: terminal

[0036] Tr: transistor

[0037] I W : write current

[0038] C1, C2: capacitor

[0039] 311, 321: free layer

[0040] 312, 322: fixed layer

[0041] 313, 323: dielectric layer

[0042] OUT: output signal

[0043] VDD, V READ , V1, V2: voltage

[0044] T0, T1: time

[0045] 700: bit cell

[0046] 711-713 gate

[0047] 721-722: active region

[0048] 731-732: on-device metal

[0049] 741: wire

[0050] 751: conductive line

[0051] 761-762: metal line

[0052] VD1-VD3, VM1: via

[0053] FN: fin structure

[0054] CPP: crystal poly silicon pitch

[0055] 800: method

[0056] 810, 820, 830, 1640: operations

[0057] 900: EDA system

[0058] 902: processor, hardware processor

[0059] 904: storage media, non-transitory computer readable storage media

[0060] 906: computer program code (instructions)

[0061] 908: bus

[0062] 910: I / O interface

[0063] 912: network interface

[0064] 914: network

[0065] 916: manufacturing tool

[0066] 920: IC layout

[0067] 922: design specification

[0068] 1000: IC manufacturing system

[0069] 1020: design room

[0070] 1022: IC design layout

[0071] 1030: mask room

[0072] 1032: data preparation

[0073] 1044: mask manufacturing

[0074] 1045: mask (reticle)

[0075] 1050: IC wafer fab

[0076] 1052: wafer manufacturing

[0077] 1053: (semiconductor) wafer

[0078] 1060: IC element DETAILED DESCRIPTION

[0079] The following disclosure provides many different embodiments, or examples, for implementing various characteristics of the provided subject matter. Specific examples of elements and arrangements are described in order to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, forming a first feature over or on a second feature can include embodiments in which the first and second features are formed directly on each other, and can also include embodiments in which additional features are formed between the first and second features such that the first and second features can not be directly contacting. Additionally, the present disclosure can repeat use of certain elements or names throughout the description in a similar way as in the following examples, which can make the description seem repetitive. This repetition is done for the sake of simplicity and clarity and is not intended to cause confusion.

[0080] The terminology used in this description is generally intended for the purposes of describing particular embodiments and is not intended to limit the scope of the present disclosure. Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The examples given are intended to be illustrative and not restrictive. The description is not intended to limit any embodiments to the forms disclosed herein. Many modifications and variations will be apparent to those of ordinary skill in the art, and the scope of the present disclosure is not limited to the specific embodiments described herein.

[0081] As used herein, the terms "comprises," "comprising," "includes," "including," "has," "having," and the like are to be construed as being open-ended (i.e., to mean including but not limited to) unless specifically indicated to the contrary.

[0082] Reference throughout this specification to "an embodiment" or "some embodiments" means that a described feature, structure, implementation, or characteristic is included in at least one embodiment. Thus, the appearances of the phrases "in one embodiment" or "in some embodiments" in various places throughout this specification are not necessarily referring to the same embodiment. Furthermore, the particular features, structures, implementations, or characteristics can be combined in any suitable manner in one or more embodiments.

[0083] Furthermore, spatial or directional terms, such as "below," "above," "left," "right," "up," "down," "top," "bottom," and the like, can be used herein for ease of describing the illustrated examples in the drawings. The spatial and directional terms should not be interpreted strictly except in the context in which they are used in the description. The device can be oriented in other ways (rotated at 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0084] As used herein, “approximately,” “about,” “approximately,” or “substantially” should generally refer to any approximation of a given value or range, which varies depending on the various fields involved, and its scope should be consistent with the broadest interpretation understood by those skilled in the art to cover all such modifications and similar structures. In some embodiments, it should generally refer to within twenty percent of a given value or range, preferably within ten percent, and more preferably within five percent. The numerical values ​​given herein are approximate, meaning that unless explicitly stated otherwise, the terms “approximately,” “about,” “approximately,” or “substantially” can be inferred to mean other approximations.

[0085] A physically unclonable function (PUF) generator is typically a physical structure within an integrated circuit that provides several corresponding PUF response outputs in response to a challenge signal input to the PUF generator. The unique characteristics of the integrated circuit are established by such challenge-response pairs provided by the PUF generator. In some embodiments, a PUF generator, referred to as a weak PUF, generates PUF response outputs based on bits stored in the PUF generator, which are further associated with all elements in the corresponding challenge input. Therefore, such a PUF generator provides greater resistance to machine learning attacks compared to a strong PUF generator, which generates PUF response outputs based on one bit of metadata stored in all bits of the PUF generator, and this bit metadata is associated with only one element in the challenge input. In some embodiments, the PUF cell array comprises bits with one transistor and two magnetic tunnel junction (MTJ) memory cells, where MTJ toggling is not required to generate the PUF response output. By comparing the voltage levels of the data lines coupled to the two MTJ memory cells and a small read current, the data status of the corresponding bit cell is determined and output as a PUF response.

[0086] For reference Figure 1 . Figure 1 This is a schematic diagram of a Physically Unforgeable Function (PUF) generator 100 according to some embodiments. Figure 1 In the illustrated embodiment, the PUF generator 100 includes a PUF cell array 110, a row decoder 120, and a column decoder 130. The row decoder 120 and column decoder 130 are coupled to several bit cells BC in the PUF cell array 110 (further shown in...). Figure 2). In the illustrated embodiment, the PUF generator 100 also includes a sense amplification circuit 140, an input / output (I / O) circuit 150, and a PUF control circuit 160. In some embodiments, all of the components are coupled to each other and further coupled to the PUF control circuit 160. In some embodiments, the I / O circuit 150 is directly coupled to the PUF control circuit 160. In some embodiments, the PUF control circuit 160 is implemented in a separate block that is not embedded in the PUF cell array 110. In some alternative embodiments, the PUF control circuit 160 is embedded in the PUF cell array 110.

[0087] The PUF cell array 110 is to generate a PUF response output 102 in response to a challenge input 101 and based on a data state of a bit cell of a plurality of bit cells BC in the PUF cell array 110 when the PUF control circuit 160 receives a request (e.g., a challenge input corresponding to accessing a PUF signature of the PUF cell array 110, etc.) through the I / O circuit 150. Further, the PUF control circuit 160 is to transmit the PUF response output 102 through the I / O circuit 150. In some embodiments, the PUF control circuit 160 is further to receive a request (e.g., a request for power to the coupled PUF cell array 110) through the I / O circuit 150.

[0088] In some embodiments, the PUF control circuit 160 is to control (e.g., increase or decrease) a voltage level of a supply voltage applied to each of the bit cells BC, control (e.g., increase or decrease) a voltage level applied to each word line coupled to the row decoder 120, as discussed in more detail below. In some embodiments, the PUF control circuit 160 is to enable a voltage supply to at least one selected column and at least one selected row in response to the challenge input.

[0089] Figure 1 The configurations are provided for illustrative purposes. Different implementations are also within the scope of the present disclosure. For example, in some embodiments, the PUF generator 100 also includes a time control circuit that controls and synchronizes pulse signals when reading (fetching) and / or writing (registering) operations.

[0090] Reference is now made to Figure 2 corresponding to Figure 1 , Figure 2is part of the PUF generator 100. For illustration, the PUF cell array 110 includes bit cells BC arranged in a configuration of rows and columns. Each of the n columns has one of the first data lines BL1 1 -BL1 n and one of the second data lines BL2 1 -BL2 n, and each of the m rows has one of the word lines WL1 -WLm. More specifically, the first data line and the second data line of each column are coupled to the bit cells BC disposed in that column, respectively, and each bit cell on the column is disposed in a different row and coupled to an individual (different) word line. In other words, each bit cell BC of the PUF cell array 110 has one terminal coupled to a first data line of one column of the PUF cell array 110, another terminal coupled to a second data line of the column of the PUF cell array 110, and yet another terminal coupled to a word line of one row of the PUF cell array 110. In some embodiments, the first data lines BL1 1 -BL1 n and the second data lines BL2 1 -BL2 n are arranged in parallel in a vertical direction, and the word lines WL1 -WLm are arranged in parallel in a horizontal direction (i.e., perpendicular to the first and second data lines BL1 1 -BL1 n, BL2 1 -BL2 n). In some embodiments, the bit cells BC of each row in the PUF cell array 110 are connected to each other by the word line for that row, as shown in Figure 2

[0091] Further, as shown in Figure 2 each bit cell BC also has a terminal coupled to a source line SL, and a voltage V SL is applied on the source line SL. In some embodiments, the voltage V SL is different in the enrollment operation and the retrieval operation of the PUF cell array. In some embodiments, the source lines are arranged in parallel in a horizontal direction (in other words, perpendicular to the first and second data lines BL1 1 -BL1 n, BL2 1 -BL2 n) and parallel to the word lines WL1 -WLm.

[0092] The row decoder 120 is configured to receive a row address of the PUF cell array 110 from the PUF control circuit 160 and apply a word line voltage to activate a corresponding word line accordingly. The column decoder 130 is configured to receive a column address of the PUF cell array 110 from the PUF control circuit 160 and apply voltages to corresponding first and second data lines accordingly. In some embodiments, the row address and the column address correspond to a word address related to a challenge input received by the PUF generator 100. Through the cooperation of the row decoder 120 and the column decoder 130, a bit cell BC in the PUF cell array 110 is selected for access.

[0093] In some embodiments, each bit cell BC has two terminals coupled to two terminals of a sense amplifier arranged in the same column, respectively. The sense amplifier 141 in each column is included in the PUF cell array 110.​Figure 1 The sensing amplifier circuit 140 is used to compare the voltage levels of the first data line and the second data line in the same column to generate an output signal as a PUF response output 102. In some embodiments, the output signal represents the data state of the selected bit cell BC.

[0094] Figure 2 The configuration provided is for illustrative purposes. Different implementation methods are also within the scope of this case.

[0095] For reference Figure 3 . Figure 3 This corresponds to some implementation examples. Figures 1-2 A schematic diagram of a portion of the PUF generator 100 during the registration operation. (See diagram below.) Figure 3 As shown in the embodiments, the bit cell BC includes memory cells 310-320 and a transistor Tr. Specifically, taking the bit cell BC coupled to the first data line BL11, the second data line BL21, and the word line WL1 as an example, memory cell 310 includes a terminal coupled to the first data line BL11 and the sense amplifier 141, and memory cell 320 includes a terminal coupled to the second data line BL21 and another terminal of the sense amplifier 141. The other terminals of memory cells 310-320 are coupled to one terminal of the transistor Tr. The other terminal of the transistor Tr is coupled to the source line SL, and the control terminal of the transistor Tr is coupled to the word line WL1. In some embodiments, the PUF generator 100 also includes capacitors C1 and C2 coupled between memory cells 310-320 and the sense amplifier 141. In some embodiments, memory cells 310-320 include a magnetic tunneling junction (MTJ), and the transistor Tr is implemented as an N-type metal-oxide semiconductor.

[0096] In some embodiments, such as Figure 4A As shown, memory cells 310-320 are multilayer structures and include convertible ferromagnetic layers 311 and 321 (also called free layers) and fixed ferromagnetic layers 312 and 322 (also called fixed layers) separated by thin dielectric layers 313 and 323 (e.g., thin oxide layers).

[0097] In some embodiments, the resistance value of memory cell 310 is substantially different from that of memory cell 320. For example, when a switchable ferromagnetic layer, such as... Figure 4A In the memory cell 310, the magnetic moment of 311 (indicated by the arrow) is parallel to that of a fixed ferromagnetic layer, such as 312, and the memory cell 310 is configured to have a low resistance state. Conversely, when the switchable ferromagnetic layer, such as... Figure 4AIn the memory cell 321, the magnetic moment (indicated by the arrow) is antiparallel to the magnetic moment of a fixed ferromagnetic layer, such as 322, and the memory cell 320 is configured to have a high-resistance state. In some embodiments, a low-resistance state of the memory cell 310 means that the resistance value of the memory cell 310 is substantially less than the resistance value of the memory cell 320 in the high-resistance state.

[0098] Continue to refer to Figure 3 In some embodiments, during a registration operation (also known as a write operation), bit cells BC are accessed to store bit data (e.g., logical values). For example, the magnetic moments of memory cells 310-320 are initially antiparallel to each other, and both memory cells 310-320 have a high-resistance state. In some embodiments, the resistance state of memory cells 310-320 is provided in a magnetic field annealing process.

[0099] During operation, when the source line SL is grounded, voltage VDD is applied through word line WL1 to the control terminal of transistor Tr and to both the first data line BL11 and the second data line BL21. Write current I... W The write current I flows into the source line SL from the first data line BL11 and the second data line BL21. W It is the current I flowing through memory cell 310 L and the current I flowing through memory cell 320 R The total current. Due to process variations in the manufacture of memory cells 310-320, the slight difference in resistance between memory cells 310-320 causes the current I... L and I R One of them is greater than the other, for example, current I L Greater than current I R In this way, the magnetic moment of the convertible ferromagnetic layer in memory cell 310 is reversed to be parallel to the magnetic moment of the fixed ferromagnetic layer. Therefore, the resistance state of memory cell 310 changes from a high resistance state to a low resistance state. Accordingly, when the resistance state of memory cell 310 is a parallel resistance state (in other words, a low resistance state) and the resistance state of memory cell 320 is an antiparallel resistance state (in other words, a high resistance state), memory cells 310 and 320 have different resistance states.

[0100] Furthermore, when the write current I W For current I L When the number increases, the two terminals of transistor Tr ( Figure 3 The voltage V between terminals n1 and n2 shown DS Accordingly, it increases. For memory cell 320, the voltage between its two terminals equals the voltage VDD minus V. DSThe voltage drops, and the resistance state of memory cell 320 remains unchanged, which is the antiparallel state.

[0101] Also refer to Figure 3 and Figure 4A The bit cell BC includes a memory cell 310 with a low resistance state and a memory cell 320 with a high resistance state. The bit cell BC stores logic "1 (high logic state)".

[0102] In different embodiments, such as Figure 3 and 4B As shown in the figure, when the current I R Greater than current I L At this time, the magnetic moment of the convertible ferromagnetic layer in memory cell 320 flips to be parallel to the magnetic moment of the fixed ferromagnetic layer. Therefore, the resistance state of memory cell 320 changes from a high-resistance state to a low-resistance state. Correspondingly, the resistance state of memory cell 320 is a parallel resistance state (in other words, a low-resistance state), and the resistance state of memory cell 310 is an anti-parallel resistance state (in other words, a high-resistance state). In the above embodiment, Figure 4B The bit cell BC includes a memory cell 310 with a high resistance state and a memory cell 320 with a low resistance state. The bit cell BC stores logic "0 (low logic state)".

[0103] In other words, based on the above, when Figures 4A-4B When the bit unit BC in the middle has different logic values, Figures 4A-4B The memory cell 310 of the bit cell BC in the memory has different resistance states, and Figures 4A-4B The memory cell 320 of the bit cell BC in the memory has different resistance states.

[0104] Furthermore, in some embodiments, when the word line address of a specific bit cell BC in the PUF cell array 110 is selected to correspond to a specific challenge input, the bit data stored in each bit cell BC is associated with a specific challenge input. Therefore, while referring to... Figure 4A and Figure 4B ,like Figure 3 The data lines shown are arranged in the same column to couple the same first data line BL11 and the same second data line BL22. Figure 4A The bit unit BC in Figure 4B The bit units BC in the text, coupled to character lines WL1 and WL2 respectively, store bit data related to different challenge inputs.

[0105] Now also refer to Figures 5-6 According to some embodiments, Figure 5 It corresponds to Figures 1-2A schematic diagram of a portion of the PUF generator 100 during a read operation. According to some embodiments, Figure 6 is a schematic diagram illustrating waveforms of signals corresponding to Figure 5 the PUF generator 100.

[0106] In some embodiments of the read operation, in response to a challenge input, a bitcell is selected, and the bit data stored in the selected bitcell BC is read out to generate an output signal OUT through the sense amplifier 141. In the following paragraphs, the bitcell BC coupled to the wordline WL1, the first data line BL1, and the second data line BL2 is provided for illustrative purposes. The configuration of the bitcells BC of the PUF cell array 110 is similar to the bitcell BC described. Accordingly, the repetitive description is omitted herein.

[0107] More specifically, as shown in Figure 6 , the wordline WL1 coupled to the selected bitcell BC is activated at time TO to start the read operation by applying a voltage VDD to the wordline WL1. The read voltage V READ is applied to the source line SL. Accordingly, Figure 5 the transistor Tr in R conducts to transmit and cause the read current I READ to flow to the memory cells 310-320. In some embodiments, the voltages VDD and V READ are different from each other. In some embodiments, the voltage V L is less than the voltage VDD. In addition, the first data line BL11 and the second data line BL2 are discharged to about 0 volt before time TO, and are charged by the current I R flowing through the memory cell 310 and the current I L flowing through the memory cell 320, respectively.

[0108] In some embodiments, the magnitude of the current I R and the current I L are substantially different from each other during the read operation. To illustrate, with reference to Figure 4A and Figures 5-6 , when the memory cell 310 has a low resistance state (e.g., parallel state) and the memory cell 320 has a high resistance state (e.g., anti-parallel state), the current I R is greater than the current I L . Accordingly, the speed of the first data line BL11 charged by the current I R is faster than the speed of the second data line BL2 charged by the current I Figure 6At time T1, the voltage V1 of the first data line BL1 is configured to have a higher voltage level (V2) than that of the second data line BL2. The sense amplifier 141 compares the voltage levels of the first data line BL11 and the second data line BL2 to generate an output signal OUT. In other words, the sense amplifier 141 compares the two terminals of the selected bit cell to determine the data state of the bit data stored in the selected bit cell BC. In some embodiments, when the voltage level of the first data line BL11 is greater than the voltage level of the second data line BL21, such as... Figure 4A As shown in the embodiment, the output signal indicates that the data state is logic "1".

[0109] Conversely, in Figure 4B In the illustrated embodiment, when memory cell 310 has a high resistance state and memory cell 320 has a low resistance state, the current I... L Less than current I R Therefore, through current I L The charging speed of the first data line BL11 is relative to the current I passing through it. R The charging speed of the second data line BL2 is slower, and the voltage level of the first data line BL11 is lower than the voltage level of the second data line BL21. Accordingly, the output signal indicates that the data status is logic "0".

[0110] In some methods, the PUF cell array comprises a bit cell with three or more transistors for storing bit data. Therefore, the PUF cell array suffers from area loss. With a configuration having an embodiment of this invention, by using a bit cell with one transistor and two MTJ memory cells, the area required for the bit cell is significantly reduced compared to some methods.

[0111] In other methods, by using challenge pulses to transition the state of MTJ cells in a bit cell and determining the transition rate of the MTJ cells in a bit cell, the inter-hamming distance between PUF cell arrays is relatively low, at approximately 45.83%, compared to the ideal 50%. Furthermore, in such methods, reading one bit consumes a significant amount of energy, approximately 3.9 pJ, within approximately 90 ns. Compared to other methods, with the configuration of an embodiment of this invention, only approximately 13 fJ of energy is needed to access one bit cell in approximately 10 ns. In other words, using the configuration of an embodiment of this invention, energy consumption, operating speed, and space utilization are improved.

[0112] Figures 3-5 The configuration provided is for illustrative purposes. Different implementations are also within the scope of this invention. For example, in some embodiments, capacitors C1-C2 are omitted.

[0113] Reference will now be made Figure 7 According to some embodiments, Figure 7 is a layout view of a portion of the PUF generator 100 corresponding to Figures 1-5 A layout view of a portion of the PUF generator 100 corresponding to the bitcell 700 is shown in FIG. 7A. In some embodiments, the fin structure FN is in a first layer. The gate electrodes 711-713 are in a second layer above the first layer. The conductive segments 731-732 are in a third layer above the second layer. The conductive lines 751 and the metal lines 761-762 are in a fifth layer above the third layer. The conductive line 751 corresponds to the source line SL. The metal line 761 corresponds to one of the first data lines, e.g., BL11. The metal line 762 corresponds to one of the second data lines, e.g., BL21. The memory cell 320 is disposed between the gate electrodes 712-713.

[0114] In some embodiments, the conductive segment 731 corresponds to a source terminal of the transistor Tr coupled to the source line SL, and the conductive segment 732 corresponds to a drain terminal of the transistor Tr coupled to the memory cell 310-320. The gate electrode 712 corresponds to a control terminal of the transistor Tr. The gate electrodes 711 and 713 are considered dummy gate electrodes, where in some embodiments, a “dummy” gate electrode refers to a gate electrode that does not have an electrical connection to a metal-oxide-semiconductor device, and does not have a function to the circuit. The conductive line 751 corresponds to the source line SL.

[0115] In some embodiments, the fin structure FN extends along an x-axis direction. The gate electrodes 711-713 and the conductive segments 731-732 extend along a y-axis direction and are separated from each other in the x-axis direction. The conductive line 751, the metal lines 761-762, and the conductive line 751 extend along the x-axis direction and are separated from each other in the y-axis direction. The memory cell 320 is disposed between the gate electrodes 712-713.

[0116] The conductive segment 731 is coupled to the conductive line 751 and to the active region 721 through the via VD1. Correspondingly, the source terminal of the transistor Tr is coupled to the source line SL. The conductive segment 732 is coupled to the active region 722 and to the memory cell 310 through the via VD2. Correspondingly, the drain terminal of the transistor Tr is coupled to the memory cell 310, which is further coupled to one of the metal lines 761 corresponding to one of the first data lines, e.g., BL11. The conductive segment 732 is further coupled to the conductive line 741 through the via VM1. The conductive line 741 is coupled to the metal line 761 corresponding to one of the second data lines, e.g., BL21, through the via VM1.

[0117] In some embodiments, gates 711-713 are separated from each other by a polysilicon distance, for example, approximately 54 nanometers. The diameter of MTJ memory cells 310-320 is, for example, approximately 30 nanometers, and the memory cells 310-320 are separated by a distance, for example, approximately 90 nanometers. The parameters of the components described above are provided for illustrative purposes and are not intended to limit the scope of this invention.

[0118] Figure 7 The configuration is provided for illustrative purposes. Different implementations are also within the scope of this invention. For example, in some embodiments, both memory cells 310-320 are arranged between gates 712-713.

[0119] For reference Figure 8 According to some embodiments, Figure 8 It corresponds Figures 1-7 A flowchart illustrating the operation of the PUF generator 100. It should be understood that additional operations may be provided for other embodiments of the method. Figure 8 The processes shown are before, during, and after the illustrated procedures, and some of the operations can be substituted or removed. The order of operations / processes can be changed. The same symbols are used to represent the same elements in different perspectives and illustrated embodiments. References Figures 1-7 The PUF generator 100 in the method 800 includes the operations 810-830 described below.

[0120] In operation 810, Figure 1 In the middle, the Physically Unforgeable Function (PUF) generator 100 receives challenge input 101.

[0121] When operating 820, such as Figure 2 As shown, in response to the word line address associated with challenge input 101, bit cells BC in PUF cell array 110 are accessed for read or write operations.

[0122] In some embodiments, the access bit unit BC also includes an operation in which a voltage is compared by means of a sensing amplifier 141 during a read operation, the voltage being for generating such a voltage. Figure 5 The voltage of the output signal OUT shown, for example, in Figure 4A The voltage at the terminal of the first data line BL11 of memory cell 310 and, for example, the voltage at the terminal of the second data line BL22 of memory cell 320 are coupled together. Other terminals of memory cells 310-320 are mutually coupled to receive the read voltage V applied to the source line SL. READ .

[0123] In some embodiments, the access bit unit BC further includes, in a read operation, the operation of transmitting a read voltage from the source line SL to the other terminals of the memory units 310-320 via a transistor Tr coupled to the source line SL and the other terminals of the memory units 310-320.

[0124] In some embodiments, the access bit cell BC further includes an operation of charging a first data line during a read operation, the first data line being, for example, BL11 coupled to memory cell 310 to allow a signal, such as current I from memory cell 310, to pass through. L The voltage level ranges from, for example, 0 volts to a voltage level V1. The access bit cell BC also includes the operation of charging a second data line during a read operation. This second data line is, for example, BL21 coupled to memory cell 320 to allow the passage of a signal, such as current I from memory cell 320. R From a voltage level having, for example, 0 volts to a voltage level having voltage V2.

[0125] In some embodiments, the access bit unit BC further includes the operation of controlling transistor Tr in a read operation by applying a word line voltage, such as voltage VDD, to the control terminal of transistor Tr. The access bit unit BC also includes applying a read voltage VDD in a read operation. READ Operation on the source line SL. In some embodiments, the voltage V is read. READ Less than the voltage applied to the character line (e.g., voltage VDD) and greater than 0 volts.

[0126] In some embodiments, during a read operation, memory cell 310 has a resistive state, and memory cell 320 has a different resistive state than that of memory cell 310, such as... Figures 4A-4B As shown.

[0127] In some embodiments, the access bit cell BC further includes applying a voltage during a write operation, such as a voltage VDD on the terminals of memory cells 310 and 320 coupled to the first data line BL11 and the second data line BL22, and applying a voltage, such as a ground voltage less than VDD, on the source line SL. In some embodiments, the voltage VDD is different from voltages V1 and V2.

[0128] In some embodiments, as described in the write operation above, specifically one of memory cells 310-320, for example Figure 4A The resistance state of memory cell 310 in the memory cell 310 changes from an antiparallel resistance state at the magnetic tunneling junction to a parallel resistance state. The resistance state of the other memory cell 310-320, for example, memory cell 310, remains in an antiparallel state.

[0129] Now toFigure 9 Reference is made to. Figure 9 A block diagram of an electronic design automation (EDA) system 900 for designing an integrated circuit layout design according to an embodiment. The EDA system 900 is used to implement one or more steps of the method 800 disclosed in Figure 8 and further explained in conjunction with Figures 1-7 In some embodiments, the EDA system 900 comprises an APR system.

[0130] In some embodiments, the EDA system 900 is a general computing element comprising a hardware processor 902 and a non-transitory computer-readable storage medium 904. The storage medium 904 has encoded therein (i.e., stores) computer program code (instructions), i.e., a set of executable instructions. Execution of the instructions 906 by the hardware processor 902 represents (at least in part) an EDA tool that implements, for example, part or all of the method 800.

[0131] The processor 902 is electrically coupled to the computer-readable storage medium 904 via a bus 908. The processor 902 is also electrically coupled by the bus 908 to an I / O interface 910 and a fabrication tool 916. A network interface 912 is also electrically connected to the processor 902 via the bus 908. The network interface 912 is connected to a network 914 so that the processor 902 and the computer-readable storage medium 904 can be connected to external elements via the network 914. The processor 902 is used to execute the computer program code 906 encoded in the computer-readable storage medium 904 so as to make the system 900 available for performing part or all of the indicated processes and / or methods. In one or more embodiments, the processor 902 is a central processing unit (CPU), a multiprocessor, a distributed processing system, a special application integrated circuit (ASIC), and / or a suitable processing unit.

[0132] In one or more embodiments, computer-readable storage media 904 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or apparatus or device). For example, computer-readable storage media 904 includes semiconductor or solid state memory, magnetic tape, removable computer diskette, random access memory (RAM), read-only memory (ROM), rigid disks and / or optical disk. In one or more embodiments using optical disks, computer-readable storage media 904 includes compact disk - read only memory (CD-ROM), compact disk-read / write (CD-R / W) and / or digital video disk (DVD).

[0133] In one or more embodiments, storage media 904 stores computer program code 906 for causing EDA system 900 (where this execution represents (at least part of) an EDA tool) to be available for performing part or all of the indicated process and / or method. In one or more embodiments, storage media 904 also stores information that facilitates performing part or all of the indicated process and / or method. In one or more embodiments, storage media 904 stores an IC layout map 920 that includes standard cells, such as the standard cells included in bitcell 700 discussed above with respect to Figure 7 In one or more embodiments, EDA system 900 includes a display interface 916 coupled to processor 902. Display interface 916 allows EDA system 900 to display information to a user. Display interface 916 includes a display screen, such as a cathode ray tube (CRT) monitor, a liquid crystal display (LCD) monitor, a plasma display, a thin film transistor display, a light emitting diode display, or a projection display. In one or more embodiments, display interface 916 includes a touch screen display, such as a resistive touch screen, a capacitive touch screen, a surface acoustic wave touch screen, an infrared touch screen, or an optical imaging touch screen. In one or more embodiments, display interface 916 includes a speaker, a sound card, or a headphone jack.

[0134] EDA system 900 includes an I / O interface 910. I / O interface 910 is coupled to external circuitry. In one or more embodiments, I / O interface 910 includes a keyboard, a keypad, a mouse, a trackball, a trackpad, a touch screen, and / or cursor direction keys for communicating information and commands to processor 902.

[0135] EDA system 900 also includes a network interface 912 coupled to processor 902. Network interface 912 allows EDA system 900 to communicate with a network 914 to which one or more other computer systems are connected. Network interface 912 includes a wireless network interface, such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA, or a wired network interface, such as ETHERNET, USB, or IEEE-964. In one or more embodiments, part or all of the indicated process and / or method is implemented in two or more systems 900.

[0136] EDA system 900 also includes manufacturing tools 916 coupled to processor 902. Manufacturing tools 916 are used to manufacture integrated circuits according to design files processed by processor 902, e.g., in Figures 1-7 PUF generator 100 illustrated in FIG. 1.

[0137] EDA system 900 is used to receive information via I / O interface 910. Information received via I / O interface 910 includes one or more of instructions, data, design rules, library of standard cells, and / or other parameters for processing by processor 902. Information is transferred to processor 902 via bus 908. EDA system 900 is used to receive information related to a UI via I / O interface 910. Information is stored in computer-readable medium 904 as design specification 922.

[0138] In some embodiments, some or all of the noted processes and / or methods are implemented as a separate software application for execution by a processor. In some embodiments, some or all of the noted processes and / or methods are implemented as a software application that is part of an additional software application. In some embodiments, some or all of the noted processes and / or methods are implemented as a plug-in to a software application. In some embodiments, at least one of the noted processes and / or methods is implemented as a software application that is part of an EDA tool. In some embodiments, some or all of the noted processes and / or methods are implemented as a software application used by EDA system 900. In some embodiments, a layout including standard cells is generated using other suitable layout generation tools, such as Virtuoso by CADENCE DESIGN SYSTEMS.

[0139] In some embodiments, the processes are implemented as functions of a program stored in a non-transitory computer-readable recording medium. Examples of the non-transitory computer-readable recording medium include, but are not limited to, one or more of external / removable and / or internal / built-in storage or memory units, such as optical discs (such as DVDs), magnetic discs (such as hard discs), semiconductor memories (such as ROMs, RAMs), memory cards, and the like.

[0140] Figure 10 A block diagram of an IC manufacturing system 1000 and an IC manufacturing flow associated therewith according to some embodiments. In some embodiments, at least one of (A) one or more semiconductor masks or (B) at least one element in a layer of a semiconductor integrated circuit is manufactured using IC manufacturing system 1000 based on a layout.

[0141] In Figure 10In this IC manufacturing system 1000, entities such as a design room 1020, a mask room 1030, and an IC manufacturer / fabrication plant (“wafer fab”) 1050 interact with each other in the design, development, and manufacturing cycle and / or services related to the manufacture of an IC component 1060. These entities in the IC manufacturing system 1000 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet or the Internet. These communication networks include wired and / or wireless communication channels. Each entity interacts with one or more of the other entities and provides services to and / or receives services from one or more of the other entities. In some embodiments, two or more of the design room 1020, mask room 1030, and IC wafer fab 1050 are owned by a single entity. In some embodiments, two or more of the design room 1020, the shielding room 1030, and the IC wafer fab 1050 coexist in a common facility and use common resources.

[0142] Design studio (or design team) 1020 produces an IC design layout 1022. IC design layout 1022 includes portions for the PUF generator 100 (e.g., in...). Figure 7 The various geometric patterns designed by the bit unit 700 shown in the figure, for example, in Figure 7 The IC layout design is depicted in the diagram. These geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that make up the various components of the IC element 1060 to be manufactured. Various layers are combined to form various IC features. For example, a portion of the IC layout diagram 1022 includes various IC features to be formed in a semiconductor substrate (such as a silicon wafer) and various metal layers disposed on the semiconductor substrate, such as active regions, gate electrodes, source and drain electrodes, conductive segments, or conductions of interlayer interconnects. Design room 1020 performs an appropriate design process to form the IC layout diagram 1022. This design process includes one or more of logic design, physical design, or placement and routing. The IC layout diagram 1022 is presented in one or more data files containing information of geometric patterns. For example, the IC layout diagram 1022 may be expressed in a GDSII file format or a DFII file format.

[0143] Mask room 1030 includes data preparation 1032 and mask manufacturing 1044. Mask room 1030 uses IC design layout 1022 to manufacture one or more masks 1045 to be used in fabricating various layers of IC device 1060 according to IC design layout 1022. Mask room 1030 performs mask data preparation 1032, in which IC design layout 1022 is translated into a representative data file (RDF). Mask data preparation 1032 provides the RDF to mask manufacturing 1044. Mask manufacturing 1044 includes a mask writer. The mask writer converts the RDF into an image on a substrate such as mask (reticle) 1045 or semiconductor wafer 1053. Design layout 1022 is manufactured by mask data preparation 1032 to comply with the specific characteristics of the mask writer and / or the requirements of IC foundry 1050. In Figure 10 Data preparation 1032 and mask manufacturing 1044 are shown as separate components in the figure. In some embodiments, data preparation 1032 and mask manufacturing 1044 can be collectively referred to as mask data preparation.

[0144] In some embodiments, data preparation 1032 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as errors that can result from diffraction, interference, other process effects, and the like. OPC adjusts IC design layout 1022. In some embodiments, data preparation 1032 includes additional resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase shift masks, other suitable techniques, and the like, or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem.

[0145] In some embodiments, data preparation 1032 includes a mask rule checker (MRC), which checks IC design layout 1022 that has undergone OPC against a set of mask creation rules that contain certain geometric and / or connectivity restrictions to ensure sufficient margins to account for variability in the semiconductor fabrication process, and the like. In some embodiments, the MRC modifies IC design layout 1022 to compensate for restrictions during mask manufacturing 1044, which can undo portions of the modifications performed by OPC in order to comply with the mask creation rules.

[0146] In some embodiments, data preparation 1032 includes lithography process checking (LPC), which simulates the processing to be performed by IC foundry 1050 to manufacture IC device 1060. LPC simulates this processing based on IC design layout 1022 to create a simulated manufactured device, such as IC device 1060. The processing parameters in LPC simulation can include parameters associated with various processes of the IC manufacturing cycle, parameters associated with tools used to manufacture the IC, and / or other aspects of the manufacturing process. LPC takes into account various factors, such as aerial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, and the like, or combinations thereof. In some embodiments, after a simulated manufactured device has been created by LPC, if the simulated device is not close enough in shape to meet design rules, then OPC and / or MRC are repeated to further improve IC design layout 1022.

[0147] It should be appreciated that the above description of mask data preparation 1032 has been simplified for clarity. In some embodiments, data preparation 1032 includes additional features, such as logic operations (LOP), to modify IC design layout 1022 according to manufacturing rules. Additionally, the processes applied to IC design layout 1022 during data preparation 1032 can be performed in a variety of different orders.

[0148] After data preparation 1032 and during mask fabrication 1044, a mask 1045 or a group of masks 1045 is fabricated based on the modified IC design layout 1022. In some embodiments, mask fabrication 1044 includes performing one or more lithography exposures based on the IC design layout 1022. In some embodiments, an e-beam or multiple e-beam mechanism is used to form a pattern on a mask (photomask or reticle) 1045 based on the modified IC design layout 1022. The mask 1045 can be formed in various techniques. In some embodiments, the mask 1045 is formed using binary technology. In some embodiments, the mask pattern includes opaque regions and transparent regions. A beam of radiation, such as an ultra violet (UV) beam, used to expose a layer of image-sensitive material (e.g., photoresist) that has been coated on a wafer is blocked by the opaque regions and transmitted through the transparent regions. In one example, a binary mask version of the mask 1045 includes a transparent substrate (e.g., fused quartz) and opaque material (e.g., chromium) coated in the opaque regions of the binary mask. In another example, the mask 1045 is formed using phase shift technology. In a phase shift mask (PSM) version of the mask 1045, various features in the pattern formed on the phase shift mask are designed to have appropriate phase differences to enhance resolution and imaging quality. In various examples, the phase shift mask can be an attenuated PSM or an alternating PSM. The mask resulting from mask fabrication 1044 is used in various processes. For example, the mask(s) are used in ion implantation processes to form various doped regions in a semiconductor wafer 1053, in etching processes to form various etched regions in the semiconductor wafer 1053, and / or in other suitable processes.

[0149] IC foundry 1050 includes wafer fabrication 1052. IC foundry 1050 is an IC manufacturing enterprise that includes one or more fabrication facilities for manufacturing of a variety of different IC products. In some embodiments, IC foundry 1050 is a semiconductor foundry. For example, there can be a fabrication facility for front-end-of-line (FEOL) manufacturing of a plurality of IC products, while a second fabrication facility can provide back-end-of-line (BEOL) manufacturing for interconnection and packaging of the IC products, and a third fabrication facility can provide other services for the foundry enterprise.

[0150] IC foundry 1050 uses the mask 1045 manufactured by the mask room 1030 to manufacture IC devices 1060. Thus, the IC foundry 1050 uses the IC design layout 1022, at least indirectly, to manufacture the IC devices 1060. In some embodiments, a semiconductor wafer 1053 is manufactured by the IC foundry 1050 using the mask 1045 to form the IC devices 1060. In some embodiments, IC fabrication includes performing one or more lithography exposures based, at least indirectly, on the IC design layout 1022. The semiconductor wafer 1053 includes a silicon substrate or other appropriate substrate having material layers formed thereon. The semiconductor wafer 1053 further includes one or more of various doped regions, dielectric features, multilevel interconnects, and the like (formed in subsequent fabrication steps).

[0151] As described above, one embodiment provides a semiconductor device including a physically unclonable function (PUF) generator. The PUF generator includes a bitcell having a transistor and two MTJ memory cells. In an enrollment operation, the two MTJ in the cell randomly have different states, thus providing uniqueness and randomness of the PUF generator. Furthermore, with less components in the bitcell and reduced read current in the shorter access time of the bitcell, improved area usage, energy consumption, and operating speed are provided.

[0152] In some embodiments, a semiconductor device is provided. The device includes an array of physically unclonable function (PUF) cells, the array of PUF cells including a plurality of bitcells and responsive to a challenge input and based on a data state of one of the bitcells, generating a physically unclonable function response output. Each of the bitcells stores a bit of data and includes a transistor having a control terminal coupled to a wordline and a first terminal coupled to a source line, a first memory cell having a first terminal coupled to a first data line and a second terminal coupled to a second terminal of the transistor, and a second memory cell having a first terminal coupled to a second data line different from the first data line and a second terminal, the second terminal of the second memory cell being coupled at the second terminal of the transistor and the second terminal of the first memory cell.

[0153] In some embodiments, a resistance value of the first memory cell is substantially different from a resistance value of the second memory cell.

[0154] In some embodiments, the semiconductor device further includes a sense amplifier comparing a voltage level of the first data line to a voltage level of the second data line to generate an output signal as the PUF response output, the output signal representing the data state of a corresponding one of the bitcells.

[0155] In some embodiments, the output signal has a high logic state when the voltage level of the first data line is greater than the voltage level of the second data line. The output signal has a low logic state when the voltage level of the second data line is greater than the voltage level of the first data line.

[0156] In some embodiments, in a read operation of a first bitcell of the bitcells, a wordline voltage is different from a read voltage, the wordline voltage is at a control terminal of a transistor in the first bitcell, and the read voltage is at a first terminal of the transistor in the first bitcell.

[0157] In some embodiments, in a read operation of the PUF cell array, a first read current flowing through the first memory cell has a substantially different magnitude than a second read current flowing through the second memory cell.

[0158] In some embodiments, a wordline coupled to a selected bitcell of the bitcells is activated in response to a wordline address corresponding to a challenge input.

[0159] In some embodiments, the first memory cell and the second memory cell have a magnetic tunnel junction.

[0160] In some embodiments, when a first memory cell in a first bitcell of the bitcells has a first resistance state and a second memory cell in the first bitcell has a second resistance state different from the first resistance state, the first bitcell stores a first logic state. When the first memory cell in a second bitcell of the bitcells has the second resistance state and the second memory cell in the second bitcell has the first resistance state, the second bitcell stores a second logic state different from the first logic state.

[0161] In some embodiments, a method of operating a semiconductor is provided and includes the following operations: receiving, by a physically unclonable function generator, a challenge input; accessing, in response to a wordline address associated with the challenge input, a first bitcell in a physically unclonable function cell array, wherein accessing the first bitcell; and outputting, by the physically unclonable function generator, a physically unclonable function response output based on an output signal, the physically unclonable function response output having a high logic state when a first voltage is greater than a second voltage or having a low logic state when the first voltage is less than the second voltage. Accessing the first bitcell includes comparing, in a read operation, the first voltage and the second voltage by a sense amplifier to generate the output signal, the first voltage being at a first terminal of a first memory cell in the first bitcell, the first voltage being at a first terminal of a second memory cell in the first bitcell, a second terminal of the first memory cell and a second terminal of the second memory cell being coupled to each other to receive a read voltage.

[0162] In some embodiments, accessing the first bitcell further includes the following operations: in a read operation, a read voltage is transmitted from the source line to the second terminal of the first memory cell and the second terminal of the second memory cell through a transistor coupled between the source line and the second terminal of the first memory cell and the second terminal of the second memory cell.

[0163] In some embodiments, accessing the first bitcell further includes the following operations: in a read operation, a first data line coupled to the first terminal of the first memory cell is charged by a first signal received from the first memory cell to charge a voltage level of the first data line from a voltage level of a third voltage to a voltage level equal to a first voltage, wherein the third voltage is different from the first voltage and a second voltage. Accessing the first bitcell further includes the following operations: a second data line is charged by a second signal received from the second memory cell to charge a voltage level of the second data line from a voltage level of the third voltage to a voltage level equal to the second voltage, the second data line being coupled to the first terminal of the second memory cell.

[0164] In some embodiments, accessing the first bitcell further includes the following operations: in a read operation, a transistor is turned on by applying a word line voltage at a control terminal of the transistor, the transistor being coupled between the source line and the second terminal of the first memory cell and the second terminal of the second memory cell, and applying a read voltage to the source line, wherein the read voltage is less than the word line voltage and greater than a third voltage.

[0165] In some embodiments, in a read operation, the first memory cell has a first resistance state and the second memory cell has a second resistance state different from the first resistance state.

[0166] In some embodiments, the transistor is coupled between the source line and the second terminal of the first memory cell and the second terminal of the second memory cell.

[0167] In some embodiments, accessing the first bitcell further includes the following operations: in a write operation, a third voltage different from the first voltage and the second voltage is applied to the first terminal of the first memory cell and the first terminal of the second memory cell, and a fourth voltage less than the third voltage is applied to the source line.

[0168] In some embodiments, in a write operation, a resistance state of one of the first memory cell and the second memory cell is changed from an anti-parallel resistance state to a parallel resistance state of a magnetic tunnel junction, and a resistance state of the other of the first memory cell and the second memory cell is the anti-parallel resistance state.

[0169] In some embodiments, a semiconductor device is provided. The semiconductor device includes a sense amplifier and a first bitcell among an array of physically unclonable function units. The first bitcell stores first bit data related to a first challenge input. The first bitcell has a first terminal coupled to a first terminal of the sense amplifier, a second terminal coupled to a second terminal of the sense amplifier different from the first terminal, and a third terminal coupled to a source line. In response to a read operation of the first bitcell performed in response to an activation of a word source line coupled to the first bitcell, the sense amplifier compares a first voltage at the first terminal of the first bitcell and a second voltage at the second terminal of the first bitcell to generate an output signal as a physically unclonable function response output, the output signal representing a first data state of the first bit data.

[0170] In some embodiments, the first bitcell includes a transistor having a control terminal coupled to the word source line and a first terminal coupled to the third terminal of the first bitcell.

[0171] a first magnetic tunnel junction memory cell having a free layer coupled to the first terminal of the first bitcell and a fixed layer coupled to the second terminal of the transistor, and a second magnetic tunnel junction memory cell having a free layer coupled to the second terminal of the first bitcell and a fixed layer coupled to the second terminal of the transistor.

[0172] In some embodiments, the first magnetic tunnel junction and the second magnetic tunnel junction memory cell have different resistance states.

[0173] In some embodiments, the semiconductor device includes a second bitcell storing second bit data different from the first bit data, the second bit data related to a second challenge input different from the first challenge input. Each of the first bitcell and the second bitcell has a first memory cell coupled to the first terminal of the sense amplifier and a second memory cell coupled to the second terminal of the sense amplifier. The first memory cell in the first bitcell and the first memory cell in the second bitcell have different resistance states, and the second memory cell in the first bitcell and the second memory cell in the second bitcell have different resistance states.

Claims

1. A semiconductor device, characterized by comprising: A physical unclonable function unit array including a plurality of bit cells and configured to generate a physical unclonable function response output in response to a challenge input and based on a data state of a bit cell of the plurality of bit cells, wherein each of the plurality of bit cells is configured to store a bit of data and includes: a transistor having a control terminal coupled to a word line; a first memory cell having a first terminal coupled to a first data line; and a second memory cell having a first terminal coupled to a first terminal and a second terminal of a second data line, the second data line being different from the first data line, wherein the transistor further has a first terminal and a second terminal, the first terminal of the transistor being coupled to a second terminal of the first memory cell and a second terminal of the second memory cell, the second terminal of the transistor being coupled to a source line, the source line being different from the first data line and the second data line, wherein the first memory cell and the second memory cell are configured to simultaneously pull up a voltage level of the first data line and a voltage level of the second data line in response to a voltage level of the source line. a resistance value of the first memory cell is different from a resistance value of the second memory cell.

2. The semiconductor device according to claim 1, wherein further comprising:

3. The semiconductor device according to claim 1, wherein a sense amplifier configured to compare the voltage level of the first data line and the voltage level of the second data line to generate an output signal as the physical unclonable function response output, the output signal representing a data state of a corresponding bit cell of the plurality of bit cells. the output signal has a high logic state when the voltage level of the first data line is greater than the voltage level of the second data line, 4. The semiconductor device according to claim 3, wherein the output signal has a low logic state when the voltage level of the second data line is greater than the voltage level of the first data line. in a read operation of a first bit cell of the plurality of bit cells, a word line voltage at the control terminal of the transistor in the first bit cell is different from a read voltage at the first terminal of the transistor in the first bit cell.

5. The semiconductor device according to claim 1, wherein in a read operation of the physical unclonable function unit array, a flow of a first read current through the first memory cell is different from a flow of a second read current through the second memory cell.

6. The semiconductor device according to claim 1, wherein the word line coupled to a selected bit cell of the plurality of bit cells is activated in response to a word line address corresponding to the challenge input.

7. The semiconductor device according to claim 1, wherein the first memory cell and the second memory cell have magnetic tunnel junctions.

8. The semiconductor device according to claim 1, wherein when the first memory cell in a first bit cell of the plurality of bit cells has a first resistance state and the second memory cell in the first bit cell has a second resistance state different from the first resistance state, the first bit cell is configured to store a first logic state; and 9. The semiconductor device according to claim 8, wherein ​ ​ When the first memory cell in a second bit cell of the plurality of bit cells has the second resistance state and the second memory cell in the second bit cell has the first resistance state, the second bit cell is to store a second logic state different from the first logic state.

10. A method of operating a semiconductor device, characterized by, Including: receiving, by a physically unclonable function generator, a challenge input; in response to a word line address related to the challenge input, accessing a first bit cell in an array of physically unclonable function cells, wherein accessing the first bit cell includes: in a read operation, comparing, by a sense amplifier, a first voltage at a first terminal of a first memory cell in the first bit cell and a second voltage at a first terminal of a second memory cell in the first bit cell to generate an output signal, wherein a second terminal of the first memory cell and a second terminal of the second memory cell are coupled to each other to receive a read voltage; and outputting, by the physically unclonable function generator, a physically unclonable function response output based on the output signal, the physically unclonable function response output having a high logic state when the first voltage is greater than the second voltage, or the physically unclonable function response output having a low logic state when the first voltage is less than the second voltage.

11. The operating method of claim 10, wherein, Accessing the first bit cell further includes: in the read operation, transmitting the read voltage from a source line to the second terminal of the first memory cell and the second terminal of the second memory cell through a transistor coupled between the source line and the second terminal of the first memory cell and the second terminal of the second memory cell.

12. The operating method of claim 10, wherein, Accessing the first bit cell further includes: in the read operation, charging a first data line coupled to a first terminal of the first memory cell with a first signal received from the first memory cell to charge a voltage level of the first data line from a voltage level of a third voltage to a voltage level equal to the first voltage, wherein the third voltage is different from the first voltage and the second voltage; charging a second data line with a second signal received from the second memory cell to charge a voltage level of the second data line from the voltage level of the third voltage to a voltage level equal to the second voltage, the second data line being coupled to a first terminal of the second memory cell.

13. The operating method of claim 12, wherein, Accessing the first bit cell further includes: in the read operation, turning on a transistor by applying a word line voltage at a control terminal of the transistor, the transistor being coupled between a source line and the second terminal of the first memory cell and the second terminal of the second memory cell, and applying a read voltage to the source line, wherein the read voltage is less than the word line voltage and greater than the third voltage.

14. The operating method of claim 10, wherein, In the read operation, the first memory cell has a first resistance state and the second memory cell has a second resistance state different from the first resistance state.

15. The operating method of claim 10, wherein, a transistor is coupled between the source line and the second terminal of the first memory cell, the second terminal of the second memory cell; wherein accessing the first bitcell further comprises: in a write operation, applying a third voltage different from the first voltage and the second voltage at the first terminal of the first memory cell and the first terminal of the second memory cell; and applying a fourth voltage less than the third voltage on the source line.

16. The operating method of claim 15, wherein, in the write operation, a resistance state of one of the first memory cell and the second memory cell transitions from an anti-parallel resistance state of a magnetic tunnel junction to a parallel resistance state, and a resistance state of the other of the first memory cell and the second memory cell is the anti-parallel resistance state.

17. A semiconductor device, characterized by comprising: comprises: a sense amplifier; and a first bitcell, among an array of physically unclonable function cells, to store a first bit of data related to a first challenge input, wherein the first bitcell has a first terminal coupled to a first terminal of the sense amplifier, a second terminal coupled to a second terminal of the sense amplifier different from the first terminal, and a third terminal coupled to a source line; wherein in response to a read operation of the first bitcell being performed in response to an activation operation of a word source line coupled to the first bitcell, the sense amplifier is to compare a first voltage at the first terminal of the first bitcell and a second voltage at the second terminal of the first bitcell to generate an output signal as a physically unclonable function response output, the output signal representing a first data state of the first bit of data.

18. The semiconductor device of claim 17, wherein, the first bitcell comprises: a transistor having a control terminal coupled to the word source line and a first terminal coupled to the third terminal of the first bitcell; a first magnetic tunnel junction memory cell having a free layer coupled to the first terminal of the first bitcell and a fixed layer coupled to a second terminal of the transistor; and a second magnetic tunnel junction memory cell having a free layer coupled to the second terminal of the first bitcell and a fixed layer coupled to the second terminal of the transistor. the first and second magnetic tunnel junction memory cells have different resistance states.

19. The semiconductor device of claim 18, wherein, further comprises:

20. The semiconductor device of claim 17, wherein, a second bitcell to store a second bit of data different from the first bit of data, the second bit of data related to a second challenge input different from the first challenge input, wherein each of the first and second bitcells has a first memory cell coupled to the first terminal of the sense amplifier and a second memory cell coupled to the second terminal of the sense amplifier, ​ wherein the first memory cell in the first bit cell and the first memory cell in the second bit cell have different resistance states, and the second memory cell in the first bit cell and the second memory cell in the second bit cell have different resistance states.

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