Method for manufacturing a memory

Abstract

The present invention discloses a method for manufacturing a memory device, belonging to the field of semiconductor technology. The method comprises: providing a substrate on which a trench and a stacked structure having a wordline layer are formed; forming a second dielectric material layer in the trench and on the stacked structure, wherein the second dielectric material layer buries each of the stacked structures and seals the trenches between adjacent stacked structures into air gaps; implanting ions for reducing the dielectric constant K into at least a portion of the thickness of the second dielectric material layer; and performing an annealing process to convert part or all of the second dielectric material layer into a third dielectric material layer. After forming the air gap, carbon ions and / or fluorine ions are implanted into a predetermined depth of the second dielectric material layer to reduce the dielectric constant around the air gap, thereby reducing the composite parasitic capacitance caused by introducing the air gap and reducing the distance between the wordline structures.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a memory. Background Art

[0002] Dielectric materials are essential for integrated circuits, providing insulation and isolation between conductors. Dielectric materials commonly used in integrated circuits have a dielectric constant between 3.8 and 4.5, such as silicon oxide. To reduce leakage current, parasitic capacitance between conductors, and heat generation in integrated circuits, the semiconductor industry currently employs low-K (dielectric constant) or ultra-low-K dielectric materials. Low-K dielectric materials typically have a dielectric constant of around 3-3.5, such as FSG (Fluorine-Doped Silicate Glass, K=3.5), AMAT (Applied Materials)'s BDI (Black Diamond I, K=3.0), and LAM (Lam Research Corporation)'s CDO (Carbon Doped Oxide, K=3.0). Ultra-low-K thin film materials (such as AMAT's BDII and BDIII) have a dielectric constant of around 2.5.

[0003] While all of the aforementioned dielectric materials can significantly reduce parasitic capacitance in integrated circuits, air, as a dielectric material, has a lower dielectric constant (K) than these materials, approaching 1. Therefore, in some integrated circuits, an air gap (or air gap dielectric layer) structure is introduced to further reduce parasitic capacitance. For example, in NAND flash memory chips, the use of an air gap structure between word lines can reduce the parasitic capacitance that increases due to the excessive reduction in the WL-WL (word line-to-word line structure) or BL-BL (bit line-to-bit line structure) distance.

[0004] However, in the electrical testing of NAND flash memory chips, the inventors found that although the Air gap process was adopted, there was still a large composite parasitic capacitance between WL-WL. The factors affecting this composite parasitic capacitance include: first, the thickness and K value of the dielectric material layer (such as low-K dielectric material) at the top and bottom of the air gap; second, the thickness and K value of the dielectric material layer (such as silicon dioxide) on the sidewall of the air gap. Summary of the Invention

[0005] The object of the present invention is to provide a method for manufacturing a memory to solve the problem of composite parasitic capacitance between word line structures.

[0006] To solve the above technical problems, the present invention provides a method for manufacturing a memory, comprising the following steps:

[0007] Providing a substrate, on which a stack structure separated by a plurality of trenches is formed, the stack structure including a word line layer, and adjacent word line layers of the stack structure are separated by the trenches;

[0008] forming a second dielectric material layer in the trenches and on the stacked structures, wherein the second dielectric material layer buries each of the stacked structures and seals the trenches between adjacent stacked structures into air gaps;

[0009] implanting ions for reducing the dielectric constant K into at least a portion of the thickness of the second dielectric material layer;

[0010] Annealing is performed to cause the implanted ions to cause lattice reorganization at least in the second dielectric material layer, so that part or all of the second dielectric material layer is converted into a third dielectric material layer, and the dielectric constant of the third dielectric material layer is lower than that of the second dielectric material layer.

[0011] Preferably, the material of the second dielectric material layer includes at least one of a high-K dielectric, silicon oxide, and a low-K dielectric. The dielectric constant K of the high-K dielectric is higher than that of silicon oxide, and the dielectric constant K of the low-K dielectric is lower than that of silicon oxide.

[0012] Preferably, a plasma enhanced chemical vapor deposition process is adopted and a process gas including SiH 4 is used to deposit and form the second dielectric material layer in the trench and on the stack structure.

[0013] Preferably, the step of forming the groove and the stack structure on the substrate includes: depositing a floating gate dielectric layer, a floating gate layer, an inter-gate dielectric layer, the word line layer and a word line protection layer on the substrate in sequence; and etching the word line protection layer, the word line layer, the inter-gate dielectric layer, the floating gate layer and the floating gate dielectric layer to the top surface of the substrate in sequence to form the stack structure.

[0014] Preferably, before forming the second dielectric material layer and after forming the stack structure, the method further includes: forming a first dielectric material layer on the sidewalls of the stack structure and the substrate located between the stack structures.

[0015] Preferably, the second dielectric material layer also covers the inner surface of the first dielectric material layer and the sidewalls of the stacked structure exposed by the first dielectric material layer, and the deposition rate of the second dielectric material layer on the top surface of the stacked structure is greater than the deposition rate of the second dielectric material layer on the inner surface of the groove.

[0016] Preferably, the ion implantation depth is such that the portion of the second dielectric material layer covering the top of the trench is converted into the third dielectric material layer after the annealing treatment.

[0017] Preferably, the ions for reducing the dielectric constant include carbon ions and / or fluorine ions.

[0018] Preferably, the ion injection depth also allows the ions to be injected into at least a portion of the thickness of the second dielectric material layer located in the trench, so that at least a portion of the second dielectric material layer located in the trench is converted into the third dielectric material layer after the annealing treatment.

[0019] Preferably, the annealing process adopts a spike annealing process, the annealing temperature is 900° C. to 1200° C., and the annealing time is 210 ms to 250 ms.

[0020] In the memory manufacturing method provided by the present invention, after forming the air gap, carbon ions or fluorine ions are implanted into a predetermined depth of the second dielectric material layer to convert part or all of the second dielectric material layer located at the top of the stacked structure into a third dielectric material layer with a lower dielectric constant. The ion implantation depth is further deepened, so that at least part of the second dielectric material layer in the trench is converted into the third dielectric material layer with a lower dielectric constant after the annealing process, thereby reducing the dielectric constants of the second dielectric material layer and the first dielectric material layer, thereby reducing the composite parasitic capacitance caused by introducing the air gap and reducing the distance between WL-WL (word line structure). BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 is a schematic diagram of the air gap structure under the current technology;

[0022] Figure 2 It is a flowchart of the method for manufacturing the memory provided by the present invention;

[0023] Figure 3 It is a schematic diagram of the structure of the stacked structure formed on the substrate and the first dielectric material layer provided by the present invention;

[0024] Figure 4 is a schematic structural diagram of the present invention after metal silicide is formed on top of the stacked structure provided;

[0025] Figure 5 is a schematic structural diagram of the present invention after a second dielectric material layer is formed on top of the provided stacked structure;

[0026] Figures 6 to 9 Schematic diagrams of the structures of four embodiments of the third dielectric material layer formed after annealing treatment according to the present invention.

[0027] In the picture:

[0028] 1. Substrate; 2. Stacked structure; 21. Floating gate layer; 22. Intergate dielectric layer; 23. Word line layer; 24. Word line protection layer; 3. First dielectric material layer; 4. Metal silicide; 5. Second dielectric material layer; 6. Air gap; 7. Trench; 8. Third dielectric material layer. DETAILED DESCRIPTION

[0029] The following is a detailed description of the memory manufacturing method proposed by the present invention, with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description and claims. It should be noted that the drawings are highly simplified and not to exact scale, and are intended solely to facilitate and clarify the purpose of illustrating the embodiments of the present invention.

[0030] The air gap itself has parasitic capacitance. As technology advances, the distance between WL-WL (word line structure) continues to shrink, such as Figure 1 A schematic diagram of a conventional air gap structure is shown. The arrows indicate the width of the air gaps and the distance between the wordline structures. It can be seen that the width of the air gaps between the wordline structures and the thickness of the sidewalls on the wordline structures are close to 1:1, and the dielectric constant of air is close to 1, making it difficult to further reduce the dielectric constant of air itself. Therefore, it is urgent to reduce the dielectric constant of the dielectric material layer and / or the first dielectric material layer above the air gap to reduce the composite parasitic capacitance of the air gap.

[0031] Based on this, the core idea of ​​the present invention is to reduce the composite parasitic capacitance of the air gap by injecting ions that reduce the dielectric constant, such as carbon ions or fluorine ions or a combination of carbon ions and fluorine ions, into the second dielectric material layer and part of the first dielectric material layer above the air gap.

[0032] For details, please refer to Figures 2 to 9 , which is a schematic diagram of an embodiment of the present invention.

[0033] S1 , providing a substrate 1 , on which stacked structures 2 separated from each other by a plurality of trenches 7 are formed. The stacked structures 2 include word line layers 23 , and the word line layers 23 of adjacent stacked structures 2 are separated by the trenches 7 .

[0034] Specifically, the steps of forming a plurality of trenches 7 and a stacked structure 2 on the substrate 1 include: depositing a floating gate dielectric layer (not marked), a floating gate layer 21, an inter-gate dielectric layer 22, a word line layer 23 and a word line protection layer 24 on the substrate 1 in sequence; and etching the word line protection layer 24, the word line layer 23, the inter-gate dielectric layer 22, and the floating gate layer 21 to the top surface of the substrate 1 in sequence to form a stacked structure 2 having a trench 7, wherein the floating gate layer 21 in the stacked structure 2 is a floating gate of the memory, and the word line layer 23 is a control gate of the memory, that is, a word line (WL) of the memory.

[0035] In one embodiment, the floating gate layer 21 and the word line layer 23 are polysilicon layers, the intergate dielectric layer 22 is an ONO layer (silicon oxide layer-silicon nitride layer-silicon oxide layer), and the word line protection layer 24 is silicon nitride.

[0036] S2, such as Figure 3 As shown, a first dielectric material layer 3 is formed on the sidewalls of the stacked structure 2 and on the substrate 1 located between the stacked structures 2, wherein the material of the first dielectric material layer 3 is silicon oxide. Optionally, the first dielectric material layer 3 exposes the top of the stacked structure 2 and extends downward from the sidewalls of the wordline layer 23 of the stacked structure 2 to cover the surface of the substrate 1 exposed at the bottom of the trench 7. At the same time, the first dielectric material layer 3 completely covers the sidewalls of the wordline layer 23, and the portion of the first dielectric material layer 3 covering the sidewalls of the wordline layer 23 serves as a wordline sidewall. In other embodiments of the present invention, the first dielectric material layer 3 may also cover the top surface of the stacked structure 2 and the inner surface of the trench 7.

[0037] In one embodiment, after forming the stack structure 2 and before forming the first dielectric material layer 3, the word line protection layer 24 on the top surface of the word line layer 23 is removed to expose the top surface of the word line layer 23 of the stack structure 2 and protect the remaining device surfaces, and metal is deposited and a high temperature annealing process is performed after the metal deposition, and the unreacted metal is removed to form a metal silicide 4 on the top surface of the word line layer 23, as shown in FIG. Figure 4 As shown, for example, nickel silicide.

[0038] S3, such as Figure 5 As shown, a second dielectric material layer 5 is formed in the trenches 7 and on the stacked structures 2 using a plasma-enhanced chemical vapor deposition process using a process gas including SiH4. The second dielectric material layer 5 is deposited in the trenches 7 and on the stacked structures 2. The second dielectric material layer 5 buries each stacked structure 2. The larger depth-to-width ratio of the trenches 7 between adjacent stacked structures 2 is utilized to seal the trenches 7 early during the deposition process, and the trenches 7 between adjacent stacked structures 2 are enclosed as air gaps 6. The material of the second dielectric material layer 5 includes at least one of a high-K dielectric, silicon oxide, and a low-K dielectric. The high-K dielectric has a higher dielectric constant K than silicon oxide, and the low-K dielectric has a lower dielectric constant K than silicon oxide.

[0039] In actual implementation, part of the material of the second dielectric material layer 5 will also fall into the groove 7 between the stacked structures 2, so that the second dielectric material layer 5 also covers the inner surface of the first dielectric material layer 3 and the sidewalls of the stacked structure 2 exposed by the first dielectric material layer 3, and taking advantage of the large depth-to-width ratio of the groove 7, the second dielectric material layer 5 is not easy to fill into the interior of the groove 7. As a result, the deposition rate of the second dielectric material layer 5 on the top surface of the stacked structure 2 is greater than the deposition rate of the second dielectric material layer 5 on the inner surface of the groove 7, and then the deposition of the second dielectric material layer 5 may cause the groove 7 to be sealed in advance to form an air gap 6. Among them, the material of the second dielectric material layer 5 can be the same as or different from the material of the first dielectric material layer 3. As an example, the material of the second dielectric material layer 5 is the same as that of the first dielectric material layer 3, both of which are silicon oxide.

[0040] S4 , implanting ions for reducing the dielectric constant K and containing no hydrogen into at least a portion of the thickness of the second dielectric material layer 5 , wherein the ions for reducing the dielectric constant K include carbon ions and / or fluorine ions.

[0041] In one embodiment, Figure 6 By vertically injecting ions into the second dielectric material layer 5, the ion implantation depth is such that the portion of the second dielectric material layer 5 covering the top of the trench 7, or the portion of the second dielectric material layer 5 covering the top of the stacked structure 2 (i.e., the portion of the second dielectric material layer 5 located on the top of the air gap 6), can be partially or completely converted into a third dielectric material layer 8 having a dielectric constant K smaller than that of the second dielectric material layer 5 after undergoing annealing treatment in the subsequent step S5. As a result, the dielectric constant K of at least the dielectric material layer covering the top portion of the trench 7 can be reduced, that is, the K value of the dielectric material layer on the top of the air gap 6 can be reduced, thereby reducing the composite parasitic capacitance between word lines to a certain extent.

[0042] Further, if Figure 7 As shown, the ion implantation depth enables the ions to be implanted not only into the second dielectric material layer 5 at the top of the air gap 6, but also into part or all of the thickness of the second dielectric material layer 5 on the sidewalls of the trench 7. After the subsequent annealing treatment in step S5, the second dielectric material layer 5 on the sidewalls of the air gap 6 can be partially or completely converted into the third dielectric material layer 8. As a result, not only the K value of the dielectric material layer at the top of the air gap is reduced, but also the K value of the dielectric material layer on the sidewalls of the air gap 6 can be reduced, thereby further reducing the composite parasitic capacitance between word lines.

[0043] Furthermore, if Figure 8The depth of the ion implantation not only allows the ions to be implanted into the second dielectric material layer 5 on the top and sidewalls of the air gap 6, but also allows the ions to pass through the second dielectric material layer 5 on the sidewalls of the air gap 6 and be implanted into at least a portion of the thickness of the first dielectric material layer 3 covered by the second dielectric material layer 5. Therefore, after the subsequent step S5, the portion of the first dielectric material layer 3 into which the ions are implanted can also be converted into the third dielectric material layer 8 after annealing, thereby reducing the dielectric constant K of the dielectric material layer on the sidewalls of the stacked structure 2, further reducing the K value of the dielectric material layer on the sidewalls of the air gap 6, and thus further reducing the composite parasitic capacitance between word lines.

[0044] Optimally, as Figure 9 ions are not only implanted into the second dielectric material layer 5 throughout the entire thickness of the top, bottom, and sidewalls of the air gap 6, but are also implanted into the entire thickness of the first dielectric material layer 3. As a result, both the first dielectric material layer 3 and the second dielectric material layer 5 around the air gap 6 (including the top and sidewalls) can be converted into the third dielectric material layer 8 through annealing, thereby minimizing the composite parasitic capacitance between word lines.

[0045] Since ion implantation is used, hydrogen elements are not introduced during the ion implantation process, thereby avoiding the negative effects caused by the increase in the hydrogen content in silicon oxide. When the line width of the stacked structure 2 is less than or equal to the current technology node, or for the structure that also uses the air gap dielectric layer technology, the method of injecting ions to reduce parasitic capacitance can still be implemented.

[0046] S5, performing an annealing process so that the implanted ions cause lattice reorganization in at least the second dielectric material layer 5, so that part or all of the second dielectric material layer 5 is converted into a third dielectric material layer 8, and the dielectric constant of the third dielectric material layer 8 is lower than that of the second dielectric material layer 5. The annealing process adopts a spike annealing process, the annealing temperature is 900° C. to 1200° C., and the annealing time is 210 ms to 250 ms.

[0047] As described in step S4, the ion implantation depth is such that at least a portion of the second dielectric material layer 5 covering the top of the trench 7 is converted into the third dielectric material layer 8 after annealing. Furthermore, the ion implantation depth is such that the ions are also implanted into at least a portion of the thickness of the first dielectric material layer 3, so that at least a portion of the first dielectric material layer 3 is converted into the third dielectric material layer 8 after annealing, thereby reducing the dielectric constant of the dielectric material around the air gap 6.

[0048] In summary, in the method for manufacturing a memory provided by an embodiment of the present invention, after forming the air gap 6, carbon ions and / or fluorine ions are implanted into a predetermined depth of the second dielectric material layer 5 covering the top of the stacked structure 2, so that at least a portion of the second dielectric material layer 5 covering the top of the stacked structure 2 is converted into a third dielectric material layer 8 having a lower dielectric constant, and at least a portion of the first dielectric material layer 3 is also converted into the third dielectric material layer 8 having a lower dielectric constant, thereby reducing the composite parasitic capacitance caused by introducing the air gap 6 and reducing the distance between WL-WL (word line structure).

[0049] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A method for manufacturing a memory, characterized in that: The following steps are involved: Providing a substrate, on which a stack structure separated by a plurality of trenches is formed, the stack structure including a word line layer, and adjacent word line layers of the stack structure are separated by the trenches; forming a second dielectric material layer in the trenches and on the stacked structures, wherein the second dielectric material layer buries each of the stacked structures and seals the trenches between adjacent stacked structures into air gaps; implanting ions for reducing the dielectric constant K into at least a portion of the thickness of the second dielectric material layer; Annealing is performed to cause the implanted ions to cause lattice reorganization at least in the second dielectric material layer, so that part or all of the second dielectric material layer is converted into a third dielectric material layer, and the dielectric constant of the third dielectric material layer is lower than that of the second dielectric material layer.

2. The method for manufacturing a memory according to claim 1, wherein: The material of the second dielectric material layer includes at least one of a high-K dielectric, silicon oxide, and a low-K dielectric. The dielectric constant K of the high-K dielectric is higher than that of silicon oxide, and the dielectric constant K of the low-K dielectric is lower than that of silicon oxide.

3. The method for manufacturing a memory according to claim 2, wherein: A plasma enhanced chemical vapor deposition process is adopted using a process gas including SiH 4 to deposit and form the second dielectric material layer in the trench and on the stack structure.

4. The method for manufacturing a memory according to claim 1, wherein: The steps of forming the trench and the stack structure on the substrate include: depositing a floating gate dielectric layer, a floating gate layer, an inter-gate dielectric layer, the word line layer and a word line protection layer on the substrate in sequence; and etching the word line protection layer, the word line layer, the inter-gate dielectric layer, the floating gate layer and the floating gate dielectric layer to the top surface of the substrate in sequence to form the stack structure.

5. The method for manufacturing a memory according to claim 1, wherein: Before forming the second dielectric material layer and after forming the stack structure, the method further includes: forming a first dielectric material layer on the sidewalls of the stack structure and the substrate located between the stack structures.

6. The method for manufacturing a memory according to claim 5, wherein: The second dielectric material layer also covers the inner surface of the first dielectric material layer and the sidewalls of the stacked structure exposed by the first dielectric material layer, and the deposition rate of the second dielectric material layer on the top surface of the stacked structure is greater than the deposition rate of the second dielectric material layer on the inner surface of the groove.

7. The method for manufacturing a memory according to claim 1, wherein: The ion implantation depth is such that the portion of the second dielectric material layer covering the top of the stacked structure is converted into the third dielectric material layer after the annealing process.

8. The method for manufacturing a memory according to claim 1, wherein: The ions for reducing the dielectric constant K include carbon ions and / or fluorine ions.

9. The method for manufacturing a memory according to claim 1, wherein: The ion implantation depth also allows the ions to be implanted into at least a portion of the thickness of the second dielectric material layer in the trench, so that at least a portion of the second dielectric material layer in the trench is converted into the third dielectric material layer after the annealing process.

10. The method for manufacturing a memory according to claim 1, wherein: The annealing process adopts a spike annealing process, the annealing temperature is 900° C. to 1200° C., and the annealing time is 210ms to 250ms.

Images