A recessed Fin-MOSFET gate structure HEMT and manufacturing method

Abstract

The present invention discloses a recessed Fin-MOSFET gate structure HEMT and a manufacturing method thereof, belonging to the field of microelectronics and solid electronics. A substrate, a buffer layer, a channel layer, a barrier layer, a P-GaN layer and a gate electrode are grown from bottom to top, and a source electrode and a drain electrode are grown on both sides of the channel layer; through partial etching of the P-GaN layer and deposition of a gate dielectric, a normally-on Fin-MOSFET controlled by the gate electrode voltage is connected in parallel at both ends of an equivalent Schottky diode D SJ formed by the gate electrode and the P-GaN layer; a recessed region is provided in the barrier layer below the P-GaN layer, which is used to improve the gate control ability of the device, and can jointly determine the threshold voltage of the device with the lateral size of the fin, reduce the dependence of the threshold voltage on the lateral size of the fin and the requirements for the lateral process size.

Description

Technical Field

[0001] The present invention relates to the technical field of microelectronics and solid state electronics, and particularly to a recessed Fin-MOSFET gate structure HEMT and a manufacturing method thereof. Background Art

[0002] Group III nitrides belong to the third-generation semiconductor materials, which have excellent characteristics such as a large bandgap width, a high electron saturation velocity, and being resistant to high temperature, high voltage, and radiation. They are ideal materials for preparing power electronic devices. Compared with power electronic devices based on Si and GaAs materials, GaN-based high electron mobility transistors (HEMTs) have a broader application prospect in the fields of high temperature, high frequency, and high power. The heterojunction is the basic structure of GaN-based HEMT devices. Due to the unique spontaneous polarization and piezoelectric polarization effects of GaN materials, a high-concentration two-dimensional electron gas naturally exists at the channel of GaN-based HEMT devices. The P-type gate technology depletes the two-dimensional electron gas at the channel by growing a layer of p-GaN on the barrier layer. This method has strong process controllability and can be mass-produced repeatedly. It is a very promising enhancement-type manufacturing method.

[0003] The most common gate structure of commercial p-GaN HEMT devices is as Figure 1 shown. From top to bottom, it is a stacked structure of gate metal / p-GaN / AlGaN / GaN. A Schottky contact is usually used between the gate metal and p-GaN. The equivalent electrical model is as Figure 1 shown, which is a Schottky diode D SJ formed by the gate metal and p-GaN and a p-i-n diode D pin connected in series in the reverse direction, having problems such as high requirements for process preparation of the threshold voltage, weak threshold voltage regulation ability, low threshold voltage (<2V), small gate voltage swing, and easy drift of the threshold voltage. Summary of the Invention

[0004] The purpose of the present invention is to overcome the problems of the prior art and provide a recessed Fin-MOSFET gate structure HEMT and a manufacturing method thereof.

[0005] The object of the present invention is achieved by the following technical solutions: A recessed Fin-MOSFET gate structure HEMT of the present invention includes a substrate, a buffer layer, a channel layer, a barrier layer, a P-GaN layer, and a gate electrode that are grown in layers from bottom to top along the vertical direction of the device. A heterojunction is formed between the channel layer and the barrier layer. The barrier layer has a bandgap wider than that of the channel layer, and a large amount of two-dimensional electron gas (2DEG) exists at the heterojunction interface. Source electrodes and drain electrodes are grown oppositely on both sides of the channel layer. The source electrodes and drain electrodes reach the barrier layer in the vertical direction and penetrate the P-GaN layer, and both the source electrodes and drain electrodes are ohmic contact electrodes, and the gate electrode is a P-GaN Schottky contact electrode. Among them, the material of the substrate is any one of Si, diamond, SiC, sapphire, and GaN; the buffer layer is any one or combination containing AlN, AlGaN, GaN, and SiN; the heterojunction is a group-III nitride-based material, such as a combination of two or more of GaN, AlGaN, InN, AlN, InGaN, and InAlGaN, such as AlGaN / GaN, AlInN / GaN, AlGaN / InGaN / GaN, or AlGaN / AlN / GaN.

[0006] Further, through partial etching of the p-GaN layer and gate dielectric deposition, a normally-on Fin-MOSFET controlled by the gate electrode voltage is connected in parallel at both ends of the equivalent Schottky diode D SJ formed by the gate electrode and the P-GaN layer, that is, a Fin-MOSFET is introduced into the p-GaN gate structure, and one end of the Fin-MOSFET is connected to the source electrode through an ohmic contact. Specifically, partial etching of the p-GaN layer means performing fin etching on the P-GaN layer to form a fin-shaped P-GaN layer; gate dielectric deposition means depositing an insulating dielectric layer for isolation under the gate electrode.

[0007] Furthermore, there is a recessed area in the barrier layer below the P-GaN layer.

[0008] In an example, the P-GaN layer is a fin-shaped P-GaN layer and only exists under the gate electrode. An ohmic contact metal electrode, a dielectric layer, and a gate electrode are grown on the P-GaN layer from bottom to top. Among them, the ohmic contact metal electrode is grown on the fin surface of the P-GaN layer; the dielectric layer covers the ohmic contact metal electrode and the sidewalls of the P-GaN layer fins; the gate electrode covers the dielectric layer and the surface of the P-GaN layer. In summary, there is a metal electrode (ohmic contact metal electrode) that forms an ohmic contact with the P-GaN at the top of the fin after P-GaN etching. This ohmic contact metal electrode is connected to the source electrode, and at the same time, this ohmic contact metal electrode is isolated from the gate electrode through the dielectric layer. Further, a recessed area is etched in the barrier layer below the P-GaN layer.

[0009] In one example, a passivation layer is deposited on the regions between the source electrode and the gate electrode, between the gate electrode and the drain electrode, and on the surfaces of the gate electrode, the source electrode, and the drain electrode.

[0010] In one example, the length of the fin structure is 30 nm - 200 nm, and the height is 60 nm - 400 nm.

[0011] In one example, the ohmic contact metal electrode is an alloy layer prepared from a first conductive material and a second conductive material. The first conductive material is one or a combination of more than one of Ti, Al, Ni, Au, Pd; the second conductive material is one or a combination of more than one of Ti, Al, Ni, Au, Pd. It should be noted that since the ohmic contact metal electrode is an alloy layer, the materials of the first conductive material and the second conductive material are different.

[0012] In one example, the dielectric layer is Al 2 O 3 、SiO 2 、any one of SiNx.

[0013] It should be further noted that the technical features corresponding to each example in the above HEMT based on the recessed Fin - MOSFET gate structure can be combined or replaced with each other to form a new technical solution.

[0014] The present invention also includes a manufacturing method of a recessed Fin - MOSFET gate structure HEMT, comprising the following steps:

[0015] S1’: Grow a buffer layer, a channel layer, and a barrier layer on the substrate in sequence; wherein, the buffer layer is 1 μm - 3 μm; the GaN channel layer is 300 nm thick; the barrier layer is 10 nm - 15 nm.

[0016] S2’: Etch the barrier layer to form a barrier layer with a recessed region; specifically, first form a mask pattern for the recessed region, and then etch the barrier layer to obtain a barrier layer with a recessed region.

[0017] S3’: Secondarily epitaxially grow a P - GaN layer on the barrier layer with a recessed region, and the recessed region is located below the P - GaN layer; specifically, grow a GaN layer doped with Mg on the barrier layer, and anneal the GaN capping layer doped with Mg, thereby realizing the fabrication of the P - GaN layer.

[0018] S4’: Fabricate an ohmic contact metal electrode on the surface of the P - GaN layer; specifically, first form a mask pattern for the P - GaN ohmic contact region on the surface of the P - GaN layer, and fabricate the P - GaN ohmic contact electrode by evaporation. After evaporation, perform metal lift - off, and then perform annealing treatment to complete the fabrication of the ohmic contact metal electrode.

[0019] S5’: Perform fin etching on the P-GaN layer to form a fin-structured P-GaN layer; specifically, use the ohmic contact metal electrode as a hard mask to etch the P-GaN layer to obtain a fin-structured P-GaN layer.

[0020] S6’: Fabricate a dielectric layer on the ohmic contact metal electrode and the sidewalls of the P-GaN layer fins; specifically, deposit a dielectric layer on the surface of the HEMT device, then prepare a mask pattern for the dielectric layer, and remove the dielectric layer in the areas other than the fin sidewalls and the top, and finally remove the photoresist.

[0021] S7’: Fabricate a gate electrode on the dielectric layer; specifically, first prepare a mask pattern covering the entire gate electrode area, then perform gate metal evaporation so that the gate metal covers the entire dielectric layer and the surface of the P-GaN layer, and after evaporation, perform lift-off to obtain a complete gate electrode.

[0022] S8’: Remove the P-GaN layer outside the gate electrode area; specifically, use the gate electrode as a hard mask to etch and remove the P-GaN layer outside the gate electrode area.

[0023] S9’: Fabricate a source electrode and a drain electrode on the barrier layer with a recessed area. Specifically, first form a mask pattern for the source electrode area and a mask pattern for the drain electrode area, evaporate metal to fabricate the source electrode and the drain electrode, perform lift-off after evaporation, and perform annealing treatment to complete the fabrication of the source electrode and the drain electrode.

[0024] In one example, the method further includes a passivation protection step:

[0025] Deposit a passivation layer on the barrier layer with a recessed area, and the passivation layer covers the area between the source electrode and the gate electrode, the area between the gate electrode and the drain electrode, and the surfaces of the gate electrode, the source electrode, and the drain electrode.

[0026] In one example, the method further includes an electrode lead fabrication step:

[0027] Fabricate an electrode pattern;

[0028] Remove the passivation layer in the electrode area to form an interconnection opening;

[0029] Fabricate a mask pattern for the electrode lead;

[0030] Perform lead electrode metal evaporation on the substrate with the fabricated mask, and finally perform lift-off after the lead electrode metal evaporation is completed to obtain a complete lead electrode.

[0031] It should be further noted that the technical features corresponding to the various examples in the above manufacturing method of the HEMT with a recessed Fin-MOSFET gate structure can be combined or replaced with each other to form a new technical solution.

[0032] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0033] 1. In one example, by introducing a normally-on Fin-MOSFET into the p-GaN gate structure, the gate electrode controls the potential of the p-GaN layer by regulating the Fin-MOSFET switch and changes the concentration of the two-dimensional electron gas in the channel, so that the threshold voltage of the device does not solely depend on the epitaxial layer structure (buffer layer, channel layer, barrier layer, P-GaN layer), thereby improving the problem of small threshold voltage of the traditional P-GaN HEMT. At the same time, a recessed region is formed in the barrier layer below the P-GaN layer. On the one hand, the gate control ability can be further improved by thinning the thickness of the barrier layer below the Fin-p-GaN. On the other hand, the device threshold voltage is jointly determined by the barrier layer thickness and the fin lateral dimension, reducing the dependence of the threshold voltage on the fin lateral dimension and the requirements for lateral process dimensions, which is beneficial to large-scale mass production;

[0034] In addition, there is a two-dimensional electron gas below the FET region, which can serve as a conductive channel and does not affect the concentration of the two-dimensional electron gas below the gate electrode in the on-state, that is, it has no impact on the on-state resistance. The introduction of the gate-cascaded FET structure does not sacrifice chip area and does not incur additional mass production costs.

[0035] Furthermore, in the present application, the p-GaN in the Fin-FET gate structure is connected to the source through an ohmic contact. The charges accumulated in the p-GaN layer due to gate voltage stress or off-state stress can be quickly replenished through the ohmic contact after the stress is removed. Therefore, the threshold voltage drift phenomenon can be suppressed and the operating stability of the device can be improved.

[0036] 2. In one example, the contact area between the P-GaN layer and the ohmic contact metal electrode connected to the source is large enough, and the suppression effect on the threshold voltage drift is more significant. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The following further details the specific embodiments of the present invention with reference to the drawings. The drawings described herein are used to provide a further understanding of the present application and form a part of the present application. The same reference numerals are used to represent the same or similar parts in these drawings. The schematic embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation of the present application.

[0038] Figure 1 Schematic diagram of the gate structure of a traditional p-GaN HEMT and its equivalent circuit model;

[0039] Figure 2 Schematic diagram of the p-GaN HEMT device structure of the recessed Fin-MOSFET gate structure of the present invention;

[0040] Figure 3Schematic diagram of the recessed Fin-MOSFET structure and its equivalent circuit model of the present invention;

[0041] In the figure: substrate - 1, buffer layer - 2, channel layer - 3, barrier layer - 4, ohmic contact metal electrode - 5, P-GaN layer - 6, dielectric layer - 7, gate electrode - 8, source electrode - 9, drain electrode - 10, two-dimensional electron gas - 11, recessed area - 13. Specific embodiments

[0042] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of them. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0043] In the description of the present invention, it should be noted that the directions or positional relationships indicated by terms such as "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present invention. In addition, the use of ordinal numbers (for example, "first and second", "first to fourth", etc.) is to distinguish objects and is not limited to this order, and should not be construed as indicating or implying relative importance.

[0044] In the description of the present invention, it should be noted that unless otherwise clearly specified and limited, the terms "installation", "connection", and "connection" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the internal communication of two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.

[0045] In addition, the technical features involved in different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0046] The present invention also includes a recessed Fin-MOSFET gate structure HEMT, as Figure 2 - Figure 3As shown, it includes an Si substrate 1, an AlN buffer layer 2, an i-GaN channel layer 3, and an AlGaN barrier layer 4 that are stacked and grown from bottom to top in the vertical direction of the device. Active electrodes 9 and drain electrodes 10 are grown oppositely on both sides of the channel layer 3. The source electrode 9 and the drain electrode 10 are both ohmic contact electrodes. The ohmic contact metal includes one or more of Ti, Al, Ni, and Au. In this example, the source electrode 9 and the drain electrode 10 are both sequentially selected as Ti / Al / Ni / Au, where the thickness of Ti is 20 nm, the thickness of Al is 120 nm, the thickness of Ni is 45 nm, and the thickness of Au is 55 nm. More specifically, the buffer layer 2 is 2 μm; the GaN channel layer 3 is 300 nm; the AlGaN barrier layer 4 is 12 nm, and the Al component ratio is 25%. A two-dimensional electron gas 11 is formed at the contact position between the GaN layer and the AlGaN barrier layer 4 to obtain an AlGaN / GaN heterojunction. A fin-type structure P-GaN layer 6 with a P-type doping concentration of 1×10 18 cm -3 is grown on the heterojunction. The fin height is 100 nm and the length is 80 nm. Further, a recessed area 13 is etched in the barrier layer below the P-GaN layer, and the depth is 1 nm to the thickness of the AlGaN barrier layer.

[0047] Further, an Ni / Au ohmic contact metal electrode 5 that is in ohmic contact with the P-GaN layer 6 is grown on the top of the fin of the P-GaN layer 6. The ohmic contact metal electrode 5 is connected to the source electrode; an SiO 2 dielectric layer 7 is grown on the ohmic contact metal electrode 5 and the sidewall of the fin of the P-GaN layer 6. The ohmic contact metal electrode 5 is isolated from the gate electrode 8 through the dielectric layer 7; an Ni / Au gate electrode 8 with a thickness of 200 nm is prepared on the surface of the dielectric layer 7 and the P-GaN layer 6, and the gate electrode 8 is a P-GaN Schottky contact electrode. In this way, a Fin-MOSFET is introduced into the p-GaN gate structure. The Fin-MOSFET shares a gate with the HEMT, and one end of the Fin-MOSFET is connected between an equivalent Schottky diode D SJ and a pin diode D pin , and the other end is connected to the source electrode 9 through an ohmic contact electrode. Among them, the material of the ohmic contact metal electrode 5 is Ni / Au, where the thickness of Ni is 20 nm and the thickness of Au is 20 nm. More specifically, in the regions between the source electrode 9 and the gate electrode 8, between the gate electrode 8 and the drain electrode 10, and on the surfaces of the gate electrode 8, the source electrode 9, and the drain electrode 10, an SiN passivation layer with a thickness of 50 nm is also deposited.

[0048] In this application, by introducing a normally-on Fin-MOSFET into the p-GaN gate structure, on the one hand, it can strengthen the control ability of the gate over the cascaded transistors. At the same gate voltage, the fin field-effect transistor is more likely to be pinched off, thus more easily controlling the device channel and improving the overall gate control ability of the device. On the other hand, the gate electrode 8 controls the potential of the P-GaN layer 6 by regulating the Fin-MOSFET switch and changes the concentration of the two-dimensional electron gas 11 in the channel, thereby achieving the purpose of controlling the switching of the HEMT device. At the same time, a recessed area 13 is formed in the barrier layer below the P-GaN layer. On the one hand, it can further improve the gate control ability by thinning the thickness of the barrier layer below p-GaN. On the other hand, the threshold voltage of the device is jointly determined by the barrier layer thickness and the fin lateral dimension, reducing the dependence of the threshold voltage on the fin lateral dimension and the requirements for lateral process dimensions, which is conducive to large-scale mass production. Therefore, the threshold voltage of the HEMT device can be regulated by changing the performance of the MOSFET device. Through reasonable size design (such as the width of the fins of the P-GaN layer 6, the thickness of the barrier layer, etc.) and doping concentration design, a higher HEMT threshold voltage can be obtained. At the same time, the electrons in the channel region still maintain a high mobility, and the concentration of the two-dimensional electron gas 11 in the non-channel region is not affected, ensuring the on-state characteristics of the device.

[0049] At the same time, there is a two-dimensional electron gas 11 below the Fin-MOSFET region introduced in this application, which can act as a conductive connection, without affecting the concentration of the two-dimensional electron gas 11 below the gate electrode 8 in the on-state, that is, it has no effect on the on-state resistance. The introduction of the gate-cascaded FET structure does not sacrifice chip area and does not increase the mass production cost additionally.

[0050] Furthermore, in the Fin-MOSFET gate structure of this application, p-GaN is connected to the source through an ohmic contact. The charges accumulated in the P-GaN layer 6 due to gate voltage stress or off-state stress can be quickly replenished through the ohmic contact after the stress is removed. Therefore, the threshold voltage drift phenomenon can be suppressed.

[0051] Furthermore, by introducing a normally-on Fin-MOSFET in this application, when no gate voltage is applied, the FET is in the on-state, and the entire p-GaN layer is at the same potential as the ohmic contact electrode, that is, connected to the source, and the voltage is 0V. Therefore, the device reverse conduction turn-on voltage V DS has no relation with the forward conduction threshold voltage of the device. In summary, when the HEMT of this application is in the off-state, the normally-on Fin-MOSFET clamps the potential of p-GaN at 0V. The reverse conduction voltage drop of the HEMT device has nothing to do with the forward conduction threshold voltage and does not increase with the increase of the forward conduction threshold voltage. Therefore, the device can achieve a small reverse conduction loss while obtaining a high threshold voltage.

[0052] Based on the same inventive concept as the above example of the recessed Fin-MOSFET gate structure HEMT, the present invention also includes a manufacturing method for the recessed Fin-MOSFET gate structure HEMT, comprising the following steps:

[0053] S1’: Grow a buffer layer 2, a GaN channel layer 3, and an AlGaN barrier layer 4 on a substrate 1 in sequence to form an AlGaN / GaN heterojunction; specifically, grow a buffer layer 2 with a thickness of 2 μm on a sapphire substrate 1 wafer; grow a 300-nm-thick GaN layer on the buffer layer 2; grow a 12-nm AlGaN barrier layer 4 on the GaN layer, where the Al component accounts for 25%.

[0054] S2’: Etch the barrier layer to form a barrier layer with a recessed region 13; specifically, spin-coat photoresist using a spin coater at a rotational speed of 5000 rpm to obtain a photoresist mask thickness of 0.8 μm; bake in a high-temperature oven at 80 °C for 10 min, and use an NSR1755I7A lithography machine for exposure to form a mask pattern for the Recessed region (recessed region 13); use a NETWON-type inductively coupled plasma etcher to etch the AlGaN barrier layer in a Cl 2 plasma at an etching rate of 1 nm / s, and the etching depth is 1 nm to the thickness of the AlGaN barrier layer.

[0055] S3’: Secondary epitaxially grow a P-GaN layer on the barrier layer with the recessed region 13, and the recessed region 13 is located below the P-GaN layer; specifically, use the MOCVD process to grow a 200-nm-thick GaN layer doped with Mg on the AlGaN barrier layer 4; perform thermal annealing in an N 2 atmosphere at 900 °C for 20 minutes to activate the doped Mg, and obtain a P-GaN layer 6 with a P-type doping concentration of 1×10 18 cm -3 .

[0056] S4’: Fabricate an ohmic contact metal electrode 5 on the surface of the P-GaN layer 6; specifically, bake in a high-temperature oven at 80 °C for 10 min, use an NSR1755I7A lithography machine for exposure to form a mask pattern for the P-GaN ohmic contact region; use an Ohmiker-50 electron beam evaporation platform to fabricate the P-GaN ohmic contact electrode at an evaporation rate of 0.1 nm / s. The ohmic contact metal electrode 5 is selected as Ni / Au, where the Ni thickness is 20 nm and the Au thickness is 20 nm; after evaporation, perform metal lift-off; then use an RTP500 rapid thermal annealing furnace to perform rapid thermal annealing in an O 2 atmosphere at 550 °C for 5 min to alloy the ohmic contact metal and complete the fabrication of the ohmic contact metal electrode 5.

[0057] S5’: Perform fin etching on the P-GaN layer 6 to form a fin-structured P-GaN layer 6. Specifically, using the p-GaN ohmic contact electrode as a hard mask, perform fin etching in Cl 2 plasma with an etching rate of 1 nm / s, and the etching depth is 100 nm.

[0058] S6’: Fabricate a dielectric layer 7 on the ohmic contact metal electrode 5 and the fin sidewalls. Specifically, use a PECVD790 deposition equipment with O 2 as the O source and SiH 4 as the Si source, with a deposition temperature of 250 °C, deposit a 20-nm-thick SiO 2 on the top layer, which serves as the isolation between the p-GaN ohmic contact and the gate electrode 8, and at the same time serves as the isolation between the fin sidewalls and the gate electrode 8, i.e., the gate dielectric of the parasitic MOSFET. Use a spin coater to spin-coat at a speed of 3500 rpm to obtain a photoresist mask; then use an NSR1755I7A lithography machine for exposure to form a mask pattern of the isolation dielectric; use an ICP98c-type inductively coupled plasma etching machine to etch and remove the 20-nm-thick SiO 4 layer in the CF 2 plasma at an etching rate of 0.5 nm / s in the area other than the fin sidewalls and the top, and finally remove the photoresist;

[0059] S7’: Fabricate a gate electrode 8 on the dielectric layer 7. Specifically, use a spin coater to spin-coat at a speed of 5000 rpm to obtain a photoresist mask with a thickness of 0.8 μm; bake it in a high-temperature oven at 80 °C for 10 min, use an NSR1755I7A lithography machine for exposure, and perform photolithography alignment to form a mask pattern of the gate area covering the entire gate; use an Ohmiker-50 electron beam evaporation platform to evaporate the gate metal at an evaporation rate of 0.1 nm / s, so that the gate metal covers the entire dielectric layer 7 and the surface of the P-GaN layer 6. The gate metal is sequentially selected as Ni / Au, where the thickness of Ni is 20 nm and the thickness of Au is 200 nm; after evaporation, perform metal lift-off to obtain a complete gate electrode 8.

[0060] S8’: Remove the P-GaN layer 6 outside the gate electrode 8 area. Specifically, use the gate electrode 8 as a hard mask, and use a NETWON-type inductively coupled plasma etching machine to etch and remove the P-GaN layer 6 outside the gate area in Cl 2 plasma at an etching rate of 0.5 nm / s;

[0061] S9’: Fabricate the source electrode 9 and the drain electrode 10 on the barrier layer with the recessed region 13. Specifically, spin-coat photoresist at a rotational speed of 5000 rpm using a spin coater to obtain a photoresist mask thickness of 0.8 μm; bake it in a high-temperature oven at 80 °C for 10 min, and use an NSR1755I7A lithography machine for exposure to form the source and drain region mask patterns; use an Ohmiker-50 electron beam evaporation platform to fabricate the source electrode 9 and the drain electrode 10 at an evaporation rate of 0.1 nm / s. The source and drain metals are successively selected as Ti / Al / Ni / Au, where the thickness of Ti is 20 nm, the thickness of Al is 120 nm, the thickness of Ni is 45 nm, and the thickness of Au is 55 nm; after the evaporation of the source and drain metals is completed, metal lift-off is performed; then use an RTP500 rapid thermal annealing furnace to perform rapid thermal annealing in an N 2 atmosphere at 870 °C for 30 s to alloy the ohmic contact metal and complete the fabrication of the source electrode 9 and the drain electrode 10.

[0062] S10’: Passivation protection; specifically, use a PECVD790 deposition device with NH 3 as the N source and SiH 4 as the Si source, with a deposition temperature of 250 °C, deposit a SiN layer with a thickness of 50 nm on the uppermost AlGaN barrier layer 4 to form passivation between the source electrode 9 and the gate electrode 8 and between the drain electrode 10 and the gate electrode 8. At the same time, the SiN layer is deposited on the surfaces of the source electrode 9, the drain electrode 10, and the gate electrode 8 to form a passivation layer, completing the passivation treatment.

[0063] S11’: Fabricate the electrode leads, including the steps of interconnect opening and interconnect lead fabrication. Specifically, the interconnect opening includes: spin-coat positive photoresist on the surface of the epitaxial material at a rotational speed of 5000 rpm to obtain a photoresist mask with a thickness of 0.8 μm, then bake it in a high-temperature oven at 80 °C for 10 min, and then use an NSR1755I7A lithography machine for lithography to obtain the electrode pattern; use an ICP98c inductively coupled plasma etching machine to etch and remove the 50-nm-thick SiN layer in the electrode region in a CF 4 plasma at an etching rate of 0.5 nm / s to form the interconnect opening. The interconnect lead fabrication includes: use a spin coater to spin-coat positive photoresist at a rotational speed of 5000 rpm; use an NSR1755I7A lithography machine for exposure to form the electrode lead mask pattern; use an Ohmiker-50 electron beam evaporation platform to evaporate the lead electrode metal on the substrate with the fabricated mask at an evaporation rate of 0.3 nm / s. The metal selected is Ti with a thickness of 20 nm and Au with a thickness of 200 nm; finally, after the evaporation of the lead electrode metal is completed, lift-off is performed to obtain the complete lead electrode.

[0064] The above specific embodiments are detailed descriptions of the present invention. It cannot be determined that the specific embodiments of the present invention are only limited to these descriptions. For those of ordinary skill in the technical field to which the present invention pertains, without departing from the concept of the present invention, several simple deductions and substitutions can still be made, which should all be regarded as falling within the protection scope of the present invention.

Claims

1. A recessed Fin-MOSFET gate structure HEMT, comprising a substrate, a buffer layer, a channel layer, a barrier layer, a P-GaN layer and a gate electrode which are stacked and grown from bottom to top along the vertical direction of the device. A heterojunction is formed between the channel layer and the barrier layer. Source electrodes and drain electrodes are grown oppositely on both sides of the channel layer. The source electrodes and the drain electrodes are both ohmic contact electrodes. It is characterized in that: Perform fin etching on the P-GaN layer to form a fin-structured P-GaN layer, deposit an insulating dielectric layer for isolation under the gate electrode, and form an equivalent Schottky diode D composed of the gate electrode and the P-GaN layer SJ A normally-on Fin-MOSFET controlled by the gate electrode voltage is connected in parallel at both ends. The Fin-MOSFET shares a gate with the HEMT, and one end of the Fin-MOSFET is connected to the equivalent Schottky diode D SJ and the pin diode D pin in between, and the other end is connected to the source electrode through an ohmic contact metal electrode; the pin diode D pin is composed of a P-GaN layer, a barrier layer, and a channel layer; There is a recessed area in the barrier layer below the P-GaN layer; An ohmic contact metal electrode, a dielectric layer and a gate electrode are grown on the P-GaN layer from bottom to top respectively. The ohmic contact metal electrode is grown on the fin surface of the P-GaN layer. The dielectric layer covers the ohmic contact metal electrode and the sidewalls of the P-GaN layer fins. The gate electrode covers the dielectric layer and the surface of the P-GaN layer; A recessed area is etched in the barrier layer below the P-GaN layer.

2. A recessed Fin-MOSFET gate structure HEMT according to claim 1, It is characterized in that: Passivation layers are deposited in the area between the source electrode and the gate electrode, the area between the gate electrode and the drain electrode, and on the surfaces of the gate electrode, the source electrode and the drain electrode.

3. A recessed Fin-MOSFET gate structure HEMT according to claim 1, It is characterized in that: The length of the fin structure is 30nm - 200nm, and the height is 60nm - 400nm.

4. A recessed Fin-MOSFET gate structure HEMT according to claim 1, It is characterized in that: The ohmic contact metal electrode is an alloy layer prepared from a first conductive material and a second conductive material. The first conductive material is one or a combination of more of Ti, Al, Ni, Au, Pd; the second conductive material is one or a combination of more of Ti, Al, Ni, Au, Pd.

5. A recessed Fin-MOSFET gate structure HEMT according to claim 1, It is characterized in that: The dielectric layer is Al 2 O 3 , SiO 2 , or SiNx 6. A manufacturing method of a recessed Fin-MOSFET gate structure HEMT according to any one of claims 1 - 5, It is characterized in that: It includes the following steps: Growing a buffer layer, a channel layer and a barrier layer on the substrate in sequence; Etching the barrier layer to form a barrier layer with a recessed area; Secondarily epitaxially growing a P-GaN layer on the barrier layer with the recessed area, and the recessed area is located below the P-GaN layer; Fabricating an ohmic contact metal electrode on the surface of the P-GaN layer; Performing fin etching on the P-GaN layer to form a fin structure P-GaN layer; Fabricating a dielectric layer on the ohmic contact metal electrode and the sidewalls of the P-GaN layer fins; Fabricating a gate electrode on the dielectric layer; Removing the P-GaN layer outside the gate electrode area; Fabricating source electrodes and drain electrodes on the barrier layer with the recessed area.

7. A manufacturing method of a recessed Fin-MOSFET gate structure HEMT according to claim 6, It is characterized in that: The method further includes a passivation protection step: Depositing a passivation layer on the barrier layer with the recessed area, and the passivation layer covers the area between the source electrode and the gate electrode, the area between the gate electrode and the drain electrode, and the surfaces of the gate electrode, the source electrode and the drain electrode.

8. The manufacturing method of a recessed Fin-MOSFET gate structure HEMT according to claim 6, characterized in that: the method further includes an electrode lead manufacturing step: manufacturing an electrode pattern; removing the passivation layer in the electrode area to form an interconnection opening; manufacturing a mask pattern for the electrode lead; performing lead electrode metal evaporation on the substrate with the mask fabricated, and finally performing stripping after the lead electrode metal evaporation is completed to obtain a complete lead electrode.

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