Control circuit and memory for charge pump

Abstract

The application relates to the technical field of charge pumps, and discloses a control circuit for a charge pump. The control circuit is provided with an anti-creeping unit, which disconnects the output control unit from the power supply when the input voltage changes from a high level to a low level, thereby avoiding the creeping caused by the backflow of the output voltage to the power supply and improving the stability of the output voltage. The application further discloses a memory.

Description

Technical Field

[0001] This application relates to the field of charge pump technology, and for example to a control circuit and memory for a charge pump. Background Technology

[0002] In recent years, charge pumps have been widely used. Charge pumps are ideal for low-power industrial, personal electronics, and telecommunications applications. Key features and benefits include: elimination of inductor problems and higher efficiency at lower input voltages.

[0003] In low-voltage charge pump designs, voltage multiplier circuits are often used to raise the potential of each stage of the charge pump.

[0004] In the process of implementing the embodiments of this disclosure, at least the following problems were found in the related art:

[0005] Traditional voltage doubler circuits have significant leakage current to the power supply at the moment of output high potential. Therefore, the output voltage of the voltage doubler circuit cannot be guaranteed to reach twice the power supply voltage. Summary of the Invention

[0006] To provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. This summary is not intended as a general commentary, nor is it intended to identify key / important components or describe the scope of protection of these embodiments, but rather as a prelude to the detailed description that follows.

[0007] This disclosure provides a control circuit and memory for a charge pump to improve the stability of the charge pump output voltage.

[0008] In some embodiments, the control circuit for the charge pump includes: an input control unit, an output control unit, and a leakage protection unit, wherein a first input terminal of the input control unit is electrically connected to an input voltage, and a second input terminal of the input control unit is electrically connected to a power supply voltage; the input terminal of the output control unit is connected to the output terminal of the input control unit via a pump capacitor, and the output control unit is configured to output an output voltage twice that of the power supply voltage; the input terminal of the leakage protection unit is electrically connected to the power supply voltage, and the output terminal of the leakage protection unit is connected to the second input terminal of the output control unit, and the leakage protection unit is configured to disconnect the output control unit from the power supply voltage when the input voltage changes from a high level to a low level.

[0009] Optionally, the input control unit specifically includes: a first PMOS transistor and a first NMOS transistor, wherein the gate of the first PMOS transistor is electrically connected to the input voltage, and the source of the first PMOS transistor is electrically connected to the power supply voltage; and the gate of the first NMOS transistor is electrically connected to the input voltage, the source of the first NMOS transistor is grounded, and the drain of the first NMOS transistor and the drain of the first PMOS transistor are jointly connected to the first terminal of the pump capacitor.

[0010] Optionally, the output control unit specifically includes: a second PMOS transistor, a third PMOS transistor, and a second NOMS transistor, wherein the gate of the second PMOS transistor is connected to the output terminal of the leakage protection unit, and the source of the second PMOS transistor is electrically connected to the power supply voltage; the gate of the third PMOS transistor is electrically connected to the input voltage, and the source of the third PMOS transistor and the drain of the second PMOS transistor are jointly connected to the second terminal of the pump capacitor; the gate of the second NOMS transistor is electrically connected to the power supply voltage, the source of the second NOMS transistor is grounded, and the drain of the second NOMS transistor and the drain of the third PMOS transistor are jointly connected to the output voltage of the output control unit.

[0011] Optionally, the leakage protection unit specifically includes: a third NMOS transistor and a fourth PMOS transistor, wherein the gate of the third NMOS transistor is electrically connected to the input voltage, and the source of the third NMOS transistor is grounded; the gate of the fourth PMOS transistor is electrically connected to the input voltage, the source of the fourth PMOS transistor is electrically connected to the power supply voltage through the second PMOS transistor, and the drain of the fourth PMOS transistor is electrically connected to the drain of the third NMOS transistor.

[0012] Optionally, the control circuit further includes an inverter, the input terminal of which is electrically connected to the input voltage, and the output terminal of which is connected to the input control unit, the output control unit, and the leakage protection unit.

[0013] Optionally, the input control unit is specifically configured to: when the input voltage is low, connect the first NMOS transistor to ground so that the first voltage at the first terminal of the pump capacitor is 0; when the input voltage changes from low to high, connect the first PMOS transistor to the power supply voltage so that the first voltage at the first terminal of the pump capacitor becomes the power supply voltage.

[0014] Optionally, the output control unit is specifically configured to: when the input voltage is low, connect the third NMOS transistor to ground, so that the second terminal of the pump voltage is connected to the power supply voltage through the second PMOS transistor, thereby making the second voltage of the second terminal of the pump voltage the power supply voltage.

[0015] Optionally, the leakage protection unit is specifically used to: when the input voltage changes from low level to high level, the fourth PMOS transistor is turned on, so that the second PMOS transistor is disconnected from the power supply voltage, preventing the second voltage at the second terminal of the pump capacitor from flowing to the power supply voltage.

[0016] In some embodiments, the memory includes: the control circuit for the charge pump described above, the input terminal of the control circuit being connected to a power supply terminal; and a storage array connected to the output terminal of the control circuit.

[0017] Optionally, the memory is an EEPROM memory.

[0018] The control circuit and memory for a charge pump provided in this disclosure can achieve the following technical effects:

[0019] By using the leakage protection unit, the connection between the output control unit and the power supply is disconnected when the input voltage changes from high level to low level, thereby avoiding leakage caused by the output voltage flowing back to the power supply voltage and improving the stability of the output voltage.

[0020] The above general description and the description below are exemplary and illustrative only and are not intended to limit this application. Attached Figure Description

[0021] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations and drawings do not constitute a limitation on the embodiments. Elements having the same reference numerals in the drawings are shown as similar elements. The drawings are not to be scaled. And wherein:

[0022] Figure 1 This is a schematic diagram of a voltage multiplier circuit.

[0023] Figure 2 This is a schematic diagram of another voltage multiplier circuit;

[0024] Figure 3 This is a schematic diagram of a control circuit for a charge pump provided in an embodiment of this disclosure;

[0025] Figure 4 This is a schematic diagram of another control circuit for a charge pump provided in an embodiment of this disclosure. Detailed Implementation

[0026] To provide a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for illustrative purposes only and are not intended to limit the embodiments of this disclosure. In the following technical description, for ease of explanation, several details are used to provide a full understanding of the disclosed embodiments. However, one or more embodiments may still be implemented without these details. In other cases, well-known structures and devices may be simplified in their depiction to simplify the drawings.

[0027] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this disclosure described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0028] In this disclosure, the terms "upper," "lower," "inner," "middle," "outer," "front," and "rear," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are primarily for better description of the embodiments of this disclosure and their implementations, and are not intended to limit the indicated devices, elements, or components to having a specific orientation, or to require them to be constructed and operated in a specific orientation. Furthermore, some of the aforementioned terms may be used to indicate other meanings besides orientation or positional relationship; for example, the term "upper" may in some cases indicate a dependency or connection relationship. Those skilled in the art can understand the specific meaning of these terms in the embodiments of this disclosure according to the specific circumstances.

[0029] Furthermore, the terms "set up," "connect," and "fix" should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral structure; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or it can be an internal connection between two devices, components, or parts. Those skilled in the art can understand the specific meaning of the above terms in the embodiments of this disclosure according to the specific circumstances.

[0030] Unless otherwise stated, the term "multiple" means two or more.

[0031] In this embodiment of the disclosure, the character " / " indicates that the objects before and after it are in an "or" relationship. For example, A / B means: A or B.

[0032] The term "and / or" describes an association between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or A and B.

[0033] It should be noted that, unless otherwise specified, the embodiments and features described in the present disclosure can be combined with each other.

[0034] As described in the background section, in related technologies, voltage multiplier circuits are often used to achieve the effect of the output voltage being twice the power supply voltage. Figure 1 This is a voltage multiplier circuit, such as Figure 1 As shown: The voltage multiplier circuit includes capacitor C pump The first terminal V0 is connected to the input control unit, and the other terminal V1 is connected to the output control unit. When the input voltage V... in When the voltage is low, V0 is grounded through the input control unit, and V1 is connected to the power supply voltage V through the output control unit. dd When the input voltage becomes high, V0 is connected to the power supply voltage V through the input control unit. dd Due to the characteristics of a capacitor, V1 is boosted to twice the voltage V. dd At this time, the output control unit disconnects from V. dd The connection ensures that the V1 voltage remains at twice the V. dd .

[0035] Specifically, Figure 2 This is a schematic diagram of a specific voltage multiplier circuit in related technologies. For example... Figure 2 As shown, when the input voltage V in When the voltage is low, the inverter outputs a high level. At this time, N1 is turned on, and V0 = 0. Simultaneously, N2 is turned on, and V... out =0, making P2 conduct, V I Connected to the power supply voltage, i.e., V1 = V dd .

[0036] When the input voltage V in When the voltage becomes high, it outputs a low level through the inverter. At this time, P1 is turned on, and V0 is connected to the power supply voltage, i.e., V0 = V dd The pressure difference is maintained at point V1, therefore V1 = 2 * V dd At the same time, P3 is turned on, causing V to... out =V1, and then P2 is turned off.

[0037] However, due to V out Become 2*V dd It will take some time, especially in V. load In the case of a larger value, V out The rate of increase is relatively slow, and P0 cannot be quickly turned off during this process, thus causing V1 to rise from V... dd Become 2*V dd A large instantaneous current sometimes flows back to V. dd This leads to Vout Voltage drop.

[0038] To prevent leakage, this embodiment connects a leakage protection unit to the output terminal of the capacitor in the voltage multiplier circuit. The leakage protection unit disconnects the connection between the capacitor's output terminal and the power supply the instant the voltage at the capacitor's output terminal rises to twice the power supply voltage, thus stabilizing the output voltage at twice the power supply voltage, effectively avoiding leakage and improving the stability of the output voltage.

[0039] Figure 3 This is a schematic diagram of a control circuit for a charge pump according to an embodiment of the present invention. See below for reference. Figure 3 The control circuit is described in detail.

[0040] like Figure 3 As shown, the control circuit for the charge pump includes: an input control unit 201, an output control unit 202, and a leakage protection unit 203.

[0041] The first input terminal of the input control unit 201 is connected to the input voltage V. in Electrically connected, the second input terminal of the input control unit 201 is connected to the power supply voltage V. dd Electrical connection;

[0042] The input terminal of the output control unit 202 is connected to the pump capacitor C. pump Connected to the output terminal of the input control unit 201, the output control unit 202 is configured to output twice the power supply voltage V. dd ; output voltage;

[0043] In this embodiment, the input terminal of the leakage protection unit 203 in the control circuit is connected to the power supply voltage V. dd Electrically connected, the output terminal of the leakage protection unit 203 is connected to the second input terminal of the output control unit 202, and the leakage protection unit 203 is configured to operate at the input voltage V. in When the output level changes from high to low, the output control unit 202 is disconnected from the power supply voltage V. dd The connection.

[0044] Thus, in the pump capacitor C pump The voltage value V1 at the second terminal is from V dd Become 2*V dd In an instant, the leakage protection unit 203 quickly shuts off the output control unit 202 from the power supply voltage V. dd To prevent voltage from flowing back to the power supply voltage V dd The resulting leakage current causes the output voltage V to... out Able to maintain 2*V dd .

[0045] Figure 4 This is a schematic diagram of another control circuit for a charge pump provided in this disclosure embodiment. Refer to the following... Figure 4 The control circuit is described in detail.

[0046] In this embodiment, the input control unit 201 specifically includes a first PMOS transistor P1 and a first NMOS transistor N1. The gate of the first PMOS transistor P1 is connected to the input voltage V. in Electrically connected, the source of the first PMOS transistor P1 is connected to the power supply voltage V. dd Electrical connection; and, the gate of the first NMOS transistor N1 is connected to the input voltage V. in Electrically connected, the source of the first NMOS transistor N1 is grounded, and the drain of the first NMOS transistor N1 and the drain of the first PMOS transistor P1 are connected to the first terminal V0 of the pump capacitor.

[0047] Optionally, the output control unit 202 specifically includes: a second PMOS transistor P2, a third PMOS transistor P3, and a second NMOS transistor N2. The gate of the second PMOS transistor P2 is connected to the output terminal of the leakage protection unit 203, and the source of the second PMOS transistor P2 is connected to the power supply voltage V. dd Electrical connection; the gate of the third PMOS transistor P3 is connected to the input voltage V. in Electrically connected, the source of the third PMOS transistor P3 and the drain of the second PMOS transistor P2 are both connected to the second terminal V1 of the pump capacitor; the gate of the second PMOS transistor N2 is connected to the power supply voltage V. dd Electrically connected, the source of the second NOMS transistor N2 is grounded, and the drain of the second NOMS transistor N and the drain of the third PMOS transistor P3 are connected together to the output voltage V of the output control unit 202. out .

[0048] Optionally, the aforementioned leakage protection unit 203 specifically includes: a third NMOS transistor N3 and a fourth PMOS transistor P4, wherein the gate of the third NMOS transistor N3 is connected to the input voltage V. in Electrically connected, the source of the third NMOS transistor N3 is grounded; the gate of the fourth PMOS transistor P4 is connected to the input voltage V. in Electrically connected, the source of the fourth PMOS transistor P4 is connected to the power supply voltage V through the second PMOS transistor P2. dd Electrical connection: the drain of the fourth PMOS transistor P4 is electrically connected to the drain of the third NMOS transistor N3.

[0049] Optionally, the control circuit further includes an inverter D, the input terminal of which is connected to the input voltage V.in Electrically connected, the output terminal of the inverter D is connected to the input control unit 201, the output control unit 202 and the leakage protection unit 203 respectively.

[0050] Optionally, the input control unit 201 is specifically configured to: when the input voltage V in When the input voltage V is low, the first NMOS transistor N1 is connected to ground, so that the first voltage at the first terminal V0 of the pump capacitor is 0; when the input voltage V in When the voltage changes from low to high, the first PMOS transistor P1 and the power supply voltage V dd Connect the circuit so that the first voltage at the first terminal V0 of the pump capacitor becomes the power supply voltage V. dd .

[0051] Optionally, the output control unit 202 is specifically configured to: when the input voltage V in When the voltage is low, the third NMOS transistor N3 is connected to ground, so that the second terminal V1 of the pump voltage is connected to the power supply voltage V through the second PMOS transistor P2. dd This connects the two terminals of the pump voltage V1, making the second voltage equal to the power supply voltage V. dd .

[0052] Optionally, the leakage protection unit 203 is specifically used to: when the input voltage V in When the voltage level changes from low to high, the fourth PMOS transistor P4 turns on, causing the second PMOS transistor P2 to disconnect from the power supply voltage V. dd The connection prevents the second voltage at the second terminal V1 of the pump capacitor from flowing to the power supply voltage V. dd .

[0053] In specific operation, at the input voltage V in During one signal cycle, the input voltage V in When the voltage level is low, inverter D outputs a high level. At this time, the first NMOS transistor N1 receives a high level and turns on, and the pump capacitor C... pump The first terminal V0 is grounded, and the voltage at point V0 is 0. Simultaneously, the gate of the third NMOS transistor N3 receives a high level and conducts, causing the gate of P2 to be grounded and P2 to conduct. This causes the second terminal V1 of the pump capacitor to be connected to the power supply voltage V. dd When connected, V0=0, V1=V dd .

[0054] When the input voltage V in When the voltage level changes to high, inverter D outputs a low level. At this time, the gate of the first PMOS transistor P1 receives a high level, causing P1 to conduct. The first terminal V0 of the pump capacitor is connected to the power supply voltage V.dd Connected, V0=V dd Due to the characteristic that the voltage across the pump capacitor cannot change abruptly, the voltage difference between the second terminal V1 and the first terminal V0 of the pump capacitor remains at V. dd That is, at this time V0=V dd V=2*V dd This achieves a doubling of voltage output.

[0055] Furthermore, the gate of the fourth PMOS transistor P4 receives a low level and turns on, causing the gate of P2 to connect to the second terminal V1 of the pump capacitor. At this time, the voltage of V1 is 2*V. dd Therefore, P2 is turned off instantaneously. In the control circuit of this embodiment, because the connection between the second PMOS transistor P2 and the power supply voltage is disconnected the instant the input voltage changes from low to high, it prevents the voltage at the second terminal V1 of the pump capacitor from flowing in reverse through the second PMOS transistor P2 to the power supply voltage V. dd The resulting leakage current improves circuit performance.

[0056] This invention also discloses a memory, which includes a control circuit for a charge pump as described in any of the above embodiments, the input terminal of which is connected to a power supply terminal; and a storage array, which is connected to the output terminal of the control circuit.

[0057] The control circuit for the charge pump provided in this embodiment can boost the lower power supply voltage received at its input terminal and output it, thereby providing a higher programming voltage for the memory array.

[0058] Specifically, the memory can be an EEPROM memory.

[0059] The foregoing description and accompanying drawings fully illustrate embodiments of the present disclosure to enable those skilled in the art to practice them. Other embodiments may include structural and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the order of operation may vary. Parts and features of some embodiments may be included or substituted for parts and features of other embodiments. Embodiments of the present disclosure are not limited to the structures described above and shown in the accompanying drawings, and various modifications and changes may be made without departing from its scope. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A control circuit for a charge pump, characterized in that, include: The system comprises an input control unit, an output control unit, and a leakage protection unit. The first input terminal of the input control unit is electrically connected to the input voltage, and the second input terminal of the input control unit is electrically connected to the power supply voltage. The input terminal of the output control unit is connected to the output terminal of the input control unit through a pump capacitor, and the output control unit is configured to output an output voltage twice that of the power supply voltage. The input terminal of the leakage protection unit is electrically connected to the power supply voltage, and the output terminal of the leakage protection unit is connected to the second input terminal of the output control unit. The leakage protection unit is configured to disconnect the output control unit from the power supply voltage when the input voltage changes from a high level to a low level. The input control unit specifically includes a first PMOS transistor and a first NMOS transistor, wherein, The gate of the first PMOS transistor is electrically connected to the input voltage, and the source of the first PMOS transistor is electrically connected to the power supply voltage; and, The gate of the first NMOS transistor is electrically connected to the input voltage, the source of the first NMOS transistor is grounded, and the drain of the first NMOS transistor and the drain of the first PMOS transistor are connected to the first terminal of the pump capacitor. The output control unit specifically includes: a second PMOS transistor, a third PMOS transistor, and a second NMOS transistor, wherein... The gate of the second PMOS transistor is connected to the output terminal of the leakage protection unit, and the source of the second PMOS transistor is electrically connected to the power supply voltage. The gate of the third PMOS transistor is electrically connected to the input voltage, and the source of the third PMOS transistor and the drain of the second PMOS transistor are connected together to the second terminal of the pump capacitor. The gate of the second NMOS transistor is electrically connected to the input voltage, the source of the second NMOS transistor is grounded, and the drain of the second NMOS transistor and the drain of the third PMOS transistor are connected together to the output voltage of the output control unit. Specifically, the leakage protection unit includes a third NMOS transistor and a fourth PMOS transistor. The gate of the third NMOS transistor is electrically connected to the input voltage, and the source of the third NMOS transistor is grounded. The gate of the fourth PMOS transistor is electrically connected to the input voltage, the source of the fourth PMOS transistor is electrically connected to the power supply voltage through the second PMOS transistor, and the drain of the fourth PMOS transistor is electrically connected to the drain of the third NMOS transistor.

2. The control circuit according to claim 1, characterized in that, The control circuit also includes: An inverter, the input terminal of which is electrically connected to the input voltage, and the output terminal of which is connected to the input control unit, the output control unit, and the leakage protection unit, respectively.

3. The control circuit according to claim 1, characterized in that, The input control unit is specifically used for: When the input voltage is low, the first NMOS transistor is connected to ground, so that the first voltage at the first terminal of the pump capacitor is 0; When the input voltage changes from low level to high level, the first PMOS transistor is connected to the power supply voltage, so that the first voltage at the first terminal of the pump capacitor becomes the power supply voltage.

4. The control circuit according to claim 1, characterized in that, The output control unit is specifically used for: When the input voltage is low, the third NMOS transistor is connected to ground, so that the second terminal of the pump capacitor is connected to the power supply voltage through the second PMOS transistor, thereby making the second voltage of the second terminal of the pump capacitor the power supply voltage.

5. The control circuit according to claim 1, characterized in that, The leakage protection unit is specifically used for: When the input voltage changes from low level to high level, the fourth PMOS transistor is turned on, so that the second PMOS transistor is disconnected from the power supply voltage, preventing the second voltage at the second terminal of the pump capacitor from flowing to the power supply voltage.

6. A control circuit for a charge pump, characterized in that, include: The system comprises an input control unit, an output control unit, and a leakage protection unit. The first input terminal of the input control unit is electrically connected to the input voltage, and the second input terminal of the input control unit is electrically connected to the power supply voltage. The input terminal of the output control unit is connected to the output terminal of the input control unit through a pump capacitor, and the output control unit is configured to output an output voltage twice that of the power supply voltage. The input terminal of the leakage protection unit is electrically connected to the power supply voltage, and the output terminal of the leakage protection unit is connected to the second input terminal of the output control unit. The leakage protection unit is configured to disconnect the output control unit from the power supply voltage when the input voltage changes from a high level to a low level. The input control unit specifically includes a first PMOS transistor and a first NMOS transistor, wherein, The gate of the first PMOS transistor is electrically connected to the input voltage, and the source of the first PMOS transistor is electrically connected to the power supply voltage; and, The gate of the first NMOS transistor is electrically connected to the input voltage, the source of the first NMOS transistor is grounded, and the drain of the first NMOS transistor and the drain of the first PMOS transistor are connected to the first terminal of the pump capacitor. Specifically, the input control unit is used for: When the input voltage is low, the first NMOS transistor is connected to ground, so that the first voltage at the first terminal of the pump capacitor is 0; When the input voltage changes from low level to high level, the first PMOS transistor is connected to the power supply voltage, so that the first voltage at the first terminal of the pump capacitor becomes the power supply voltage.

7. The control circuit according to claim 6, characterized in that, The output control unit specifically includes: a second PMOS transistor, a third PMOS transistor, and a second NMOS transistor, wherein... The gate of the second PMOS transistor is connected to the output terminal of the leakage protection unit, and the source of the second PMOS transistor is electrically connected to the power supply voltage. The gate of the third PMOS transistor is electrically connected to the input voltage, and the source of the third PMOS transistor and the drain of the second PMOS transistor are connected together to the second terminal of the pump capacitor. The gate of the second NMOS transistor is electrically connected to the input voltage, the source of the second NMOS transistor is grounded, and the drain of the second NMOS transistor and the drain of the third PMOS transistor are connected together to the output voltage of the output control unit.

8. A memory, characterized in that, include: The control circuit for a charge pump as described in any one of claims 1-7, wherein the input terminal of the control circuit is connected to the power supply terminal; as well as The storage array is connected to the output of the control circuit.

9. The memory according to claim 8, characterized in that, The memory is an EEPROM memory.

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