Relaxation oscillator and relaxation oscillation method

Abstract

The present application provides a relaxation oscillator and a relaxation oscillation method. The relaxation oscillator provided by the present application can include: a resistance-capacitance (RC) circuit configured to perform an RC charging operation to set a first voltage, perform an RC discharging operation to set a second voltage, and perform a reset operation to reset the first voltage to a first reference voltage and reset the second voltage to a second reference voltage; an integration capacitor; a sampling circuit configured to perform a charge transfer operation to sample a voltage difference between the first voltage and the second voltage and transfer the voltage difference to the integration capacitor; and a controllable oscillator configured to generate an output clock in response to a control input provided by the integration capacitor. The implementation of the embodiments of the present application realizes an ultra-low power relaxation oscillator design.

Description

Technical Field

[0001] This invention relates to an oscillator design, and more specifically, to a relaxation oscillator and related relaxation oscillation method that samples the voltage difference between the voltage generated by charging and discharging a resistor-capacitor (RC) circuit to control the output clock frequency of a controllable oscillator. Background Technology

[0002] Many electronic devices operate using one or more clocks. These clocks are typically generated using oscillators. Many different types of oscillators exist and can be implemented in various systems. A typical integrated circuit (IC) usually includes one or more on-chip oscillators to generate clock signals. For example, a relaxation oscillator can be used to generate an output clock with a target frequency. One characteristic of a relaxation oscillator is its ability to generate an output clock without requiring a reference clock. A typical relaxation oscillator design may include multiple current sources and / or a continuous comparator. However, a continuous comparator is a power-consuming component, and current sources generally have high quiescent current. Therefore, a typical relaxation oscillator design may not meet the requirements of low-power applications. Thus, an innovative ultra-low-power relaxation oscillator design is needed. Summary of the Invention

[0003] This invention provides a relaxation oscillator and a relaxation oscillation method.

[0004] The present invention provides a relaxation oscillator, which may include: a resistor-capacitor (RC) circuit configured to perform an RC charging operation to set a first voltage, an RC discharging operation to set a second voltage, and a reset operation to reset the first voltage to a first reference voltage and the second voltage to a second reference voltage; an integrating capacitor; a sampling circuit configured to perform a charge transfer operation to sample the voltage difference between the first voltage and the second voltage and to transmit the voltage difference to the integrating capacitor; and a controllable oscillator configured to generate an output clock in response to a control input provided by the integrating capacitor.

[0005] The present invention provides a relaxation oscillation method comprising: performing a resistor-capacitor (RC) charging operation to set a first voltage; performing an RC discharging operation to set a second voltage; performing a charge transfer operation to sample the voltage difference between the first voltage and the second voltage and transmit the voltage difference to an integrating capacitor; generating an output clock by a controllable oscillator in response to a control input provided by the integrating capacitor; and performing a reset operation to reset the first voltage to a first reference voltage and the second voltage to a second reference voltage.

[0006] As can be seen from the above, the embodiments of the present invention provide control input through an integrating capacitor and provide two voltages to sample the control input at the integrating capacitor, thereby realizing an ultra-low power relaxation oscillator design. Attached Figure Description

[0007] Figure 1 This is a block diagram illustrating the basic architecture of a relaxation oscillator according to an embodiment of the present invention.

[0008] Figure 2 This is a diagram illustrating the circuit design of a relaxation oscillator according to an embodiment of the present invention.

[0009] Figure 3 This is a waveform diagram illustrating the output clock, multiple switch control signals, and amplifier enable control signal according to an embodiment of the present invention.

[0010] Figure 4 This is a diagram illustrating a relaxation oscillator operating during the RC charging phase according to an embodiment of the present invention.

[0011] Figure 5 This is a diagram illustrating an RC charging operation according to an embodiment of the present invention.

[0012] Figure 6 This is a diagram illustrating a relaxation oscillator operating in the RC discharge stage according to an embodiment of the present invention.

[0013] Figure 7 This is a diagram illustrating the RC discharge operation according to an embodiment of the present invention.

[0014] Figure 8 This is a diagram illustrating a relaxation oscillator operating in the charge transport phase according to an embodiment of the present invention.

[0015] Figure 9 This is a diagram illustrating a charge transport operation according to an embodiment of the present invention.

[0016] Figure 10 This is a diagram illustrating a relaxation oscillator operating during a reset phase according to an embodiment of the present invention.

[0017] Figure 11 This diagram illustrates the situation where the frequency of the output clock generated by the relaxation oscillator deviates from the target frequency value.

[0018] Figure 12 This is a schematic diagram illustrating the case where the output clock frequency of a relaxation oscillator equals the target frequency value.

[0019] Figure 13 This is a flowchart illustrating a relaxation oscillation method according to an embodiment of the present invention. Detailed Implementation

[0020] Certain terms are used in the specification and claims to refer to specific components. Those skilled in the art will understand that hardware manufacturers may use different names to refer to the same component. This specification and claims do not distinguish components based on differences in name, but rather on differences in function. The terms "comprising" and "including" used throughout the specification and claims are open-ended and should be interpreted as "comprising but not limited to." "Substantially" or "approximately" means that within an acceptable margin of error, those skilled in the art can solve the technical problem and substantially achieve the technical effect within a certain margin of error. Furthermore, the terms "coupled" or "coupled" herein include any direct and indirect electrical connection means. Therefore, if a first device is described as coupled to a second device, it means that the first device can be directly electrically connected to the second device, or indirectly electrically connected to the second device through other devices or connection means. The following description is a preferred mode for carrying out the invention and is intended to illustrate the spirit of the invention rather than to limit the scope of protection of the invention. The scope of protection of the invention shall be determined by the claims.

[0021] The following description represents the preferred embodiments of the present invention. These descriptions are intended to set forth the general principles of the invention and not to limit it. The scope of protection of the present invention should be determined based on the claims.

[0022] Figure 1 This is a block diagram illustrating the basic architecture of a relaxation oscillator according to an embodiment of the present invention. The relaxation oscillator 100 includes a resistor-capacitor (RC) circuit 102, a sampling circuit 104, an integrating capacitor 106, a controllable oscillator 108, and a control signal generation circuit 110. The RC circuit 102 includes one or more resistors and one or more capacitors, and is arranged to perform an RC charging operation to set a voltage V. CN Perform an RC discharge operation to set another voltage V. CP And perform a reset operation to adjust the voltage V. CN Reset to a reference voltage (e.g., ground voltage GND) and set voltage V CP Reset to another reference voltage (e.g., supply voltage V) DD For example, RC circuit 102 can be implemented by a switching RC circuit. Sampling circuit 104 is used to perform charge transfer operation to sample voltage V. CN With V CPThe voltage difference ΔV between the two voltages is transmitted to the integrating capacitor 106. For example, the sampling circuit 104 can be implemented by a unity-gain amplifier for amplifying DC voltages. The controllable oscillator 108 is arranged to respond to a control input (e.g., voltage input V) provided by the integrating capacitor 106. INT The controllable oscillator 108 generates an output clock CKOUT. For example, the controllable oscillator 108 can be implemented by a voltage-controlled oscillator (VCO), and the frequency of the output clock CKOUT is controlled by the voltage input of the VCO. The control signal generation circuit 110 is arranged to generate a plurality of control signals to control the timing of operation of the circuit components included in the RC circuit 102 and the sampling circuit 104. For example, the control signal generation circuit 110 can generate a plurality of clock signals as a plurality of control signals with reference to the output clock CKOUT, wherein the frequency of each control signal is lower than the frequency of the output clock CKOUT.

[0023] In this embodiment, the controllable oscillator 108 uses the control input V provided by the integrating capacitor 106. INT The output clock CKOUT is generated. Therefore, the proposed relaxation oscillator 100 does not require a power-consuming continuous comparator. Furthermore, the RC circuit 102 is used to provide two voltages V. CN and V CP They sample the control input V used to control the integrating capacitor 106. INTThe voltage difference ΔV. Therefore, the proposed relaxation oscillator 100 does not require a current source with high quiescent current. With the RC circuit 102 implemented by a switching RC circuit, the switching RC circuit can operate at an RC switching frequency much lower than the output clock CKOUT frequency. Therefore, the power requirements of the switching RC circuit can be relaxed. Furthermore, the bandwidth and power requirements of the subsequent sampling circuit 104 can be relaxed. The control signal generated by the control signal generation circuit 110 can be a non-overlapping clock signal for non-overlapping phase control of the proposed relaxation oscillator 100. Therefore, the control signal generation circuit 110 can be implemented with simple power supply logic circuitry to save power. Furthermore, the circuit components of the RC circuit 102 and the sampling circuit 104 are active during the on-period (logic high) of the relevant control signal generated by the control signal generation circuit 110, and inactive during the off-period (logic low) of the relevant control signal generated by the control signal generation circuit 110. In other words, all circuit components of the RC circuit 102 and the sampling circuit 104 are not always operational, resulting in lower power consumption. In short, the relaxation oscillator 100 employs an ultra-low power relaxation oscillator design. Further details of the relaxation oscillator 100 are described with reference to the accompanying drawings.

[0024] Figure 2 This is a diagram illustrating the circuit design of a relaxation oscillator according to an embodiment of the present invention. The relaxation oscillator 200 is based on... Figure 1 The basic architecture of the relaxation oscillator 100 is shown. For example, Figure 1 The RC circuit 102 shown can be derived from... Figure 2 The switch RC circuit 202 shown is implemented as follows: Figure 1 The sampling circuit 104 shown can be derived from... Figure 2 The unity-gain amplifier 204 shown is implemented as follows: Figure 1 The integrating capacitor 106 shown can be made from Figure 2 The integrating capacitor C shown INT accomplish, Figure 1 The controllable oscillator 108 shown can be derived from... Figure 2 The VCO 206 implementation shown is as follows: Figure 1 The control signal generation circuit 110 shown can be generated by... Figure 2 The phase generator circuit 208 shown is implemented (labeled "Phase Gen.").

[0025] It should be noted that the use of a unity-gain amplifier 204 to implement the sampling circuit 104 is for illustrative purposes only and does not constitute a limitation of the present invention. In practice, any method capable of sampling the voltage difference between the voltages generated by RC charging and RC discharging and passing the sampled voltage difference to the subsequent integrating capacitor can be used to implement the sampling circuit 104. These alternative designs are all within the scope of protection of the present invention.

[0026] The switching RC circuit 202 includes a resistor R, multiple capacitors C1 and C2, and multiple switches SW1, SW2, SW3, SW4, SW5, SW6, SW7, SW8, SW9, SW10, SW11, SW12, SW13, and SW14. In this embodiment, the switching RC circuit 202 employs a two-phase RC charging / discharging method to save area. For example, the resistor R is used during the RC charging phase and reused during the RC discharging phase. However, this is for illustrative purposes only and does not imply limitation of the invention. Optionally, the switching RC circuit 202 can be modified to have one resistor and one capacitor used during the RC charging phase and another resistor and another capacitor used during the RC discharging phase.

[0027] Switches SW1-SW14 can be divided into several switch-based circuits. The switch-based circuits including switches SW1, SW4, and SW6 are controlled by the same switch control signal CK_P1. The switch-based circuits including switches SW2, SW10, and SW12 are controlled by the same switch control signal CK_P2. The switch-based circuits including switches SW5, SW7, SW11, and SW13 are controlled by the same switch control signal CK_P3. The switch-based circuits including switches SW3, SW8, SW9, and SW14 are controlled by the same switch control signal CK_RST. Furthermore, the unity-gain amplifier 204 is controlled by the amplifier enable control signal AMP_EN.

[0028] The switching RC circuit 202 is controlled by switching control signals CK_P1, CK_P2, CK_P3, and CK_RST, and the unity-gain amplifier 204 is controlled by the amplifier enable control signal AMP_EN, so that the relaxation oscillator 200 sequentially enters the RC charging stage, RC discharging stage, charge transfer stage, and reset stage. In the first stage (RC charging stage), an RC charging operation is performed at the switching RC circuit 202. In the second stage (RC discharging stage), an RC discharging operation is performed at the switching RC circuit 202. In the third stage (charge transfer stage), the unity-gain amplifier 204 performs a charge transfer operation. In the fourth stage (reset stage), the switching RC circuit 202 performs a reset operation. The first, second, third, and fourth stages may not overlap in the time domain. Figure 3This diagram illustrates the waveforms of the output clock CKOUT, switch control signals CK_P1, CK_P2, CK_P3, CK_RST, and amplifier enable control signal AMP_EN according to an embodiment of the present invention. The phase generator circuit 208 receives the output clock CKOUT and generates the switch control signals CK_P1, CK_P2, CK_P3, CK_RST, and amplifier enable control signal AMP_EN based on the output clock CKOUT. The frequency of each of the switch control signals CK_P1, CK_P2, CK_P3, CK_RST, and amplifier enable control signal AMP_EN is lower than the frequency of the output clock CKOUT. For example, the frequency of the output clock CKOUT is 32kHz, and the switch control signals CK_P1, CK_P2, CK_P3, CK_RST, and amplifier enable control signal AMP_EN are all clock signals with frequencies lower than 32kHz.

[0029] At the RC circuit 202, an RC charging operation is performed when the switch control signal CK_P1 is at a logic high level, and not when the switch control signal CK_P1 is at a logic low level. Specifically, switches SW1, SW4, and SW6 are switched on during the enable phase of the switch control signal CK_P1 (CK_P1 = 1) and switched off during the disable phase of the switch control signal CK_P1 (CK_P1 = 0). An RC charging operation is performed once every N clock cycles of the output clock CKOUT, where N is an integer greater than 1. Figure 3 As shown, an RC charging operation can be performed once every 16 clock cycles of the output clock CKOUT.

[0030] At switch RC circuit 202, an RC discharge operation is performed when the switch control signal CK_P2 is at a logic high level, and not when the switch control signal CK_P2 is at a logic low level. Specifically, switches SW2, SW10, and SW12 are turned on during the enable phase of switch control signal CK_P2 (CK_P2 = 1) and turned off during the disable phase of switch control signal CK_P2 (CK_P2 = 0). An RC discharge operation is performed once every N clock cycles of the output clock CKOUT, where N is an integer greater than 1. Figure 3 As shown, an RC discharge operation can be performed once every 16 clock cycles of the output clock CKOUT.

[0031] At unity-gain amplifier 204, a charge transfer operation is performed when the switch control signal CK_P3 is at a logic high level, and not when the switch control signal CK_P3 is at a logic low level. Specifically, switches SW5, SW7, SW11, and SW13 are turned on during the enable phase of the switch control signal CK_P3 (CK_P3 = 1) and turned off during the disable phase of the switch control signal CK_P3 (CK_P3 = 0). A charge transfer operation is performed once every N clock cycles of the output clock CKOUT, where N is an integer greater than 1. Figure 3 As shown, a charge transfer operation can be performed once every 16 clock cycles of the output clock CKOUT.

[0032] At switch RC circuit 202, a reset operation is performed when the switch control signal CK_RST is at a logic high level, and not when the switch control signal CK_RST is at a logic low level. Specifically, switches SW3, SW8, SW9, and SW14 are turned on during the enable phase of the switch control signal CK_RST (CK_RST = 1) and turned off during the disable phase of the switch control signal CK_RST (CK_RST = 0). A reset operation is performed every N clock cycles of the output clock CKOUT, where N is an integer greater than 1. Figure 3 As shown, a reset operation can be performed once every 16 clock cycles of the output clock CKOUT.

[0033] Regarding the unity-gain amplifier 204, it is responsible for processing the voltage difference ΔV (ΔV = V). CN -V CP The signal is transferred from the preceding switching RC circuit 202 to the following integrating capacitor C. INTThe charge transfer operation is performed. The turn-on phase of the amplifier enable control signal AMP_EN overlaps with the turn-on phase of the switch control signal CK_P3, and the turn-on phase of the amplifier enable control signal AMP_EN is not shorter than the turn-on phase of the switch control signal CK_P3. To ensure stable operation of the unity-gain amplifier 204 during the charge transfer operation, the start time of the turn-on phase of the amplifier enable control signal AMP_EN can be intentionally advanced to earlier than the start time of the turn-on phase of the switch control signal CK_P3, and the end time of the turn-on phase of the amplifier enable control signal AMP_EN can be internally delayed to later than the end time of the turn-on phase of the switch control signal CK_P3. In this embodiment, one turn-on phase of the amplifier enable control signal AMP_EN lasts for 11 clock cycles of the output clock CKOUT (approximately 70% of the 16 clock cycles of the output clock CKOUT). In other words, the unity-gain amplifier 204 can be controlled by the amplifier enable control signal AMP_EN with a 70% duty cycle to save power. However, this is for illustrative purposes only and does not imply limitation of the invention. Furthermore, the enable phase of the amplifier enable control signal AMP_EN does not overlap with any of the enable phases of the switch control signals CK_P1, CK_P2, and CK_RST.

[0034] The relaxation oscillator 200 can sequentially and repeatedly enter four stages (including RC charging stage, RC discharging stage, charge transfer stage and reset stage) to reduce the frequency offset of the output clock CKOUT and to make the frequency of the output clock CKOUT have the target frequency value. Figure 4 This is a schematic diagram of a relaxation oscillator 200 operating in the RC charging phase according to an embodiment of the present invention. Switches SW1, SW4, and SW6 are turned on by switch control signal CK_P1 (CK_P1 = 1). Switches SW2, SW10, and SW12 are turned off by switch control signal CK_P2 (CK_P2 = 0), causing one end of resistor R to be disconnected from the reference voltage GND, and the other end to be disconnected from one plate of capacitor C2, and the other plate of capacitor C2 to be disconnected from the reference voltage GND. Switches SW5, SW7, SW11, and SW13 are turned off by switch control signal CK_P3 (CK_P3 = 0), causing both plates of capacitor C1 and both plates of capacitor C2 to be disconnected from the unity-gain amplifier 204. Switches SW3, SW8, SW9, and SW14 are turned off by the switch control signal CK_RST (CK_RTS = 0), causing one plate of capacitor C1 to be disconnected from the reference voltage GND, and the other plate of capacitor C1 to also be disconnected from the reference voltage GND. One plate of capacitor C2 is connected to the reference voltage V. DDThe capacitor is disconnected, and the other plate of capacitor C2 is disconnected from the reference voltage GND. Furthermore, unity-gain amplifier 204 is disabled by the amplifier enable control signal AMP_EN (AMP_EN = 0).

[0035] During the RC charging operation, one end of resistor R is connected to the reference voltage V. DD The other end of resistor R is connected to one plate of capacitor C1, and the other plate of capacitor C1 is connected to the reference voltage GND. Therefore, the voltage V across one plate of capacitor C1 is... CN Charging begins from an initial voltage level (e.g., reference voltage GND) via an RC charging operation. Figure 5 This diagram illustrates an RC charging operation according to an embodiment of the present invention. Integrating capacitor C INT Disconnect capacitors C1 and C2. Therefore, the integrating capacitor C... INT The control input V on one of the plates INT Unaffected by RC charging operation and remaining unchanged. VCO 206 responds to the integrating capacitor C. INT Maintained control input V INT The output clock CKOUT is generated. Phase generator 208 generates a switch control signal CK_P1 based on the output clock CKOUT, where the length T of the on-state phase of the switch control signal CK_P1 depends on the frequency of the output clock CKOUT. Specifically, the length T of the on-state phase of the switch control signal CK_P1 is inversely proportional to the frequency of the output clock CKOUT. At the end of the RC charging operation, the voltage V on one plate of capacitor C1... CN It can be expressed by the following formula.

[0036]

[0037] In formula (1) above, The target voltage level, V, represents zero frequency deviation. OS1 This represents the offset caused by frequency shift.

[0038] Figure 6 This diagram illustrates a relaxation oscillator 200 operating in the RC discharge phase according to an embodiment of the present invention. Switches SW2, SW10, and SW12 are turned on by switch control signal CK_P2 (CK_P2 = 1). Switches SW1, SW4, and SW6 are turned off by switch control signal CK_P1 (CK_P1 = 0), causing one end of resistor R to be connected to the reference voltage V. DDWhen the capacitor is open, the other end of resistor R is disconnected from one plate of capacitor C1, and the other plate of capacitor C1 is disconnected from the reference voltage GND. Switches SW5, SW7, SW11, and SW13 are turned off by the switch control signal CK_P3 (CK_P3 = 0), causing both plates of capacitor C1 and both plates of capacitor C2 to be disconnected from the unity-gain amplifier 204. Switches SW3, SW8, SW9, and SW14 are turned off by the switch control signal CK_RST (CK_RTS = 0), causing one plate of capacitor C1 to be disconnected from the reference voltage GND, and the other plate of capacitor C1 to also be disconnected from the reference voltage GND. One plate of capacitor C2 is connected to the reference voltage V. DD The capacitor is disconnected, and the other plate of capacitor C2 is disconnected from the reference voltage GND. Furthermore, unity-gain amplifier 204 is disabled by the amplifier enable control signal AMP_EN (AMP_EN = 0).

[0039] During the RC discharge operation, one end of resistor R is connected to the reference voltage GND, and the other end of resistor R is connected to one plate of capacitor C2. The other plate of capacitor C2 is also connected to the reference voltage GND. Therefore, the voltage V across one plate of capacitor C2 is... CP The voltage level is reduced from the initial voltage level (e.g., reference voltage V) through an RC discharge operation. DD Discharge begins. Figure 7 This diagram illustrates the RC discharge operation according to an embodiment of the present invention. Integrating capacitor C INT Disconnect capacitors C1 and C2. Therefore, the integrating capacitor C... INT The control input V on one of the plates INT Unaffected by RC discharge operation and remaining unchanged. VCO 206 responds to the integrator C. INT Maintained control input V INT The output clock CKOUT is generated. Phase generator 208 generates a switch control signal CK_P2 based on the output clock CKOUT, where the length T of the on-state phase of switch control signal CK_P2 is equal to the length T of the on-state phase of switch control signal CK_P1, and also depends on the frequency of the output clock CKOUT. At the end of the RC discharge operation, the voltage V on one plate of capacitor C2... CP It can be expressed by the following formula.

[0040]

[0041] In formula (2) above, The target voltage level, V, represents the zero-frequency offset. OS2 This represents the offset caused by frequency shift.

[0042] After the RC charging and RC discharging phases are completed, the relaxation oscillator 200 enters the charge transfer phase. If the current frequency of the output clock CKOUT is equal to the target frequency value, the voltage V obtained at the end of the RC charging operation is... CN and the voltage V obtained at the end of the RC discharge operation CP They should be at the same voltage level (e.g., If the voltage V obtained at the end of the RC charging operation CN The voltage V obtained at the end of the RC discharge operation CP If the frequency is different, it indicates that the current frequency of the output clock CKOUT deviates from the target frequency value, and the control input V should be adjusted. INT To compensate for frequency shift. For example... Figure 5 and Figure 7 As shown, in this embodiment, the voltage V obtained at the end of the RC charging operation is... CN The voltage V obtained at the end of the RC discharge operation CP There is a voltage difference ΔV (ΔV = V) CN -V CP =V OS1 +V OS2 The relaxation oscillator 200 enters the charge transfer phase to transfer the voltage difference ΔV to the integrating capacitor C. INT It should be noted that the voltage difference ΔV can be positive or negative, depending on the length T of the turn-on phase of the switch control signals CK_P1 / CK_P2 (i.e., the frequency offset direction of the output clock CKOUT).

[0043] Figure 8 This diagram illustrates a relaxation oscillator 200 operating in the charge transport phase according to an embodiment of the present invention. Switches SW5, SW7, SW11, and SW13 are turned on by switch control signal CK_P3 (CK_P3 = 1). Switches SW1, SW4, and SW6 are turned off by switch control signal CK_P1 (CK_P1 = 0), such that one end of resistor R is connected to the reference voltage V. DD When the capacitor is open, the other end of resistor R is disconnected from one plate of capacitor C1, and the other plate of capacitor C1 is disconnected from the reference voltage GND. Switches SW2, SW10, and SW12 are turned off by the switch control signal CK_P2 (CK_P2 = 0), causing one end of resistor R to be disconnected from the reference voltage GND, and the other end of resistor R to be disconnected from one plate of capacitor C2, and the other plate of capacitor C2 to be disconnected from the reference voltage GND. Switches SW3, SW8, SW9, and SW14 are turned off by the switch control signal CK_RST (CK_RST = 0), causing one plate of capacitor C1 to be disconnected from the reference voltage GND, and the other plate of capacitor C1 to be disconnected from the reference voltage GND, while one plate of capacitor C2 is disconnected from the reference voltage V. DDWhen disconnected, the other plate of capacitor C2 is disconnected from the reference voltage GND. Furthermore, unity-gain amplifier 204 is enabled by the amplifier enable control signal AMP_EN (AMP_EN = 1).

[0044] During the charge transfer operation of the unity-gain amplifier 204, one plate of capacitor C1 and one plate of capacitor C2 are both connected to the inverting input (-) of the unity-gain amplifier 204, and the other plates of capacitor C1 and C2 are both connected to the output of the unity-gain amplifier 204, where the output of the unity-gain amplifier 204 is coupled to the non-inverting input (+). Since the two plates of capacitor C1 are coupled to the output and inverting input of the unity-gain amplifier 204 respectively, the unity-gain amplifier 204 operates such that the voltage levels of the two plates of capacitor C1 are the same, meaning that the charge stored in capacitor C1 will be removed. Similarly, since the two plates of capacitor C2 are coupled to the output and inverting input of the unity-gain amplifier 204, the unity-gain amplifier 204 operates such that the two plates of capacitor C2 have the same voltage level, meaning that the charge stored in capacitor C2 will be removed. In this embodiment, since the charge in capacitors C1, C2 and C... INT The voltage difference is redistributed between them by the voltage difference ΔV (ΔV = V). CN -V CP =V OS1 +V OS2 The charge difference ΔQ (ΔQ=ΔV / C) generated INT ) is applied to the integrating capacitor C INT .

[0045] Figure 9 This diagram illustrates charge transfer operation according to an embodiment of the present invention. Capacitors C1 and C2 can be configured to have the same capacitance value C. When switches SW5, SW7, SW11, and SW13 are turned on, the output of the unity-gain amplifier 204 remains at the integrating capacitor C. INT Control input V at the output terminal INT Therefore, as Figure 9 The upper part shows the bottom plate voltage V of capacitors C1 and C2. BOT By the same control input V INT Settings (V) BOT =V INT At this point, the top plate voltage of capacitor C1 becomes... The voltage across the top plate of capacitor C2 becomes Next, in capacitors C1, C2, C INTCharge redistribution occurs between them, making The energy is transferred from capacitor C1 to capacitor C2, C·V OS1 From the integrating capacitor C INT Transferred to capacitor C1, C·V OS2 From the integrating capacitor C INT Transferred to capacitor C2. (As shown) Figure 9 As shown in the lower half, after the charge redistribution is complete, in the integrating capacitor C INT The control input V is maintained at the location INT Updated to V INT,2 (V INT,2 =V INT -C·(V OS1 +V OS2 ) / C INT Additionally, the unity-gain amplifier 204 is connected via the same control input V. INT，2 Set the base voltage V for capacitors C1 and C2 BOT Due to the integrating capacitor C INT The control input V is maintained at the location INT The charge transfer operation performed by the unity-gain amplifier 204 is adjusted, so the VCO 206 responds to the updated control input V. INT,2 This is used to adjust the frequency of the output clock CKOUT. For example, when the voltage difference ΔV (ΔV = V) is... CN -V CP When the voltage difference ΔV is positive, VCO 206 can reduce the frequency of the output clock CKOUT. For example, when the voltage difference ΔV (ΔV = V...) is positive... CN -V CP When the value is negative, VCO 206 can increase the frequency of the output clock CKOUT.

[0046] After the charge transfer phase is completed, the relaxation oscillator 200 enters the reset phase to reset the voltage V. CN Reset to the initial voltage level (e.g., reference voltage GND) and set voltage V CP Reset to the initial voltage level (e.g., reference voltage V) DD This will be used for the next round of frequency offset detection and calibration. Figure 10 This diagram illustrates a relaxation oscillator 200 operating during a reset phase according to an embodiment of the present invention. Switches SW3, SW8, SW9, and SW14 are turned on by the switch control signal CK_RST (CK_RST = 1). Switches SW1, SW4, and SW6 are turned off by the switch control signal CK_P1 (CK_P1 = 0), causing one end of resistor R to be connected to the reference voltage V. DDWhen the capacitor is open, the other end of resistor R is disconnected from one plate of capacitor C1, and the other plate of capacitor C1 is disconnected from the reference voltage GND. Switches SW2, SW10, and SW12 are turned off by the switch control signal CK_P2 (CK_P2 = 0), causing one end of resistor R to be disconnected from the reference voltage GND, and the other end of resistor R to be disconnected from one plate of capacitor C2, and the other plate of capacitor C2 to be disconnected from the reference voltage GND. Switches SW5, SW7, SW11, and SW13 are turned off by the switch control signal CK_P3 (CK_P3 = 0), causing both plates of capacitor C1 and both plates of capacitor C2 to be disconnected from the unity-gain amplifier 204. Furthermore, the unity-gain amplifier 204 is disabled by the amplifier enable control signal AMP_EN (AMP_EN = 0).

[0047] During the reset operation of the RC switch circuit 202, one plate of capacitor C1 is connected to the reference voltage GND, the other plate of capacitor C1 is connected to the reference voltage GND, and one plate of capacitor C2 is connected to the reference voltage V. DD The other plate of capacitor C2 is connected to the reference voltage GND. Therefore, during the reset operation, the voltage V CN Discharge to reference voltage GND, and voltage V CP Charge to reference voltage V DD At the end of the reset operation, the voltage V CN Equal to reference voltage GND, voltage V CP Equal to reference voltage V DD After the reset phase is completed, the relaxation oscillator 200 re-enters four phases (including RC charging phase, RC discharging phase, charge transfer phase, and reset phase) to reduce / eliminate any frequency offset that the output clock CKOUT still has.

[0048] The frequency offset of the output clock CKOUT reflects the voltage V obtained at the end of the RC charging operation. CN The voltage V obtained at the end of the RC discharge operation CP The voltage difference ΔV (ΔV = V) between them CN -V CP Therefore, in order to reduce the non-zero frequency offset of the output clock CKOUT indicated by the non-zero voltage difference ΔV, the control input V of VCO 206 needs to be adjusted by the non-zero voltage difference ΔV. INT . Figure 11 This is a schematic diagram illustrating the situation where the frequency of the output clock CKOUT deviates from the target frequency value. Figure 12This diagram illustrates the scenario where the frequency of the output clock CKOUT equals the target frequency. Assuming the current frequency of the output clock CKOUT is higher than the target frequency, the on-state of the switch control signals CK_P1 / CK_P2 is equal to T1, which is shorter than T2. ​​Therefore, the voltage V obtained at the end of the RC charging operation... CN The voltage V obtained at the end of the RC discharge operation CP There exists a positive voltage difference ΔV, i.e., ΔV = V. CN -V CP >0. Positive voltage difference ΔV (ΔV=ΔQ / C) INT It is transferred to the integrating capacitor C. INT Therefore, from the current control input V INT Subtracting the positive voltage difference ΔV from the middle results in an updated control input V. INT,2 It has a lower voltage level. It responds to the updated control input V. INT,2 VCO 206 generates an output clock CKOUT with a lower frequency, which increases the on-state of the switching control signals CK_P1 / CK_P2. Assume the updated control input V fed into VCO 206... INT,2 Under the control of [unclear], the frequency of the output clock CKOUT is equal to the target frequency value. Since the turn-on phase of the switch control signals CK_P1 / CK_P2 is equal to T2, the voltage V obtained at the end of the RC charging operation is [unclear]. CN The voltage V obtained at the end of the RC discharge operation CP There is no voltage difference ΔV (ΔV=0) between them, therefore no current control input V is applied. INT (V INT =V INT,2 Adjust the voltage.

[0049] Figure 13 This is a flowchart illustrating a relaxation oscillation method according to an embodiment of the present invention. The relaxation oscillation method can be implemented by a relaxation oscillator 100 / 200. If the results are substantially the same, it is not necessary to follow the procedure. Figure 13 The steps are performed in the exact order shown. In step 1302, a resistor-capacitor (RC) charging operation is performed to set a first voltage. In step 1304, an RC discharging operation is performed to set a second voltage. In step 1306, a charge transfer operation is performed to sample the voltage difference between the first and second voltages and transfer this voltage difference to an integrating capacitor. In step 1308, in response to the control input provided by the integrating capacitor, an output clock is generated at the controllable oscillator. In step 1310, a reset operation is performed to reset the first voltage to a first reference voltage and the second voltage to a second reference voltage. Since those skilled in the art can readily understand the details of each step after reading the above paragraphs concerning the relaxation oscillator 100 / 200, further descriptions are omitted here for brevity.

[0050] In the above embodiments, an RC charging operation (RC charging phase) is followed by an RC discharging operation (RC discharging phase). However, this is for illustrative purposes only and does not imply limitation of the invention. Alternatively, an RC discharging operation (RC discharging phase) can be followed by an RC charging operation (RC charging phase), which also achieves the same generated voltage V. CN and V CP This is intended to indicate the frequency state of the output clock CKOUT before the charge transfer operation (charge transfer) is performed. This alternative design also falls within the scope of this invention.

[0051] While the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the scope of the invention. Any person skilled in the art can make some modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention shall be determined by the claims.

Claims

1. A relaxation oscillator, characterized in that, include: A resistor-capacitor circuit is configured to perform a resistor-capacitor charging operation to set a first voltage, perform a resistor-capacitor discharging operation to set a second voltage, and perform a reset operation to reset the first voltage to a first reference voltage and the second voltage to a second reference voltage; Integrating capacitor; The sampling circuit is configured to perform a charge transfer operation to sample the voltage difference between the first voltage and the second voltage and transmit the voltage difference to the integrating capacitor; and A controllable oscillator is configured to generate an output clock in response to a control input provided by the integrating capacitor; Specifically, the resistor-capacitor charging operation is performed in the first stage; the resistor-capacitor discharging operation is performed in the second stage; the charge transfer operation is performed in the third stage; and the reset operation is performed in the fourth stage; and the first, second, third and fourth stages are non-overlapping stages.

2. The relaxation oscillator as described in claim 1, characterized in that, This resistor-capacitor circuit is a switched resistor-capacitor circuit, which includes: A resistor; A first capacitor includes plates that maintain the first voltage; The second capacitor includes plates that maintain the second voltage; and One-switch network; During the resistor-capacitor charging operation, the switching network is configured to connect the resistor to the first capacitor and disconnect the resistor from the second capacitor; during the resistor-capacitor discharging operation, the switching network is configured to connect the resistor to the second capacitor and disconnect the resistor from the first capacitor.

3. The relaxation oscillator as described in claim 2, characterized in that, The switching network includes: A switch-based circuit, wherein during the resistor-capacitor charging operation, is configured to connect one end of the resistor to the second reference voltage, the other end of the resistor to the plate of the first capacitor, and the other plate of the first capacitor to the first reference voltage; and during the non-resistor-capacitor charging operation, the switch-based circuit is configured to disconnect one end of the resistor from the second reference voltage, disconnect the other end of the resistor from the plate of the first capacitor, and disconnect the other plate of the first capacitor from the first reference voltage.

4. The relaxation oscillator as described in claim 3, characterized in that, Also includes: A control signal generation circuit is configured to generate a switch control signal according to the output clock and provide the switch control signal to the switch-based circuit, wherein the frequency of the switch control signal is lower than the frequency of the output clock.

5. The relaxation oscillator as described in claim 2, characterized in that, The switching network includes: A switch-based circuit, wherein during the resistor-capacitor discharge operation phase, the switch-based circuit is configured to connect one end of the resistor to the first reference voltage, the other end of the resistor to the plate of the second capacitor, and the other plate of the second capacitor to the first reference voltage; and during the phase when the resistor-capacitor discharge operation is not performed, the switch-based circuit is configured to disconnect one end of the resistor from the first reference voltage, disconnect the other end of the resistor from the plate of the second capacitor, and disconnect the other plate of the second capacitor from the first reference voltage.

6. The relaxation oscillator as described in claim 5, characterized in that, Also includes: A control signal generation circuit is configured to generate a switch control signal according to the output clock and provide the switch control signal to the switch-based circuit, wherein the frequency of the switch control signal is lower than the frequency of the output clock.

7. The relaxation oscillator as described in claim 2, characterized in that, The switching network includes: A switch-based circuit, wherein during the phase of performing the charge transfer operation, the switch-based circuit is configured to connect the first capacitor's plate, the other plate of the first capacitor, the second capacitor's plate, and the other plate of the second capacitor to the sampling circuit; and during the phase of not performing the charge transfer operation, the switch-based circuit is configured to disconnect the first capacitor's plate, the other plate of the first capacitor, the second capacitor's plate, and the other plate of the second capacitor from the sampling circuit.

8. The relaxation oscillator as described in claim 7, characterized in that, Also includes: A control signal generation circuit is configured to generate a switch control signal according to the output clock and provide the switch control signal to the switch-based circuit, wherein the frequency of the switch control signal is lower than the frequency of the output clock.

9. The relaxation oscillator as described in claim 7, characterized in that, The sampling circuit includes: A unity-gain amplifier includes a non-inverting input, an inverting input, and an output, wherein the output is coupled to the non-inverting input and the inverting input is coupled to the integrating capacitor. During the charge transfer operation, the switch-based circuit is configured to connect the plate of the first capacitor and the other plate of the second capacitor to the inverting input of the unity-gain amplifier, and is further configured to connect the other plate of the first capacitor and the plate of the second capacitor to the output of the unity-gain amplifier; and During the phase when the charge transfer operation is not performed, the switch-based circuit is configured to disconnect the plate of the first capacitor and the other plate of the second capacitor from the inverting input of the unity-gain amplifier, and is also configured to disconnect the other plate of the first capacitor and the plate of the second capacitor from the output of the unity-gain amplifier.

10. The relaxation oscillator as described in claim 9, characterized in that, The inverting input of the unity-gain amplifier is coupled to one plate of the integrating capacitor, the other plate of the integrating capacitor is coupled to the first reference voltage, and the control input of the controllable oscillator is held on the plate of the integrating capacitor.

11. The relaxation oscillator as described in claim 9, characterized in that, The unity-gain amplifier is turned on during the charge transfer operation, and is disabled during the resistor-capacitor charging operation, the resistor-capacitor discharging operation, and the reset operation.

12. The relaxation oscillator as described in claim 9, characterized in that, Also includes: A control signal generation circuit is configured to generate an amplifier enable control signal according to the output clock and provide the amplifier enable control signal to the unity-gain amplifier, wherein the frequency of the amplifier enable control signal is lower than the frequency of the output clock.

13. The relaxation oscillator as described in claim 2, characterized in that, The switching network includes: A switch-based circuit, wherein during the phase of performing the reset operation, the switch-based circuit is configured to connect one plate of the first capacitor to the first reference voltage, the other plate of the first capacitor to the first reference voltage, one plate of the second capacitor to the second reference voltage, and the other plate of the second capacitor to the first reference voltage; and during the phase of not performing the reset operation, the switch-based circuit is configured to disconnect one plate of the first capacitor from the first reference voltage, the other plate of the first capacitor from the first reference voltage, one plate of the second capacitor from the second reference voltage, and the other plate of the second capacitor from the first reference voltage.

14. The relaxation oscillator as described in claim 13, characterized in that, Also includes: A control signal generation circuit is configured to generate a switch control signal based on an output clock and provide the switch control signal to the switch-based circuit, wherein the frequency of the switch control signal is lower than the frequency of the output clock.

15. A relaxation oscillation method, characterized in that, include: Perform a resistor-capacitor charging operation to set the first voltage; Perform a resistor-capacitor discharge operation to set the second voltage; Perform a charge transfer operation to sample the voltage difference between the first voltage and the second voltage and transfer the voltage difference to the integrating capacitor; In response to the control input provided by the integrating capacitor, a controllable oscillator generates an output clock. and Perform a reset operation to reset the first voltage to the first reference voltage and the second voltage to the second reference voltage; Specifically, the resistor-capacitor charging operation is performed in the first stage; the resistor-capacitor discharging operation is performed in the second stage; the charge transfer operation is performed in the third stage; and the reset operation is performed in the fourth stage; and the first, second, third and fourth stages are non-overlapping stages.

16. The relaxation oscillation method as described in claim 15, characterized in that, The resistor-capacitor charging operation is performed once every N output clock cycles, where N is an integer greater than 1.

17. The relaxation oscillation method as described in claim 15, characterized in that, The resistor-capacitor discharge operation is performed once every N output clock cycles, where N is an integer greater than 1.

18. The relaxation oscillation method as described in claim 15, characterized in that, The charge transfer operation is performed once every N output clock cycles, where N is an integer greater than 1.

19. The relaxation oscillation method as described in claim 15, characterized in that, The reset operation is performed once every N output clock cycles, where N is an integer greater than 1.

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