A full-swing input voltage-to-time converter based on voltage boosting technology

Abstract

The present invention belongs to the field of integrated circuit technology, and is specifically a full-swing input voltage-to-time converter based on voltage boosting technology. The voltage-to-time converter circuit of the present invention is composed of a differential structure, including two single-ended circuits with identical working modes and circuit connections: the P terminal and the N terminal; each single-ended structure includes: a voltage boost sampling module, a discharge current source, and a threshold voltage detection module; the voltage input signal V inP and V inN The time output signals start and stop are finally generated by sequentially passing through the cascaded voltage-lift sampling module, discharge current source and threshold voltage detection module. The present invention uses the front-end voltage-lift sampling module to level-shift the input signal as a whole upward, ensuring that the transistors in the current mirror are always in the saturation region during the discharge process. The input signal swing can be widened to the full swing, greatly improving the linearity and output time range of the voltage-to-time converter.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and in particular relates to a full-swing input voltage-to-time converter. Background Art

[0002] With the continuous advancement of semiconductor technology and the continuous reduction of power supply voltages, the design of traditional voltage-domain analog-to-digital converters (ADCs) has become increasingly challenging. However, time-domain ADCs (TDADCs) have continued to attract attention due to their predominantly digital circuitry and high-speed time quantization. A TDADC consists of a voltage-to-time converter (VTC) and a time-to-digital converter (TDDC). The VTC performs the conversion from the analog domain to the time domain, converting the differential input voltage into two rising clock edges; the TDDC quantizes the time difference between the two time signals into a digital code value. As the front-end circuit of a TDADC, the VTC's performance impacts the overall TDADC. Generally speaking, a smaller VTC input range improves linearity. However, too small an input swing reduces the conversion rate, limiting the high-speed application of TDADCs. The current bottleneck in VTC design is how to maximize the input swing while maintaining linearity. Summary of the Invention

[0003] The object of the present invention is to provide a voltage-to-time converter with high linearity and full-swing input.

[0004] The full-swing input voltage-to-time converter provided by the present invention is based on voltage boosting technology and consists of a differential structure, such as Figure 1 As shown, it includes two single-ended circuits with identical working modes and circuit connections: the P-end (100) and the N-end (200); taking the P-end circuit (100) as an example, each single-ended structure specifically includes: a voltage raising sampling module (110), a discharge current source (120), and a threshold voltage detection module (130); wherein the voltage input signal V inP and V inN The time output signals start and stop are finally generated through the cascaded voltage raising sampling module (110), the discharge current source (120) and the threshold voltage detection module (130). The working principle is as follows: the input voltage V inP The voltage is sampled by the voltage raising sampling module, and the raised voltage VP is obtained through the control of different timings and the combination of voltages V1 and V2. Then the discharge current source discharges the VP node, and the threshold voltage detection module detects the potential state of the VP node. When the potential is lower than the threshold voltage V th When , the output signal level flips from low to high, generating a rising edge time signal start.

[0005] The voltage rise sampling module (110) is as follows: Figure 3 As shown, the single-ended structure includes a switch S0 (111) controlled by the timing ck0, a switch S1 (112) controlled by the timing ck1, a switch S2 (113) controlled by the timing ck2n, and a sampling capacitor C S (114), of which:

[0006] One end of switch S0 is connected to DC voltage V1, and the other end is connected to sampling capacitor C S The upper plate of switch S1 is connected to the input voltage V inP , one end is connected to the sampling capacitor C S The lower plate of the switch S1; one end of the switch S1 is connected to the DC voltage V2, and the other end is connected to the sampling capacitor C S The lower plate.

[0007] The switch S0 (111) in the voltage-raising sampling module (110) adopts a transmission gate structure, comprising a PMOS transistor and an NMOS transistor, and the two transistors are driven by a high voltage, wherein:

[0008] The source of the PMOS transistor is connected to the drain of the NMOS transistor and is connected to the node VP. The drain of the PMOS transistor is connected to the source of the NMOS transistor and is connected to the DC voltage V1. The gate of the NMOS transistor is connected to the clock ck0, and the gate of the PMOS transistor is connected to the clock ck0n, which is the inverse phase of ck0. When ck0 is high, the switch S0 is turned on, and the DC voltage V1 is connected to the sampling capacitor C. S When ck0 is low, switch S0 is turned off.

[0009] The switch S1 (112) in the voltage boost sampling module (110) adopts a gate voltage bootstrap switch structure with an additional virtual NMOS transistor, wherein:

[0010] The source terminals of the sampling transistors of the switch S1 are connected to the differential input voltage V inP and V inN , and the source and drain of the virtual NMOS transistor are connected to the sampling capacitor C S The drain of the P-end virtual NMOS transistor is connected to the drain of the sampling transistor of the N-end switch S1, the drain of the N-end virtual NMOS transistor is connected to the drain of the sampling transistor of the P-end switch S1, and the gates of the two virtual NMOS transistors at the N and P ends are connected to the ground; the sampling phase is controlled by ck1. When ck1 is high, the switch S1 is turned on and the differential input voltage is sampled to the sampling capacitor C S When ck1 is at a low level, the switch S1 is turned off.

[0011] The switch S2 (113) in the voltage-lift sampling module (110) uses a single NMOS transistor. When ck2n is at a high level, the switch S2 is turned on, and the DC voltage V2 is connected to the sampling capacitor C S When ck2n is low, switch S1 is turned off. ck2n is the inverted phase of ck2.

[0012] Taking the P-terminal circuit (100) as an example, its working process is as follows: first, ck0 is high, the switch S0 is turned on, and the DC voltage V1 is connected to the sampling capacitor C S Then ck1 is high, switch S1 is turned on, and the input voltage V inP is sampled to the sampling capacitor C S Then ck0 is low, switch S0 is turned off, then ck1 is low, switch S1 is turned off; then ck2n is high, switch S2 is turned on, and the DC voltage V2 is connected to the sampling capacitor C S The lower plate of the VP node is obtained by raising the voltage VP; then ck3 is at a high level, controlling the discharge current source (120) to discharge the VP node, and the threshold voltage detection module (130) detects the potential state of the VP node. When the potential is lower than the threshold voltage V th When , the output signal level flips from low to high, generating a rising edge time signal start.

[0013] The discharge current source (120) includes an NMOS transistor and a cascode current mirror controlled by a timing ck3; wherein, when ck3 is at a high level, the NMOS transistor is turned on, and the cascode current mirror discharges the VP node; when ck3 is at a low level, the NMOS transistor is turned off, and the cascode current mirror does not work.

[0014] The cascode current mirror is composed of four NMOS transistors, such as Figure 4 As shown, the drain of the first transistor is connected to the input reference current, the gate and the drain are connected, and are connected to the gate of the third transistor, and the source is connected to the drain of the second transistor; the drain and the gate of the second transistor are connected, and are connected to the gate of the fourth transistor, and the source is grounded; the drain of the third transistor is connected to the source of the NMOS transistor controlled by the timing ck3, and the source is connected to the drain of the fourth transistor; the source of the fourth transistor is grounded; the drain of the NMOS transistor controlled by the timing ck3 is connected to the node VP, and the gate is connected to the clock phase ck3.

[0015] The threshold voltage detection module (130) is composed of two PMOS transistors P1 and P2 and four NMOS transistors N1, N2, N3, and N4. Figure 5 As shown, where:

[0016] The sources of P1 and P2 are connected to VDD, the gates of P1 and P2 are connected and connected to the drain of P1, the drain of P1 is connected to the drain of N1, the drain of P2 is connected to the drain of N2, and connected to the input of an inverter. The output of the inverter is the clock signal start or stop; the gate of N1 is connected to node VP or VN, and the gate of N2 is connected to the threshold voltage V th , N1 is connected to the source of N2 and connected to the drain of N3, the gate of N3 is connected to the timing ck3, the source is connected to the drain of N4, and the gate of N4 is connected to the bias voltage V b , the source is grounded.

[0017] The entire working process of the voltage-to-time converter adopts four-phase timing control, such as Figure 2 As shown in the figure, ck0 occupies one-fifth of the clock cycle. The rising edges of ck0, ck1 and ck2 are at the same time. The falling edge of ck1 is delayed by 10ps compared with the falling edge of ck0. The falling edge of ck2 is delayed by 10ps compared with the falling edge of ck1. ck2n is the inverted phase of ck2. The rising edge of ck3 is delayed by 80ps compared with the rising edge of ck2n. The falling edge of ck3 is at the same time as the rising edge of ck0.

[0018] Furthermore, the two transistors of the switch S0 (111) are driven with a high voltage, and all other transistors are driven with a standard voltage.

[0019] The full-swing input voltage-to-time converter using voltage boosting technology proposed in the present invention uses a voltage boosting sampling module at the front end to level-shift the input signal as a whole. The node voltage obtained after boosting is:

[0020] V P = V 1 + V 2 - V inP， (1)

[0021] V N = V 1 + V 2 - V inN， (2)

[0022] By ensuring that the transistors in the current mirror are always in the saturation region during the discharge process, the input signal swing can be widened to the full swing, greatly improving the linearity and output time range of the voltage-to-time converter. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 FIG. 1 is a schematic diagram of the architecture of a full-swing input voltage-to-time converter using voltage boosting technology according to the present invention.

[0024] Figure 2 This is the complete control timing diagram of the four phases in the voltage-to-time converter.

[0025] Figure 3 This is the circuit diagram of the fully differential input voltage boost sampling module.

[0026] Figure 4 This is a schematic diagram of the cascode current mirror circuit.

[0027] Figure 5 This is a circuit diagram of the threshold voltage detection module. DETAILED DESCRIPTION

[0028] The following, in conjunction with the accompanying drawings, further describes the full-swing input voltage-to-time converter of the present invention using voltage step-up technology. It is worth noting that the full-swing input voltage-to-time converter provided by the present invention can achieve a variety of different performance indicators and performance, and can also have a variety of application scenarios. The following examples only provide a typical implementation circuit of the present invention, which is intended only to illustrate the formation and use of the present invention and is not intended to limit the present invention.

[0029] The present invention provides a high-linearity, full-swing input voltage-to-time converter and its internal module circuit. One implementation example is a voltage-to-time converter with a sampling rate of 1GS / s and a differential input voltage of 1.8V, which serves as the front-end circuit of a time-domain analog-to-digital converter. To meet the 10-bit resolution requirement of the time-domain analog-to-digital converter, the single-ended sampling capacitor of the voltage-to-time converter is 500fF. In this example, the standard power supply voltage is 0.9V, and the high power supply voltage driving switch S0 is 2.5V. The DC voltage V1 is set to 500mV, and the DC voltage V2 is set to 900mV, raising the full-swing input voltage from -0.9V to 0.9V to 0.5V to 1.4V.

[0030] The sampling rate is 1GHz, and the timing arrangement is as follows: ck0 occupies one-fifth of the clock period, the high-level time of ck1 is 200ps, the period from the falling edge of ck2 to the rising edge of ck3 is 80ps, the rising edges of the clocks of ck0, ck1 and ck2 are at the same time, the falling edge of ck1 is delayed by 10ps from the falling edge of ck0, the falling edge of ck2 is delayed by 10ps from the falling edge of ck1, ck2n is the inverted phase of ck2; the rising edge of ck3 is delayed by 80ps from the rising edge of ck2n, the falling edge of ck3 is at the same time as the rising edge of ck0, and the high-level time of ck3 is 700ps.

[0031] In this example, the full-swing input voltage-to-time converter proposed in the present invention, which utilizes voltage-boosting technology, uses a front-end voltage-boosting sampling module to level-shift the entire input signal upward, ensuring that the transistors in the current mirror remain in the saturation region during discharge. This widens the input signal swing to the full swing, significantly improving the linearity and output time range of the voltage-to-time converter. Furthermore, the two cross-coupled dummy transistors in switch S0 eliminate the feedthrough effect introduced by parasitic capacitance during high-frequency operation, thereby improving sampling linearity.

[0032] Although the contents and advantages of the present invention have been disclosed in detail as above, it must be noted that the scope of the present invention is not limited to the specific embodiments such as the methods and steps described in the specification. Without departing from the spirit and scope of the present invention, any person skilled in the art can make many variations and modifications based on the contents disclosed by the present invention, which should also be regarded as the scope of protection of the present invention.

Claims

1. A full-swing input voltage-to-time converter based on voltage boosting technology, characterized in that: It is composed of a differential structure, including two single-ended circuits with identical working modes and circuit connections: the P terminal (100) and the N terminal (200); each single-ended structure specifically includes: a voltage rise sampling module (110), a discharge current source (120), and a threshold voltage detection module (130); wherein the voltage input signal V inP and V inN The time output signals start and stop are finally generated by sequentially passing through the cascaded voltage raising sampling module (110), the discharge current source (120) and the threshold voltage detection module (130); The voltage raising sampling module (110) comprises a switch S0 (111) controlled by a timing ck0, a switch S1 (112) controlled by a timing ck1, a switch S2 (113) controlled by a timing ck2n, and a sampling capacitor C S (114), of which: One end of switch S0 is connected to DC voltage V1, and the other end is connected to sampling capacitor C S The upper plate of switch S1 is connected to the input voltage V inP , the other end is connected to the sampling capacitor C S The lower plate of the switch S2; one end of the switch S2 is connected to the DC voltage V2, and the other end is connected to the sampling capacitor C S The lower plate; The discharge current source (120) includes an NMOS transistor and a cascode current mirror controlled by a timing ck3; when ck3 is at a high level, the NMOS transistor is turned on, and the cascode current mirror discharges the VP node; when ck3 is at a low level, the NMOS transistor is turned off, and the cascode current mirror does not work; The threshold voltage detection module (130) is composed of two PMOS transistors P1 and P2 and four NMOS transistors N1, N2, N3, and N4, wherein: The sources of P1 and P2 are connected to VDD, the gates of P1 and P2 are connected and connected to the drain of P1, the drain of P1 is connected to the drain of N1, the drain of P2 is connected to the drain of N2, and connected to the input of an inverter. The output of the inverter is the clock signal start or stop; the gate of N1 is connected to node VP or VN, and the gate of N2 is connected to the threshold voltage V th , N1 is connected to the source of N2 and to the drain of N3, the gate of N3 is connected to the timing ck3, the source of N3 is connected to the drain of N4, and the gate of N4 is connected to the bias voltage V b , the source of N4 is grounded.

2. The full-swing input voltage-to-time converter according to claim 1, wherein: In the voltage-raising sampling module (110), the switch S0 (111) adopts a transmission gate structure, including a PMOS transistor and an NMOS transistor, and the two transistors are driven by a high voltage, wherein: The source of the PMOS transistor is connected to the drain of the NMOS transistor and is connected to the node VP. The drain of the PMOS transistor is connected to the source of the NMOS transistor and is connected to the DC voltage V1. The gate of the NMOS transistor is connected to the clock ck0, and the gate of the PMOS transistor is connected to the clock ck0n, which is the inverse phase of ck0. When ck0 is high, the switch S0 is turned on, and the DC voltage V1 is connected to the sampling capacitor C. S When ck0 is low, switch S0 is turned off.

3. The full-swing input voltage-to-time converter according to claim 2, wherein: In the voltage-lift sampling module (110), the switch S1 (112) adopts a gate voltage bootstrap switch structure with an additional virtual NMOS transistor, wherein: The source terminals of the sampling transistors of the switch S1 are connected to the differential input voltage V inP and V inN , and the source and drain of the virtual NMOS transistor are connected to the sampling capacitor C S The drain of the P-end virtual NMOS transistor is connected to the drain of the sampling transistor of the N-end switch S1, the drain of the N-end virtual NMOS transistor is connected to the drain of the sampling transistor of the P-end switch S1, and the gates of the two virtual NMOS transistors at the N and P ends are connected to the ground; the sampling phase is controlled by ck1. When ck1 is high, the switch S1 is turned on and the differential input voltage is sampled to the sampling capacitor C S When ck1 is at a low level, the switch S1 is turned off.

4. The full-swing input voltage-to-time converter according to claim 3, wherein: In the voltage-raising sampling module (110), the switch S2 (113) uses a single NMOS transistor. When ck2n is at a high level, the switch S2 is turned on, and the DC voltage V2 is connected to the sampling capacitor C S When ck2n is at a low level, the switch S1 is turned off; wherein ck2n is the inverted phase of ck2.

5. The full-swing input voltage-to-time converter according to claim 4, wherein: The working process is as follows: first, ck0 is high, switch S0 is turned on, and DC voltage V1 is connected to sampling capacitor C S Then ck1 is high, switch S1 is turned on, and the input voltage V inP is sampled to the sampling capacitor C S Then ck0 is low, switch S0 is turned off, then ck1 is low, switch S1 is turned off; then ck2n is high, switch S2 is turned on, and the DC voltage V2 is connected to the sampling capacitor C S The lower plate of the VP node is obtained by raising the voltage VP; then ck3 is at a high level, controlling the discharge current source (120) to discharge the VP node, and the threshold voltage detection module (130) detects the potential state of the VP node. When the potential is lower than the threshold voltage V th When , the output signal level flips from low to high, generating a rising edge time signal start.

6. The full-swing input voltage-to-time converter according to claim 4, wherein: In the discharge current source (120), the cascode current mirror is composed of four NMOS transistors; the drain of the first transistor is connected to the input reference current, the gate and the drain are connected, and are connected to the gate of the third transistor, and the source is connected to the drain of the second transistor; the drain of the second transistor is connected to the gate, and is connected to the gate of the fourth transistor, and the source is grounded; the drain of the third transistor is connected to the source of the NMOS transistor controlled by the timing ck3, and the source is connected to the drain of the fourth transistor; the source of the fourth transistor is grounded; the drain of the NMOS transistor controlled by the timing ck3 is connected to the node VP, and the gate is connected to the clock phase ck3.

7. The full-swing input voltage-to-time converter according to claim 5, wherein: The entire working process adopts four-phase timing control. CK0 occupies one-fifth of the clock cycle. The rising edges of CK0, CK1 and CK2 are at the same time. The falling edge of CK1 is delayed by 10ps than that of CK0. The falling edge of CK2 is delayed by 10ps than that of CK1. CK2n is the inverted phase of CK2. The rising edge of CK3 is delayed by 80ps than that of CK2n. The falling edge of CK3 is at the same time as the rising edge of CK0.

8. The full-swing input voltage-to-time converter according to claim 2, wherein: In the voltage-raising sampling module (110), the two transistors of the switch S0 (111) are driven by a high voltage, and all other transistors are driven by a standard voltage.

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