Multi-module computing platform clock synchronization system, method, electronic device and medium

Abstract

An embodiment of the present application provides a clock synchronization system, method, electronic device, and medium for a multi-module computing platform. The system includes: a clock subsystem is respectively connected to a master node and each slave node through working clock signal connections; the master node is respectively connected to each slave node through PPS signal connections; the master node is configured to run a 1588 protocol stack to parse the second pulse to obtain GPS time and PPS signal; the clock subsystem is configured to respectively provide the required working clock to the master node and each slave node; each node in the master node and each slave node is configured to calibrate the accumulated error of the corresponding counter according to the PPS signal. In this way, the slave nodes in the system do not require support for the 1588 protocol. The master and slave nodes use the same clock subsystem, and the master and slave nodes calibrate the master and slave node clock counters according to the PPS signal, improving the clock synchronization accuracy of the multi-module computing platform, reducing the engineering implementation difficulty, and thus effectively reducing the development and verification costs.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular, to a clock synchronization system, method, electronic device and medium for a multi-module computing platform. Background Art

[0002] Due to the requirements of computing power and functional safety, the computing platforms in the automotive and industrial fields will integrate multiple computing power chips (System on Chip, SOC) plus automotive-grade MCUs (Microcontroller Unit, MCU). Moreover, due to the requirements of computing real-time performance and determinism, these computing units need to achieve clock synchronization with external sensors, where the external sensors include V2X sensors. Currently, for different computing units within a computing platform to achieve clock synchronization, the common method is to implement it based on the 1588V2 protocol. The clock synchronization protocol 1588V2 mainly solves the clock synchronization of different computing and switching nodes in the Ethernet network. It requires the operating system to include the corresponding protocol, and the chip physical layer can implement the corresponding protocol. The content clauses involved in the time synchronization protocol 1588V2 are very numerous. To perfectly achieve clock synchronization, a large amount of labor cost needs to be invested and it takes a long time. Summary of the Invention

[0003] To solve the above technical problems, embodiments of the present invention provide a clock synchronization system, method, electronic device and medium for a multi-module computing platform.

[0004] In a first aspect, embodiments of the present invention provide a clock synchronization method for a multi-module computing platform, including: The clock synchronization system for the multi-module computing platform includes:

[0005] A master node, a clock subsystem and multiple slave nodes, and the master node and each of the slave nodes respectively include a counter;

[0006] The clock subsystem is respectively connected to the master node and each of the slave nodes through working clock signal connections;

[0007] The master node is respectively connected to each of the slave nodes through PPS signal connections;

[0008] The master node is configured to run the 1588 protocol stack to parse the second pulse to obtain GPS time and PPS signal;

[0009] The clock subsystem is configured to respectively provide the required working clock to the master node and each of the slave nodes;

[0010] Each node in the master node and each of the slave nodes is configured to calibrate the cumulative error of the corresponding counter according to the PPS signal.

[0011] According to a specific embodiment of the present disclosure, the clock subsystem is composed of a reference clock source and a clock buffer, and the reference clock source is electrically connected to the clock buffer. Alternatively, the clock subsystem is composed of a reference clock source and a phase-locked loop, and the reference clock source is electrically connected to the phase-locked loop;

[0012] The clock buffer or the phase-locked loop includes multiple channels, and each of the channels is electrically connected to the master node and each of the slave nodes respectively.

[0013] According to a specific embodiment of the present disclosure, each node among the master node and each of the slave nodes is configured to obtain the clock frequency and the frequency division ratio of the corresponding channel, and calibrate the accumulated error of the corresponding counter according to the clock frequency, the frequency division ratio, and the PPS signal.

[0014] According to a specific embodiment of the present disclosure, each node among the master node and each of the slave nodes is configured to calibrate the accumulated error of the corresponding counter once per second according to the PPS signal.

[0015] According to a specific embodiment of the present disclosure, each of the slave nodes includes a real-time processor, and a corresponding counter is arranged on the real-time processor.

[0016] According to a specific embodiment of the present disclosure, the master node is further configured to receive the second pulse from the GPS.

[0017] In a second aspect, an embodiment of the present invention provides a multi-module computing platform clock synchronization method, which is applied to the multi-module computing platform clock synchronization system provided in the first aspect. The method includes:

[0018] Parsing the second pulse through the master node running the 1588 protocol stack to obtain the GPS time and the PPS signal;

[0019] Providing the required working clocks to the master node and each of the slave nodes respectively through the clock subsystem;

[0020] Calibrating the accumulated error of the corresponding counter by each node among the master node and each of the slave nodes according to the PPS signal.

[0021] According to a specific embodiment of the present disclosure, the step of calibrating the accumulated error of the corresponding counter by each node among the master node and each of the slave nodes according to the PPS signal includes:

[0022] Obtaining the clock frequency and the frequency division ratio of the corresponding channel by each node among the master node and each of the slave nodes, and calibrating the accumulated error of the corresponding counter according to the clock frequency, the frequency division ratio, and the PPS signal.

[0023] In a third aspect, an embodiment of the present invention provides an electronic device, including a memory and a processor. The memory is used to store a computer program, and the computer program executes the multi-module computing platform clock synchronization method provided in the second aspect when running on the processor.

[0024] In a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium, which stores a computer program, and the computer program executes the multi-module computing platform clock synchronization method provided in the second aspect when running on a processor.

[0025] For the multi-module computing platform clock synchronization system, method, electronic device and medium provided in the present application above, slave nodes in the multi-module computing platform synchronization system do not require support for the 1588 protocol. The master node and the slave node use the same clock subsystem, and the master node and the slave node calibrate the master node and slave node clock counters according to the PPS signal, improving the clock synchronization accuracy of the multi-module computing platform, reducing the engineering implementation difficulty, and thus effectively reducing the development and verification cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions of the present invention, the accompanying drawings required for the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as limiting the protection scope of the present invention. In each drawing, similar components are numbered similarly.

[0027] Figure 1 Shows a schematic architecture diagram of a clock synchronization system based on the 1588V2 protocol in the prior art;

[0028] Figure 2 Shows a schematic structural diagram of a multi-module computing platform clock synchronization system provided in an embodiment of the present application;

[0029] Figure 3 Shows another schematic structural diagram of a multi-module computing platform clock synchronization system provided in an embodiment of the present application;

[0030] Figure 4 Shows another schematic structural diagram of a multi-module computing platform clock synchronization system provided in an embodiment of the present application;

[0031] Figure 5 Shows a schematic flow diagram of a multi-module computing platform clock synchronization method provided in an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0032] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some of the embodiments of the present invention, rather than all of the embodiments.

[0033] The components of the embodiments of the present invention that are generally described and illustrated in the accompanying drawings herein can be arranged and designed in a variety of different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely represents selected embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts fall within the scope of protection of the present invention.

[0034] Hereinafter, the terms "comprising", "having" and their cognates that can be used in various embodiments of the present invention are only intended to represent specific features, numbers, steps, operations, elements, components or combinations of the foregoing items, and should not be construed as first excluding the existence of one or more other features, numbers, steps, operations, elements, components or combinations of the foregoing items or precluding the possibility of adding one or more features, numbers, steps, operations, elements, components or combinations of the foregoing items.

[0035] In addition, the terms "first", "second", "third", etc. are only used for distinguishing descriptions and should not be construed as indicating or implying relative importance.

[0036] Unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the various embodiments of the present invention belong. The terms (such as those defined in a general-use dictionary) will be interpreted as having the same meaning as the contextual meaning in the relevant technical field and will not be interpreted as having an idealized meaning or an overly formal meaning unless clearly defined in the various embodiments of the present invention.

[0037] See Figure 1 , the basic principle of achieving synchronization based on the 1588V2 protocol is as follows: One of the computing modules (usually an automotive-grade MCU) receives the recommended positioning information (GPRMC) and the Pulse Per Second (PPS) signal from the GPS. The GPRMC message contains UTC time information, and the UTC time information can be used as the standard time. Among them, Universal Time Coordinated (UTC) is also known as Coordinated Universal Time, World Standard Time, and International Atomic Time. This automotive-grade MCU becomes the global master node of the clock for the entire computing platform, and other computing modules SOCs are slave nodes of the clock. In Figure 1Among them, other computing modules SOC include SOC1, SOC12, ..., SOCn, and SOC1, SOC12, ..., SOCn respectively have counters 1, 2, ..., n. The other computing modules SOC receive the PPS signal and the general Precise Time Protocol (gPTP) signal sent by the in-vehicle MCU through the Ethernet (ETH) channel.

[0038] The slave nodes (SOC) and the master node (MCU) achieve time synchronization of CLK_mcu, CLK_1, CLK_2, ..., CLK_n through the 1588V2 protocol (802.1AS). Essentially, the counter statistical values of all master and slave nodes are consistent. To achieve clock synchronization of the computing modules in the entire computing platform, the following four problems need to be solved: confirmation of the master node in the entire clock domain, clock frequency differences among all master and slave nodes, link delay between the master and slave nodes, and residence time of data packets on each node.

[0039] It should be noted that the clock synchronization protocol 1588v2 mainly solves the clock synchronization of different computing and switching nodes in the Ethernet network. In a complex Ethernet network, there are a large number of nodes, the clock frequency accuracy of different nodes cannot be planned in advance, the delays on the links are different, and they also change dynamically. The residence time of data on each node is even more unpredictable and unplannable. To achieve 1588V2 time synchronization, it is required that the operating system contains the corresponding protocol, and it is required that the chip physical layer can implement the corresponding protocol. The content clauses involved in the time synchronization protocol 1588V2 are very numerous, and perfect implementation requires the experience of engineers and a considerable investment cost.

[0040] Embodiment 1

[0041] This embodiment provides a clock synchronization system for a multi-module computing platform.

[0042] Please refer to Figure 2 , the clock synchronization system 100 for a multi-module computing platform includes: a master node 20, a clock subsystem 10, and multiple slave nodes. In Figure 1 , the multiple slave nodes are respectively represented as slave node 1, slave node 2, ..., slave node n. The master node 20 includes a counter_m, and the slave nodes 1, 2, ..., n respectively include counters_1, counters_2, ..., counters_n. The clock subsystem 10 is respectively connected to the master node 20, slave node 1, slave node 2, ..., slave node n through working clock signal connections. The master node 20 is respectively connected to the slave nodes 1, 2, ..., n through PPS signal connections.

[0043] Among them, the master node 20 is used to run the 1588 protocol stack to parse the second pulse, and obtain the GPS time and the PPS signal; the clock subsystem 10 is used to provide the required working clocks to the master node 20, slave node 1, slave node 2, ..., slave node n respectively; each node in the master node 20, slave node 1, slave node 2, ..., slave node n is used to calibrate the accumulated error of the corresponding counter according to the PPS signal.

[0044] In this embodiment, the master node 20 is used to receive the second pulse from the Global Positioning System (GPS). Among them, the second pulse includes the Recommended Minimum Specific GNSS Sentence (GPRMC) and the PPS signal. There is UTC time information in the GPRMC message, and the UTC time information can be used as the standard time. It should be noted that the master node 20 supports the 1588 protocol parsing function, and the slave node 1, slave node 2, ..., slave node n are not required to have the 1588 protocol parsing function.

[0045] In this embodiment, to improve the calibration accuracy, each node in the master node 20, slave node 1, slave node 2, ..., slave node n is used to calibrate the accumulated error of the corresponding counter once per second according to the PPS signal.

[0046] Please refer to Figure 3 , Figure 3 Compared with Figure 2 , the difference is that it shows a specific structural example of the clock subsystem 10. Figure 3 In Figure 3 , the clock subsystem 10 is composed of a reference clock source 101 and a clock buffer 102. The reference clock source 101 is electrically connected to the clock buffer 102. Alternatively, the clock subsystem 10 is composed of a reference clock source 101 and a phase-locked loop (not shown in

[0047] The clock buffer 102 or the phase-locked loop includes multiple channels, and each of the channels is electrically connected to each node in the master node 20, slave node 1, slave node 2, ..., slave node n.

[0048] It should be noted that when the clock subsystem 10 is composed of a reference clock source 101 and a clock buffer 102, the clock buffer 102 provides working clocks with the same frequency to each node in the master node 20, slave node 1, slave node 2, ..., slave node n through each channel. When the clock subsystem 10 is composed of a reference clock source 101 and a phase-locked loop, the phase-locked loop provides the required working clocks to each node in the master node 20, slave node 1, slave node 2, ..., slave node n through each channel. Among them, the frequencies of the working clocks required by the master node and each slave node may be the same or different, and need to be determined according to the system requirements of the master node and each slave node.

[0049] It should be noted that each node in slave node 1, slave node 2, ..., slave node n includes an R5 processor, and corresponding counters are set on the real-time processor.

[0050] In this embodiment, the real-time processor can be an R5 processor or other types of processors, which is not limited here.

[0051] In this embodiment, each node in the master node 20, slave node 1, slave node 2, ..., slave node n is used to obtain the clock frequency and division ratio of the corresponding channel, and calibrate the accumulated error of the corresponding counter according to the clock frequency, the division ratio, and the PPS signal.

[0052] In this embodiment, the clock buffer provides working clocks with the same frequency to the master node and all slave nodes, so the statistical values of the counters of the master node and the slave nodes are exactly the same. The reference clock source 101 of the clock subsystem 10 can be a crystal or a crystal oscillator. It should be noted that even if different frequencies of working clocks need to be generated by the phase-locked loop, the division ratio can be directly input into the counter for conversion.

[0053] Since the master node and the slave nodes of the multi-module computing platform clock synchronization system 100 commonly use the same reference clock source and the same clock buffur (or phase-locked loop) chip, the working clock frequencies and precisions received by the master node and all slave nodes are consistent, and at least the counting errors between the master and slave nodes are extremely small in a short time.

[0054] The master node and all slave nodes calibrate the accumulated error of the counter once per second with the PPS signal, and the standard value corresponding to the PPS signal can be calculated in advance. The calculation method is to determine the value accumulated by the PPS according to the working clock average, that is, to determine the statistical value of the counter according to the working clock average. For example, if the working clock frequency is 25 MHz, then the value accumulated by each PPS should be 25000000.

[0055] The following is combined with Figure 4An example is given for a specific application scenario of the clock synchronization system of the multi-module computing platform. Figure 4 In this example, the in-vehicle computing platform 400 consists of an automotive-grade MCU and four computing power chips (System on Chip, SOC). Each computing power chip contains an R5 real-time processor inside. Figure 4 In this example, the four computing power chips are SOC1, SOC2, SOC3, and SOC4 respectively. The working principle of the in-vehicle computing platform 400: The automotive-grade MCU, as the master node, can parse the 1588 protocol and receive the second pulse from the GPS. SOC1, SOC2, SOC3, and SOC4, as slave nodes, are not required to have the function of parsing the 1588 protocol. Both the master and slave nodes have calculators, and the counters of the four slave nodes are arranged on the R5 processor. The automotive-grade MCU has a counter _mcu, SOC1 has a counter _1, SOC2 has a counter _2, SOC3 has a counter _3, and SOC4 has a counter _4. On the in-vehicle computing platform, each node is on the same PCB single board, the number of nodes is small, the clock frequencies and precisions of different nodes can be planned in advance, the delay on the link is at the ns level and is deterministic, and the data residence time on each node can be accurately counted by the R5 processor on the SOC.

[0056] The oscillator and the phase-locked loop (Clk_PLL) form the clock subsystem of the entire platform, providing working clocks for the master node and the slave nodes. The clock frequency output by each channel of the phase-locked loop and the frequency division ratio of each channel are confirmed by the corresponding computing power chip. For example, Figure 4 in this example, the four computing power chips SOC1, SOC2, SOC3, and SOC4 may require different clock frequencies, so the frequency division ratio of each channel is also different. SOC1, SOC2, SOC3, and SOC4 need to know the frequency division ratio of the corresponding channel to correct the counter. The master node and the slave nodes use the received PPS signal to calibrate the values of the counters once per second.

[0057] The multi-module computing platform clock synchronization system provided by the embodiments of the present application does not require the slave nodes in the multi-module computing platform synchronization system to support the 1588 protocol. The master node and the slave nodes use the same clock subsystem, and the master node and the slave nodes calibrate the clock counters of the master node and the slave nodes according to the PPS signal, improving the clock synchronization accuracy of the multi-module computing platform, reducing the engineering implementation difficulty, and thus effectively reducing the development and verification costs.

[0058] Embodiment 2

[0059] This embodiment provides a multi-module computing platform clock synchronization method, which is applied to the multi-module computing platform clock synchronization system provided by the embodiment.

[0060] Please refer toFigure 5 , the clock synchronization method for a multi-module computing platform includes:

[0061] Step S501, parsing the second pulse through the master node running the 1588 protocol stack to obtain the GPS time and the PPS signal;

[0062] Step S502, providing the required working clocks to the master node and each slave node respectively through the clock subsystem;

[0063] Step S503, calibrating the cumulative error of the corresponding counter by each node in the master node and each slave node according to the PPS signal.

[0064] In an embodiment, step S503 includes:

[0065] Obtaining the clock frequency and the frequency division ratio of the corresponding channel by each node in the master node and each slave node, and calibrating the cumulative error of the corresponding counter according to the clock frequency, the frequency division ratio and the PPS signal.

[0066] The clock synchronization method for the multi-module computing platform provided in this embodiment is applied to the clock synchronization system for the multi-module computing platform provided in the embodiment, and has the functions corresponding to the clock synchronization system for the multi-module computing platform. To avoid repetition, it will not be elaborated here.

[0067] Embodiment 3

[0068] In addition, an embodiment of the present disclosure provides an electronic device, including a memory and a processor, where the memory stores a computer program, and the computer program, when running on the processor, executes the clock synchronization method for the multi-module computing platform provided in Embodiment 2.

[0069] The electronic device provided in this embodiment can implement the clock synchronization method for the multi-module computing platform provided in Embodiment 2. To avoid repetition, it will not be elaborated here.

[0070] Embodiment 4

[0071] The present application also provides a computer-readable storage medium, on which a computer program is stored, and the computer program, when executed by a processor, implements the clock synchronization method for the multi-module computing platform provided in Embodiment 2.

[0072] In this embodiment, the computer-readable storage medium may be a read-only memory (ROM for short), a random access memory (RAM for short), a magnetic disk or an optical disc, etc.

[0073] The computer-readable storage medium provided in this embodiment can implement the multi-module computing platform clock synchronization method provided in Embodiment 1. To avoid repetition, it will not be elaborated here.

[0074] It should be noted that in this article, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or terminal. Without further limitation, an element defined by the statement "including a..." does not exclude the existence of additional identical elements in the process, method, article or terminal including the element.

[0075] Through the description of the above embodiments, those skilled in the art can clearly understand that the above-described embodiment method can be implemented by means of software plus a necessary general hardware platform. Of course, it can also be implemented by hardware, but in many cases the former is a better implementation. Based on such an understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. The computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions for causing a terminal (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in various embodiments of the present application.

[0076] The embodiments of the present application have been described above in conjunction with the accompanying drawings. However, the present application is not limited to the above specific embodiments. The above specific embodiments are merely illustrative and not restrictive. Under the inspiration of the present application, those of ordinary skill in the art can also make many forms without departing from the purpose of the present application and the scope protected by the claims, and all of them belong to the protection scope of the present application.

Claims

1. A clock synchronization system for a multi-module computing platform, characterized in that, The multi-module computing platform clock synchronization system includes: A master node, a clock subsystem, and multiple slave nodes. The master node and each of the slave nodes respectively include a counter; The clock subsystem is respectively connected to the master node and each of the slave nodes through working clock signal connections. The clock subsystem is composed of a reference clock source and a clock buffer, and the reference clock source is electrically connected to the clock buffer. Alternatively, the clock subsystem is composed of a reference clock source and a phase-locked loop, and the reference clock source is electrically connected to the phase-locked loop; The clock buffer or the phase-locked loop includes multiple channels, and each of the channels is respectively electrically connected to the master node and each of the slave nodes; The master node is respectively connected to each of the slave nodes through PPS signal connections; The master node is used to run the 1588 protocol stack to parse the second pulse to obtain GPS time and PPS signal; The clock subsystem is used to respectively provide the required working clock to the master node and each of the slave nodes; Each node in the master node and each of the slave nodes is used to calibrate the accumulated error of the corresponding counter according to the PPS signal.

2. The multi-module computing platform clock synchronization system according to claim 1, wherein Each node in the master node and each of the slave nodes is used to obtain the clock frequency and frequency division ratio of the corresponding channel, and calibrate the accumulated error of the corresponding counter according to the clock frequency, the frequency division ratio, and the PPS signal.

3. The multi-module computing platform clock synchronization system according to claim 1, wherein Each node in the master node and each of the slave nodes is used to calibrate the accumulated error of the corresponding counter once per second according to the PPS signal.

4. The multi-module computing platform clock synchronization system according to claim 1, characterized in that, Each of the slave nodes includes a real-time processor, and a corresponding counter is set on the real-time processor.

5. The multi-module computing platform clock synchronization system according to claim 1, wherein The master node is further used to receive the second pulse from GPS.

6. A clock synchronization method for a multi-module computing platform, characterized in that, Applied to the multi-module computing platform clock synchronization system according to any one of claims 1-5, the method includes: Parsing the second pulse through the master node running the 1588 protocol stack to obtain GPS time and PPS signal; Respectively providing the required working clock to the master node and each slave node through the clock subsystem; Calibrating the accumulated error of the corresponding counter by each node in the master node and each of the slave nodes according to the PPS signal.

7. The method for clock synchronization of a multi-module computing platform according to claim 6, wherein The calibrating the accumulated error of the corresponding counter by each node in the master node and each of the slave nodes according to the PPS signal includes: Obtaining the clock frequency and frequency division ratio of the corresponding channel by each node in the master node and each of the slave nodes, and calibrating the accumulated error of the corresponding counter according to the clock frequency, the frequency division ratio, and the PPS signal.

8. An electronic device, characterized in that, Including a memory and a processor. The memory is used to store a computer program, and the computer program executes the multi-module computing platform clock synchronization method according to claim 6 or 7 when running on the processor.

9. A computer-readable storage medium, characterized in that, It stores a computer program, and the computer program executes the multi-module computing platform clock synchronization method according to claim 6 or 7 when running on the processor.

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