A high-voltage interlock detection system, method, and electric vehicle

Abstract

The present application discloses a high-voltage interlock detection system, comprising: a constant-current source switching circuit, which receives a PWM signal source signal and forms two detection circuits with opposite current directions between the constant-current source switching circuit and the high-voltage interlock loop; an operational amplifier circuit, where different pressure differences formed by the two detection circuits with opposite current directions are input to the operational amplifier circuit, and the operational amplifier circuit outputs a PWM detection signal; a detection unit, which detects the PWM detection signal and the sampling voltage in the detection circuit, and judges the fault of the high-voltage interlock loop according to the duty cycle in the PWM detection signal and the sampling voltage. Through the injection of two PWM signal sources, two current loops are formed in the detection circuit in cooperation with the turn-off of the constant-current source switching circuit, so that the operational amplifier circuit can output a PWM detection signal, and by detecting the frequency and duty cycle of the PWM detection signal and the voltage detection point in the detection circuit, it is judged whether there is a fault in the high-voltage interlock loop and what type of fault it is.

Description

Technical Field

[0001] This application relates to the field of automotive control technologies, and particularly to a high-voltage interlock detection system, method, and electric vehicle. Background Art

[0002] With the advancement of the new energy strategy, new energy vehicles have developed rapidly. Different from traditional vehicle powertrain systems, new energy vehicle powertrain systems include a large number of high-voltage and high-current components, such as motors and motor controllers, battery packs and battery management systems, high-voltage distribution boxes, on-vehicle chargers, etc. The use of a large number of high-voltage and high-current components also brings relatively large safety hazards. Therefore, the high-voltage interlock detection system in high-voltage safety is crucial in the high-voltage detection circuit.

[0003] High-voltage interlock (HVIL) in electric vehicles, which is short for the high-voltage interlock loop (Hazardous Voltage Interlock Loop), refers to using low-voltage signals to check all branches connected to the high-voltage bus in an electric vehicle, including the electrical connection integrity (continuity) of system loops such as the entire battery system, wires, connectors, DCDC, motor controllers, high-voltage boxes, and protective covers.

[0004] Currently, high-voltage interlock signals are mainly used to monitor the connection status of the high-voltage interlock loop, that is, to detect the low-voltage harness connected to the high-voltage interlock loop of a new energy vehicle. This low-voltage harness connects the high-voltage connectors in the vehicle's high-voltage interlock loop in series. By detecting the interlock signals on this low-voltage harness, the status of the high-voltage interlock loop is further monitored. However, the current solution cannot accurately locate the specific position of the loosening of the high-voltage interlock loop, which is not conducive to the maintenance and troubleshooting of the high-voltage interlock loop of electric vehicles, and cannot diagnose the faults that occur in the detection circuit itself. Summary of the Invention

[0005] This application provides a high-voltage interlock detection system, method, and electric vehicle to solve the problem of how to accurately locate the position and type of faults that occur in the high-voltage interlock loop.

[0006] To solve the above technical problems, the present application provides a high-voltage interlock detection system, electrically connected to a high-voltage interlock circuit, including: a constant-current source switching circuit, receiving a PWM (pulse Width Modulation) signal source signal, forming two detection circuits with opposite current directions between the constant-current source switching circuit and the high-voltage interlock circuit; an operational amplifier circuit, the two detection circuits with opposite current directions form different voltage differences and input them to the operational amplifier circuit, and the operational amplifier circuit outputs a PWM detection signal; a detection unit, the detection unit detects the PWM detection signal and the sampling voltage in the detection circuit, and judges the fault of the high-voltage interlock circuit according to the duty cycle in the PWM detection signal and the sampling voltage.

[0007] Further, the constant-current source switching circuit includes: a first transistor, a second transistor, a third transistor, and a fourth transistor. The base of the first transistor is connected to a first PWM signal source, the collector of the first transistor is connected to the emitter of the third transistor, the emitter of the first transistor is connected to a first constant current source, the base of the third transistor is connected to a second PWM signal source, the collector of the third transistor is connected to a second constant current source, the first end of the fourth transistor is connected to the first constant current source, the second end of the fourth transistor is connected to the first end of the second transistor, and the second end of the fourth transistor is connected to the second constant current source.

[0008] Further, the high-voltage interlock detection system is connected to a first high-voltage interlock circuit and a second high-voltage interlock circuit. The high-voltage interlock detection system further includes a first resistor and a second resistor. The first constant current source, the first transistor, the first resistor, the first high-voltage interlock circuit, the second resistor, the second high-voltage interlock circuit, the second transistor, and the second constant current source are sequentially connected to form a first detection circuit.

[0009] Further, the first constant current source, the fourth transistor, the second high-voltage interlock circuit, the second resistor, the first high-voltage interlock circuit, the first resistor, the third transistor, and the second constant current source form a second detection circuit, and the current direction of the second detection circuit is opposite to that of the first detection circuit.

[0010] Further, the operational amplifier circuit includes a first comparator, a second comparator, and a third comparator. A first input terminal of the first comparator is connected to one end of the first resistor, a second input terminal of the first comparator is connected to the other end of the first resistor, an output terminal of the first comparator is respectively connected to a second input terminal of the second comparator and a first input terminal of the third comparator, a first input terminal of the second comparator and a second input terminal of the third comparator are both connected to a reference voltage, and output terminals of the second comparator and the third comparator are both connected to the detection unit.

[0011] Further, the output terminal of the second comparator outputs a first PWM detection signal, and the output terminal of the third comparator outputs a second PWM detection signal.

[0012] Further, the input frequencies and duty cycles of the first PWM signal source and the second PWM signal source are the same.

[0013] Further, the input frequencies of the first PWM signal source and the second PWM signal source are both 88HZ, and the duty cycle is 50%.

[0014] The present invention also provides a detection method for a high-voltage interlock detection system, including: receiving a PWM signal source signal to form two detection loops with opposite current directions between the constant current source switching circuit and the high-voltage interlock loop; the two detection loops with opposite current directions form different pressure differences and input them to the operational amplifier circuit, and the operational amplifier circuit outputs a PWM detection signal; the detection unit detects the PWM detection signal and the sampling voltage in the detection loop, and determines the fault of the high-voltage interlock loop according to the duty cycle in the PWM detection signal and the sampling voltage.

[0015] Further, the constant current source switching circuit includes: a first transistor, a second transistor, a third transistor, and a fourth transistor. The base of the first transistor is connected to the first PWM signal source, the collector of the first transistor is connected to the emitter of the third transistor, the emitter of the first transistor is connected to the first constant current source, the base of the third transistor is connected to the second PWM signal source, the collector of the third transistor is connected to the second constant current source, a first end of the fourth transistor is connected to the first constant current source, a second end of the fourth transistor is connected to a first end of the second transistor, a second end of the fourth transistor is connected to the second constant current source, the third transistor and the fourth transistor are closed, and the first transistor and the second transistor are open, so as to form a counterclockwise current loop between the constant current source switching circuit and the high-voltage interlock loop.

[0016] Further, the third transistor and the fourth transistor are turned off, and the first transistor and the second transistor are turned on, forming a clockwise current loop between the constant current source switching circuit and the high-voltage interlock loop.

[0017] Further, if the duty cycle of the PWM detection signal is within [X - a, X + a], the high-voltage interlock loop is not open or broken, where X is the duty cycle set by the PWM signal source and a is the redundancy set by the high-voltage interlock detection system.

[0018] Further, calculate the current of the detection loop according to the voltage difference between the two input terminals of the operational amplifier circuit and the resistors connected to the two input terminals of the operational amplifier circuit; calculate the total voltage difference of the detection loop according to the sampled voltage detected by the detection unit, and calculate the total resistance of the detection loop according to the current of the detection loop and the total voltage difference of the detection loop. When the total resistance of the detection loop is less than the resistance threshold set by the vehicle environment, there is no large resistance value fault in the detection loop. When the total resistance of the detection loop is greater than or equal to the resistance threshold set by the vehicle environment, there is a large resistance value fault in the detection loop.

[0019] Further, the PWM detection signal includes a first PWM detection signal and a second PWM detection signal, the high-voltage interlock loop includes the first high-voltage interlock loop and the second high-voltage interlock loop. If the duty cycles of the first PWM detection signal and the second PWM detection signal are both within [0, a], then there is an open circuit in the first high-voltage interlock loop or the second high-voltage interlock loop, where a is the redundancy set by the high-voltage interlock detection system.

[0020] Further, a first resistor, a first high-voltage interlock loop, a second resistor, and a second high-voltage interlock loop are connected in series to the constant current source switching circuit in sequence. The two ends of the first resistor are respectively connected to the first input terminal and the second input terminal of the first comparator in the operational amplifier circuit. If the voltage difference between the second input terminal voltage of the first comparator and the ground voltage at the connection between the second resistor and the second high-voltage interlock loop is greater than or equal to the voltage difference threshold, then the first high-voltage interlock loop is open.

[0021] Further, the constant current source switching circuit includes: a first transistor, a second transistor, a third transistor, and a fourth transistor. The base of the first transistor is connected to a first PWM signal source, the collector of the first transistor is connected to the emitter of the third transistor, the emitter of the first transistor is connected to a first constant current source, the base of the third transistor is connected to a second PWM signal source, the collector of the third transistor is connected to a second constant current source, the first end of the fourth transistor is connected to the first constant current source, the second end of the fourth transistor is connected to the first end of the second transistor, and the second end of the fourth transistor is connected to the second constant current source. If the voltage difference between the voltage to ground at the connection between the second resistor and the second high-voltage interlock loop and the voltage to ground at the connection between the fourth transistor and the second transistor is greater than or equal to the voltage difference threshold, the second high-voltage interlock loop is open.

[0022] Further, the voltage difference threshold is 6V.

[0023] Further, the PWM detection signal includes a first PWM detection signal and a second PWM detection signal. If the duty cycle of the first PWM detection signal is within [X - a, X + a], and the duty cycle of the second PWM detection signal is within [0, a], there is a short negative pole fault in the high-voltage interlock loop, where X is the duty cycle set by the PWM signal source, and a is the redundancy set by the high-voltage interlock detection system.

[0024] Further, the PWM detection signal includes a first PWM detection signal and a second PWM detection signal. If the duty cycle of the second PWM detection signal is within [X - a, X + a], and the duty cycle of the first PWM detection signal is within [0, a], there is a short power supply fault in the high-voltage interlock loop, where X is the duty cycle set by the PWM signal source, and a is the redundancy set by the high-voltage interlock detection system.

[0025] The present invention also provides an electric vehicle, including the above-mentioned high-voltage interlock detection system.

[0026] The technical solution of the present application has at least the following advantages:

[0027] By injecting two PWM signal sources and cooperating with the turn-off of the constant current source switching circuit to form two current loops in the clockwise and counterclockwise directions in the detection loop, the operational amplifier circuit can output PWM detection signals, and by detecting the frequency, duty cycle of the PWM detection signals, and the voltage detection points in the detection loop, it is determined whether there is a fault in the high-voltage interlock loop and what type of fault it is.

[0028] The present application also provides an electric vehicle, which has the same beneficial effects as the above-mentioned high-voltage interlock detection system. Description of the Drawings

[0029] To more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the following will briefly introduce the drawings required for the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0030] Figure 1 A detection method using a high-voltage interlock detection system provided by an embodiment of the present invention;

[0031] Figure 2 A schematic structural diagram of a high-voltage interlock detection system provided by an embodiment of the present invention. Specific embodiments

[0032] The following will clearly and completely describe the technical solutions in the present application in conjunction with the drawings. Obviously, the described embodiments are some embodiments of the present application, rather than all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present application.

[0033] In the description of the present application, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present application. In addition, the terms "first", "second", and "third" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance.

[0034] In the description of the present application, it should be noted that unless otherwise clearly specified and limited, the terms "installation", "connection", and "connection" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can also be the communication inside two elements. It can be a wireless connection or a wired connection. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances.

[0035] In addition, the technical features involved in different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0036] The present invention provides a high-voltage interlock detection system, which is electrically connected to a high-voltage interlock circuit to detect the location and type of faults in the high-voltage interlock circuit, and includes:

[0037] A constant current source switching circuit, which receives a PWM signal source signal and forms two detection circuits with opposite current directions between the constant current source switching circuit and the high-voltage interlock circuit;

[0038] An operational amplifier circuit, where the two detection circuits with opposite current directions form different pressure differences and are input to the operational amplifier circuit, and the operational amplifier circuit outputs a PWM detection signal;

[0039] A detection unit, which detects the PWM detection signal and the sampling voltage in the detection circuit, and determines the fault of the high-voltage interlock circuit according to the duty cycle in the PWM detection signal and the sampling voltage.

[0040] By injecting two PWM signal sources and cooperating with the turn-off of the constant current source switching circuit, two current circuits in the clockwise and counterclockwise directions are formed in the detection circuit, so that the operational amplifier circuit can output a PWM detection signal, and by detecting the frequency and duty cycle of the PWM detection signal and the voltage detection point in the detection circuit, it is determined whether there is a fault in the high-voltage interlock circuit and what type of fault it is.

[0041] Figure 1 It is a detection method using the high-voltage interlock detection system provided by the embodiment of the present invention. Refer to Figure 1 The present invention provides a detection method using a high-voltage interlock detection system, including:

[0042] S11. Receive a PWM signal source signal and form two detection circuits with opposite current directions between the constant current source switching circuit and the high-voltage interlock circuit;

[0043] S12. The two detection circuits with opposite current directions form different pressure differences and are input to the operational amplifier circuit, and the operational amplifier circuit outputs a PWM detection signal;

[0044] S13. The detection unit detects the PWM detection signal and the sampling voltage in the detection circuit, and determines the fault of the high-voltage interlock circuit according to the duty cycle in the PWM detection signal and the sampling voltage.

[0045] Embodiment 1

[0046] Figure 2 It is a structural schematic diagram of the high-voltage interlock detection system provided by the embodiment of the present invention. Refer to Figure 2, the constant current source switching circuit includes: a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4. The base of the first transistor T1 is connected to a first PWM signal source, the collector of the first transistor T1 is connected to the emitter of the third transistor T3, the emitter of the first transistor T1 is connected to a first constant current source A1, the base of the third transistor T3 is connected to a second PWM signal source, the collector of the third transistor T3 is connected to a second constant current source, the first end of the fourth transistor T4 is connected to the first constant current source, the second end of the fourth transistor T4 is connected to the first end of the second transistor, and the second end of the fourth transistor T4 is connected to the second constant current source.

[0047] The input frequencies and duty cycles of the first PWM signal source and the second PWM signal source are the same. By inputting two PWM signal sources with the same frequency and opposite duty cycles, the conduction directions of the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are controlled to form two current loops in the clockwise and counterclockwise directions. In the embodiment of the present invention, the input frequencies of the first PWM signal source and the second PWM signal source are both 88HZ, the duty cycle is 50%, and the duty cycle directions are opposite.

[0048] The high-voltage interlock loop includes a first high-voltage interlock loop SEG1 and a second high-voltage interlock loop SEG2. The high-voltage interlock detection system further includes a first resistor R1 and a second resistor R2. The first constant current source, the first transistor T1, the first resistor R1, the first high-voltage interlock loop SEG1, the second resistor R2, the second high-voltage interlock loop SEG2, the second transistor T2, and the second constant current source are sequentially connected to form a first detection loop; the first constant current source, the fourth transistor T4, the second high-voltage interlock loop SEG2, the second resistor R2, the first high-voltage interlock loop SEG1, the first resistor R1, the third transistor T3, and the second constant current source form a second detection loop. The current direction of the second detection loop is opposite to the current direction of the first detection loop. In the embodiment of the present invention, the current of the first detection loop is in the clockwise direction, and the current direction of the second detection loop is in the counterclockwise direction.

[0049] The third transistor and the fourth transistor are closed, and the first transistor and the second transistor are disconnected, forming a counterclockwise current loop between the constant current source switching circuit and the high-voltage interlock loop.

[0050] The third transistor and the fourth transistor are disconnected, and the first transistor and the second transistor are closed, forming a clockwise current loop between the constant current source switching circuit and the high-voltage interlock loop.

[0051] The operational amplifier circuit includes a first comparator, a second comparator, and a third comparator. One end of a first resistor R1 is connected to a first input terminal of the first comparator, and the other end of the first resistor R1 is connected to a second input terminal of the first comparator. An output terminal of the first comparator is respectively connected to a second input terminal of the second comparator and a first input terminal of the third comparator. A first input terminal of the second comparator and a second input terminal of the third comparator are both connected to a reference voltage VREF. Output terminals of the second comparator and the third comparator are both connected to the detection unit. Further, the output terminal of the second comparator outputs a first PWM detection signal, and the output terminal of the third comparator outputs a second PWM detection signal.

[0052] By comparing the voltage magnitudes of the voltage V1 at the first input terminal of the first comparator and the voltage V2 at the second input terminal of the first comparator, a continuous voltage value is output at the output terminal of the first comparator. This continuous voltage value is input to the second input terminal of the second comparator and compared with the reference voltage VREF input to the first input terminal of the second comparator to determine whether the voltage of the first PWM detection signal output at the output terminal of the second comparator is high level or low level; this continuous voltage value is input to the first input terminal of the third comparator and compared with the reference voltage VREF input to the second input terminal of the third comparator to determine whether the voltage of the second PWM detection signal output at the output terminal of the third comparator is high level or low level.

[0053] Through the injection of two PWM signal sources (a first PWM signal source and a second PWM signal source), and in cooperation with the turning off of a first transistor, a second transistor, a third transistor, and a fourth transistor, two current loops, clockwise and counterclockwise, are formed in the detection loop, enabling both the second comparator and the third comparator to output PWM detection signals. By detecting the frequency, duty cycle of the PWM detection signals, and the voltage detection points in the detection loop, it is determined whether there is a fault in the high-voltage interlock loop and what type of fault it is.

[0054] If the duty cycle of the PWM detection signal is within [X - a, X + a], that is, the duty cycles of both the first PWM detection signal and the second PWM detection signal are within the range of [X - a, X + a], the high-voltage interlock loop is not open or broken, where X is the duty cycle set by the PWM signal source, that is, the same duty cycle set by the first PWM signal source and the second PWM signal source, and a is the redundancy amount set by the high-voltage interlock detection system.

[0055] The current of the detection loop is calculated according to the voltage difference between the two input terminals of the operational amplifier circuit and the resistor connected to the two input terminals of the operational amplifier circuit; in the first embodiment of the present invention, the current of the detection loop is calculated as I=(V1-V2) / R2, wherein V1 is the voltage of the first input terminal of the first comparator, and V2 is the voltage of the second input terminal of the first comparator;

[0056] The total voltage difference of the detection loop is calculated according to the sampled voltage detected by the detection unit, and the total resistance of the detection loop is calculated according to the current of the detection loop and the total voltage difference of the detection loop. In the first embodiment of the present invention, the total voltage difference of the detection loop is V1-V4, V1 is the voltage of the first input terminal of the first comparator, and V4 is the voltage to the ground at the connection point between the fourth transistor and the second transistor. The total resistance R of the detection loop is calculated according to the total voltage difference V1-V4 of the detection loop and the current I of the detection loop. 总 =(V1–V4) / I. When the total resistance of the detection circuit is less than the resistance threshold set by the vehicle environment, the detection circuit does not have a large resistance fault; when the total resistance of the detection circuit is greater than or equal to the resistance threshold set by the vehicle environment, the detection circuit has a large resistance fault.

[0057] If the duty cycle of the first PWM detection signal and the duty cycle of the second PWM detection signal are both within [0, a], that is, the duty cycle of the first PWM detection signal and the duty cycle of the second PWM detection signal are both less than or equal to 6%, then the first high-voltage interlocking loop SEG1 or the second high-voltage interlocking loop SEG2 is open, where a is the redundancy set by the high-voltage interlocking detection system; if the voltage difference between the second input terminal voltage V2 of the first comparator and the ground voltage V3 at the connection point of the second resistor R2 and the second high-voltage interlocking loop SEG2 is greater than or equal to 6V, then the first high-voltage interlocking loop SEG1 is open; when the first high-voltage interlocking loop SEG1 is open, the clockwise current loop formed by the first detection loop and the counterclockwise current loop formed by the second detection loop Both current loops are blocked, so the duty cycles of the first PWM detection signal and the second PWM detection signal are close to 0. When the detection loop forms a clockwise current loop, the voltage of the second input terminal voltage V2 of the first comparator is close to the power supply voltage, and the voltage of the ground voltage V3 at the connection between the second resistor R2 and the second high-voltage interlocking loop SEG2 is close to 0. When the detection loop forms a counterclockwise current loop, the voltage of the ground voltage V3 at the connection between the second resistor R2 and the second high-voltage interlocking loop SEG2 is close to the power supply voltage, and the voltage of the second input terminal voltage V2 of the first comparator is close to 0. Therefore, no matter what direction the current is formed by the detection loop, the voltage difference |V3-V2| is the largest. In Embodiment 1 of the present invention, the threshold value of the voltage difference |V3-V2| is 6V.

[0058] If the voltage difference between the voltage V3 of the connection between the second resistor R2 and the second high-voltage interlock loop SEG2 and the ground and the voltage V4 of the connection between the fourth transistor and the second transistor is greater than or equal to 6V, then the second high-voltage interlock loop SEG2 is open. When the second high-voltage interlock loop SEG2 is open, the clockwise current loop formed by the first detection loop and the counterclockwise current loop formed by the second detection loop are both not conductive. Therefore, the duty cycles of the first PWM detection signal and the second PWM detection signal are both close to 0. When the detection loop forms a clockwise current loop, the voltage V3 of the connection between the second resistor R2 and the second high-voltage interlock loop SEG2 is close to the power supply voltage, and the voltage V4 of the connection between the fourth transistor and the second transistor is close to 0. When the detection loop forms a counterclockwise current loop, the voltage V4 of the connection between the fourth transistor and the second transistor is close to the power supply voltage, and the voltage V3 of the connection between the second resistor R2 and the second high-voltage interlock loop SEG2 is close to 0. Therefore, regardless of the direction of the current formed by the detection loop, the voltage difference |V3 - V4| is the largest. In the first embodiment of the present invention, the threshold of the voltage difference |V3 - V4| is 6V.

[0059] The PWM detection signal includes a first PWM detection signal and a second PWM detection signal. If the duty cycle of the first PWM detection signal is within [X - a, X + a], and the duty cycle of the second PWM detection signal is within [0, a], there is a short negative pole fault in the high-voltage interlock loop, where X is the duty cycle set by the PWM signal source, and a is the redundancy set by the high-voltage interlock detection system. When a short negative pole fault occurs in the high-voltage interlock loop, the detection loop forms a clockwise current loop, the first PWM detection signal is high level, and the second PWM detection signal is low level. When the detection loop forms a counterclockwise current loop, the first PWM detection signal is low level, and the second PWM detection signal is low level. Therefore, when a short negative pole fault occurs in the high-voltage interlock loop, the second PWM detection signal is always low level, that is, the duty cycle of the second PWM detection signal is close to 0, while the duty cycle of the first PWM detection signal is within [X - a, X + a] (the duty cycle is normal).

[0060] The PWM detection signal includes a first PWM detection signal and a second PWM detection signal. If the duty cycle of the second PWM detection signal is within [X - a, X + a], and the duty cycle of the first PWM detection signal is within [0, a], there is a short power supply fault in the high-voltage interlock loop, where X is the duty cycle set by the PWM signal source and a is the redundancy set by the high-voltage interlock detection system. When a short power supply fault occurs in the high-voltage interlock loop, a clockwise current loop is formed in the detection loop, the first PWM detection signal is at a low level, and the second PWM detection signal is at a high level. When a counterclockwise current loop is formed in the detection loop, the first PWM detection signal is at a low level and the second PWM detection signal is at a low level. Therefore, when a short power supply fault occurs in the high-voltage interlock loop, the first PWM detection signal is always at a low level, that is, the duty cycle of the first PWM detection signal is close to 0, while the duty cycle of the second PWM detection signal is within [X - a, X + a] (the duty cycle is normal).

[0061] If none of the above situations are met, it indicates that there are other faults in the high-voltage interlock detection system.

[0062] To solve the above technical problems, the present invention also provides an electric vehicle, including the high-voltage interlock detection system as described in any one of the above.

[0063] For the introduction of an electric vehicle provided by the present invention, please refer to the above embodiments, and the present invention will not be elaborated herein.

[0064] In addition, the present invention also provides a computer device. The computer device includes a memory and a processor. The memory can be used to store a computer program, and the processor runs the computer program, so that the computer device executes the above method or the functions of each module in the high-voltage interlock detection system.

[0065] The memory may include a program storage area and a data storage area. Among them, the program storage area can store an operating system, application programs required for at least one function (such as a sound playback function, an image playback function, etc.). The data storage area can store data created according to the use of the mobile terminal (such as audio data, phone book, etc.). In addition, the memory can include a high-speed random access memory, and can also include a non-volatile memory, such as at least one magnetic disk storage device, a flash memory device, or other volatile solid-state storage devices.

[0066] This embodiment also provides a computer storage medium for storing the computer program used in the above computer device.

[0067] In several embodiments provided by the present application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architectures, functions, and operations of devices, methods, and computer program products according to multiple embodiments of the present application. In this regard, each block in the flowchart or block diagram may represent a module, a program segment, or a part of code, and a module, a program segment, or a part of code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than that marked in the accompanying drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, and the combination of blocks in the block diagram and / or flowchart, can be implemented by a dedicated hardware-based system for performing the specified functions or actions, or can be implemented by a combination of dedicated hardware and computer instructions.

[0068] In addition, in each embodiment of the present application, each functional module can be integrated together to form an independent part, or each module can exist alone, or two or more modules can be integrated to form an independent part.

[0069] If the function is implemented in the form of a software functional module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods in each embodiment of the present application. The aforementioned storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (ROMs), random access memories (RAMs), magnetic disks, or optical discs that can store program codes.

[0070] Obviously, the above embodiments are merely examples given for clear illustration and are not limitations on the implementation manners. For those of ordinary skill in the art, other different forms of changes or variations can be made based on the above description. It is not necessary and impossible to enumerate all the implementation manners here. And the obvious changes or variations derived therefrom are still within the protection scope of the present application.

Claims

1. A high-voltage interlock detection system, electrically connected to a high-voltage interlock circuit, characterized in that, Including: A constant current source switching circuit for receiving a PWM signal source signal and forming two detection circuits with opposite current directions between the constant current source switching circuit and the high voltage interlock loop; An operational amplifier circuit, where the two detection circuits with opposite current directions form different voltage differences and are input to the operational amplifier circuit, and the operational amplifier circuit is used to output a PWM detection signal; A detection unit for detecting the PWM detection signal and the sampling voltage in the detection circuit, and judging the fault of the high voltage interlock loop according to the duty cycle in the PWM detection signal and the sampling voltage; The PWM detection signal includes a first PWM detection signal and a second PWM detection signal, and the high voltage interlock loop includes a first high voltage interlock loop and a second high voltage interlock loop; If the duty cycles of the first PWM detection signal and the second PWM detection signal are both within [0, a], then there is an open circuit in the first high voltage interlock loop or the second high voltage interlock loop, where a is the redundancy set by the high voltage interlock detection system; A first resistor, a first high voltage interlock loop, a second resistor, and a second high voltage interlock loop are connected in series to the constant current source switching circuit in sequence. The two ends of the first resistor are respectively connected to the first input terminal and the second input terminal of the operational amplifier circuit. If the voltage difference between the voltage at the second input terminal of the operational amplifier circuit and the voltage to ground at the connection between the second resistor and the second high voltage interlock loop is greater than or equal to the voltage difference threshold, then the first high voltage interlock loop is open; The constant current source switching circuit includes: a first constant current source, a second constant current source, a first transistor, a second transistor, a third transistor, and a fourth transistor. The base of the first transistor is connected to the first PWM signal source, the collector of the first transistor is connected to the emitter of the third transistor, the emitter of the first transistor is connected to the first constant current source, the base of the third transistor is connected to the second PWM signal source, the collector of the third transistor is connected to the second constant current source, the first end of the fourth transistor is connected to the first constant current source, the second end of the fourth transistor is connected to the first end of the second transistor, and the second end of the fourth transistor is connected to the second constant current source. If the voltage difference between the voltage to ground at the connection between the second resistor and the second high voltage interlock loop and the voltage to ground at the connection between the fourth transistor and the second transistor is greater than or equal to the voltage difference threshold, the second high voltage interlock loop is open; Calculate the current of the detection loop according to the voltage difference between the two input terminals of the operational amplifier circuit and the resistors connected to the two input terminals of the operational amplifier circuit; calculate the total voltage difference of the detection loop according to the sampled voltage detected by the detection unit, and calculate the total resistance of the detection loop according to the current of the detection loop and the total voltage difference of the detection loop. When the total resistance of the detection loop is less than the resistance threshold set by the vehicle environment, there is no large resistance fault in the detection loop. When the total resistance of the detection loop is greater than or equal to the resistance threshold set by the vehicle environment, there is a large resistance fault in the detection loop.

2. The high-voltage interlock detection system according to claim 1, characterized in that The first constant current source, the first transistor, the first resistor, the first high voltage interlock loop, the second resistor, the second high voltage interlock loop, the second transistor and the second constant current source are connected in sequence to form a first detection loop.

3. The high-voltage interlock detection system according to claim 2, characterized in that, The first constant current source, the fourth transistor, the second high voltage interlock loop, the second resistor, the first high voltage interlock loop, the first resistor, the third transistor and the second constant current source form a second detection loop, and the current direction of the second detection loop is opposite to that of the first detection loop.

4. The high-voltage interlock detection system according to claim 3, wherein The operational amplifier circuit includes a first comparator, a second comparator and a third comparator. The first input terminal of the first comparator is connected to one end of the first resistor, the second input terminal of the first comparator is connected to the other end of the first resistor, the output terminal of the first comparator is respectively connected to the second input terminal of the second comparator and the first input terminal of the third comparator, the first input terminals of the second comparator and the third comparator are both connected to a reference voltage, and the output terminals of the second comparator and the third comparator are both connected to the detection unit.

5. The high-voltage interlock detection system according to claim 4, wherein, The output terminal of the second comparator outputs a first PWM detection signal, and the output terminal of the third comparator outputs a second PWM detection signal.

6. The high-voltage interlock detection system according to claim 1, characterized in that The input frequencies and duty cycles of the first PWM signal source and the second PWM signal source are the same.

7. The high-voltage interlock detection system according to claim 6, wherein, The input frequencies of the first PWM signal source and the second PWM signal source are both 88HZ, and the duty cycle is 50%.

8. A detection method for a high-voltage interlock detection system, characterized in that, Including: Receive the signal of the PWM signal source and form two detection loops with opposite current directions between the constant current source switch circuit and the high voltage interlock loop; The two detection loops with opposite current directions form different voltage differences and input them into the operational amplifier circuit, and the operational amplifier circuit outputs a PWM detection signal; The detection unit detects the PWM detection signal and the sampled voltage in the detection loop, and judges the fault of the high voltage interlock loop according to the duty cycle in the PWM detection signal and the sampled voltage; The PWM detection signal includes a first PWM detection signal and a second PWM detection signal, and the high voltage interlock loop includes a first high voltage interlock loop and a second high voltage interlock loop; If the duty cycles of the first PWM detection signal and the second PWM detection signal are both within [0, a], there is an open circuit in the first high-voltage interlock loop or the second high-voltage interlock loop, where a is the redundancy set by the high-voltage interlock detection system; The first resistor, the first high-voltage interlock loop, the second resistor, and the second high-voltage interlock loop are connected in series in turn and then connected to the constant current source switching circuit. The two ends of the first resistor are respectively connected to the first input terminal and the second input terminal of the operational amplifier circuit in the operational amplifier circuit. If the voltage difference between the voltage at the second input terminal of the operational amplifier circuit and the voltage to ground at the connection between the second resistor and the second high-voltage interlock loop is greater than or equal to the voltage difference threshold, the first high-voltage interlock loop is open; The constant current source switching circuit includes: a first constant current source, a second constant current source, a first transistor, a second transistor, a third transistor, and a fourth transistor. The base of the first transistor is connected to the first PWM signal source, the collector of the first transistor is connected to the emitter of the third transistor, the emitter of the first transistor is connected to the first constant current source, the base of the third transistor is connected to the second PWM signal source, the collector of the third transistor is connected to the second constant current source, the first end of the fourth transistor is connected to the first constant current source, the second end of the fourth transistor is connected to the first end of the second transistor, and the second end of the fourth transistor is connected to the second constant current source. If the voltage difference between the voltage to ground at the connection between the second resistor and the second high-voltage interlock loop and the voltage to ground at the connection between the fourth transistor and the second transistor is greater than or equal to the voltage difference threshold, the second high-voltage interlock loop is open; Calculate the current of the detection loop according to the voltage difference between the two input terminals of the operational amplifier circuit and the resistors connected to the two input terminals of the operational amplifier circuit; calculate the total voltage difference of the detection loop according to the sampled voltage detected by the detection unit, and calculate the total resistance of the detection loop according to the current of the detection loop and the total voltage difference of the detection loop. When the total resistance of the detection loop is less than the resistance threshold set by the vehicle environment, there is no large resistance fault in the detection loop. When the total resistance of the detection loop is greater than or equal to the resistance threshold set by the vehicle environment, there is a large resistance fault in the detection loop.

9. The detection method of the high-voltage interlock detection system according to claim 8, wherein The third transistor and the fourth transistor are closed, and the first transistor and the second transistor are open, forming a counterclockwise current loop between the constant current source switching circuit and the high-voltage interlock loop.

10. The detection method of the high-voltage interlock detection system according to claim 9, characterized in that, The third transistor and the fourth transistor are open, and the first transistor and the second transistor are closed, forming a clockwise current loop between the constant current source switching circuit and the high-voltage interlock loop.

11. The detection method of the high-voltage interlock detection system according to claim 8, characterized in that, If the duty cycle of the PWM detection signal is within [X - a, X + a], the high-voltage interlock loop is not open or broken, where X is the duty cycle set by the PWM signal source and a is the redundancy set by the high-voltage interlock detection system.

12. The detection method of the high-voltage interlock detection system according to claim 8, characterized in that, Both ends of the first resistor are respectively connected to the first input terminal and the second input terminal of the first comparator in the operational amplifier circuit. If the voltage difference between the voltage at the second input terminal of the first comparator and the ground voltage at the connection between the second resistor and the second high-voltage interlock loop is greater than or equal to the voltage difference threshold, the first high-voltage interlock loop is open.

13. The detection method of the high-voltage interlock detection system according to claim 8 or 12, characterized in that, The voltage difference threshold is 6V.

14. The detection method of the high-voltage interlock detection system according to claim 8, characterized in that, The PWM detection signal includes a first PWM detection signal and a second PWM detection signal. If the duty cycle of the first PWM detection signal is within [X - a, X + a] and the duty cycle of the second PWM detection signal is within [0, a], there is a short negative pole fault in the high-voltage interlock loop, where X is the duty cycle set by the PWM signal source and a is the redundancy set by the high-voltage interlock detection system.

15. The detection method of the high-voltage interlock detection system according to claim 8, characterized in that, The PWM detection signal includes a first PWM detection signal and a second PWM detection signal. If the duty cycle of the second PWM detection signal is within [X - a, X + a] and the duty cycle of the first PWM detection signal is within [0, a], there is a short power supply fault in the high-voltage interlock loop, where X is the duty cycle set by the PWM signal source and a is the redundancy set by the high-voltage interlock detection system.

16. An electric vehicle, characterized in that, Including the high-voltage interlock detection system according to any one of claims 1-7.

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