Method, device and electronic equipment for generating random instruction verifiers

Abstract

Embodiments of the present application provide a method, device and electronic equipment for generating a random instruction verification program, the method comprising: obtaining an instruction template of a directional instruction sequence to be generated when it is determined that a generation constraint condition of the directional instruction sequence is satisfied, the instruction template containing operation code constraint information of the directional instruction sequence; judging whether the directional instruction sequence contains a jump instruction according to the operation code constraint information; if the directional instruction sequence contains a jump instruction, determining a storage space corresponding to the directional instruction sequence according to the instruction template and the jump instruction; if the directional instruction sequence does not contain a jump instruction, allocating a storage space to the directional instruction sequence according to a number of instructions contained in the directional instruction sequence; and generating the directional instruction sequence in the storage space according to the instruction template. Embodiments of the present application are beneficial to improving the generation efficiency of a random verification program.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, and in particular, to a method and device for generating random instruction verification program and electronic equipment. BACKGROUND

[0002] With the development of ultra large scale integrated circuit technology, the structure of microprocessor is more and more complex, and more and more functions are integrated on a single microprocessor chip. The instruction set of microprocessor is continuously expanded, and the number and types of instructions are greatly increased, which leads to the complexity of microprocessor function verification and long verification period, and inevitably affects the development time of the processor.

[0003] Therefore, how to generate a more efficient test program method, improve the generation efficiency and quality of random instruction verification program, and accelerate the convergence speed of microprocessor function verification coverage rate, has become a problem to be solved. SUMMARY

[0004] The embodiments of the present application provide a method and device for generating random instruction verification program and electronic equipment, which can improve the generation efficiency and quality of random instruction verification program and accelerate the convergence speed of microprocessor function verification coverage rate.

[0005] In order to solve the above problems, the embodiments of the present application disclose a method for generating random instruction verification program, the random instruction verification program is used for function verification of microprocessor, the random instruction verification program includes a directional instruction sequence, and the method comprises the following steps:

[0006] When it is determined that the generation constraint condition of the directional instruction sequence is met, an instruction template of the directional instruction sequence to be generated is acquired, wherein the instruction template contains operation code constraint information of the directional instruction sequence;

[0007] It is judged whether the directional instruction sequence contains a jump instruction according to the operation code constraint information;

[0008] If the directional instruction sequence contains a jump instruction, a storage space corresponding to the directional instruction sequence is determined according to the instruction template and the jump instruction;

[0009] The directional instruction sequence is generated in the storage space according to the instruction template.

[0010] On the other hand, the embodiments of the present application disclose a device for generating random instruction verification program, the random instruction verification program is used for function verification of microprocessor, the random instruction verification program includes a directional instruction sequence, and the device comprises:

[0011] An instruction template obtaining module is configured to obtain an instruction template of the to-be-generated directional instruction sequence when it is determined that the generation constraint condition of the directional instruction sequence is met, wherein the instruction template contains operation code constraint information of the directional instruction sequence;

[0012] A jump instruction judging module is configured to judge whether the directional instruction sequence contains a jump instruction according to the operation code constraint information.

[0013] A first determining module is configured to determine a storage space corresponding to the directional instruction sequence according to the instruction template and the jump instruction if the directional instruction sequence contains a jump instruction.

[0014] An instruction sequence generating module is configured to generate the directional instruction sequence in the storage space according to the instruction template.

[0015] In another aspect, the embodiment of the present application further discloses an electronic device, which comprises a processor, a memory, a communication interface and a communication bus, the processor, the memory and the communication interface complete communication with each other through the communication bus; the memory is used for storing at least one executable instruction, and the executable instruction makes the processor execute the method for generating a random instruction verification program.

[0016] The embodiment of the present application further discloses a readable storage medium, when the instruction in the storage medium is executed by the processor of the electronic device, the electronic device can execute the method for generating a random instruction verification program.

[0017] The embodiment of the present application has the following advantages:

[0018] The method, device and electronic device for generating a random instruction verification program provided by the embodiment of the present application can judge whether the directional instruction sequence contains a jump instruction according to the operation code constraint information contained in the instruction template corresponding to the to-be-generated directional instruction sequence, and then select different ways to allocate storage space for the directional instruction sequence. Specifically, if the directional instruction sequence contains a jump instruction, the storage space corresponding to the directional instruction sequence is determined according to the instruction template and the jump instruction; if the directional instruction sequence does not contain a jump instruction, the storage space is allocated for the directional instruction sequence according to the number of instructions contained in the directional instruction sequence. Finally, the directional instruction sequence is generated in the storage space according to the instruction template. The embodiment of the present application can avoid the failure of generating the directional instruction sequence due to the occupation of the storage space in the process of generating the directional instruction sequence, ensure the success rate of generating the directional instruction sequence, and be beneficial to improving the generation efficiency and quality of the random verification program and accelerating the convergence speed of the microprocessor function verification coverage. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the description of the embodiments of the present application. Obviously, the drawings described in the following description are only some embodiments of the present application, and all other drawings obtained by those of ordinary skill in the art without creative labor based on these drawings also belong to the protection scope of the present application.

[0020] Figure 1 is a method flow chart for generating a random instruction verification program according to an embodiment of the present application;

[0021] Figure 2 is a step flow chart for determining a storage space according to an embodiment of the present application;

[0022] Figure 3 is a storage space allocation schematic diagram according to an embodiment of the present application;

[0023] Figure 4 is another storage space allocation schematic diagram according to an embodiment of the present application;

[0024] Figure 5 is a step flow chart for generating a second instruction sub-sequence according to an embodiment of the present application;

[0025] Figure 6 is a step flow chart for executing a directional instruction sequence according to an embodiment of the present application;

[0026] Figure 7 is a step flow chart for generating a loop instruction group according to an embodiment of the present application;

[0027] Figure 8 is a step flow chart for generating a directional instruction sequence according to an embodiment of the present application;

[0028] Figure 9 is a structure block diagram of a device for generating a random instruction verification program according to an embodiment of the present application;

[0029] Figure 10 is a structure block diagram of an electronic device for generating a random instruction verification program according to an embodiment of the present application. DETAILED DESCRIPTION

[0030] The technical solutions of the embodiments of the present application will be described clearly and completely in the following with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, and all other embodiments obtained by those of ordinary skill in the art without creative labor based on these embodiments also belong to the protection scope of the present application.

[0031] Method embodiments

[0032] ReferenceFigure 1 Fig. 1 shows a flow chart of a method for generating a random instruction verification program according to an embodiment of the present application, which can include the following steps:

[0033] In step 101, an instruction template of a directional instruction sequence to be generated is obtained when it is determined that the generation constraint condition of the directional instruction sequence is satisfied, wherein the instruction template contains operation code constraint information of the directional instruction sequence.

[0034] In step 102, it is determined whether the directional instruction sequence contains a jump instruction according to the operation code constraint information.

[0035] In step 103, if the directional instruction sequence contains a jump instruction, a storage space corresponding to the directional instruction sequence is determined according to the instruction template and the jump instruction.

[0036] In step 104, if the directional instruction sequence does not contain a jump instruction, a storage space is allocated to the directional instruction sequence according to the number of instructions contained in the directional instruction sequence.

[0037] In step 105, the directional instruction sequence is generated in the storage space according to the instruction template.

[0038] It should be noted that the method for generating a random instruction verification program provided by the embodiment of the present application is mainly used for generating a random instruction verification program containing a directional instruction sequence, which is used for function verification of a microprocessor to simulate the execution process of the microprocessor on the directional instruction sequence in actual application.

[0039] The method for generating a random instruction verification program provided by the embodiment of the present application can be realized in the form of software, hardware, firmware or any combination thereof, for example, loaded and executed by a microprocessor in a mobile phone, a digital camera, a tablet computer, a notebook computer, a desktop computer, a network server and the like, so as to simplify the generation process of the random instruction verification program and improve the verification efficiency of the microprocessor.

[0040] As an example, the method for generating a random instruction verification program is applicable to a computing device, which is any electronic device having a computing function, such as a mobile phone, a digital camera, a tablet computer, a notebook computer, a desktop computer, a network server, etc., and can load and execute the method for generating a random instruction verification program. The computing device can include a central processing unit (CPU) or a graphics processing unit (GPU), a digital signal processor, or other forms of processing units having data processing and / or instruction execution capabilities, a storage unit, etc. The computing device can also be installed with an operating system, an application programming interface, etc., to implement the method for generating a random instruction verification program provided by the embodiments of the present application through running codes or execution.

[0041] It can be understood that the random instruction verification program is an instruction sequence generated based on some constraint information in some way, and the instruction types included in the random instruction verification program and the number of instructions corresponding to each instruction type can be randomly set. In actual applications, the instructions in the random instruction verification program can be divided into random instructions and directional instructions according to the constraint information or the instruction generation manner. Among them, the instruction type and the instruction sequence of the random instruction are usually unconstrained, and the weight value of each instruction type can be preset in advance, and the instruction type of the random instruction generated at a certain moment can be randomly selected according to the weight value corresponding to each instruction type in the process of generating the random instruction verification program. Compared with the random instruction, the instruction type and the instruction sequence of the directional instruction are usually fixed. A plurality of directional instructions form a directional instruction sequence, and the arrangement order of each directional instruction in the directional instruction sequence is fixed. When generating the directional instruction sequence, the corresponding instruction template can be set according to the actual demand, and the required instruction types are arranged in order on the instruction template, so that the corresponding directional instruction sequence is generated according to the instruction template in the process of generating the random instruction verification program.

[0042] In the embodiments of the present application, the "template" strategy can be used to generate the directional instruction sequence in the random instruction verification program. It should be noted that the instruction types included in the directional instruction sequence are usually determined by the operation code constraint information. According to the instruction types included in the directional instruction sequence to be generated, the execution demand, etc., the instruction template used to generate the directional instruction sequence is divided into four categories in the embodiments of the present application:

[0043] 1) The first instruction template (sequence_operate_mode, SOM): the operation code constraint information and the operand constraint information of the directional instruction sequence to be generated are included in the instruction template, and the execution demand is that the generated directional instruction sequence does not need to be executed in a loop;

[0044] 2) the second instruction template (sequence_operate_cycle_mode, SOC M): the instruction template contains the operation code constraint information and the operand constraint information of the to-be-generated directional instruction sequence, and the execution requirement is that the to-be-generated directional instruction sequence needs to be executed in a loop;

[0045] 3) the third instruction template (sequence_mode, SM): the instruction template contains the operation code constraint information of the to-be-generated directional instruction sequence, and the execution requirement is that the to-be-generated directional instruction sequence does not need to be executed in a loop;

[0046] 4) the fourth instruction template (sequence_cycle_mode, SCM): the instruction template contains the operation code constraint information of the to-be-generated directional instruction sequence, and the execution requirement is that the to-be-generated directional instruction sequence needs to be executed in a loop.

[0047] The operation code constraint information is used to constrain the instruction type of an instruction, and the operand constraint information is used to constrain the data source required by the operation of the instruction execution. An instruction is usually composed of two parts, namely, an operation code and an operand. The operation code determines the instruction type of the instruction, that is, limits the operation to be completed by the instruction; and the operand determines the data participating in the operation and the storage address of the data when the instruction is executed. For example, an addition instruction "add $1 $2 $3" has an operation code "add" and an operand "$1 $2 $3". According to the operation code and the operand, it can be determined that the addition instruction is used to add the values in registers $1 and $2 and store the result in register $3.

[0048] In actual application, the corresponding instruction template can be selected to generate the directional instruction sequence in the random instruction verification program according to the actual test requirement. For example, if the test requirement is to test the loop execution of the directional instruction sequence, the second instruction template or the fourth instruction template can be selected to generate the directional instruction sequence; if the test requirement does not contain the test of the loop execution process of the directional instruction sequence, the first instruction template or the third instruction template can be selected to generate the directional instruction sequence.

[0049] In the embodiment of the application, according to the operation code constraint information in the instruction template, the instruction type of each instruction included in the to-be-generated directional instruction sequence can be determined. Further, if the instruction template also contains the operand constraint information, the operand of each instruction in the to-be-generated directional instruction sequence can be directly set according to the operand constraint information, without the need to manually set or randomly generate the operand of each instruction.

[0050] It can be understood that the directional instruction sequence generated by the embodiment of the present application does not exist alone in the random instruction verification program, but is allowed to be embedded in different positions of the random instruction verification program. Alternatively, the method further comprises: generating a random instruction according to a preset rule; generating the directional instruction sequence when a generation constraint condition of the directional instruction sequence is met, and continuing to generate the random instruction after the directional instruction sequence is generated; and obtaining the random instruction verification program according to the directional instruction sequence and the random instruction. Taking the random instruction verification program comprising the random instruction and the directional instruction sequence as an example, when the random instruction verification program is generated, the random instruction can be generated according to a preset rule, wherein the preset rule can be determined according to the test requirement of the random instruction verification program. The generation constraint condition of the directional instruction sequence can be that the current instruction to be generated is the first instruction in the directional instruction sequence. If it is determined that the generation constraint condition of the directional instruction sequence is met, the directional instruction sequence can be generated by using the method provided by the embodiment of the present application, and the random instruction is continued to be generated after the directional instruction sequence is generated. The random instruction and the directional instruction sequence jointly constitute the random instruction verification program. In other words, the instruction sequence contained in the random instruction verification program generated based on the method for generating the random instruction verification program provided by the embodiment of the present application can be divided into two categories: one is the directional instruction sequence obtained according to the scheme provided by the present application, and the other is the instruction sequence generated by using other generation methods, such as the random instruction, the loop instruction sequence, and the like.

[0051] Since the position of the generated directional instruction sequence in the random instruction verification program is not fixed, in the process of generating the directional instruction sequence, the current storage space can have been written with other instructions, and the directional instruction sequence is not allowed to be written again. The execution order of the instructions in the directional instruction sequence is fixed, and therefore a continuous storage space is required to write the directional instruction sequence. If the current storage space is already occupied, the storage space needs to be reallocated for the directional instruction sequence.

[0052] In the process of generating the random instruction, if the current storage space is occupied, the storage space of the random instruction to be generated can be selected by inserting a jump instruction. However, in the process of generating the directional instruction sequence, other instructions are not allowed to be inserted into the directional instruction sequence, and therefore the storage space of the directional instruction sequence cannot be reallocated by inserting a jump instruction.

[0053] To solve this problem, to realize the continuous storage of the directional instruction sequence, the embodiment of the present application first judges whether the directional instruction sequence to be generated contains a jump instruction through the operation code constraint information in the instruction template when generating the directional instruction sequence. If the directional instruction sequence contains a jump instruction, the storage space corresponding to the directional instruction sequence can be further determined according to the instruction template and the jump instruction. If the directional instruction sequence does not contain a jump instruction, the storage space for the directional instruction sequence can be directly allocated according to the number of instructions contained in the directional instruction sequence. Finally, the directional instruction sequence is generated in the determined storage space according to the instruction template.

[0054] For example, if the directional instruction sequence does not contain a jump instruction, each instruction in the directional instruction sequence generated according to the four types of instruction templates SOM, SOCM, SCM and SM provided by the embodiment of the present application will be sequentially executed. For electronic devices with the same processor core, the storage space occupied by each instruction generated is fixed, so when the instructions in the directional instruction sequence are sequentially executed, the size of the storage space required by the directional instruction sequence can be determined according to the number of instructions contained in the directional instruction sequence. For example, assuming that the storage space required by the binary code of an instruction is 32 bits, i.e. 4 bytes, and the number of instructions contained in the directional instruction sequence to be generated is N, the storage space required by the directional instruction sequence is 4*N bytes. After determining the size of the storage space required by the directional instruction sequence, when generating the directional instruction sequence, only a continuous space not less than the storage space required by the directional instruction sequence needs to be found as the storage space of the directional instruction sequence, so that the continuous storage of the directional instruction sequence can be realized, and the generation failure of the directional instruction sequence caused by the occupation of the storage space in the process of generating the directional instruction sequence can be avoided.

[0055] If the directional instruction sequence contains a jump instruction, the storage space corresponding to the directional instruction sequence is determined according to the instruction template and the jump instruction. Specifically, in the embodiment of the present application, different ways can be selected to determine the storage space corresponding to the directional instruction sequence to be generated for different instruction templates.

[0056] As an example, step 103 of determining the storage space corresponding to the directional instruction sequence according to the instruction template and the jump instruction comprises:

[0057] Sub-step 1031, splitting the directional instruction sequence into at least two sequentially executed instruction subsequences according to the jump instruction, wherein the instruction subsequences include a first instruction subsequence and a second instruction subsequence;

[0058] Sub-step 1032, allocating a first storage space for the first instruction subsequence according to the number of instructions contained in the first instruction subsequence;

[0059] Sub-step 1033, allocating a second storage space for the second instruction sub-sequence according to the constraint condition of the operand of the instruction template for the directional instruction sequence;

[0060] Sub-step 1034, determining the first storage space corresponding to the first instruction sub-sequence and the second storage space corresponding to the second instruction sub-sequence as the storage space of the directional instruction sequence.

[0061] The last instruction of the first instruction sub-sequence is a jump instruction, i.e., the last instruction of the first instruction sub-sequence is a jump instruction; the second instruction sub-sequence does not contain a jump instruction; in the instruction execution process, the first instruction sub-sequence is executed earlier than the corresponding second instruction sub-sequence.

[0062] If the directional instruction sequence contains a jump instruction, the directional instruction sequence will not be sequentially stored in the process of generating the directional instruction sequence, but will go to the storage space corresponding to the target address of the jump instruction to generate the next instruction of the jump instruction, which results in that the storage space corresponding to the directional instruction sequence is discontinuous, and if other instructions have been written in the storage space corresponding to the target address of the jump instruction, the next instruction of the jump instruction cannot be normally generated, resulting in the failure of the directional instruction sequence.

[0063] The specific process of generating the directional instruction sequence will be illustrated below by taking the four instruction templates provided by the embodiments of the present application as examples. Referring to Table 1, the four instruction templates provided by the embodiments of the present application are shown.

[0064] Table 1

[0065]

[0066] The first instruction template and the second instruction template contain the opcode constraint information and the operand constraint information of the directional instruction sequence, so the opcodes and the operands of each instruction in the directional instruction sequence to be generated are constrained. The third instruction template and the fourth instruction template contain only the opcode constraint information of the directional instruction sequence, and do not contain the operand constraint information of the directional instruction sequence, so only the opcodes of each directional instruction in the directional instruction sequence to be generated are constrained. The opcode "add.s / sub.s" indicates that the directional instruction to be generated is an addition instruction / subtraction instruction, and the value taken out of the register needs to be calculated as single-precision data when the directional instruction is executed; the opcode "add.d / sub.d" indicates that the directional instruction to be generated is an addition instruction / subtraction instruction, and the value taken out of the register needs to be calculated as double-precision data when the directional instruction is executed.

[0067] If the operation code of a certain instruction in the directional instruction sequence is "add", it indicates that the instruction is an addition instruction; "add $1$2$3" indicates that the operation code and the operands of the to-be-generated directional instruction are all constrained, the to-be-generated directional instruction is an addition instruction, which is used to add the value in register $2 and the value in register $3, and store the result in register $1. The operation code "sub" is used to indicate that the to-be-generated directional instruction is a subtraction instruction, and the minuend and the subtrahend are determined by the operands. Taking "sub $3$2$1" as an example, it indicates that the to-be-generated directional instruction is a subtraction instruction, the subtrahend is the value in register $2, the minuend is the value in register $1, and the result needs to be stored in register $3. The operation code "b" indicates that the to-be-generated directional instruction is a jump instruction, and the target address is determined by the current address of the jump instruction and the operand. Taking "b $3 12" as an example, assuming that the current address of the jump instruction is CurPC, then according to the first instruction template, the storage address of the next instruction of the jump instruction, that is, the instruction "add $6$5$1", in the directional instruction sequence is "CurPC+12", in other words, the instruction "add $6$5$1" is generated in the storage space corresponding to "CurPC+12", instead of being sequentially stored in the next storage space adjacent to CurPC, that is, the storage space corresponding to "CurPC+4". If the storage space corresponding to "CurPC+12" has already written other instructions, for example, random instructions generated before the directional instruction sequence, it will cause the instruction "add $6$5$1" to be unable to be normally generated, and affect the success rate of generating the directional instruction sequence.

[0068] To solve this problem, the embodiment of the present application determines the storage space corresponding to the directional instruction sequence according to the instruction template and the jump instruction in the case that the directional instruction sequence contains a jump instruction. Referring to Figure 2 , a step flow chart for determining the storage space provided by the embodiment of the present application is shown. As Figure 2As shown, in the case that the embodiment of the present application contains a jump instruction in the directional instruction sequence, the directional instruction sequence is first split into at least two sequentially executed instruction sub-sequences according to the jump instruction. Taking the directional instruction sequence corresponding to the fourth instruction template in Table 1 as an example, the directional instruction sequence <sequence_scm> can be split into a first instruction sub-sequence (add.s+sub.s+b) and a second instruction sub-sequence (sub.d+add.d). It should be noted that since the jump instruction causes the storage address of the next instruction to be discontinuous with the storage address of the jump instruction, the embodiment of the present application splits the directional instruction sequence into the first instruction sub-sequence and the second instruction sub-sequence according to the jump instruction, in order to ensure that the storage space corresponding to each instruction sub-sequence after splitting is continuous. Therefore, the jump instruction in the directional instruction sequence can only be used as the last instruction of the first instruction sub-sequence, i.e., the last instruction in the first instruction sub-sequence, and cannot be used as the first instruction of the second instruction sub-sequence (the first instruction in the first instruction sub-sequence). Furthermore, for the first instruction sub-sequence and the second instruction sub-sequence split by the same jump instruction, the first instruction sub-sequence is executed before the second instruction sub-sequence, so as to ensure the sequential execution of the directional instruction sequence.

[0069] After splitting the directional instruction sequence into the first instruction sub-sequence and the second instruction sub-sequence, a storage space is allocated for the first instruction sub-sequence according to the number of instructions contained in the first instruction sub-sequence. Taking the directional instruction sub-sequence <sequence_scm> corresponding to the fourth instruction template shown in Table 1 as an example, the first instruction sub-sequence (add.s+sub.s+b) after splitting contains 3 instructions, and assuming that the storage space required by the binary code of one instruction is 32 bits, i.e., 4 bytes, the storage space required by the first instruction sub-sequence should be no less than 12 bytes. Therefore, when generating the directional instruction sequence, only a continuous space of no less than 12 bytes needs to be found as the storage space of the first instruction sub-sequence.

[0070] For the second instruction sub-sequence, a second storage space needs to be allocated for the second instruction sub-sequence according to the constraints of the operands of the directional instruction sequence by the instruction template. Specifically, if the instruction template has constraints on the operands of each instruction in the directional instruction sequence, i.e., the instruction template contains operand constraint information, a dedicated storage space can be allocated for the second instruction sub-sequence, which is used to store the second instruction sub-sequence; if the instruction template does not have constraints on the operands of each instruction in the directional instruction sequence, i.e., the instruction template does not contain operand constraint information, a storage space can be allocated for the second instruction sub-sequence according to the number of instructions contained in the second instruction sub-sequence.

[0071] Optionally, sub-step 1033 comprises:

[0072] Step S11, judging whether the instruction template contains the operand constraint information of the directional instruction sequence or not.

[0073] Step S12, if the instruction template contains the operand constraint information of the directional instruction sequence, determining the reserved space as the second storage space corresponding to the second instruction sub-sequence, and the reserved space does not allow other instructions except the second instruction sub-sequence to be written into.

[0074] Step S13, if the instruction template does not contain the operand constraint information of the directional instruction sequence, allocating the storage space for the second instruction sub-sequence according to the number of instructions contained in the second instruction sub-sequence, wherein the target jump address of the jump instruction corresponding to the second instruction sub-sequence belongs to the second storage space.

[0075] For the second instruction sub-sequence, if the instruction template contains the operand constraint information of the directional instruction sequence, such as the first instruction template and the second instruction template in the embodiment of the present application, the operand of the jump instruction in the directional instruction sequence has been specified, the target jump address of the jump instruction cannot be changed, and other instructions can have been stored at the target address of the jump instruction, so that the directional instruction sequence cannot be normally generated. For this case, the embodiment of the present application predefines a reserved space in the memory space, the reserved space does not allow other instructions except the second instruction sub-sequence to be written into, in other words, the constraint information of the reserved space is that the reserved space cannot be occupied by other instructions before the directional instruction sequence is generated. In the case that the directional instruction sequence contains the jump instruction and the instruction template contains the operand constraint information of the directional instruction sequence, the reserved space is used as the second storage space corresponding to the second instruction sub-sequence, so that the failure of the directional instruction sequence to be generated due to other instructions being written into the target address of the jump instruction is avoided.

[0076] Referring to Figure 3 , a storage space allocation diagram provided by the embodiment of the present application is shown. As Figure 3As shown in Table 1, the directional instruction sequence<sequence_som> It is split into a first instruction subsequence (add $1$2$3+sub $3$2$1+sub $5$4$4+b $3 12) and a second instruction subsequence (add $6$5$1). The first storage space for the first instruction subsequence is determined based on the number of instructions it contains. This is because the first instruction template contains a directed instruction sequence.<sequence_som> The operand constraint information is used, therefore the second instruction subsequence is written into the reserved space. No other instructions besides the second instruction subsequence can be written into the reserved space, ensuring the normal generation of the second instruction subsequence.

[0077] If the instruction template does not contain operand constraint information for the directed instruction sequence, such as the third and fourth instruction templates in this embodiment, then the operands of the jump instructions in the directed instruction sequence are not specified, and their target jump addresses can be set. Therefore, in this case, a second storage space can be allocated to the second instruction subsequence based on the number of instructions it contains, and the target jump address of the jump instruction corresponding to the second instruction subsequence can be set to the address corresponding to the second storage space. For example, the target jump address of the jump instruction can be set to the starting address of the storage address corresponding to the second instruction subsequence. (Refer to...) Figure 4 This illustrates another storage space allocation diagram provided by an embodiment of the present invention. Figure 4 As shown in Table 1, the directional instruction sequence<sequence_scm> It is split into a first instruction subsequence (add.s + sub.s + b) and a second instruction subsequence (sub.d + add.d). The storage space for the first instruction subsequence is determined by the number of instructions it contains. Since the fourth instruction template does not contain a directed instruction sequence...<sequence_scm> The operand constraint information allows the jump instruction "b" to be used to control the target address and jump to the second memory space corresponding to the second instruction subsequence to generate the second instruction subsequence. The second memory space corresponding to the second instruction subsequence is determined based on the number of instructions it contains. Table 1 shows the directional instruction sequences.<sequence_scm> For example, the second instruction subsequence (sub.d+add.d) after splitting contains 2 instructions. Assuming that the binary encoding of an instruction requires 32 bits, or 4 bytes, the second storage space required for the second instruction subsequence is 8 bytes. Therefore, a contiguous space of not less than 8 bytes is allocated as the second storage space for the second instruction subsequence.

[0078] Reference Figure 5 The diagram illustrates a flowchart of steps for generating a second instruction subsequence according to an embodiment of the present invention.Figure 5 In the embodiment of the present application, the instruction sequence contains a jump instruction, and the instruction template does not contain the operand constraint information of the instruction sequence. The step of generating the instruction sequence in the storage space according to the instruction template includes:

[0079] In step S21, the distance between the first address of the second storage space corresponding to the second instruction sub-sequence and the storage address of the jump instruction is calculated to obtain the immediate number of the jump instruction.

[0080] In step S22, the immediate number is determined as the operand of the jump instruction.

[0081] In step S23, the jump instruction is executed to jump to the second storage space corresponding to the second instruction sub-sequence according to the operand to generate the second instruction sub-sequence.

[0082] In the embodiment of the present application, if the instruction sequence contains a jump instruction, and the instruction template does not contain the operand constraint information of the instruction sequence, when the second instruction sub-sequence corresponding to the instruction sub-sequence is generated, the second storage space can be allocated to the second instruction sub-sequence according to the number of instructions contained in the second instruction sub-sequence. Then, the first address of the second storage space is taken as the target jump address of the jump instruction corresponding to the second instruction sub-sequence. By executing the jump instruction, the second instruction sub-sequence is generated in the second storage space instead of other storage space.

[0083] It should be noted that the target address of the jump instruction can be expressed as: target jump address = storage address of jump instruction + operand. Since the instruction template of the instruction sequence does not contain the operand constraint information, the operand of the jump instruction is not constrained, and thus an immediate number can be generated according to actual needs, and the generated immediate number is taken as the operand of the jump instruction. In the embodiment of the present application, in order to control the target jump address of the jump instruction to be the first address of the second storage space of the second instruction sub-sequence, the immediate number of the jump instruction can be calculated according to the distance between the first address of the second storage space corresponding to the second instruction sub-sequence and the storage address of the jump instruction. Specifically, the difference between the first address of the second storage space corresponding to the second instruction sub-sequence and the storage address of the jump instruction is taken as the immediate number of the jump instruction. Then, the calculated immediate number is taken as the operand of the jump instruction. Finally, the jump instruction is executed, and the program jumps from the storage address of the jump instruction to the first address of the second storage space, and the second instruction sub-sequence is generated in the second storage space starting from the first address of the second storage space.

[0084] In an alternative embodiment of the present application, the execution requirement of the instruction template includes cyclically executing the directed instruction sequence, after the directed instruction sequence is generated in the storage space according to the instruction template, the method of the embodiment further includes:

[0085] Step S31, judging whether the directed instruction sequence contains a loop body according to the instruction template;

[0086] Step S32, if the directed instruction sequence contains a loop body, sequentially executing the directed instruction sequence, and continuing to sequentially generate the random instruction in the random instruction verification program when a loop end condition is met;

[0087] Step S33, if the directed instruction sequence does not contain a loop body, generating a loop instruction group and executing to make the directed instruction sequence be cyclically executed.

[0088] It should be noted that a loop body contains a group of instructions, the group of instructions in the loop body is repeatedly executed until the loop end condition is met, the execution of the group of instructions in the loop body is ended, the loop body is jumped, and the random instruction in the random instruction verification program is sequentially generated.

[0089] It can be understood that the execution requirement of the instruction template includes cyclically executing the directed instruction sequence, which does not mean that the directed instruction sequence generated based on the instruction template itself contains a loop body. Whether the directed instruction sequence contains a loop body is determined by the operation code constraint information and the operand constraint information contained in the instruction template.

[0090] If the target address of a jump instruction and / or a fetch instruction in the directed instruction sequence to be generated is the storage address of a certain instruction in the directed instruction sequence before the jump instruction and / or the fetch instruction, when the directed instruction sequence is executed, the instructions between the target address of the jump instruction and / or the fetch instruction and the storage address of the jump instruction and / or the fetch instruction are cyclically executed to form a loop body, in other words, the directed instruction sequence itself contains a loop body.

[0091] If there is no jump instruction and / or fetch instruction whose target address is the storage address of a certain instruction in the directed instruction sequence to be generated, it is indicated that the directed instruction sequence does not contain a loop body.

[0092] In the embodiment of the present application, if the execution requirement of the instruction template includes cyclically executing the directed instruction sequence, it is necessary to judge whether the directed instruction sequence contains a loop body, and different processing modes are selected for different cases. Referring to Figure 6 , a step flowchart of executing a directed instruction sequence provided by an embodiment of the present application is shown. As shown in Figure 6As shown, in the embodiment of the present application, before executing the directional instruction sequence, it is judged whether the directional instruction sequence contains a loop body according to the corresponding instruction template. If the directional instruction sequence contains a loop body, the directional instruction sequence can be executed in sequence. And when the loop end condition is met, the random generation process of the random instruction program is returned to, and the random instruction in the random instruction verification program is continuously generated in sequence. If the directional instruction sequence does not contain a loop body, a loop instruction group needs to be inserted after the directional instruction sequence and executed, so as to realize the loop execution of the directional instruction sequence through the loop instruction group.

[0093] As an example, in the embodiment of the present application, when the loop instruction group is generated, the "start-end" strategy can be adopted, that is, the start position and the end position of the loop body are controllable. In an optional embodiment of the present application, the step S33 of generating and executing the loop instruction group so as to make the directional instruction sequence be executed in loop comprises:

[0094] The step S331 comprises: determining a first address corresponding to the start position of the loop body and a second address corresponding to the end position of the loop body according to the instruction template;

[0095] The step S332 comprises: generating a loop instruction group according to the distance between the first address and the second address;

[0096] The step S333 comprises: executing the loop instruction group, and after executing the instruction stored in the second address, jumping out of the loop instruction group and continuously generating the random instruction in the random instruction verification program in sequence.

[0097] When the loop body is generated based on the "start-end" strategy, the first address corresponding to the start position of the loop body and the second address corresponding to the end position of the loop body are determined according to the instruction template. Then, the loop instruction group is generated according to the distance between the first address and the second address. The loop instruction group is executed, and after executing the instruction stored in the second address, the loop instruction group is jumped out, and the random instruction in the random instruction verification program is continuously generated in sequence.

[0098] It should be noted that when the loop body is constructed, the fetch addresses corresponding to the internal instructions of the loop body form a closed loop, so that the loop body can be formed, which requires that the fetch address corresponding to the end position in the loop body is the first address corresponding to the start position of the loop body. In the embodiment of the present application, the corresponding end instruction group is generated according to the distance between the first address corresponding to the start position of the loop body and the second address corresponding to the end position of the loop body, so that when the loop body is generated, the distance between the first address and the second address is compared, and different loop instruction groups are selected.

[0099] As an example, the step S332 comprises:

[0100] A11, comparing the distance between the first address and the second address with a preset threshold value;

[0101] A12, if the distance between the first address and the second address is less than or equal to the preset threshold value, generating a non-zero instruction fetching instruction, the non-zero instruction fetching instruction containing a first operand; the instruction fetching address of the non-zero instruction fetching instruction when satisfying the instruction fetching condition is the first address, and the instruction fetching address of the non-zero instruction fetching instruction when not satisfying the instruction fetching condition is the second address;

[0102] The step S333 comprises:

[0103] A13, executing the non-zero instruction fetching instruction to determine the target instruction fetching address of the non-zero instruction fetching instruction according to the first operand;

[0104] A14, if the first operand is not equal to 0, determining the target instruction fetching address of the non-zero instruction fetching instruction as the first address, obtaining the instruction stored in the first address and executing;

[0105] A15, if the first operand is equal to 0, determining the target instruction fetching address of the non-zero instruction fetching instruction as the second address, obtaining the instruction stored in the second address and executing.

[0106] Referring to Figure 7 , a step flow chart of generating a loop instruction group is shown. As shown in Figure 7 , in the embodiment of the present application, if the distance between the first address and the second address is less than or equal to the preset threshold value, a non-zero instruction fetching instruction is generated. The non-zero instruction fetching instruction contains a first operand, the initial value of the first operand is greater than 0, and the first operand is reduced by 1 each time the non-zero instruction fetching instruction is executed.

[0107] It should be noted that the fetch range of a non-zero fetch instruction is fixed, and jumps can only occur within a certain fetch range. That is, the maximum jump distance between the storage address of the non-zero fetch instruction and the target fetch address is less than or equal to its fetch range. Since the fetch range of a non-zero fetch instruction is usually relatively small, in this embodiment of the invention, when generating the end instruction group of the loop body, if the distance between the first address corresponding to the start position of the loop body and the second address corresponding to the end position is less than or equal to a preset threshold, then the non-zero fetch instruction can be used as the end instruction group of the loop body. The fetch address when the non-zero fetch instruction meets the fetch condition is the first address, and the fetch address when the non-zero fetch instruction does not meet the fetch condition is the second address.

[0108] After generating the loop instruction group in the directed instruction sequence, the loop instruction group is executed. When the non-zero fetch instruction is executed for the first time, since the initial value of the first operand is greater than 0, the fetch condition for the non-zero fetch instruction is met, and the program jumps to the first address, that is, returns to the beginning of the loop body. At the same time, the first operand of the non-zero fetch instruction is continuously decremented by 1 as the loop body is executed. When the first operand becomes 0, the fetch condition for instruction BN is no longer met, and the target fetch address is no longer the first address corresponding to the beginning of the loop body, so the loop ends. At this time, the target fetch address of the non-zero fetch instruction is the second address corresponding to the end address, and the instruction stored in the second address is fetched and executed. After executing the instruction stored in the second address, the end condition of the loop body is met, and the random instructions in the random instruction verification program can continue to be generated sequentially.

[0109] As another example, step S332, which generates a loop instruction group based on the distance between the first address and the second address, includes:

[0110] A21. If the distance between the first address and the second address is greater than a preset threshold, then generate an equal-zero fetch instruction and a direct fetch instruction, wherein the equal-zero fetch instruction includes a second operand;

[0111] Step S333, executing the loop instruction group, includes:

[0112] A22. Execute the zero-fetch instruction to determine the target fetch address of the zero-fetch instruction based on the second operand;

[0113] A23. If the second operand is not equal to 0, then determine the target fetch address of the zero-fetch instruction as the storage address of the direct fetch instruction, obtain the direct fetch instruction and execute it;

[0114] A24, if the second operand equals 0, then determine the target fetch address of the zero-equivalent fetch instruction as the second address, fetch the instruction stored in the second address and execute.

[0115] The zero-equivalent fetch instruction contains a second operand, the initial value of the second operand is greater than 0, and the second operand is decremented by 1 each time the zero-equivalent fetch instruction is executed. The direct fetch instruction contains a third operand, which is determined according to the first address. The storage address of the zero-equivalent fetch instruction is adjacent to the storage address of the direct fetch instruction, and the storage address of the zero-equivalent fetch instruction precedes the storage address of the direct fetch instruction. The fetch address of the zero-equivalent fetch instruction when the fetch condition is met is the second address, and the fetch address of the zero-equivalent fetch instruction when the fetch condition is not met is the storage address of the direct fetch instruction.

[0116] It should be noted that the fetch range of the zero-equivalent fetch instruction is fixed, and the jump can only be made within a certain fetch range, i.e. the maximum jump distance between the storage address of the zero-equivalent fetch instruction and the target fetch address is less than or equal to the fetch range. In the embodiment of the present application, if the distance between the first address corresponding to the start position of the loop body and the second address corresponding to the end position of the loop body is greater than a preset threshold, the zero-equivalent fetch instruction (BE) and the direct fetch instruction (J) can be combined as the end instruction group of the loop body in the present application.

[0117] As shown in Figure 7 If the distance between the first address and the second address is greater than a preset threshold, the zero-equivalent fetch instruction (BE) and the direct fetch instruction (J) are generated. The zero-equivalent fetch instruction contains a second operand, the initial value of the second operand is greater than 0, and the second operand is decremented by 1 each time the zero-equivalent fetch instruction is executed. The direct fetch instruction contains a third operand, which is determined according to the first address, and by executing the direct fetch instruction, the start position of the loop body can be returned directly. The execution process of the zero-equivalent fetch instruction (BE) and the direct fetch instruction (J) is as follows: executing the zero-equivalent fetch instruction, if the second operand of the instruction BE is not 0, it is determined that the fetch condition of the instruction BE is not met, and the target fetch address of the instruction BE is the storage address of the direct fetch instruction J, i.e. the direct fetch instruction is executed next to return to the start position of the loop body. If the second operand of BE is 0, it is determined that the fetch condition of the instruction BE is met, and the target fetch address of the instruction BE is the second address corresponding to the end position of the loop body. Next, the instruction at the end position is executed, and the random instruction in the random instruction verification program is sequentially generated.

[0118] It should be noted that the preset threshold can be determined according to the value range of the instruction BN, and is generally the maximum distance of the value of the BN. The initial values of the first operand of the instruction BN and the second operand of the instruction BE can be determined according to the loop count of the loop body to be tested, and the embodiment of the application can control the loop count of the loop body by controlling the size of the operand of the instruction BN or the instruction BE. The embodiment of the application can support the customization requirements of the composition of the loop body and the loop count of the loop body.

[0119] Referring to Figure 8 , a step flowchart of generating a directional instruction sequence provided by an embodiment of the application is shown. As Figure 8 indicated, in an optional embodiment of the application, the step 105 of generating the directional instruction sequence in the storage space according to the instruction template comprises:

[0120] Sub-step 1051, judging whether the instruction template contains the operand constraint information of the directional instruction sequence;

[0121] Sub-step 1052, if the instruction template contains the operand constraint information of the directional instruction sequence, generating the directional instruction sequence in the storage space according to the operation code constraint information and the operand constraint information;

[0122] Sub-step 1053, if the instruction template does not contain the operand constraint information of the directional instruction sequence, randomly generating the operands of each instruction in the directional instruction sequence;

[0123] Sub-step 1054, generating the directional instruction sequence in the storage space according to the operation code constraint information and the operands of each instruction in the directional instruction sequence.

[0124] In the embodiment of the application, when generating the directional instruction sequence according to the instruction template, it is necessary to first judge whether the instruction template contains the operand constraint information of the directional instruction sequence. If the instruction template does not contain the operand constraint information of the directional instruction sequence, it indicates that the operands of each instruction in the directional instruction sequence to be generated are not specified, in which case the operands of each instruction can be randomly generated, and then the directional instruction sequence is generated according to the operation code constraint information in the instruction template and the randomly generated operands. Specifically, the instruction type of each directional instruction in the directional instruction sequence to be generated is determined according to the operation code constraint information in the instruction template, and the corresponding operation code is allocated to each instruction according to the instruction type of each instruction. Then, the operands of each directional instruction in the directional instruction sequence are randomly generated, and each directional instruction in the directional instruction sequence is generated according to the operation code and the operands.

[0125] If the instruction template contains the operand constraint information of the directed instruction sequence, the directed instruction sequence can be generated directly according to the operation code constraint information and the operand constraint information contained in the instruction template. Specifically, the instruction type of each directed instruction in the directed instruction sequence to be generated is determined according to the operation code constraint information in the instruction template, a corresponding operation code is assigned to each directed instruction according to the instruction type of each directed instruction, and the value of the operand of each directed instruction is determined further according to the operand constraint information. Then, each directed instruction in the directed instruction sequence is generated according to the operation code and the operand.

[0126] In summary, the embodiment of the present application provides a method for generating a random instruction verification program. The method can determine whether the directed instruction sequence contains a jump instruction according to the operation code constraint information contained in the instruction template corresponding to the directed instruction sequence to be generated, and then select different ways to allocate storage space for the directed instruction sequence. Specifically, if the directed instruction sequence contains a jump instruction, the storage space corresponding to the directed instruction sequence is determined according to the instruction template and the jump instruction; if the directed instruction sequence does not contain a jump instruction, the storage space for the directed instruction sequence is allocated according to the number of instructions contained in the directed instruction sequence. Finally, the directed instruction sequence is generated in the storage space according to the instruction template. The embodiment of the present application can avoid the failure of generating the directed instruction sequence due to the occupation of the storage space in the process of generating the directed instruction sequence, ensure the success rate of generating the directed instruction sequence, and be beneficial to improving the generation efficiency and quality of the random verification program and accelerating the convergence speed of the microprocessor function verification coverage. Moreover, the directed instruction sequence generated in the embodiment of the present application can realize the verification of the specific function of the microprocessor, which is beneficial to enhancing the verification ability of the random instruction verification program and improving the verification efficiency of the microprocessor.

[0127] It should be noted that, for the method embodiment, in order to simply describe, it is expressed as a series of action combinations, but those skilled in the art should know that the embodiment of the present application is not limited by the described action order, because according to the embodiment of the present application, certain steps can be performed in other order or simultaneously. Secondly, those skilled in the art should know that the embodiments described in the specification all belong to preferred embodiments, and the involved actions are not necessarily required by the embodiment of the present application.

[0128] Device embodiment

[0129] Reference Figure 9 , a structure block diagram of a device for generating a random instruction verification program of the present application is shown, the random instruction verification program is used for function verification of a microprocessor, the random instruction verification program includes a directed instruction sequence, and the device specifically can include:

[0130] The instruction template obtaining module 901 is configured to obtain an instruction template of a directional instruction sequence to be generated when it is determined that the generation constraint condition of the directional instruction sequence is met, wherein the instruction template comprises operation code constraint information of the directional instruction sequence.

[0131] The jump instruction judging module 902 is configured to judge whether the directional instruction sequence comprises a jump instruction according to the operation code constraint information.

[0132] The first determining module 903 is configured to determine a storage space corresponding to the directional instruction sequence according to the instruction template and the jump instruction if the directional instruction sequence comprises the jump instruction.

[0133] The second determining module 904 is configured to allocate a storage space for the directional instruction sequence according to the number of instructions comprised by the directional instruction sequence if the directional instruction sequence does not comprise the jump instruction.

[0134] The instruction sequence generating module 905 is configured to generate the directional instruction sequence in the storage space according to the instruction template.

[0135] Optionally, the first determining module comprises:

[0136] The splitting module is configured to split the directional instruction sequence into at least two sequentially executed instruction subsequences according to the jump instruction; the instruction subsequences comprise a first instruction subsequence and a second instruction subsequence, the last instruction of the first instruction subsequence is the jump instruction, and the second instruction subsequence does not comprise the jump instruction; in the instruction execution process, the first instruction subsequence is executed earlier than the corresponding second instruction subsequence.

[0137] The first allocating sub-module is configured to allocate a first storage space for the first instruction subsequence according to the number of instructions comprised by the first instruction subsequence.

[0138] The second allocating sub-module is configured to allocate a second storage space for the second instruction subsequence according to the constraint condition of the operand of the directional instruction sequence in the instruction template.

[0139] The determining sub-module is configured to determine the first storage space corresponding to the first instruction subsequence and the second storage space corresponding to the second instruction subsequence as the storage space of the directional instruction sequence.

[0140] Optionally, the second allocating sub-module comprises:

[0141] The judging unit is configured to judge whether the instruction template comprises the operand constraint information of the directional instruction sequence.

[0142] The first determining unit is configured to determine the reserved space as a second storage space corresponding to the second instruction sub-sequence if the instruction template contains the operand constraint information of the directional instruction sequence, wherein the reserved space does not allow other instructions except the second instruction sub-sequence to be written.

[0143] The second determining unit is configured to allocate the second storage space for the second instruction sub-sequence according to the number of instructions contained in the second instruction sub-sequence if the instruction template does not contain the operand constraint information of the directional instruction sequence, wherein a target jump address of a jump instruction corresponding to the second instruction sub-sequence belongs to the second storage space.

[0144] Optionally, the instruction template does not contain the operand constraint information of the directional instruction sequence, and the instruction sequence generation module comprises:

[0145] The immediate number calculation unit is configured to calculate an immediate number of the jump instruction according to a distance between a first address of the second storage space corresponding to the second instruction sub-sequence and a storage address of the jump instruction corresponding to the second instruction sub-sequence.

[0146] The operand determining unit is configured to determine the immediate number as an operand of the jump instruction.

[0147] The second instruction sub-sequence generation unit is configured to execute the jump instruction to generate the second instruction sub-sequence in the second storage space corresponding to the second instruction sub-sequence according to the operand.

[0148] Optionally, the execution requirement of the instruction template comprises cyclically executing the directional instruction sequence, and the apparatus further comprises:

[0149] The loop body judging module is configured to judge whether the directional instruction sequence contains a loop body according to the instruction template.

[0150] The instruction sequence executing module is configured to sequentially execute the directional instruction sequence if the directional instruction sequence contains the loop body, and continue to sequentially generate a random instruction in the random instruction verification program when a loop end condition is met.

[0151] The loop instruction group generation module is configured to generate a loop instruction group and execute the loop instruction group if the directional instruction sequence does not contain the loop body, so that the directional instruction sequence is cyclically executed.

[0152] Optionally, the loop instruction group generation module comprises:

[0153] The address determining sub-module is configured to determine a first address corresponding to a start position of the loop body and a second address corresponding to an end position of the loop body according to the instruction template.

[0154] a loop instruction set generating submodule configured to generate a loop instruction set according to a distance between the first address and the second address;

[0155] a loop instruction set executing submodule configured to execute the loop instruction set and, after executing the instruction stored in the second address, jump out of the loop instruction set and continue to generate a random instruction in the random instruction verification program.

[0156] Optionally, the loop instruction set generating submodule comprises:

[0157] a first instruction generating unit configured to generate a non-zero instruction fetching instruction if the distance between the first address and the second address is less than or equal to a preset threshold; wherein the non-zero instruction fetching instruction comprises a first operand, an initial value of the first operand is greater than 0, the first operand is decremented by 1 each time the non-zero instruction fetching instruction is executed, and a fetching address when the non-zero instruction fetching instruction meets an instruction fetching condition is the first address and a fetching address when the non-zero instruction fetching instruction does not meet the instruction fetching condition is the second address;

[0158] the loop instruction set executing submodule comprises

[0159] a first instruction executing unit configured to execute the non-zero instruction fetching instruction to determine a target fetching address of the non-zero instruction fetching instruction according to the first operand;

[0160] a first address determining unit configured to determine the target fetching address of the non-zero instruction fetching instruction as the first address if the first operand is not equal to 0, and acquire and execute the instruction stored in the first address;

[0161] a second address determining unit configured to determine the target fetching address of the non-zero instruction fetching instruction as the second address if the first operand is equal to 0, and acquire and execute the instruction stored in the second address.

[0162] Optionally, the loop instruction set generating submodule comprises:

[0163] The second instruction generating unit is configured to generate a zero-equal instruction and a direct instruction if the distance between the first address and the second address is greater than a preset threshold; the zero-equal instruction contains a second operand, an initial value of the second operand is greater than 0, and the second operand is decremented by 1 each time the zero-equal instruction is executed; the direct instruction contains a third operand, the third operand is determined according to the first address; a storage address of the zero-equal instruction is adjacent to a storage address of the direct instruction, and the storage address of the zero-equal instruction is before the storage address of the direct instruction; a fetch address of the zero-equal instruction when a fetch condition is met is the second address, and a fetch address of the zero-equal instruction when the fetch condition is not met is the storage address of the direct instruction;

[0164] The loop instruction group executing submodule comprises

[0165] The second instruction executing unit is configured to execute the zero-equal instruction to determine a target fetch address of the zero-equal instruction according to the second operand;

[0166] The third address determining unit is configured to determine the target fetch address of the zero-equal instruction as the storage address of the direct instruction if the second operand is not equal to 0, and acquire and execute the direct instruction;

[0167] The fourth address determining unit is configured to determine the target fetch address of the zero-equal instruction as the second address if the second operand is equal to 0, and acquire and execute an instruction stored in the second address.

[0168] Optionally, the instruction sequence generating module comprises:

[0169] The constraint information judging submodule is configured to judge whether the operand constraint information of the directional instruction sequence is contained in the instruction template;

[0170] The first instruction sequence generating submodule is configured to generate the directional instruction sequence in the storage space according to the operation code constraint information and the operand constraint information if the operand constraint information of the directional instruction sequence is contained in the instruction template;

[0171] The operand generating submodule is configured to randomly generate the operands of each instruction in the directional instruction sequence if the operand constraint information of the directional instruction sequence is not contained in the instruction template;

[0172] The second instruction sequence generating submodule is configured to generate the directional instruction sequence in the storage space according to the operation code constraint information and the operands of each instruction in the directional instruction sequence.

[0173] Optionally, the random instruction verification program further comprises random instructions, and the device further comprises:

[0174] The first instruction generation module is configured to generate random instructions according to preset rules.

[0175] The second instruction generation module is configured to generate the directional instruction sequence when a generation constraint condition of the directional instruction sequence is met, and continue to generate random instructions after the directional instruction sequence is generated.

[0176] The verification program determination module is configured to obtain the random instruction verification program according to the directional instruction sequence and the random instructions.

[0177] In summary, the embodiment of the present application provides a device for generating a random instruction verification program, which can avoid the generation failure of a directional instruction sequence due to the occupation of storage space in the process of generating the directional instruction sequence, ensure the success rate of generating the directional instruction sequence, and be beneficial to improving the generation efficiency and quality of the random verification program and accelerating the convergence speed of the microprocessor function verification coverage. Moreover, the directional instruction sequence generated in the embodiment of the present application can realize the verification of a specific function of the microprocessor, which is beneficial to enhancing the verification ability of the random instruction verification program and improving the verification efficiency of the microprocessor.

[0178] For the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the related parts refer to the part of the method embodiment.

[0179] Each embodiment in the specification is described in a progressive manner, and each embodiment mainly describes the difference from other embodiments. The same and similar parts between the embodiments can be referred to each other.

[0180] As to the device in the above embodiments, the specific manner in which each module performs operations has been described in detail in the embodiments related to the method, and will not be described in detail here.

[0181] Reference Figure 10 is a structural schematic diagram of an electronic device provided by the embodiment of the present application. As shown in Figure 10 The electronic device comprises a processor, a memory, a communication interface and a communication bus, the processor, the memory and the communication interface complete the communication among each other through the communication bus; the memory is used to store at least one executable instruction, and the executable instruction makes the processor execute the method for generating a random instruction verification program of the foregoing embodiments.

[0182] The embodiment of the present application provides a kind of non-transitory computer readable storage medium, when the instruction in the storage medium is executed by the program or processor of terminal, make terminal can execute the method for generating random instruction verification program of the foregoing embodiment.

[0183] Each embodiment in the specification is described in a progressive manner, and each embodiment focuses on the difference from other embodiments, and the same or similar parts between each embodiment can be referred to each other.

[0184] Those skilled in the art should understand that the embodiments of the embodiments of the present application can be provided as a method, device or computer program product. Therefore, the embodiments of the present application can be in the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the embodiments of the present application can be in the form of a computer program product implemented on one or more computer usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer usable program code.

[0185] The embodiments of the present application are described with reference to flowcharts and / or block diagrams according to the method, terminal device (system) and computer program product of the embodiments of the present application. It should be understood that each flow and / or block in the flowchart and / or block diagram, and the combination of flows and / or blocks in the flowchart and / or block diagram can be realized by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device produce a means for implementing the functions specified in the flow Figure 1 The device for performing the functions specified in one or more flows and / or blocks. Figure 1 The device for performing the functions specified in one or more flows and / or blocks.

[0186] These computer program instructions can also be stored in a computer readable storage medium that can guide the computer or other programmable data processing terminal device to work in a predictable manner, so that the instructions stored in the computer readable storage medium produce a product including instruction means, which implements the functions specified in the flow Figure 1 The device for performing the functions specified in one or more flows and / or blocks. Figure 1 The device for performing the functions specified in one or more flows and / or blocks.

[0187] These computer program instructions can also be loaded into a computer or other programmable data processing terminal device, so that a series of operation steps are performed on the computer or other programmable terminal device to produce a computer implemented process, so that the instructions executed on the computer or other programmable terminal device provide a means for implementing the functions specified in the flow Figure 1 The device for performing the functions specified in one or more flows and / or blocks. Figure 1steps of a function specified in one or more blocks.

[0188] While the preferred embodiments of the application have been described, additional variations and modifications can be made to the embodiments by those of skill in the art once they have the benefit of the present disclosure. Therefore, the appended claims are intended to encompass within their scope all possible alternatives and modifications.

[0189] Finally, it should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. It is further noted that, as used herein, the singular forms "a", "an" and "the" include plural references unless the context clearly dictates otherwise. The terms "comprises", "comprising", "includes", "including" and "contains", "containing" as used herein, are intended to cover a non-exclusive inclusion such that a process, method, article, or apparatus that comprises, includes or contains one or more elements or steps does not include or exclude other elements or steps not expressly listed. The terms "comprise", "comprising", "include", "including" and "contain", "containing" are not used in their exclusive sense.

[0190] The above provides a method and device for generating a random instruction verification program, an electronic device and a storage medium, and the principles and implementation manners of the present application are described by using specific examples. The above description of the embodiments is only used to help understand the method of the present application and its core idea. For those skilled in the art, according to the idea of the present application, the specific implementation manners and application ranges can be changed, and the above description of the present application should not be understood as a limitation.

Claims

1. A method of generating a random instruction verifier, the method comprising: The random instruction verification program is used for function verification of a microprocessor, and the random instruction verification program comprises a directed instruction sequence, and the method comprises the following steps: When it is determined that the generation constraint condition of the directed instruction sequence is met, an instruction template of the directed instruction sequence to be generated is acquired, wherein the instruction template contains opcode constraint information of the directed instruction sequence; It is judged whether the directed instruction sequence contains a jump instruction according to the opcode constraint information; If the directed instruction sequence contains a jump instruction, the directed instruction sequence is split into at least two sequentially executed instruction subsequences according to the jump instruction, wherein the instruction subsequences comprise a first instruction subsequence and a second instruction subsequence, the last instruction of the first instruction subsequence is a jump instruction, and the second instruction subsequence does not contain a jump instruction; in the instruction execution process, the first instruction subsequence is executed earlier than the corresponding second instruction subsequence; A first storage space is allocated for the first instruction subsequence according to the number of instructions contained in the first instruction subsequence; A second storage space is allocated for the second instruction subsequence according to the constraint condition of the operand of the directed instruction sequence in the instruction template, or the second storage space is allocated for the second instruction subsequence according to the number of instructions contained in the second instruction subsequence; wherein the reserved space does not allow other instructions except the second instruction subsequence to be written into; The first storage space corresponding to the first instruction subsequence and the second storage space corresponding to the second instruction subsequence are determined as the storage space of the directed instruction sequence; The directed instruction sequence is generated in the storage space according to the instruction template.

2. The method of claim 1, wherein, The method that the second storage space is allocated for the second instruction subsequence according to the constraint condition of the operand of the directed instruction sequence in the instruction template, or the second storage space is allocated for the second instruction subsequence according to the number of instructions contained in the second instruction subsequence, comprises the following steps: It is judged whether the instruction template contains the operand constraint information of the directed instruction sequence; If the instruction template contains the operand constraint information of the directed instruction sequence, the reserved space is determined as the second storage space corresponding to the second instruction subsequence, wherein the reserved space does not allow other instructions except the second instruction subsequence to be written into; If the instruction template does not contain the operand constraint information of the directed instruction sequence, the second storage space is allocated for the second instruction subsequence according to the number of instructions contained in the second instruction subsequence, wherein the target jump address of the jump instruction corresponding to the second instruction subsequence belongs to the second storage space.

3. The method of claim 1, wherein, The method that the directed instruction sequence is generated in the storage space according to the instruction template, when the instruction template does not contain the operand constraint information of the directed instruction sequence, comprises the following steps: The immediate number of the jump instruction is calculated according to the distance between the first address of the second storage space corresponding to the second instruction subsequence and the storage address of the jump instruction corresponding to the second instruction subsequence. determining the immediate number as an operand of the jump instruction; executing the jump instruction to jump to a second storage space corresponding to the second instruction sub-sequence according to the operand to generate the second instruction sub-sequence.

4. The method of claim 1, wherein, The execution requirement of the instruction template includes loop execution of a directed instruction sequence, and after the directed instruction sequence is generated in the storage space according to the instruction template, the method further includes: determining whether the directed instruction sequence contains a loop body according to the instruction template; if the directed instruction sequence contains a loop body, sequentially executing the directed instruction sequence, and when a loop end condition is met, continuing to sequentially generate a random instruction in the random instruction verification program; if the directed instruction sequence does not contain a loop body, generating and executing a loop instruction group to enable the directed instruction sequence to be executed in a loop.

5. The method of claim 4, wherein, The generating and executing a loop instruction group to enable the directed instruction sequence to be executed in a loop if the directed instruction sequence does not contain a loop body includes: determining a first address corresponding to a start position of a loop body and a second address corresponding to an end position of the loop body according to the instruction template; generating a loop instruction group according to a distance between the first address and the second address; executing the loop instruction group, and after executing an instruction stored in the second address, jumping out of the loop instruction group to continue to sequentially generate a random instruction in the random instruction verification program.

6. The method of claim 5, wherein, The generating a loop instruction group according to a distance between the first address and the second address includes: if the distance between the first address and the second address is less than or equal to a preset threshold, generating a non-zero pointer instruction, wherein the non-zero pointer instruction contains a first operand, an initial value of the first operand is greater than 0, the first operand is decremented by 1 each time the non-zero pointer instruction is executed, a pointer address of the non-zero pointer instruction when a pointer condition is met is the first address, and a pointer address of the non-zero pointer instruction when the pointer condition is not met is the second address; The executing the loop instruction group includes: executing the non-zero pointer instruction to determine a target pointer address of the non-zero pointer instruction according to the first operand; if the first operand is not equal to 0, determining that the target pointer address of the non-zero pointer instruction is the first address, obtaining and executing an instruction stored in the first address; if the first operand is equal to 0, determining that the target pointer address of the non-zero pointer instruction is the second address, obtaining and executing an instruction stored in the second address.

7. The method of claim 5, wherein, The generating a loop instruction group according to a distance between the first address and the second address includes: If the distance between the first address and the second address is greater than a preset threshold, a zero-equal instruction and a direct instruction are generated, wherein the zero-equal instruction contains a second operand, an initial value of the second operand is greater than 0, and the second operand is decremented by 1 each time the zero-equal instruction is executed; the direct instruction contains a third operand, the third operand is determined according to the first address; a storage address of the zero-equal instruction is adjacent to a storage address of the direct instruction, and the storage address of the zero-equal instruction is before the storage address of the direct instruction; a fetch address of the zero-equal instruction when a fetch condition is met is the second address, and a fetch address of the zero-equal instruction when the fetch condition is not met is the storage address of the direct instruction; The execution of the loop instruction group comprises: The zero-equal instruction is executed to determine a target fetch address of the zero-equal instruction according to the second operand; If the second operand is not equal to 0, the target fetch address of the zero-equal instruction is determined as the storage address of the direct instruction, the direct instruction is acquired and executed; If the second operand is equal to 0, the target fetch address of the zero-equal instruction is determined as the second address, an instruction stored in the second address is acquired and executed.

8. The method according to any one of claims 1 to 7, characterized in that, The generation of the directional instruction sequence in the storage space according to the instruction template comprises: It is judged whether the instruction template contains operand constraint information of the directional instruction sequence; If the instruction template contains the operand constraint information of the directional instruction sequence, the directional instruction sequence is generated in the storage space according to the operation code constraint information and the operand constraint information; If the instruction template does not contain the operand constraint information of the directional instruction sequence, operands of each instruction in the directional instruction sequence are randomly generated; and the directional instruction sequence is generated in the storage space according to the operation code constraint information and the operands of each instruction in the directional instruction sequence.

9. The method according to any of claims 1 to 7, characterized in that Before the directional instruction sequence is generated in the storage space according to the instruction template, the method further comprises: If the directional instruction sequence does not contain a jump instruction, a storage space is allocated to the directional instruction sequence according to a number of instructions contained in the directional instruction sequence.

10. The method according to any one of claims 1 to 7, characterized in that, The random instruction verification program further comprises random instructions, and the method further comprises: Random instructions are generated according to a preset rule; When a generation constraint condition of the directional instruction sequence is met, the directional instruction sequence is generated, and after the directional instruction sequence is generated, the random instructions are continuously generated; The random instruction verification program is obtained according to the directional instruction sequence and the random instructions.

11. An apparatus for generating a random instruction verifier, the apparatus comprising: The random instruction verification program is used for functional verification of a microprocessor, and the random instruction verification program comprises a directional instruction sequence, and the apparatus comprises: The instruction template obtaining module is configured to obtain an instruction template of the directional instruction sequence to be generated when it is determined that the generation constraint condition of the directional instruction sequence is satisfied, wherein the instruction template contains operation code constraint information of the directional instruction sequence; The jump instruction judging module is configured to judge whether the directional instruction sequence contains a jump instruction according to the operation code constraint information; The first determining module is configured to determine the storage space corresponding to the directional instruction sequence according to the instruction template and the jump instruction if the directional instruction sequence contains the jump instruction; The instruction sequence generating module is configured to generate the directional instruction sequence in the storage space according to the instruction template; The first determining module includes: The splitting module is configured to split the directional instruction sequence into at least two sequentially executed instruction subsequences according to the jump instruction; the instruction subsequences include a first instruction subsequence and a second instruction subsequence, the last instruction of the first instruction subsequence is a jump instruction, and the second instruction subsequence does not contain a jump instruction; in the instruction execution process, the first instruction subsequence is executed earlier than the corresponding second instruction subsequence; The first allocating sub-module is configured to allocate a first storage space for the first instruction subsequence according to the number of instructions contained in the first instruction subsequence; The second allocating sub-module is configured to allocate a second storage space for the second instruction subsequence according to the reserved space allocated according to the constraint condition of the operand of the directional instruction sequence in the instruction template, or according to the number of instructions contained in the second instruction subsequence; wherein the reserved space is not allowed to be written into by instructions other than the second instruction subsequence; The determining sub-module is configured to determine the first storage space corresponding to the first instruction subsequence and the second storage space corresponding to the second instruction subsequence as the storage space of the directional instruction sequence.

12. The apparatus of claim 11, wherein, The second allocating sub-module includes: The judging unit is configured to judge whether the operand constraint information of the directional instruction sequence is contained in the instruction template; The first determining unit is configured to determine the reserved space as the second storage space corresponding to the second instruction subsequence if the operand constraint information of the directional instruction sequence is contained in the instruction template, wherein the reserved space is not allowed to be written into by instructions other than the second instruction subsequence; The second determining unit is configured to allocate a second storage space for the second instruction subsequence according to the number of instructions contained in the second instruction subsequence if the operand constraint information of the directional instruction sequence is not contained in the instruction template, wherein the target jump address of the jump instruction corresponding to the second instruction subsequence belongs to the second storage space.

13. The apparatus of claim 11, wherein, The instruction template does not contain the operand constraint information of the directional instruction sequence, and the instruction sequence generating module includes: The immediate number calculating unit is configured to calculate the immediate number of the jump instruction according to the distance between the first address of the second storage space corresponding to the second instruction subsequence and the storage address of the jump instruction corresponding to the second instruction subsequence. An operand determining unit is configured to determine the immediate number as an operand of the jump instruction; A second instruction subsequence generating unit is configured to execute the jump instruction to generate the second instruction subsequence in a second storage space corresponding to the second instruction subsequence according to the operand.

14. The apparatus of claim 11, wherein, The execution requirement of the instruction template comprises a loop execution of a sequence of directional instructions, and the apparatus further comprises: A loop body judging module is configured to judge whether the sequence of directional instructions comprises a loop body according to the instruction template; An instruction sequence executing module is configured to sequentially execute the sequence of directional instructions if the sequence of directional instructions comprises a loop body, and continue to sequentially generate random instructions in the random instruction verification program when a loop end condition is met; A loop instruction group generating module is configured to generate a loop instruction group and execute the loop instruction group if the sequence of directional instructions does not comprise a loop body, so that the sequence of directional instructions is executed in a loop.

15. The apparatus of claim 14, wherein, The loop instruction group generating module comprises: An address determining submodule is configured to determine a first address corresponding to a start position of a loop body and determine a second address corresponding to an end position of the loop body according to the instruction template; A loop instruction group generating submodule is configured to generate a loop instruction group according to a distance between the first address and the second address; A loop instruction group executing submodule is configured to execute the loop instruction group, and after executing instructions stored in the second address, jump out of the loop instruction group to continue to sequentially generate random instructions in the random instruction verification program.

16. The apparatus of claim 15, wherein, The loop instruction group generating submodule comprises: A first instruction generating unit is configured to generate a non-zero instruction fetching instruction if a distance between the first address and the second address is less than or equal to a preset threshold; the non-zero instruction fetching instruction comprises a first operand, an initial value of the first operand is greater than 0, the first operand is decremented by 1 each time the non-zero instruction fetching instruction is executed, and a fetching address of the non-zero instruction fetching instruction when a fetching condition is met is the first address, and a fetching address of the non-zero instruction fetching instruction when the fetching condition is not met is the second address; The loop instruction group executing submodule comprises A first instruction executing unit is configured to execute the non-zero instruction fetching instruction to determine a target fetching address of the non-zero instruction fetching instruction according to the first operand; A first address determining unit is configured to determine the target fetching address of the non-zero instruction fetching instruction as the first address if the first operand is not equal to 0, and acquire and execute instructions stored in the first address; A second address determining unit is configured to determine the target fetching address of the non-zero instruction fetching instruction as the second address if the first operand is equal to 0, and acquire and execute instructions stored in the second address.

17. The apparatus of claim 15, wherein, The loop instruction group generating submodule comprises: The second instruction generating unit is configured to generate a zero-equal instruction and a direct instruction if a distance between the first address and the second address is greater than a preset threshold; the zero-equal instruction contains a second operand, an initial value of the second operand is greater than 0, and the second operand is decremented by 1 each time the zero-equal instruction is executed; the direct instruction contains a third operand, the third operand is determined according to the first address; a storage address of the zero-equal instruction is adjacent to a storage address of the direct instruction, and the storage address of the zero-equal instruction is before the storage address of the direct instruction; a fetch address of the zero-equal instruction when a fetch condition of the zero-equal instruction is met is the second address, and a fetch address of the zero-equal instruction when the fetch condition of the zero-equal instruction is not met is the storage address of the direct instruction; The loop instruction group executing submodule comprises The second instruction executing unit is configured to execute the zero-equal instruction to determine a target fetch address of the zero-equal instruction according to the second operand; The third address determining unit is configured to determine the target fetch address of the zero-equal instruction as the storage address of the direct instruction if the second operand is not equal to 0, and to acquire and execute the direct instruction; The fourth address determining unit is configured to determine the target fetch address of the zero-equal instruction as the second address if the second operand is equal to 0, and to acquire and execute an instruction stored in the second address.

18. The apparatus of any of claims 11-17, wherein, The instruction sequence generating module comprises: The constraint information judging submodule is configured to judge whether the operand constraint information of the directional instruction sequence is contained in the instruction template; The first instruction sequence generating submodule is configured to generate the directional instruction sequence in the storage space according to the operation code constraint information and the operand constraint information if the operand constraint information of the directional instruction sequence is contained in the instruction template; The operand generating submodule is configured to randomly generate the operands of the instructions in the directional instruction sequence if the operand constraint information of the directional instruction sequence is not contained in the instruction template; The second instruction sequence generating submodule is configured to generate the directional instruction sequence in the storage space according to the operation code constraint information and the operands of the instructions in the directional instruction sequence.

19. The apparatus of any of claims 11-17, wherein, The apparatus further comprises: The second determining module is configured to allocate storage space for the directional instruction sequence according to a number of instructions contained in the directional instruction sequence if the directional instruction sequence does not contain a jump instruction.

20. The apparatus of any of claims 11-17, wherein, The random instruction verification program further comprises random instructions, and the apparatus further comprises: The first instruction generating module is configured to generate random instructions according to a preset rule; The second instruction generating module is configured to generate the directional instruction sequence when a generation constraint condition of the directional instruction sequence is met, and to continue generating random instructions after the directional instruction sequence is generated; The verification program determining module is configured to obtain the random instruction verification program according to the directional instruction sequence and the random instructions.

21. An electronic device, comprising: comprises: a processor, a memory, a communication interface, and a communication bus, which complete communication with each other through the communication bus; The memory is used to store executable instructions, and the executable instructions enable the processor to execute the method for generating a random instruction verification program according to any one of claims 1 to 10.

22. A readable storage medium, characterized by, When the instructions in the storage medium are executed by the processor of the electronic device, the processor can execute the method for generating a random instruction verification program according to any one of claims 1 to 10.

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