Monotonic counter memory system

Abstract

A monotonic counter memory system includes a counter circuit and a memory circuit. The counter circuit is configured to increase a count by one in response to a clock signal and output an n-bit count value, where n is a positive integer. The memory circuit includes a plurality of memory cells. The memory circuit is configured to store the count value. The count value changes by one bit at each input of the clock signal, and the count value changes in number of bit toggles less than 2 n -1 times.

Description

TECHNICAL FIELD

[0001] The present invention relates to a memory system, and more particularly, to a monotonic counter memory system. BACKGROUND

[0002] A monotonic counter is a counter that provides an incrementing value, and the value cannot be reversed to an old value. The monotonic counter is applied to various financial systems or electronic systems. In such applications, it is required that the monotonic counter continuously update its count value for a long period of time. In addition, it is required that a robust monotonic counter cope with a situation at the time of a power failure, and the monotonic counter can quickly restore its count value when power of the monotonic counter is restored. In emerging memories in which a count value can be written thereto, architecture development of the monotonic counter is an important issue in related art. SUMMARY

[0003] The present invention is directed to a monotonic counter memory system that can save a write time and a write power when a count value is written to a memory, and reduce a memory array area.

[0004] Embodiments of the present invention provide a monotonic counter memory system. The monotonic counter memory system includes a counter circuit and a memory circuit. The counter circuit is configured to increase a count by one in response to a clock signal and output an n-bit count value, where n is a positive integer. The memory circuit includes a plurality of memory cells. The memory circuit is configured to store the count value. The count value changes by one bit at each input count of the clock signal, and the count value has a number of bit toggles that is less than 2 n -1 times.

[0005] In embodiments of the present invention, the memory circuit comprises a first memory. The first memory is configured to store least significant bits of the count value.

[0006] In embodiments of the present invention, each of the least significant bits has a same total number of bit toggles.

[0007] In embodiments of the present invention, the least significant bits of the count value have k bits, and one of the k bits is designated as a last bit, where k is a positive integer.

[0008] In embodiments of the present invention, starting from an initial state, each of the least significant bits changes by one at each input count, and all of the least significant bits change once with k input counts.

[0009] In embodiments of the present invention, from a (k+1)th input count to a (2k-1)th input count, all of the least significant bits except the last bit toggle once.

[0010] In an embodiment of the invention, at the (2k)th input count, the least significant bit does not change and the last bit toggles once, and the least significant bit goes back to the initial state.

[0011] In an embodiment of the invention, the memory circuit further comprises a second memory. The second memory is configured to store the most significant bits of the count value, and the most significant bits are decoded in Gray code.

[0012] In an embodiment of the invention, at the (2k+1)th input count, the second memory increments the count by one.

[0013] In an embodiment of the invention, one bit of the count value is determined by an odd number of memory cells, and the bit content of one bit of the count value is determined by a majority vote of the odd number of memory cells.

[0014] In an embodiment of the invention, one bit of the count value is determined by an even number of memory cells, and the bit content of one bit of the count value is determined by a differential sensing of the even number of memory cells.

[0015] In an embodiment of the invention, the memory circuit is a bit-rewritable non-volatile memory.

[0016] In an embodiment of the invention, the memory circuit is a volatile memory, and during a power-off state, the count value stored in the memory circuit is written to a non-volatile memory.

[0017] In order that the foregoing and other aspects of the present disclosure can be understood in detail, a brief description of several embodiments is described with reference to the drawings. BRIEF DESCRIPTION OF DRAWINGS

[0018] The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the disclosure and together with the description serve to explain the principles of the disclosure.

[0019] Figure 1 shows a schematic diagram of a monotonic counter memory system according to an embodiment of the invention;

[0020] Figure 2 shows a schematic diagram of a Gray code of a Gray counter and a binary counter;

[0021] Figure 3 shows a schematic diagram of writing a count value to a memory circuit according to an embodiment of the invention;

[0022] Figure 4 shows a schematic diagram of a count value output from a counter circuit according to an embodiment of the invention;

[0023] BRIEF DESCRIPTION OF DRAWINGS

[0024] 100: Monotonic counter memory system;

[0025] 110: Counter circuit;

[0026] 120: Memory circuit;

[0027] 122: First memory;

[0028] 124: Second memory;

[0029] 200: Count value;

[0030] 410, 420, 430, 440: Dashed box;

[0031] CLK: Clock signal. Detailed Implementation

[0032] Figure 1 A schematic diagram of a monotonic counter memory system according to an embodiment of the present invention is shown. Figure 2 This diagram illustrates the Gray code for both Gray counters and binary counters. (Reference) Figure 1 and Figure 2 The monotonic counter memory system 100 includes a counter circuit 110 and a memory circuit 120. The counter circuit 110 is configured to respond to a counter having 2 n The counter memory system 100 increments the count by one for each input count (CLK) and outputs an n-bit count value 200, where n is a positive integer. The monotonic counter memory system 100 can count up to 2^n-1 input counts. The memory circuit 120 includes multiple memory cells configured to store the count value 200. The count value 200 changes by one bit at each input count of the clock signal CLK, and the number of bit switches in the count value is less than 2^n-1. For example, as... Figure 3 As shown, the number of switches in the second memory 124 is determined by the number of bits of MSB data stored in the first memory 122.

[0033] Counter circuit 110 includes, for example Figure 2 The Gray counter shown is illustrated. In this embodiment, the counter circuit 110 can be a monotonic counter circuit based on resistive random access memory (RRAM). For a monotonic counter circuit based on RRAM, one bit cycle time for each bit can be defined as the bit value change from 0 to 1 to 0. That is, the bit value will change from 0 to 1 and then back from 1 to 0 in one bit cycle. (The remaining text appears to be incomplete and requires further context.) Figure 2The last row shows the bit period of each bit of the Gray counter and the binary counter. Compared with the binary counter, the Gray counter has less bit period for some bits.

[0034] In this embodiment, the Gray counter can output the most significant bits (MSBs) of the count value 200 to be stored in the memory circuit 120. The MSBs of the count value 200 are decoded in the Gray code and stored in the memory circuit 120. In this embodiment, the least significant bits (LSBs) of the count value 200 can also be decoded in the Gray code and stored in the memory circuit 120, but the present application is not limited thereto. In an embodiment, the counter circuit 110 can include a binary counter for outputting the LSBs of the count value 200, and the LSBs of the count value 200 are decoded in the binary code and stored in the memory circuit 120.

[0035] The memory circuit 120 includes a plurality of memory cells and is configured to store the count value 200. In an embodiment, the memory circuit 120 can include a plurality of resistive random access memory (RRAM) cells formed in an array. In this embodiment, the memory circuit 120 includes a first memory 122 and a second memory 124 as shown in FIG. 1. Figure 3 Figure 3 A schematic diagram of writing a count value to a memory circuit according to an embodiment of the present application is shown. The first memory 122 is configured to store the LSBs of the count value 200. The second memory 124 is configured to store the MSBs of the count value 200, and the MSBs are decoded in the Gray code.

[0036] Taking the count value 200 of 32 bits as an example, the count value 200 of 32 bits includes 17 most significant bits denoted as MSB[31, 30,..., 16, 15] and 15 least significant bits denoted as LSB[14, 13,..., 1, 0]. The most significant bits MSB[31, 30,..., 16, 15] are written into the second memory 124. The most significant bits MSB[31, 30,..., 16, 15] indicate 17 bits of counter information decoded in the Gray code. In this case, the maximum bit period is 2 (17-2) = 32K periods.

[0037] ​On the other hand, the least significant bits LSB [13, 12,..., 1, 0] are stored into the first memory 122. In the present embodiment, in order to save the array size of the first memory 122, only the least significant bits of 14 bits (i.e., LSB [13, 12,..., 1, 0]) are written into the first memory 122. When the least significant bits LSB [13, 12,..., 1, 0] are read out, the last bit LSB

[14] is determined as a bit value of 0 or 1 according to the bit content of the least significant bits LSB [13, 12,..., 1, 0]. In other words, the least significant bits of the count value have k bits, and one of the k bits is designated as the last bit, where k is a positive integer, for example, k = 15 in the present embodiment. The last bit LSB

[14] is the most significant bit of the LSBs, and is determined according to the least significant bits LSB [13, 12,..., 1, 0] of the count value. In the present embodiment, the array size of the first memory 122 is 2 14 = 16K bits, and the second memory 124 is configured with the most significant bits MSB [31, 30,..., 16, 15] of 17 bits. When the least significant bits LSB [13, 12,..., 1, 0] are written by one cycle and the first memory 122 of 16K bits has a maximum bit period of 2 17 = 128K cycles, the most significant bits MSB [31, 30,..., 16, 15] will be incremented by one.

[0038] In another embodiment, in order to save more array size of the first memory 122, only the least significant bits of 13 bits (i.e., LSB [12, 11,..., 1, 0]) are written into the first memory 122, and so on. When the least significant bits LSB [12, 11,..., 1, 0] are read out, the last bits LSB [14, 13] are determined according to the bit content of the least significant bits LSB [12, 11,..., 1, 0].

[0039] In Figure 2 each cell of the first memory 122 or the second memory 124 can be implemented by a 4T4R architecture, a 6T6R architecture, or a 2T2R architecture with a majority of 5, but the present application is not limited thereto. In one embodiment, one bit of the count value 200 can be determined by an odd number of memory cells, and the bit content of the one bit of the count value 200 is determined by a majority voting of the odd number of memory cells. In another embodiment, one bit of the count value 200 can be determined by an even number of memory cells, and the bit content of the one bit of the count value 200 is determined by a differential sensing of the even number of memory cells. The method for determining the bit content by the majority voting of the odd number of memory cells or the differential sensing of the even number of memory cells can be understood with reference to the prior art in the art.

[0040] In one embodiment, the memory circuit 120 can be a bit-rewritable non-volatile memory. In another embodiment, the memory circuit 120 can be a volatile memory. During a power-off state, the count value 200 stored in the volatile memory 120 is written into a non-volatile memory (not shown) and during a power-on period, the data stored in the non-volatile memory is recovered and translated into count information. The recovery process can be understood with reference to the existing knowledge in the art. Figure 1

[0041] Figure 4 A diagram showing the count value output from the counter circuit according to an embodiment of the present application is shown. Referring to Figure 1 and Figure 4 , the counter circuit 100 can output a count value 200 having 2 most significant bits MSB[17, 16] and 16 least significant bits LSB[15, 14,..., 1, 0]. The most significant bits MSB[17, 16] and the least significant bits LSB[15, 14,..., 1, 0] are decoded in Gray code. In this embodiment, the counter circuit 100 can be a 7-bit counter and the number of bit toggles of the count value is less than 2 7 -1 = 127 times.

[0042] As shown in Figure 4 , each of the least significant bits LSB[14, 13,..., 1, 0] has the same total number of bit toggles. In this embodiment, a "walk 0 and walk 1" scheme is applied to write data 0 or data 1 into the memory circuit 120. For example, as shown in the dashed box 410, when LSB

[15] = 0, a "walk 1" scheme is applied to write data 1 into the memory circuit 120. In the dashed box 410, starting with an initial state (e.g., all zeros), exactly one bit is changed at each input count and all the least significant bits are changed once for k input counts, where k = 16. Similarly, as shown in the dashed box 420, when LSB

[15] = 1, a "walk 0" scheme is applied to write data 0 into the memory circuit 120.

[0043] ​In this embodiment, the least significant bits LSB [15, 14,..., 1, 0] of the count value 200 have k bits, where k = 16, and one LSB

[15] of the k bits is designated as the last bit. From the (k+1)th input count to the (2k-1)th input count, all the least significant bits LSB [14, 13,..., 1, 0] except the last bit LSB

[15] are toggled once, as shown in the dashed frame 420. At the (2k)th input count, the least significant bits LSB [13, 12,..., 1, 0] are not changed, and the last bit LSB

[14] is toggled once, as shown in the dashed frame 440, and the least significant bits LSB [14, 13,..., 1, 0] return to the initial state. In addition, at the (2k+1)th input count, the second memory 124 increases the count by one. That is, from the (2k)th input count to the (2k+1)th input count, the MSB

[16] changes from the bit value 0 to the bit value 1, as shown in the dashed frame 430. Therefore, by applying the "walk 0 and walk 1" scheme to write data 0 or data 1 into the memory circuit 120, the scheme can save half the size of the second memory 124.

[0044] In summary, in embodiments of the present disclosure, a monotonic counter memory system is provided, which includes a first memory for storing LSB data of a monotonic counter and a second memory for storing MSB data of the monotonic counter. The MSB data stored in the second memory is decoded in Gray code. The highest bit of the LSB data can be determined from the stored LSB data to reduce the memory array area. In addition, when a count value is written into the memory, the stored count data changes one bit at each input count to save write time and write power.

[0045] Various modifications and changes can be made to the disclosed embodiments without departing from the scope or spirit of the disclosure. It is intended that the disclosed embodiments cover all modifications and changes as fall within the scope of the appended claims and their equivalents.

Claims

1. A monotonic counter memory system, comprising: a counter circuit configured to increase a count by one in response to a clock signal and output an n-bit count value, where n is a positive integer, and a most significant bit and a least significant bit of the count value are decoded in Gray code; and a memory circuit comprising a plurality of memory cells and configured to store the count value, wherein the count value changes one bit at each input count of the clock signal and the count value toggles less than 2 n - once, wherein applying walk 0 and walk 1 writes the least significant bit into the memory circuit.

2. The monotonic counter memory system of claim 1, wherein the memory circuit comprises a first memory configured to store the least significant bits of the count value.

3. The monotonic counter memory system of claim 2, wherein each of the least significant bits has the same total number of bit toggles.

4. The monotonic counter memory system of claim 2, wherein the least significant bits of the count value have k bits, and one of the k bits is designated as a last bit, where k is a positive integer.

5. The monotonic counter memory system of claim 4, wherein starting in an initial state, one bit changes at each of the input counts, and all of the least significant bits change once every k input counts.

6. The monotonic counter memory system of claim 5, wherein from the k+1 input count to the 2k-1 input count, all of the least significant bits except the last bit toggle once.

7. The monotonic counter memory system of claim 5, wherein at the 2k input count, the least significant bits do not change and the last bit toggles once, and the least significant bits return to the initial state.

8. The monotonic counter memory system of claim 2, wherein the memory circuit further comprises a second memory configured to store the most significant bits of the count value.

9. The monotonic counter memory system of claim 8, wherein at the 2k+1 input count, the second memory increases the count by one.

10. The monotonic counter memory system of claim 1, wherein one bit of the count value is determined by an odd number of the memory cells, and a bit content of the one bit of the count value is determined by a majority vote of the odd number of memory cells.

11. The monotonic counter memory system of claim 1, wherein one bit of the count value is determined by an even number of the memory cells, and a bit content of the one bit of the count value is determined by a differential sensing of the even number of memory cells.

12. The monotonic counter memory system of claim 1, wherein the memory circuit is a bit-rewritable non-volatile memory.

13. The monotonic counter memory system of claim 1, wherein the memory circuit is a volatile memory, and during a power-off state, the count value stored in the memory circuit is written into a non-volatile memory.

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