A display panel actual charging rate test board and test method

Abstract

The present invention discloses a display panel actual charging rate test board, comprising a control unit, a first input unit, a second input unit, a third input unit, and an output unit; the first input unit, the second input unit, and the third input unit are respectively used to input different timing voltage signals according to the control instruction of the control unit; the output unit is used to output the actual output voltage signal of the display panel; the control unit is used to output the control instruction to each unit, and calculate the actual charging rate of the display panel by obtaining the actual output voltage data of the output unit and the actual input voltage data of the first input unit. A test method is also disclosed. By making the resistance of the test board consistent with the resistance and / or capacitance of the thin film transistor during operation, and inputting pulse timing voltages at different times, the accurate actual charging rate of the display panel can be obtained, thereby improving the accuracy of the test.

Description

Technical Field

[0001] The present invention relates to the technical field of display panel charging rate, and in particular to a display panel actual charging rate test board and a test method. Background Art

[0002] Display panels usually need to consider the charging conditions of transistors such as pixels. The charging ratio is an important indicator of the display panel, which reflects the characteristics of the transistor on and off. It plays an important role in the quality of the display device. Its size directly affects the display performance of the display panel, such as brightness, penetration, and picture quality. The evaluation method of the actual charging rate of the display panel has been under continuous discussion by all parties. At present, the evaluation of the charging rate is mainly simulated by simulation models. The main principle is to simulate the charging rate under different conditions (such as different grayscales, different gate high levels (VGH), different differences between the row opening time and the charging time (GOE) time, etc.) by scanning electrical parameters such as the load of the signal (Gate) and the load of the data signal (Data).

[0003] The charging rate in the existing display panel design and development stage depends on EDA software evaluation. The charging rate calculated by simulation model cannot be actually verified. There is a large gap between the evaluation result and the actual charging rate. The charging rate simulated by EDA software even misleads the project evaluation and causes waste of related resources.

[0004] In summary, a solution is needed that can more accurately test the actual charging rate of display panels so that relevant practitioners can accurately understand the actual situation of display panels, guide product precise evaluation and yield improvement, thereby improving the quality of display panels and making products more competitive. Summary of the invention

[0005] The charging rate of existing display panels cannot be verified through calculation and evaluation through simulation models of EDA software, and there is a large gap between the evaluation results and the actual charging rate, which misleads the project evaluation and leads to waste of related resources.

[0006] In view of the above problems, a display panel actual charging rate test board and a test method are proposed. By respectively setting a first adjustment circuit, a second adjustment circuit and a third adjustment circuit at the source terminal, the gate terminal, the common electrode VCOM terminal and the drain terminal of the display panel thin film crystal, the resistance and / or capacitance of the source terminal, the gate terminal, the common electrode VCOM terminal and the drain terminal are adjusted respectively, so that the resistance of the test board is consistent with the resistance and / or capacitance of the thin film transistor during operation, and pulse timing voltages at different times are input, so that the accurate actual charging rate of the display panel can be obtained, thereby improving the accuracy of the test.

[0007] A display panel actual charging rate test board is connected to a display panel thin film transistor by welding or FPC switching, comprising:

[0008] Control unit;

[0009] a first input unit;

[0010] A second input unit;

[0011] The third input unit;

[0012] Output unit;

[0013] The control unit is connected to the first input unit, the second input unit, the third input unit and the output unit respectively;

[0014] The first input unit is connected to the source terminal of the thin film transistor;

[0015] The second input unit is connected to the gate terminal of the thin film transistor;

[0016] The third input unit is connected to the common electrode VCOM terminal of the thin film transistor;

[0017] The output unit is connected to the drain terminal of the thin film transistor;

[0018] The first input unit, the second input unit, and the third input unit are respectively used to input voltage signals of different timings according to control instructions of the control unit;

[0019] The output unit is used to output the actual output voltage signal of the display panel;

[0020] The control unit is used to output control instructions to each unit, and calculate the actual charging rate of the display panel by acquiring the actual output voltage data of the output unit and the actual input voltage data of the first input unit.

[0021] In conjunction with the display panel actual charging rate test board described in the first aspect of the present invention, in a first possible implementation manner, the first input unit, the second input unit, and the third input unit respectively include:

[0022] a first regulating circuit;

[0023] a second regulating circuit;

[0024] A third regulating circuit;

[0025] The first regulating circuit is connected between the input terminal of the first input unit and the source terminal of the thin film transistor;

[0026] The second regulating circuit is connected between the input terminal of the second input unit and the gate terminal of the thin film transistor;

[0027] The third regulating circuit is connected between the input terminal of the third input unit and the common electrode VCOM terminal and the drain terminal of the thin film transistor;

[0028] Wherein, the first regulating circuit is used to adjust the capacitance and resistance of the source terminal;

[0029] The second regulating circuit is used to adjust the capacitance and resistance of the gate terminal;

[0030] The third regulating circuit is used to adjust the capacitance between the drain terminal and the common electrode VCOM terminal.

[0031] In combination with the first possible implementation manner of the first aspect of the present invention, in a second possible implementation manner, the first regulating circuit includes:

[0032] A first adjusting resistor;

[0033] A first adjustment capacitor;

[0034] A first end of the first regulating resistor is commonly connected to an input end of the first input unit and a first end of the first regulating capacitor, and a second end of the first regulating resistor is connected to a source end of the thin film transistor;

[0035] The second end of the first regulating capacitor is grounded.

[0036] In combination with the second possible implementation manner of the first aspect of the present invention, in a third possible implementation manner, the second regulating circuit includes:

[0037] A second adjusting resistor;

[0038] A second adjustment capacitor;

[0039] A first end of the second regulating resistor is commonly connected to the input end of the second input unit and the first end of the second regulating capacitor, and a second end is connected to the gate end of the thin film transistor;

[0040] The second end of the second regulating capacitor is grounded.

[0041] In combination with the third possible implementation manner of the first aspect of the present invention, in a fourth possible implementation manner, the third regulating circuit includes:

[0042] The third adjustment capacitor;

[0043] A fourth adjustment capacitor;

[0044] The first end of the third regulating capacitor is connected to the input end of the third input unit and the first end of the fourth regulating capacitor, and the second end of the third regulating capacitor is connected to the common electrode VCOM end;

[0045] The drain terminal of the thin film transistor is also connected to the second terminal of the fourth regulating capacitor.

[0046] In combination with the display panel actual charging rate test board described in the first aspect of the present invention, in a fifth possible implementation manner, the first input unit, the second input unit, and the third input unit;

[0047] In a second aspect, a display panel actual charging rate test board testing method includes:

[0048] Step 100, connecting with the thin film transistor of the display panel by welding or FPC switching;

[0049] Step 200, adjusting the resistance and / or capacitance of the source terminal, the gate terminal, the common electrode VCOM terminal and the drain terminal of the thin film transistor;

[0050] Step 300: Inputting a pulse timing voltage to the source terminal, the gate terminal and the drain terminal at time T;

[0051] Step 400: Obtain the timing voltage data of the source terminal input and the actual voltage data of the drain, and calculate the actual charging rate.

[0052] In conjunction with the display panel actual charging rate test board testing method described in the second aspect of the present invention, in a first possible implementation manner, step 200 includes:

[0053] Step 210: providing a first regulating circuit between the input terminal of the first input unit and the source terminal of the thin film transistor;

[0054] Step 220: providing a second regulating circuit between the input terminal of the second input unit and the gate terminal of the thin film transistor;

[0055] Step 230, setting the third regulating circuit between the input terminal of the third input unit and the common electrode VCOM terminal and the drain terminal of the thin film transistor;

[0056] Wherein, the first regulating circuit is used to adjust the capacitance and resistance of the source terminal;

[0057] The second regulating circuit is used to adjust the capacitance and resistance of the gate terminal;

[0058] The third regulating circuit is used to adjust the capacitance between the drain terminal and the common electrode VCOM terminal.

[0059] In combination with the first possible implementation manner of the second aspect of the present invention, in a second possible implementation manner, step 300 includes:

[0060] Step 310: at time T, the first input unit inputs a first pulse timing voltage to the source terminal;

[0061] Step 320, at the time T, the second input unit inputs a second pulse timing voltage to the gate terminal;

[0062] Step 330: At the time T, the third input unit inputs a third pulse timing voltage to the gate terminal.

[0063] In combination with the second possible implementation manner of the second aspect of the present invention, in a third possible implementation manner, step 200 further includes:

[0064] Step 240: Use the first adjustment circuit to adjust the first adjustment resistor and the first adjustment capacitor to obtain the equivalent resistance and equivalent capacitance of the source terminal of the thin film transistor of the display panel;

[0065] Step 250: Use the second regulating circuit to regulate the second regulating resistor and the second regulating capacitor to obtain the equivalent resistance and the equivalent capacitance of the gate terminal of the thin film transistor of the display panel;

[0066] Step 260: Utilize the third regulating circuit to regulate the third regulating capacitor and the fourth regulating capacitor to obtain the equivalent capacitance of the common electrode VCOM terminal and the drain terminal of the thin film transistor of the display panel.

[0067] In combination with the third possible implementation manner of the second aspect of the present invention, in a fourth possible implementation manner, step 400 includes:

[0068] Step 410, obtaining source input voltage data and drain voltage data at different times;

[0069] Step 420, using:

[0070] Actual charging rate = (drain voltage / source input voltage) × 100%, calculate the actual charging rate of the display panel.

[0071] A display panel actual charging rate test board and test method described in the present invention are implemented. By respectively setting a first adjustment circuit, a second adjustment circuit and a third adjustment circuit at the source terminal, the gate terminal, the common electrode VCOM terminal and the drain terminal of the display panel thin film crystal, the resistance and / or capacitance of the source terminal, the gate terminal, the common electrode VCOM terminal and the drain terminal are adjusted respectively, so that the resistance of the test board is consistent with the resistance and / or capacitance of the thin film transistor during operation, and pulse timing voltages at different times are input, so that the accurate actual charging rate of the display panel can be obtained, thereby improving the accuracy of the test. BRIEF DESCRIPTION OF THE DRAWINGS

[0072] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0073] Figure 1 This is a schematic diagram of the connection of a display panel actual charging rate test board module in the present invention;

[0074] Figure 2 This is a circuit connection diagram of a display panel actual charging rate test board in the present invention;

[0075] Figure 3(a)-Figure 3(e) It is a schematic diagram of input timing of a display panel actual charging rate test board in the present invention;

[0076] Figure 4 It is a schematic diagram of a first embodiment of a test method for a display panel actual charging rate test board in the present invention;

[0077] Figure 5 It is a schematic diagram of a second embodiment of a test method for a display panel actual charging rate test board in the present invention;

[0078] Figure 6 It is a schematic diagram of a third embodiment of a test method for a display panel actual charging rate test board in the present invention;

[0079] Figure 7 It is a schematic diagram of a fourth embodiment of a test method for a display panel actual charging rate test board in the present invention;

[0080] Figure 8 It is a schematic diagram of a fifth embodiment of a test method for a display panel actual charging rate test board in the present invention;

[0081] The names of the parts indicated by the numbers in the drawings are: 110 - control unit, 120 - first input unit, 130 - second input unit, 140 - third input unit, 150 - output unit, 200 - thin film transistor. DETAILED DESCRIPTION

[0082] The following will be combined with the accompanying drawings in the invention to clearly and completely describe the technical solutions in the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, other embodiments obtained by ordinary technicians in this field without creative work are all within the scope of protection of the present invention.

[0083] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0084] The charging rate of existing display panels cannot be verified through calculation and evaluation through simulation models of EDA software, and there is a large gap between the evaluation results and the actual charging rate, which misleads the project evaluation and leads to waste of related resources.

[0085] In view of the above problems, a display panel actual charging rate test board and a test method are proposed.

[0086] Embodiment 1, as Figure 1 , Figure 1 It is a connection diagram of a display panel actual charging rate test board module in the present invention.

[0087] A display panel actual charging rate test board is connected to a display panel thin film transistor 200 by welding or FPC switching, and includes a control unit 110, a first input unit 120, a second input unit 130, a third input unit 140, and an output unit 150.

[0088] The control unit 110 is connected to the first input unit 120, the second input unit 130, the third input unit 140 and the output unit 150 respectively; the first input unit 120 is connected to the source terminal of the thin film transistor 200; the second input unit 130 is connected to the gate terminal of the thin film transistor 200; the third input unit 140 is connected to the common electrode VCOM terminal of the thin film transistor 200; and the output unit 150 is connected to the drain terminal of the thin film transistor 200.

[0089] The first input unit 120, the second input unit 130, and the third input unit 140 are respectively used to input different timing voltage signals according to the control instructions of the control unit 110; the output unit 150 is used to output the actual output voltage signal of the display panel; the control unit 110 is used to output control instructions to each unit, and calculate the actual charging rate of the display panel by obtaining the actual output voltage data of the output unit 150 and the actual input voltage data of the first input unit 120.

[0090] The actual charging rate test board in the present application can be connected to the thin film transistor 200 of the display panel by welding, or can be connected through an FPC adapter board.

[0091] According to the control instructions, the first input unit 120, the second input unit 130, and the third input unit 140 respectively input voltages of different timings to the source terminal, the gate terminal, and the drain terminal of the transistor. At the same time, the first input unit 120, the second input unit 130, and the third input unit 140 respectively adjust the capacitance and / or resistance of the source terminal, the gate terminal, and the drain terminal, so that the test circuit is consistent with the actual capacitance and / or resistance of the display panel, thereby making the charging rate obtained by the test more accurate.

[0092] The first input unit 120 , the second input unit 130 , and the third input unit 140 respectively input voltages of different timings to the source terminal, the gate terminal, and the drain terminal of the transistor.

[0093] The voltages of the three at different timings can be: in the voltage input stage, a positive voltage is input to the gate terminal and a positive voltage is input to the source terminal, wherein the voltage value input to the gate terminal is greater than the voltage value input to the source terminal, and the timing diagram is shown in Figure 3(a).

[0094] The voltages of the three at different timings can also be: in the voltage input stage, a forward voltage is input to the gate terminal and a reverse voltage is input to the source terminal, wherein the absolute value of the voltage input to the gate terminal is greater than the absolute value of the voltage input to the source terminal, and the timing diagram is shown in Figure 3(b).

[0095] The voltages of the three at different timings can also be: in the voltage input stage, only the forward voltage is input to the gate terminal, and its timing diagram is shown in Figure 3(c).

[0096] The voltages of the three at different timings can also be: in the voltage input stage, only the forward voltage is input to the source terminal, and its timing diagram is shown in Figure 3(d).

[0097] The voltages of the three at different timings can also be: in the voltage input stage, only the negative voltage is input to the source terminal, and its timing diagram is shown in FIG3(e).

[0098] Embodiment 2, as Figure 2 , Figure 2 It is a circuit connection diagram of a display panel actual charging rate test board in the present invention.

[0099] Different from the embodiment, a first regulating circuit, a second regulating circuit, and a third regulating circuit are respectively added to the first input unit 120 , the second input unit 130 , and the third input unit 140 .

[0100] The first regulating circuit is connected between the input end of the first input unit 120 and the source end of the thin film transistor 200; the second regulating circuit is connected between the input end of the second input unit 130 and the gate end of the thin film transistor 200; the third regulating circuit is connected between the input end of the third input unit 140 and the common electrode VCOM end and the drain end of the thin film transistor 200; wherein, the first regulating circuit is used to adjust the capacitance and resistance of the source end; the second regulating circuit is used to adjust the capacitance and resistance of the gate end; the third regulating circuit is used to adjust the capacitance of the drain end and the common electrode VCOM end.

[0101] The first regulating circuit is used to regulate the resistance and capacitance of the source terminal so that the input resistance and capacitance of the source terminal of the test board are consistent with the resistance and capacitance of the source terminal of the thin film transistor 200 of the display panel when it is running, or are equivalent to their equivalent resistance and equivalent capacitance.

[0102] The second regulating circuit is used to regulate the resistance and capacitance of the gate terminal so that the input resistance and capacitance of the gate terminal of the test board are consistent with the resistance and capacitance of the gate terminal of the thin film transistor 200 of the display panel when it is running, or are equivalent to their equivalent resistance and equivalent capacitance.

[0103] The third regulating circuit is used to regulate the capacitance of the common electrode VCOM terminal and the drain terminal, so that the input capacitance of the drain terminal is consistent with the capacitance of the common electrode VCOM terminal and the drain terminal when the thin film transistor 200 of the display panel is in operation, or is equivalent to its equivalent capacitance. The first regulating circuit, the second regulating circuit and the third regulating circuit are respectively arranged at the source terminal, the gate terminal, the common electrode VCOM terminal and the drain terminal of the thin film crystal of the display panel to regulate the resistance and / or capacitance of the source terminal, the gate terminal, the common electrode VCOM terminal and the drain terminal respectively, so that the resistance of the test board is consistent with the resistance and / or capacitance of the thin film transistor when it is in operation, and the pulse timing voltage at different times is input, so that the actual charging rate of the display panel can be accurately obtained, thereby improving the accuracy of the test.

[0104] Embodiment 3, as Figure 2 .

[0105] The difference from the second embodiment is that the first regulating resistor and the first regulating capacitor are provided in the first regulating circuit.

[0106] The circuit connection structure of the first adjustment resistor and the first adjustment capacitor is:

[0107] A first end of the first regulating resistor is connected to the input end of the first input unit 120 and the first end of the first regulating capacitor, and a second end of the first regulating resistor is connected to the source end of the thin film transistor 200;

[0108] The second terminal of the first adjustment capacitor is grounded.

[0109] Embodiment 4, as Figure 2 .

[0110] The difference from the second embodiment is that the second regulating circuit of the present embodiment is provided with a second regulating resistor and a second regulating capacitor.

[0111] The circuit connection structure of the second regulating resistor and the second regulating capacitor is:

[0112] The first end of the second regulating resistor is connected to the input end of the second input unit 130 and the first end of the second regulating capacitor, and the second end is connected to the gate end of the thin film transistor 200; the second end of the second regulating capacitor is grounded.

[0113] Embodiment 5, as Figure 2 .

[0114] The difference from Embodiment 2 is that a third regulating capacitor and a fourth regulating capacitor are provided in the third regulating circuit in this embodiment;

[0115] The circuit connection structure of the third regulating circuit is:

[0116] A first end of the third regulating capacitor is connected to the input end of the third input unit 140 and a first end of the fourth regulating capacitor, and a second end of the third regulating capacitor is connected to the common electrode VCOM.

[0117] The drain terminal of the thin film transistor 200 is also connected to the second terminal of the fourth regulating capacitor.

[0118] In a second aspect, a method for testing a display panel actual charging rate test board is provided, using the actual charging rate test board of the first aspect.

[0119] Method embodiment 1, as Figure 4 , Figure 4 It is a schematic diagram of a first embodiment of a test method for a display panel actual charging rate test board in the present invention.

[0120] The method of embodiment 1 includes: step 100, connecting to the thin film transistor 200 of the display panel by welding or FPC conversion; step 200, adjusting the resistance and / or capacitance of the source terminal, gate terminal, common electrode VCOM terminal and drain terminal of the thin film transistor 200; step 300, inputting a pulse timing voltage to the source terminal, gate terminal and drain terminal at time T; step 400, obtaining the timing voltage data input to the source terminal and the actual voltage data of the drain, and calculating the actual charging rate.

[0121] In method embodiment 1, the actual voltage data is obtained by adjusting the resistance and / or capacitance connected to the test board so that the resistance and / or capacitance input to the test board is consistent with the resistance and / or capacitance of the source terminal, gate terminal, common electrode VCOM terminal and drain terminal of the thin film crystal when it is running, thereby improving the accuracy of the charging rate test.

[0122] In the implementation manner of the present application, the input resistance and / or capacitance specifically refers to the resistance and capacitance of the source terminal, the resistance and capacitance of the gate terminal, and the capacitance of the drain terminal.

[0123] Method embodiment 2, as Figure 5 , Figure 5 It is a schematic diagram of a second embodiment of a test method for a display panel actual charging rate test board in the present invention.

[0124] Different from method embodiment 1, this embodiment adds a first adjustment circuit, a second adjustment circuit, and a third adjustment circuit to adjust the resistance and / or capacitance of the test board input respectively, and its circuit structure is consistent with embodiments 3, 4 and 5 of the first aspect.

[0125] Step 200 includes: step 210, setting a first regulating circuit between the input end of the first input unit 120 and the source end of the thin film transistor 200; step 220, setting a second regulating circuit between the input end of the second input unit 130 and the gate end of the thin film transistor 200; step 230, setting a third regulating circuit between the input end of the third input unit 140 and the common electrode VCOM end and the drain end of the thin film transistor 200; wherein the first regulating circuit is used to adjust the capacitance and resistance of the source end; the second regulating circuit is used to adjust the capacitance and resistance of the gate end; and the third regulating circuit is used to adjust the capacitance of the drain end and the common electrode VCOM end.

[0126] Method embodiment 3, as Figure 6 , Figure 6 It is a schematic diagram of a third embodiment of a test method for a display panel actual charging rate test board in the present invention.

[0127] Different from method embodiment 2, this embodiment increases the timing pulse voltage in multiple ways, and its timing diagram is the same as that of embodiment 1 of the first aspect. Step 300 includes: step 310, at time T, the first input unit 120 inputs the first pulse timing voltage to the source terminal; step 320, at time T, the second input unit 130 inputs the second pulse timing voltage to the gate terminal; step 330, at time T, the third input unit 140 inputs the third pulse timing voltage to the gate terminal.

[0128] The voltages of the three at different timings can be shown in Figure 3(a): in the voltage input stage, a positive voltage is input to the gate terminal and a positive voltage is input to the source terminal, and the voltage value input to the gate terminal is greater than the voltage value input to the source terminal.

[0129] The voltages of the three at different timings can also be shown in Figure 3(b): in the voltage input stage, a forward voltage is input to the gate terminal, a reverse voltage is input to the source terminal, and the absolute value of the voltage input to the gate terminal is greater than the absolute value of the voltage input to the source terminal.

[0130] The voltages of the three at different timings can also be shown in Figure 3(c): In the voltage input stage, only the forward voltage is input to the gate terminal.

[0131] The voltages of the three at different timings can also be shown in Figure 3(d): In the voltage input stage, only the forward voltage is input to the source terminal.

[0132] The voltages of the three at different timings can also be shown in Figure 3(e): In the voltage input stage, only negative voltage is input to the source terminal.

[0133] Method embodiment 4, as Figure 7 , Figure 7 It is a schematic diagram of a fourth embodiment of a test method for a display panel actual charging rate test board in the present invention.

[0134] Step 200 also includes:

[0135] The circuit structure in this embodiment is consistent with the circuit structure of method embodiment 2. Step 240, using the first adjustment circuit to adjust the first adjustment resistor and the first adjustment capacitor to obtain the equivalent resistance and equivalent capacitance of the source terminal of the display panel thin film transistor 200; Step 250, using the second adjustment circuit to adjust the second adjustment resistor and the second adjustment capacitor to obtain the equivalent resistance and equivalent capacitance of the gate terminal of the display panel thin film transistor 200; Step 260, using the third adjustment circuit to adjust the third adjustment capacitor and the fourth adjustment capacitor to obtain the equivalent capacitance of the common electrode VCOM terminal and the drain terminal of the display panel thin film transistor 200.

[0136] Method embodiment 5, as Figure 8 , Figure 8 It is a schematic diagram of a fifth embodiment of a test method for a display panel actual charging rate test board in the present invention.

[0137] Step 400 includes: step 410, obtaining source input voltage data and drain voltage data at different times; step 420, calculating the actual charging rate of the display panel using actual charging rate = (drain voltage / source input voltage) × 100%.

[0138] A display panel actual charging rate test board and test method of the present invention are implemented. By respectively setting a first adjustment circuit, a second adjustment circuit and a third adjustment circuit at the source terminal, the gate terminal, the common electrode VCOM terminal and the drain terminal of the display panel thin film crystal, the resistance and / or capacitance of the source terminal, the gate terminal, the common electrode VCOM terminal and the drain terminal are adjusted respectively, so that the resistance of the test board is consistent with the resistance and / or capacitance of the thin film transistor during operation, and inputting pulse timing voltages at different times, so as to obtain an accurate display panel actual charging rate, thereby improving the accuracy of the test.

[0139] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A display panel actual charging rate test board, characterized in that: include: Control unit; a first input unit; A second input unit; The third input unit; Output unit; The control unit is connected to the first input unit, the second input unit, the third input unit and the output unit respectively; The first input unit is connected to the source terminal of the thin film transistor; The second input unit is connected to the gate terminal of the thin film transistor; The third input unit is connected to the common electrode VCOM terminal of the thin film transistor; The output unit is connected to the drain terminal of the thin film transistor; The first input unit, the second input unit, and the third input unit are respectively used to input voltage signals of different timings according to control instructions of the control unit; The output unit is used to output the actual output voltage signal of the display panel; The control unit is used to output control instructions to each unit, and calculate the actual charging rate of the display panel by acquiring the actual output voltage data of the output unit and the actual input voltage data of the first input unit.

2. The display panel actual charging rate test board according to claim 1, characterized in that: The first input unit, the second input unit, and the third input unit respectively include: a first regulating circuit; a second regulating circuit; A third regulating circuit; The first regulating circuit is connected between the input terminal of the first input unit and the source terminal of the thin film transistor; The second regulating circuit is connected between the input terminal of the second input unit and the gate terminal of the thin film transistor; The third regulating circuit is connected between the input terminal of the third input unit and the common electrode VCOM terminal and the drain terminal of the thin film transistor; Wherein, the first regulating circuit is used to adjust the capacitance and resistance of the source terminal; The second regulating circuit is used to adjust the capacitance and resistance of the gate terminal; The third regulating circuit is used to adjust the capacitance between the drain terminal and the common electrode VCOM terminal.

3. The display panel actual charging rate test board according to claim 2, characterized in that: The first regulating circuit comprises: A first adjusting resistor; A first adjustment capacitor; A first end of the first regulating resistor is commonly connected to an input end of the first input unit and a first end of the first regulating capacitor, and a second end of the first regulating resistor is connected to a source end of the thin film transistor; The second end of the first regulating capacitor is grounded.

4. The display panel actual charging rate test board according to claim 3, characterized in that: The second regulating circuit comprises: A second adjusting resistor; A second adjustment capacitor; A first end of the second regulating resistor is commonly connected to the input end of the second input unit and the first end of the second regulating capacitor, and a second end is connected to the gate end of the thin film transistor; The second end of the second regulating capacitor is grounded.

5. The display panel actual charging rate test board according to claim 4, characterized in that: The third regulating circuit comprises: The third adjustment capacitor; A fourth adjustment capacitor; The first end of the third regulating capacitor is connected to the input end of the third input unit and the first end of the fourth regulating capacitor, and the second end of the third regulating capacitor is connected to the common electrode VCOM end; The drain terminal of the thin film transistor is also connected to the second terminal of the fourth regulating capacitor.

6. A method for testing a display panel actual charging rate test board, using the actual charging rate test board according to any one of claims 1 to 5, characterized in that: include: Step 100, connecting with the thin film transistor of the display panel by welding or FPC switching; Step 200, adjusting the resistance and / or capacitance of the source terminal, the gate terminal, the common electrode VCOM terminal and the drain terminal of the thin film transistor; Step 300: Inputting a pulse timing voltage to the source terminal, the gate terminal and the drain terminal at time T; Step 400: Obtain the timing voltage data of the source terminal input and the actual voltage data of the drain, and calculate the actual charging rate.

7. The display panel actual charging rate test board testing method according to claim 6, characterized in that: The step 200 includes: Step 210: providing a first regulating circuit between the input terminal of the first input unit and the source terminal of the thin film transistor; Step 220: providing a second regulating circuit between the input terminal of the second input unit and the gate terminal of the thin film transistor; Step 230, providing a third regulating circuit between the input terminal of the third input unit and the common electrode VCOM terminal and the drain terminal of the thin film transistor; Wherein, the first regulating circuit is used to adjust the capacitance and resistance of the source terminal; The second regulating circuit is used to adjust the capacitance and resistance of the gate terminal; The third regulating circuit is used to adjust the capacitance between the drain terminal and the common electrode VCOM terminal.

8. The display panel actual charging rate test board testing method according to claim 7, characterized in that: The step 300 includes: Step 310: at time T, the first input unit inputs a first pulse timing voltage to the source terminal; Step 320, at the time T, the second input unit inputs a second pulse timing voltage to the gate terminal; Step 330: At the time T, the third input unit inputs a third pulse timing voltage to the gate terminal.

9. The display panel actual charging rate test board testing method according to claim 8, characterized in that: The step 200 further includes: Step 240: Use the first adjustment circuit to adjust the first adjustment resistor and the first adjustment capacitor to obtain the equivalent resistance and equivalent capacitance of the source terminal of the thin film transistor of the display panel; Step 250: Use the second regulating circuit to regulate the second regulating resistor and the second regulating capacitor to obtain the equivalent resistance and the equivalent capacitance of the gate terminal of the thin film transistor of the display panel; Step 260: Utilize the third regulating circuit to regulate the third regulating capacitor and the fourth regulating capacitor to obtain the equivalent capacitance of the common electrode VCOM terminal and the drain terminal of the thin film transistor of the display panel.

10. The display panel actual charging rate test board testing method according to claim 9, characterized in that: The step 400 includes: Step 410, obtaining source input voltage data and drain voltage data at different times; Step 420, using the formula: Actual charging rate = (drain voltage / source input voltage) × 100%, calculate the actual charging rate of the display panel.

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