A data transmission device, method, memory and storage system

Abstract

Embodiments of the present application provide a data transmission device, method, memory and storage system. The data transmission device comprises a post-write generator configured to generate a post-write clock signal after the end of a write operation cycle, the post-write clock signal being used to enable remaining data in to-be-written data to be loaded into a page buffer in a memory; wherein the to-be-written data is data expected to be loaded into the page buffer in the write operation cycle; and the remaining data is data in the to-be-written data that fails to be loaded into the page buffer in the write operation cycle.

Description

Technical Field

[0001] This invention relates to the field of memory technology, and in particular to a data transmission device, method, memory, and storage system. Background Technology

[0002] With the development of memory, data masking is often used to mask data that does not need to be written to memory during write operations. Currently, data masking operations affect the input of valid data during write operations. Summary of the Invention

[0003] In view of this, the present invention provides a data transmission apparatus, method, memory, and storage system, which, by setting a post-written operation, inputs a portion of valid data that could not be input into the memory during the write operation into the memory, thereby eliminating the influence of the data masking operation on the input of valid data during the write operation.

[0004] To achieve the above objectives, the technical solution of the present invention is implemented as follows:

[0005] In a first aspect, embodiments of the present invention provide a data transmission apparatus, including: a post-write generator, the post-write generator being configured to: generate a post-write clock signal after the end of a certain write operation cycle, the post-write clock signal being used to enable the remaining data in the data to be written to be loaded into the page cache in the memory;

[0006] The data to be written is the data expected to be loaded into the page cache during the write operation cycle; the remaining data is the data that failed to be loaded into the page cache during the write operation cycle.

[0007] In the above scheme, the post-write generator includes a post-write enable component and a post-write clock generation component, wherein,

[0008] The post-write enable component is used to generate a valid post-write enable signal after a certain write operation cycle ends, and send the valid post-write enable signal to the post-write clock generation component.

[0009] The post-write clock generation component is used to receive the valid post-write enable signal, and generate the post-write clock signal based on the valid post-write enable signal.

[0010] In the above scheme, the post-write enable component is also used to generate a failed post-write enable signal when the post-write clock signal meets the requirements, and send the failed post-write clock enable signal to the post-write clock component.

[0011] The post-write clock generation component is also configured to receive the failed post-write enable signal, and based on the failed post-write enable signal, to close and stop generating the post-write clock signal.

[0012] In the above scheme, the post-write enable component includes a D-type flip-flop; the D-type flip-flop includes a first input terminal, a second input terminal, and an output terminal, wherein;

[0013] The first input terminal is used to input a command latch clock signal; the command latch clock signal is generated by a command latch enable signal and a command / address sampling clock signal; the command / address sampling clock signal is a clock signal that samples the command and address on the data bus of the memory;

[0014] The second input terminal is used to input the write enable signal;

[0015] The output terminal is used to generate a valid post-write enable signal under the action of the command latch clock signal and the write enable signal, and send the valid post-write enable signal to the post-write clock generation component.

[0016] In the above scheme, the post-write clock generation component includes: a state machine and a post-write clock oscillator, wherein;

[0017] The state machine is used to receive the valid write-back enable signal, generate a trigger command based on the valid write-back enable signal, and send the trigger command to the write-back clock oscillator.

[0018] The post-write clock oscillator is used to start generating the post-write clock signal when it receives the trigger instruction sent by the state machine.

[0019] In the above scheme, the state machine is further configured to generate an exit signal when the post-write clock signal meets the requirements, and send the exit signal to the post-write enable component; the exit signal is used to cause the post-write enable component to generate a failed post-write enable signal; the failed post-write enable signal causes the state machine to shut down.

[0020] The post-write clock oscillator is further configured to: stop generating the post-write clock signal after the state machine is turned off; wherein the post-write clock signal satisfies the requirement that the number of rising or falling edges of the post-write clock signal reaches a preset threshold.

[0021] In the above scheme, the data transmission device further includes: a data serial-to-parallel converter and a write data converter; wherein,

[0022] The data serial-to-parallel converter is used to convert the serial remaining data into first parallel data having a first timing alignment with a first set of write clock signals; and to send the first parallel data to the write data converter; the set of write clock signals is generated by the subsequent write clock signal.

[0023] The write data converter, coupled to the data serial-to-parallel converter, is used to receive the first parallel data and transmit the first parallel data to the page buffer.

[0024] In the above scheme, the data transmission device further includes a mask serial-to-parallel converter for generating parallel mask data having a second timing alignment with respect to the set of write clock signals; and sending the mask data to the write data converter.

[0025] The write data converter, coupled to the mask serial-to-parallel converter, is further configured to: receive the mask data when the first parallel data generated by the data serial-to-parallel converter contains redundant data; use the mask data to hide the redundant data in the first parallel data to obtain valid data; and send the valid data to the page buffer.

[0026] In the above scheme, the data transmission device further includes: a clock driver, which is coupled to the data serial-to-parallel converter and the mask serial-to-parallel converter, and is used to generate the set of write clock signals based on the post-write clock signal.

[0027] In the above scheme, the data transmission device further includes: an address generator, used to generate a loading timing signal based on the address signal;

[0028] The clock driver is further configured to: generate the set of write clock signals with timing patterns based on the post-write clock signal and the load timing signal; the timing pattern is used to control the loading time of loading the first parallel data and the mask data into the write data converter.

[0029] In the above scheme, the data serial-to-parallel converter and the mask serial-to-parallel converter have the same structure, matching transistor delays, and matching line delays.

[0030] Secondly, embodiments of the present invention provide a data transmission method, the method comprising:

[0031] After a certain write operation cycle ends, a write clock signal is generated;

[0032] The remaining data in the data to be written is loaded into the page cache of the memory based on the post-write clock signal;

[0033] The data to be written is the data expected to be loaded into the page cache during the write operation cycle; the remaining data is the data that failed to be loaded into the page cache during the write operation cycle.

[0034] In the above scheme, the step of generating and writing the clock signal includes:

[0035] After a certain write operation cycle ends, a valid write-after enable signal is generated; the write-after clock signal is generated based on the valid write-after enable signal.

[0036] The effective write enable signal is generated based on the command latch clock signal and the write enable signal; the command latch clock signal is generated by the command latch enable signal and the command / address sampling clock signal; the command / address sampling clock signal is a clock signal that samples the commands and addresses on the data bus of the memory.

[0037] In the above scheme, generating the post-write clock signal based on the valid post-write enable signal includes:

[0038] A trigger instruction is generated based on the effective post-write enable signal;

[0039] The post-write clock signal is generated based on the trigger instruction;

[0040] When the post-write clock signal meets the requirements, an exit signal is generated;

[0041] When a failed write enable signal is obtained based on an exit signal, the generation of the write clock signal is stopped; wherein the write clock signal satisfies the requirement that the number of rising or falling edges of the write clock signal reaches a preset threshold.

[0042] In the above scheme, the method further includes:

[0043] The remaining serial data is converted into first parallel data with a first timing alignment with respect to a set of write clock signals; the set of write clock signals is generated by the subsequent write clock signals.

[0044] The first parallel data is transferred to the page cache.

[0045] In the above scheme, the method further includes:

[0046] Generate parallel mask data with a second timing alignment with respect to the set of write clock signals; send the mask data to the write data converter;

[0047] When the first parallel data contains redundant data, the mask data is received; the mask data is used to hide the redundant data in the first parallel data to obtain valid data;

[0048] Send the valid data to the page cache.

[0049] In the above scheme, the method further includes:

[0050] Loading timing signals are generated based on address signals;

[0051] The set of write clock signals with timing patterns is generated based on the post-write clock signal and the load timing signal; the timing pattern is used to control the loading time of loading the first parallel data and the mask data into the write data converter.

[0052] Thirdly, embodiments of the present invention also provide a memory, including a memory cell array; and peripheral circuitry configured to write data to the memory cell array in parallel; wherein...

[0053] The peripheral circuit includes any of the above-mentioned data transmission devices.

[0054] Fourthly, embodiments of the present invention also provide a storage system, including: one or more of the above-described memories; and a memory controller coupled to the memories; the memory controller being configured to control various operations of the memories.

[0055] In the above solution, the storage system is a solid-state drive or a memory card.

[0056] This invention provides a data transmission apparatus, method, memory, and storage system. The data transmission apparatus includes a post-write generator configured to generate a post-write clock signal after the end of a write operation cycle. This post-write clock signal enables remaining data in the data to be written to be loaded into a page buffer in the memory. The data to be written is data expected to be loaded into the page buffer during the write operation cycle; the remaining data is data in the data to be written that failed to be loaded into the page buffer during the write operation cycle. The data transmission apparatus provided by this invention, when no clock signal is available for data loading after the end of a write operation cycle, generates a post-write clock signal using a post-write generator. This post-write clock signal is then used to load the remaining data that failed to be loaded into the page buffer after the end of the write operation cycle, ensuring that all data to be written is loaded into the page buffer, thereby guaranteeing the accuracy and integrity of the data written into the page buffer. Attached Figure Description

[0057] When read in conjunction with the accompanying drawings, aspects of the invention can be best understood from the following specific embodiments. Note that, according to standard practice in industry, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the features may be arbitrarily increased or decreased.

[0058] Figure 1 This is a schematic diagram of the structure of a data transmission device provided in an embodiment of the present invention;

[0059] Figure 2 This is a schematic diagram of a post-write generator provided in an embodiment of the present invention;

[0060] Figure 3 This is a schematic diagram illustrating the structure and connection relationship of a post-write enable component and a post-write clock generation component provided in an embodiment of the present invention;

[0061] Figure 4 A schematic diagram illustrating the process of generating a post-write clock signal using a post-write enable component and a post-write clock generation component, as provided in an embodiment of the present invention.

[0062] Figure 5 A timing diagram of the generated and written clock signal provided in an embodiment of the present invention;

[0063] Figure 6 This is a functional block diagram of a serial-to-parallel converter provided in an embodiment of the present invention;

[0064] Figure 7 A functional block diagram of a clock driver provided in an embodiment of the present invention;

[0065] Figure 8 A timing diagram for generating a set of write clock signals based on a clock driver, provided for embodiments of the present invention;

[0066] Figure 9 A timing diagram of a write clock signal generated based on a post-write clock signal, provided in an embodiment of the present invention;

[0067] Figure 10 This is a timing diagram provided by an embodiment of the present invention for loading data to be written into the page cache during a write operation cycle;

[0068] Figure 11 This is another timing diagram provided by an embodiment of the present invention for loading the data to be written into the page cache during the write operation cycle;

[0069] Figure 12 The embodiments of the present invention are based on Figure 10 The sequence diagram shown is a sequence diagram in which the remaining data is written to the page cache.

[0070] Figure 13The embodiments of the present invention are based on Figure 11 Another timing diagram based on the timing diagram shown is used to write the remaining data to the page cache;

[0071] Figure 14 A flowchart illustrating a data transmission method provided in an embodiment of the present invention;

[0072] Figure 15 This is a schematic diagram of the structure of a memory provided in an embodiment of the present invention;

[0073] Figure 16 A schematic diagram of the structure of a memory including peripheral circuitry provided in an embodiment of the present invention;

[0074] Figure 17 This is a schematic diagram of the structure of a storage system provided in an embodiment of the present invention. Detailed Implementation

[0075] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and not limiting. For example, in the following description, the formation of a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Additionally, reference numerals and / or letters may be repeated in various examples. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or constructions discussed.

[0076] Furthermore, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” are used herein for ease of description to describe the relationship between one element or feature and (one or more) another element or feature as shown in the figures. Spatial relative terms are intended to cover different orientations in the use or operation of the device other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0077] In related technologies, modern electronic devices and systems include high-speed semiconductor memories for various data storage purposes. For example, Random Access Memory (RAM) is a type of memory that can be read and written in any order and is typically used to store processor-accessible working data and machine code. Dynamic Random Access Memory (DRAM) is another example, a type of RAM that can be dynamically accessed. NAND memory, also known as NAND flash memory, is a storage device superior to hard disk drives, combining the high density of EPPOM and the versatility of EEPROM structures; it is a widely used non-volatile memory. To enable operation in high-speed systems, DRAM has been developed into Synchronous Dynamic Random Access Memory (SDRAM). SDRAM includes an interface coordinated with an externally supplied system clock. The system clock is synchronized with the overall system processing speed, so read and write operations performed on SDRAM can be synchronized with the system clock. SDRAM can be classified as Single Data Rate (SDR) SDRAM and Double Data Rate (DDR) SDRAM. In SDR SDRAM, data can be read and written at either the rising or falling edge of the system clock (not both). In DDR SDRAM, data can be read and written at both the rising and falling edges of the system clock. Therefore, DDR SDRAM can have twice the data bandwidth of the system clock frequency. Similarly, NAND flash memory can also be configured to read and write data at either the rising or falling edge (not both) of the system clock, also having twice the data bandwidth of the system clock frequency.

[0078] In some cases, it is desirable to write only a portion of the data stream to memory to ensure that some data stored in memory remains unchanged. One solution is to use a write mask to mask the data stream during a write operation and prevent some data from reaching memory cells that should remain unchanged. For example, NAND flash memory can include data mask pins associated with every eight data pins, and these data mask pins can be used to indicate whether eight data bits on the eight data pins should be written to memory cells. Specifically, the mask signal at the data mask pin can force eight bits of data on the eight data pins associated with the data mask pin to change from a programming state to an erase state, thus preventing input data in the locally erased state from being written to memory cells. Similarly, DRAM can also use mask data to mask the data stream during a write operation to prevent some data from reaching memory cells that should remain unchanged.

[0079] Through research, the applicant discovered that due to the influence of data masking operations, the serial-to-parallel converter included in the memory loads some invalid data during write operations, such as 00h (hexadecimal). Loading this invalid data consumes some valid write cycles of the data strobe clock signals (DQS_T / DQS_C), resulting in a portion of the valid data that should have been loaded during the write operation remaining in the data pipeline. To solve the above technical problem, embodiments of the present invention provide a data transmission device that, by setting a post-write operation, inputs a portion of valid data that failed to be input into the memory during the write operation, thereby eliminating the influence of data masking operations on the input of valid data during the write operation.

[0080] Specifically, the technical solution of the present invention will be described in detail below with reference to the accompanying drawings.

[0081] Figure 1 This is a schematic diagram of a data transmission device provided in an embodiment of the present invention. Figure 1 As shown, the data transmission device 10 includes: a post-write generator 101, which is configured to generate a post-write clock signal after the end of a certain write operation cycle, the post-write clock signal being used to enable the remaining data in the data to be written to be loaded into the page cache 20 in the memory.

[0082] The data to be written is the data expected to be loaded into the page cache during the write operation cycle; the remaining data is the data that failed to be loaded into the page cache during the write operation cycle.

[0083] It should be noted that, based on the applicant's findings, in some cases, during a certain write operation cycle, a portion (remaining data) of the data to be written to the page cache of the memory may not be loaded into the page cache. Furthermore, after a write operation cycle ends, the DQS clock signal is stopped, causing the remaining data to fail to be loaded into the page cache due to the lack of a available clock signal. Therefore, to address this issue, this embodiment of the invention provides a data transmission apparatus comprising a post-write generator configured to generate a post-write clock signal after a write operation cycle ends, and to use this post-write clock signal to load the remaining data into the page cache 20 of the memory.

[0084] For the structure of the post-write generator 101, such as Figure 2 The diagram shown illustrates a structural schematic of a post-write generator 101 provided in an embodiment of the present invention. Figure 2 In the above, the post-write generator includes a post-write enable component 1011 and a post-write clock generation component 1012, wherein,

[0085] The post-write enable component is used to generate a valid post-write enable signal after a certain write operation cycle ends, and send the valid post-write enable signal to the post-write clock generation component.

[0086] The post-write clock generation component is used to receive the valid post-write enable signal, turn on based on the valid post-write enable signal, and generate the post-write clock signal.

[0087] In other embodiments, the write-after enable component is further configured to generate a failed write-after enable signal when the write-after clock signal meets the requirements, and send the failed write-after clock enable signal to the write-after clock component.

[0088] The post-write clock generation component is also configured to receive the failed post-write enable signal, and based on the failed post-write enable signal, to close and stop generating the post-write clock signal.

[0089] It should be noted that the post-write enable component here can be used to generate a valid post-write enable signal to enable the post-write clock generation component; it can also be used to generate a invalid post-write enable signal to disable the post-write clock generation component. The valid and invalid post-write enable signals can be collectively referred to as the post-write enable signal `en_postwt`. The validity and invalid post-write enable signals are defined by the designer. One possible approach is: when `en_postwt` is high, it is a valid post-write enable signal, which enables the post-write clock generation component to start generating the post-write clock signal; when `en_postwt` is low, it is a invalid post-write enable signal, which disables the post-write clock generation component to stop generating the post-write clock signal. Here, the period of the post-write clock signal can be different from the period of the DQS_T and DQS_C clock signals during normal writing.

[0090] It should be clear that the write-after clock signal is generated after the end of a certain write operation cycle. That is, based on the above description, it is generated after the write operation cycle in order to write the remaining data. Therefore, the write-after enable component 1011 needs a signal to trigger the generation of a valid write-after enable signal or a invalid write-after enable signal, rather than being generated continuously.

[0091] In the programming (or writing) process, the `en_write` signal is the write enable signal. This means that during the write operation cycle, even with a DQS clock, data can only be loaded into the page buffer if the `en_write` signal is valid. Therefore, a specific clock signal can be used to latch the `en_write` signal to trigger the write-after-write enable component 1011 to generate a valid write-after-write enable signal, which in turn enables the write-after-write clock generation component 1012 to generate a write-after-write clock signal, thus initiating the write-after-write operation. Based on the generated write-after-write clock signal, the remaining data is written into the page buffer 20. This approach allows the remaining data to be loaded into the page buffer 20 even without a DQS clock, using the write-after-write clock signal and with the `en_write` signal valid.

[0092] Here, the specific clock signal can be generated by the Command Latch Enable (CLE) signal and the command / address sampling clock signal. The Command Latch Enable signal is sent simultaneously with the Program Confirm Command (PMC) and is used to latch the PMC. The PMC is a confirmation command sent after data input during the programming (or writing) process. The command / address sampling clock signal is a clock signal that samples the command or address on the memory's data bus when valid, and can be abbreviated as we_n. The specific clock signal generated by the CLE signal and we_n can be called the command latch clock signal, denoted by the symbol clk_cle. Based on the foregoing description, clk_cle is used to latch en_write to generate a valid post-write enable signal to enable the post-write operation.

[0093] Specifically, regarding the structure of the post-write enable component 1011 and the post-write clock generation component 1012, one optional implementation may be as follows: Figure 3 As shown, it illustrates a structural schematic diagram of the post-write enable component and the post-write clock generation component provided in an embodiment of the present invention.

[0094] like Figure 3 As shown, the post-write enable component can be implemented using a D-type flip-flop, that is: the post-write enable component includes a D-type flip-flop; the D-type flip-flop includes a first input terminal, a second input terminal, and an output terminal, wherein;

[0095] The first input terminal is used to input a command latch clock signal; the command latch clock signal is generated by a command latch enable signal and a command / address sampling clock signal; the command / address sampling clock signal is a clock signal that samples the command and address on the data bus of the memory;

[0096] The second input terminal is used to input the write enable signal;

[0097] The output terminal is used to generate a valid post-write enable signal under the action of the command latch clock signal and the write enable signal, and send the valid post-write enable signal to the post-write clock generation component.

[0098] like Figure 3 As shown, the post-write clock generation component may include: a state machine and a post-write clock oscillator, wherein;

[0099] The state machine is used to receive the valid write-back enable signal, generate a trigger command based on the valid write-back enable signal, and send the trigger command to the write-back clock oscillator.

[0100] The post-write clock oscillator is used to start generating the post-write clock signal when it receives the trigger instruction sent by the state machine.

[0101] In some embodiments, the state machine can also be used to generate an exit signal when the post-write clock signal meets the requirements, and send the exit signal to the post-write enable component; the exit signal is used to cause the post-write enable component to generate a failed post-write enable signal; the failed post-write enable signal causes the state machine to shut down.

[0102] The post-write clock oscillator is further configured to: stop generating the post-write clock signal after the state machine is turned off; wherein the post-write clock signal satisfies the requirement that the number of rising or falling edges of the post-write clock signal reaches a preset threshold.

[0103] It should be noted that `en_osc` is the trigger instruction generated by the state machine based on the valid post-write enable signal. `clk_postwt` is the generated post-write clock signal. `stmexit_n` is the exit signal generated by the state machine when the post-write clock signal meets the requirements. Meeting the requirements for the post-write clock signal means that the number of rising or falling edges of the post-write clock signal reaches a preset threshold. The counting of rising or falling edges of the post-write clock signal can be, but is not limited to, performed by the state machine.

[0104] For the specific workflow of writing to generator 101, please refer to... Figure 4 and Figure 5 , Figure 4 A schematic diagram illustrating the process of generating a post-write clock signal using a post-write enable component and a post-write clock generation component, as provided in an embodiment of the present invention. Figure 5 This is a timing diagram of the generated and written clock signal provided in an embodiment of the present invention.

[0105] It should be noted that, Figure 4 DFF in the middle is Figure 3 The D-type flip-flop in the image, where the CK pin is... Figure 3 The first input terminal mentioned in the text; the D pin is also known as... Figure 3 The second input terminal mentioned in the text; Figure 4 The output terminal in the middle is also Figure 3 The output terminal; srt_n is the pin that receives the stmexit_n signal. Figure 5 In this context, osc_clock represents the write clock signal generated under a valid write enable signal; expected indicates that when the rising or falling edge of the write clock signal reaches a preset threshold, a signal is issued to exit the logic operation in the start state.

[0106] Based on this, the specific workflow of the post-write generator 101 can include the following: Under the action of clk_cle and en_write, a valid en_postwt is obtained (e.g., ... Figure 5 As shown (high level active), the state machine startup logic begins to work, generating en_osc, which causes the post-write clock oscillator to start generating osc_clock. Simultaneously, the state machine begins counting the rising or falling edges of the generated osc_clock. When the number of rising or falling edges of the osc_clock reaches a preset threshold, the state machine exits its logic, generating the stmexit_n signal, which causes the post-write enable component to generate a disabled post-write enable signal (e.g., as shown). Figure 5 As shown, a low-level failure causes the state machine to shut down, thereby causing the post-write clock generation component to stop generating osc_clock. At this time, the post-write clock signal that has been generated and whose number of rising or falling edges reaches a preset threshold is the post-write clock signal clk_postwt that meets the requirements.

[0107] After the write clock signal is generated, the specific method for loading the remaining data into the page buffer is as follows. In some embodiments, the data transmission device further includes: a data serial-to-parallel converter 102 and a write data converter 103; wherein,

[0108] The data serial-to-parallel converter is used to convert the serial remaining data into first parallel data having a first timing alignment with a first set of write clock signals; and to send the first parallel data to the write data converter; the set of write clock signals is generated by the subsequent write clock signal.

[0109] The write data converter, coupled to the data serial-to-parallel converter, is used to receive the first parallel data and transmit the first parallel data to the page buffer.

[0110] It should be noted that the data serial-to-parallel converter 102 outputs parallel data, such as DATA<63:0>. Specifically, the data serial-to-parallel converter 102 is configured to convert the remaining serial data (e.g., DQ<7:1>) into first parallel data (e.g., DATA<63:0>) with a first timing alignment based on a set of write clock signals (e.g., a first write clock signal wt_x1, a second write clock signal wt_x2, and a third write clock signal wt_x4). In one example, the circuit structure of the data serial-to-parallel converter 102 can be referenced. Figure 6 As shown. Figure 6 This is a schematic diagram of the circuit structure of the data serial-to-parallel converter 102 provided in an embodiment of the present invention.

[0111] return Figure 1 The data transmission apparatus shown includes a write data converter 103 that can be configured to receive the first parallel data and transmit the first parallel data to the page buffer 20.

[0112] In some embodiments, such as Figure 1 As shown, the data transmission device 10 further includes a data input buffer 107, a clock input buffer 108, an address input buffer 109, and an address latch input buffer 110. The data input buffer 107 can be configured to sample and buffer data DATA synchronously with the transition of the data strobe signal DQS from the clock input buffer 108. In the example, data DATA is received on eight pins, and the data input buffer 107 can be configured to include eight buffers to sample and buffer the signals on the eight pins respectively. The data input buffer 107 can output serial data on each of the eight paths, as indicated by DQ<7:0>. Therefore, the data strobe signal DQS can be used to synchronize the sampling of the input data DATA to generate serial data DQ<7:0>. It should be noted that the serial data DQ<7:0> comprises eight parallel bit streams, and each of the eight bit streams is a bit stream of serial data. The clock input buffer 108 can be configured to receive and shape the data strobe signal DQS. Address input buffer 109 and address latch input buffer 110.

[0113] In some embodiments, such as Figure 1 The data transmission device further includes a mask serial-to-parallel converter 104, used to generate parallel mask data having a second timing alignment with respect to the set of write clock signals; and to send the mask data to the write data converter.

[0114] The write data converter 103, coupled to the mask serial-to-parallel converter, is further configured to: receive the mask data when the first parallel data generated by the data serial-to-parallel converter contains redundant data; use the mask data to hide the redundant data of the first parallel data to obtain valid data; and send the valid data to the page buffer.

[0115] It should be noted that, due to the data serial-to-parallel converter or other reasons, when the write clock signal loads the remaining data into the page cache after use, the first parallel data obtained based on the data serial-to-parallel converter contains redundant data. In order to prevent this redundant data from affecting the operation of the memory, this embodiment of the invention uses a mask serial-to-parallel converter 104 to generate mask data, which is transmitted to the write data converter 103 together with the first parallel data. The write data converter 103 uses the mask data to hide the redundant data of the first parallel data, obtains the valid data, and loads the valid data into the page cache 20.

[0116] For the generation of a set of write clock signals, in some embodiments, such as Figure 1 As shown, the data transmission device further includes a clock driver 105, which is coupled to the data serial-to-parallel converter and the mask serial-to-parallel converter, and is used to generate the set of write clock signals based on the post-write clock signal.

[0117] In some embodiments, the data transmission device further includes: an address generator 106, configured to generate a loading timing signal based on an address signal;

[0118] The clock driver is further configured to: generate the set of write clock signals with timing patterns based on the post-write clock signal and the load timing signal; the timing pattern is used to control the loading time of loading the first parallel data and the mask data into the write data converter.

[0119] It should be noted that the aforementioned data serial-to-parallel converter and mask serial-to-parallel converter are configured to operate based on the same set of write clock signals, and this set of write clock signals can be configured as write clock signals with a timing pattern. This timing pattern controls the loading time of the first parallel data and the mask data onto the write data converter. Here, the timing pattern is generated based on a loading timing signal generated from the address signal ADDR. For example, the address generator 106 can use the three least significant bits of the address signal ADDR to generate the loading timing signal (e.g., ADD<2:00>). The loading timing signal can be used to control the timing of loading the first parallel data and the mask data onto the write data converter.

[0120] In some embodiments, the clock driver 105 may be coupled to a clock input buffer 108, an address generator 108, a data serial-to-parallel converter 102, and a mask serial-to-parallel converter 104. In an example, the clock driver 105 generates a set of write clock signals (e.g., the aforementioned first write clock signal wt_x1, second write clock signal wt_x2, and third write clock signal wt_x4) based on the post-write clock signal and the load timing signal.

[0121] It should be noted that, in Figure 1 The data transmission apparatus shown may also include: a column decoder 112, a row address decoder (not shown), and a write clock driver 111 (the clock required to write the data output by the write data converter to the page buffer), etc. These are also the components required to load the data to be written and any remaining data in the data to be written into the page buffer.

[0122] Figure 6 This is a schematic diagram of the circuit structure of a serial-to-parallel converter provided in an embodiment of the present invention. In some embodiments, both the aforementioned data serial-to-parallel converter and the mask serial-to-parallel converter can be used. Figure 6 The serial-to-parallel converter shown. Figure 6 As shown, the serial-to-parallel conversion circuit 300 is configured to convert the input bit stream IN into eight parallel bit streams D0-D7. The eight parallel bit streams D0-D7 each have a 1 / 8 bit rate of the input bit stream IN. The input bit stream IN is referred to as serial data, and the eight parallel bit streams D0-D7 are referred to as parallel data. In some examples, the data serial-to-parallel converter 102 includes eight serial-to-parallel conversion circuits 300 that perform serial-to-parallel conversion on each of DQ<7:0> to generate 64 parallel bit streams DATA<63:0>. In some embodiments, the mask serial-to-parallel converter 104 includes one serial-to-parallel conversion circuit 300 that converts serial mask data into parallel mask data, generating mask data with eight parallel bit streams.

[0123] exist Figure 6 In the serial-to-parallel conversion circuit 300, a sampling stage 310, a first shift stage 320, a third shift stage 330, and an output stage 340 may be sequentially coupled, wherein;

[0124] The sampling stage 310 can sample the input bit stream IN based on the data strobe signal DQS or the write-after clock signal. It should be noted that since the periods of DQS and the write-after clock signal may be different, sampling the input bit stream IN based on either DQS or the write-after clock signal only differs in the sampling period; everything else is similar. Therefore, the function of each component in the serial-to-parallel conversion circuit 300 will be explained using the example of sampling the input bit stream IN based on DQS, and the subsequent serial-to-parallel conversion will also be illustrated using the input bit stream IN sampled based on DQS.

[0125] That is, in some embodiments, sampling stage 310 may include: a first D flip-flop 310_1 and a second D flip-flop 310_2, wherein the first D flip-flop 310_1 may sample the input bit stream IN based on a first data strobe signal DQS_T; and the second D flip-flop 310_2 may sample the input bit stream IN based on a second data strobe signal DQS_C. In some examples, the first data strobe signal DQS_T and the second data strobe signal DQS_C have the same sampling rate, referred to as the base rate. The second data strobe signal DQS_C is phase-shifted by 180° relative to the first data strobe signal DQS_T. Thus, the input bit stream IN may include 8 bits of data transmitted at twice the base rate. In one example, the first D flip-flop 310_1 can sample the first, third, fifth, and seventh bits (e.g., D0, D2, D4, and D6) of the input bit stream IN based on the first rising edge, second rising edge, third rising edge, and fourth rising edge of the first data strobe signal DQS_T, respectively, and the second D flip-flop 310_2 can sample the second, fourth, sixth, and eighth data bits (e.g., D1, D3, D5, and D7) of the input bit stream IN based on the first rising edge, second rising edge, third rising edge, and fourth rising edge of the second data strobe signal DQS_C. The data bits sampled by the sampling stage 310 are then forwarded to the first shift stage 320.

[0126] The first shift stage 320 includes cascaded shift register paths 321-322 coupled to the sampling stage 310 to shift sampled data bits based on a first write clock signal wt_x1 and generate intermediate parallel data at nodes R0, F0, R1, and F1. For example, the first shift stage 320 includes a first cascaded shift register path 321 coupled to the first D flip-flop 310_1 to shift data bits sampled by the first D flip-flop 310_1 (e.g., the first, third, fifth, and seventh bits of the input bit stream IN (e.g., D0, D2, D4, and D6)) based on the first write clock signal wt_x1 and generate intermediate parallel data at nodes R0 and R1. Furthermore, the first shift stage 320 includes a second cascaded shift register path 322 coupled to the second D flip-flop 310_2 to shift data bits sampled by the second D flip-flop 310_2 (e.g., the second, fourth, sixth, and eighth data bits (e.g., D1, D3, D5, and D7) of the input bit stream IN based on a first write clock signal wt_x1, and to generate intermediate parallel data at nodes F0 and F1. In some examples, the first write clock signal wt_x1 may be generated based on a first data strobe signal DQS_T and a second data strobe signal DQS_C, for example, having the same frequency as the first data strobe signal DQS_T and the second data strobe signal DQS_C, and the rising edge of the first write clock signal wt_x1 may be configured to have a suitable phase shift relative to the rising edges of the first data strobe signal DQS_T and the second data strobe signal DQS_C.

[0127] In this embodiment, the first cascaded shift register path 321 includes a first D flip-flop 320_1 and a third D flip-flop 320_3 cascaded to the first D flip-flop 320_1, and the second cascaded shift register path 322 includes a second D flip-flop 320_2 and a fourth D flip-flop 320_4 cascaded to the second D flip-flop 320_2. The first D flip-flop 320_1, the second D flip-flop 320_2, the third D flip-flop 320_3, and the fourth D flip-flop 320_4 can be triggered by a first write clock signal wt_x1. For example, at the first rising edge of the first write clock signal wt_x1, the first D flip-flop 320_1 and the second D flip-flop 320_2 can shift the first and second bits (e.g., D0 and D1) of the input bit stream IN, respectively; and at the second rising edge of the first write clock signal wt_x1, the third D flip-flop 320_3 and the fourth D flip-flop 320_4 can shift the first and second bits of the input bit stream IN, respectively, and the first D flip-flop 320_1 and the second D flip-flop 320_2 can shift the third and fourth bits (e.g., D2 and D3) of the input bit stream IN, respectively, thus generating the first intermediate parallel data D0, D1, D2 and D3 at nodes R1, F1, R0 and F0, respectively.

[0128] Furthermore, at the third rising edge of the first write clock signal wt_x1, the first D flip-flop 320_1 and the second D flip-flop 320_2 can shift the fifth and sixth bits (e.g., D4 and D5) of the input bit stream IN, respectively; and at the fourth rising edge of the first write clock signal wt_x1, the third D flip-flop 320_3 and the fourth D flip-flop 320_4 can shift the fifth and sixth bits of the input bit stream, respectively, and the first D flip-flop 320_1 and the second D flip-flop 320_2 can shift the seventh and eighth bits (e.g., D6 and D7) of the input bit stream, respectively, thus generating the second intermediate parallel data D4, D5, D6 and D7 at nodes R1, F1, R0 and F0, respectively.

[0129] The second shift stage 330 can be configured to form parallel cascaded shift register paths 331-334 to shift intermediate parallel data (e.g., first intermediate parallel data D0, D1, D2, D3 and second intermediate parallel data D4, D5, D6, D7) based on a second write clock signal wt_x2, and generate parallel data (e.g., D0-D7) at nodes M1, N1, P1, Q1, M0, N0, P0, and Q0, respectively. For example, the second write clock signal wt_x2 may have a period twice that of the first write clock signal wt_x1. In other words, the frequency of the second write clock signal wt_x2 is half that of the first write clock signal wt_x1. In an embodiment, the second shift stage 330 may include four cascaded shift register paths 331-334 that shift intermediate parallel data respectively. For example, the first cascaded shift register path 331 includes a first D flip-flop 330_1 and a fifth D flip-flop 330_5 cascaded to the first D flip-flop 330_1; the second cascaded shift register path 332 includes a second D flip-flop 330_2 and a sixth D flip-flop 330_6 cascaded to the second D flip-flop 330_2; the third cascaded shift register path 333 includes a third D flip-flop 330_3 and a seventh D flip-flop 330_7 cascaded to the third D flip-flop 330_3; and the fourth cascaded shift register path 334 includes a fourth D flip-flop 330_4 and an eighth D flip-flop 330_8 cascaded to the fourth D flip-flop 330_4. The first D flip-flop 330_1, the second D flip-flop 330_2, the third D flip-flop 330_3, the fourth D flip-flop 330_4, the fifth D flip-flop 330_5, the sixth D flip-flop 330_6, the seventh D flip-flop 330_7, and the eighth D flip-flop 330_8 can be triggered by the second write clock signal wt_x2. For example, at the first rising edge of the second write clock signal wt_x2, the first D flip-flop 330_1, the second D flip-flop 330_2, the third D flip-flop 330_3, and the fourth D flip-flop 330_4 can shift the first to fourth bits (D0, D1, D2, D3) of the input bit stream IN, respectively; and at the second rising edge of the second write clock signal wt_x2, the fifth D flip-flop 330_5, the sixth D flip-flop 330_6, the seventh D flip-flop 330_7, and the eighth D flip-flop 330_8... The first to fourth bits of the input bit stream IN can be shifted separately, and the first D flip-flop 330_1, the second D flip-flop 330_2, the third D flip-flop 330_3, and the fourth D flip-flop 330_4 can shift the fifth to eighth bits (D4, D5, D6, D7) of the input bit stream IN respectively. Therefore, eight parallel data bit streams are generated at nodes M1, N1, P1, Q1, M0, N0, P0, and Q0 respectively, for example, D0, D1, D2, D3, D4, D5, D6, and D7.

[0130] Output stage 340 can be configured to output parallel data of the aforementioned eight bit streams based on a third write clock signal wt_x4. For example, the third write clock signal wt_x4 may have a period twice that of the second write clock signal wt_x2. In other words, the frequency of the third write clock signal wt_x4 is half that of the second write clock signal wt_x2 and one-quarter that of the first write clock signal wt_x1. In an embodiment, output stage 340 may include a first D flip-flop 340_1, a second D flip-flop 340_2, a third D flip-flop 340_3, a fourth D flip-flop 340_4, a fifth D flip-flop 340_5, a sixth D flip-flop 340_6, a seventh D flip-flop 340_7, and an eighth D flip-flop 340_8, all triggered by the third write clock signal wt_x4. For example, at the first rising edge of the third write clock signal wt_x4, the first D flip-flop 340_1, the second D flip-flop 340_2, the third D flip-flop 340_3, the fourth D flip-flop 340_4, the fifth D flip-flop 340_5, the sixth D flip-flop 340_6, the seventh D flip-flop 340_7 and the eighth D flip-flop 340_8 can shift the parallel data (e.g., D0, D1, D2, D3, D4, D5, D6 and D7) of the eight bit streams at nodes M1, N1, P1, Q1, M0, N0, P0 and Q0 respectively, and output the parallel data D0-D7.

[0131] Figure 7 This is a functional block diagram of a clock driver 105 according to some embodiments of the present disclosure. Figure 7 In the example, clock driver 105 may include clock divider 410 and timing control circuitry 420 coupled to clock divider 410. In an embodiment, clock divider 410 may include a first D flip-flop 411, a first inverter 413 that feeds back the Q terminal of the first D flip-flop 411 to the D terminal of the first D flip-flop 411, a second D flip-flop 412, and a second inverter 414 that feeds back the Q terminal of the second D flip-flop 412 to the D terminal of the second D flip-flop 412. The first D flip-flop 411 may be triggered by a clock signal CLKx1, and the second D flip-flop 412 may be triggered by a signal output at the Q terminal of the first D flip-flop 411. For example, the first D flip-flop 411 and the second D flip-flop 412 may be triggered by a single edge. Before operation, clock divider 410 may be cleared by, for example, a low-active signal, which clears both the first D flip-flop 411 and the second D flip-flop 412 within clock divider 410.

[0132] During a normal write operation, the x1 clock signal CLKx1 can be synchronized with the data strobe signal DQS. At the first rising edge of the x1 clock signal CLKx1, the signal at the Q terminal of the first D flip-flop 411 goes high (because the signal at the D terminal of the first D flip-flop 411 is high after the first D flip-flop 411 is cleared by the low-state active signal), and the signal at the D terminal of the first D flip-flop 411 goes low. At the second rising edge of the x1 clock signal CLKx1, the signal at the Q terminal of the first D flip-flop 411 goes low, and the signal at the D terminal of the first D flip-flop 411 goes high. And at the third rising edge of the x1 clock signal CLKx1, the signal at the Q terminal of the first D flip-flop 411 returns to high, and the signal at the D terminal of the first D flip-flop 411 returns to low. Therefore, the x1 clock signal CLKx1 can have a frequency twice that of the signal at the Q terminal of the first D flip-flop 411, or the signal at the Q terminal of the first D flip-flop 411 (i.e., the x2 clock signal CLKx2) can have a period twice that of the x1 clock signal CLKx1. Similarly, the signal at the Q terminal of the second D flip-flop 412 (i.e., the x4 clock signal CLKx4) can have a period twice that of the x2 clock signal CLKx2 and four times that of the x1 clock signal CLKx1. In another embodiment, the clock divider 410 can use two cascaded JK flip-flops or two cascaded T flip-flops instead of the first D flip-flop 411 and the second D flip-flop 412, and thus the first inverter 413 and the second inverter 414 can be omitted.

[0133] In some embodiments, during a write operation cycle, the timing control circuit 420 can generate a set of write clock signals (e.g., a first write clock signal wt_x1, a second write clock signal wt_x2, and a third write clock signal wt_x4) by combining the x1 clock signal CLKx1, the x2 clock signal CLKx2, and the x4 clock signal CLKx4 generated by the clock divider 410 based on the load timing signal (e.g., ADD<2:0>). For example, the timing control circuit 420 may include combinations of various timing and logic components (e.g., AND, OR, and NOT, multiplexers, multiplexers, flip-flops, etc.).

[0134] Figure 8 A timing diagram 800 based on the write clock signal generated by clock driver 105 is provided for an embodiment of the present invention. Figure 8As shown in the timing diagram 800, the x1 clock signal CLKx1 can be synchronized with the data strobe signal DQS. The clock divider 410 can generate an x2 clock signal CLKx2 with a period twice that of the x1 clock signal CLKx1, and an x4 clock signal CLKx4 with a period four times that of the x1 clock signal CLKx1. The timing control circuit 420 can generate a first write clock signal wt_x1 synchronized with the x1 clock signal CLKx1, generate a second write clock signal wt_x2 by inverting the x2 clock signal CLKx2, and generate a third write clock signal wt_x4 according to the start load position signal ADD<2:0>. Figure 8 The timing diagram 800 shown illustrates that when the load timing signal ADD<2:0> is “000” (as shown in 810), the third write clock signal wt_x4 can begin after three cycles of the first write clock signal wt_x1, and when the load timing signal ADD<2:0> is “100” (as shown in 820), the third write clock signal wt_x4 can begin after one cycle of the first write clock signal wt_x1. According to some other embodiments of the invention, when the start load position signal ADD<2:0> is “001”, “010”, and “011”, the third write clock signal wt_x4 can begin after two and a half (2.5) cycles, two and one and a half (1.5) cycles of the first write clock signal wt_x1, respectively.

[0135] It should be noted that the aforementioned Figure 7 and Figure 8 The diagram illustrates the generation of a set of write timings only as an example. In some embodiments, during the post-write operation, CLKx1 is synchronized with the generated post-write clock signal. The first D flip-flop 411 included in the clock divider 410 in the clock driver 105 is not active. The external CLKx1 is directly connected to CLKx2 of the timing control circuit 420, generating a second write clock signal wt_x2 synchronized with the post-write clock signal (the second write clock signal and the subsequent third write clock signal are generated based on the post-write clock signal and used to write the remaining data to the page buffer); the x4 clock signal CLKx4 is twice the period of the x2 clock signal CLKx2; the third write clock signal wt_x4 is generated according to the start load position signal ADD<2:0>. For example, when ADD<2:0> is "000", the third write clock signal wt_x4 is as follows: Figure 12 As shown in Figure 1201; for example, when ADD<2:0> is "100", the third write clock signal wt_x4 is as follows: Figure 13As shown in Figure 1301, the post-write clock signal does not include the first write clock signal wt_x1. That is, in the post-write operation, the effective clock signals are: the second write clock signal wt_x2, which is synchronized with the post-write clock signal, and the third write clock signal wt_x4, which has a period twice that of the post-write clock signal. Based on these two write clock signals, the remaining data is converted from serial to parallel and then written to the page buffer. Specifically, an exemplary timing diagram for generating the post-write clock signal is shown below. Figure 9 As shown (and) Figure 13 (The same as shown in 1301).

[0136] Figure 10 The timing diagram 1000 provided for an embodiment of the present invention loads the data to be written into the page buffer during a write operation cycle. It should be noted that since the post-write operation provided in this embodiment is performed after the write operation cycle, the specific implementation process of how the data to be written is loaded into the page buffer during the write operation cycle before the post-write is as follows: In the embodiment, the data serial-to-parallel converter 102 includes eight copies of the serial-to-parallel converter circuit structure 300 to perform serial-to-parallel conversion on the eight bit streams DQ<7:0> respectively, and the mask serial-to-parallel converter 104 includes one copy of the serial-to-parallel converter circuit structure 300 to perform serial-to-parallel conversion on the serial mask pattern. The data serial-to-parallel converter 102 and the mask serial-to-parallel converter 104 can be powered by the same set of write clock signals (e.g., ...). Figure 8 The first write clock signal wt_x1, the second write clock signal wt_x2, and the third write clock signal wt_x4 are shown as triggers. For example, the first shift stage 320 can be triggered by the first write clock signal wt_x1, the second shift stage 330 can be triggered by the second write clock signal wt_x2, and the output stage 340 can be triggered by the third write clock signal wt_x4.

[0137] In some examples, the clock divider 410 of the clock driver 105 can generate x1 clock signals CLKx1, x2 clock signals CLKx2, and x4 clock signals CLKx4 based on a base clock signal (e.g., synchronized with the data strobe signal DQS), and the timing control circuit 420 can generate a set of write clock signals (e.g., a first write clock signal wt_x1, a second write clock signal wt_x2, and a third write clock signal wt_x4) by combining the x1 clock signals CLKx1, x2 clock signals CLKx2, and x4 clock signals CLKx4 according to the load timing signal ADD<2:0> at the start of the load position. For example, the base clock signal can be synchronized with the data strobe signal DQS (e.g., data strobe signals DQS_T and DQS_C).

[0138] In an embodiment, the load timing signal ADD<2:0> can indicate the starting position in the bit stream used for writing and can indicate page buffers that do not need to be reloaded. In some examples, the first write clock signal wt_x1, the second write clock signal wt_x2, and the third write clock signal wt_x4 are generated based on the load timing signal ADD<2:0>, and the first write clock signal wt_x1, the second write clock signal wt_x2, and the third write clock signal wt_x4 control the serial-to-parallel converter circuit structure 300 to shift bits in the bit stream and form parallel data.

[0139] exist Figure 10 In the example, DQ<7:0> represents 8 parallel bit streams, and each bit stream consists of a serial stream of binary data. For example, H0 represents the 8 parallel bits that are the first bit of the 8 parallel bit streams; H1 represents the 8 parallel bits that are the second bit of the 8 parallel bit streams; H2 represents the 8 parallel bits that are the third bit of the 8 parallel bit streams; H3 represents the 8 parallel bits that are the fourth bit of the 8 parallel bit streams; and so on. In some examples, H0 is extracted from the settling time of the reference address signal (e.g., ADD<2:0>). For example, H0 is the first 8 parallel bits from the 8 parallel input bit streams DQ<7:0> in response to ADD<2:0> being settling, as shown in 1001.

[0140] exist Figure 10 In the example, DATA<63:0> represents a 64-bit parallel bit stream generated by serial-to-parallel conversion of DQ<7:0>; DMASK_N<7:0> represents 8 parallel bits, and "FF" represents the hexadecimal representation of 8 parallel binary bits "11111111"; DATA_BF<63:0> represents a 64-bit parallel bit stream that is the effective data of the combination of DATA<63:0> and DMASK_N<7:0>. For example, each bit in the serial mask pattern has a corresponding bit in each of the 8 parallel bit streams. Therefore, the first bit of DMASK_N<7:0> is DMASK_N <0> The first 8 bits of DATA<7:0> are used for the mask DATA<63:0>; the second bit is DMASK_N. <1> Used for the second 8th bit of the mask, DATA<15:8>; the third bit, DMASK_N <2> Used for the third 8th bit of the mask, DATA<23:16>; the fourth bit, DMASK_N <3> Used for the fourth 8th bit of the mask, DATA<31:24>; the fifth bit, DMASK_N <4> Used for the fifth and eighth bits of the mask, DATA<39:32>; the sixth bit, DMASK_N <5> Used for the sixth and eighth bits of the mask, DATA<47:40>; the seventh bit, DMASK_N <6> Used for the seventh and eighth bits of the mask DATA<55:48>; and the eighth bit DMASK_N <7> Used to mask the 8th bit of DATA<63:56>.

[0141] exist Figure 6 In the example, the load timing signal ADD<2:0> is “000”, and the timing patterns of the first write clock signal wt_x1, the second write clock signal wt_x2, and the third write clock signal wt_x4 are generated based on the load timing signal ADD<2:0>, as shown in 1010. Figure 10 The timing diagram 1000 shows that the first write clock signal wt_x1 can be synchronized with the base clock signal (i.e., the x1 clock signal CLKx1 generated by the clock divider 410), which is synchronized with the data strobe signal DQS_T and / or the data strobe signal DQS_C.

[0142] exist Figure 10 In the example, the base clock signal or data strobe signal DQS_T and / or data strobe signal DQS_C have a base clock rate (also referred to as the sampling rate in the context of data sampling), and DQ<7:0> is transmitted at twice the base clock rate. The data strobe signals DQS_T and DQS_C have the same sampling rate and a phase shift of approximately 180° from each other. The data strobe signals DQS_T and DQS_C are used, for example, to sample DQ<7:0> using the circuitry in sampling stage 310. For example, H0, H2, H4, H6, H8, H10, H12, H14… are sampled in response to the rising edge of the data strobe signal DQS_T; and H1, H3, H5, H7, H9, H11, H13, H15… are sampled in response to the rising edge of the data strobe signal DQS_C.

[0143] The first write clock signal wt_x1 is used, for example, in the first shift stage 320 of the eight replicas of the serial-to-parallel converter circuit structure 300 to perform serial-to-parallel conversion on the eight bit streams DQ<7:0> respectively; the second write clock signal wt_x2 is used, for example, in the second shift stage 330 of the eight replicas of the serial-to-parallel converter circuit structure 300 to perform serial-to-parallel conversion on the eight bit streams DQ<7:0> respectively; and the third write clock signal wt_x4 is used, for example, in the output stage 340 of the eight replicas of the serial-to-parallel converter circuit structure 300 to perform serial-to-parallel conversion on the eight bit streams DQ<7:0> respectively.

[0144] The first write clock signal wt_x1 is used, for example, in the first shift stage 320 of the serial-to-parallel converter circuit structure 300 to perform serial-to-parallel conversion on the serial mask pattern; the second write clock signal wt_x2 is used, for example, in the second shift stage 330 of the serial-to-parallel converter circuit structure 300 to perform serial-to-parallel conversion on the serial mask pattern; and the third write clock signal wt_x4 is used, for example, in the output stage 340 of the serial-to-parallel converter circuit structure 300 to perform serial-to-parallel conversion on the serial mask pattern.

[0145] exist Figure 10 In the example, the output stage 340 of the serial-to-parallel converter circuit structure 300, which performs serial-to-parallel conversion on the eight bit streams DQ<7:0> respectively in response to the first rising edge of the third write clock signal wt_x4, can output 64 parallel bits in DATA<63:0>, for example, as shown by "H7 H6 H5 H4 H3 H2 H1 H0"; and the output stage 340 of the serial-to-parallel converter circuit structure 300, which performs serial-to-parallel conversion on the serial mask pattern in response to the first rising edge of the third write clock signal wt_x4, can output 8 bits in DMASK_N<7:0>, for example, as shown by "FF". The 64 parallel bits in DATA<63:0> and the 8 bits in DMASK_N<7:0> are combined to generate 64 parallel bits in DATA_BF<63:0>, as shown by "H7 H6 H5 H4 H3 H2 H1 H0". For example, DMASK_N <0> Associated with H0(DATA<7:0>), and each bit in DATA<7:0> can be processed separately with DMASK_N. <0> The logical AND operation.

[0146] exist Figure 10In the example, the output stage 340 of the serial-to-parallel converter circuit structure 300, which performs serial-to-parallel conversion on the eight bit streams DQ<7:0> respectively in response to the second rising edge of the third write clock signal wt_x4, can output 64 parallel bits in DATA<63:0>, for example, as shown by "H15 H14 H13 H12 H11 H10 H9 H8"; and the output stage 340 of the serial-to-parallel converter circuit structure 300, which performs serial-to-parallel conversion on the serial mask pattern in response to the second rising edge of the third write clock signal wt_x4, can output 8 bits in DMASK_N<7:0>, for example, as shown by "FF". The 64 parallel bits in DATA<63:0> and the 8 bits in DMASK_N<7:0> are combined to generate 64 parallel bits in DATA_BF<63:0>, as shown by "H15 H14 H13 H12 H11 H10 H9 H8". For example, DMASK_N <0> Associated with H8, and can be executed on each bit of H8 individually with DMASK_N <0> The logical AND operation.

[0147] Then, the third write clock signal wt_x4 generates a clock signal clk_pb for the 64-bit parallel data to be written, which is converted by the write data converter 103, through the write clock driver 111. Based on the clock signal clk_pb and the address signal, the 64-bit parallel data to be written is written to the page buffer.

[0148] Figure 11 This is another timing diagram 700 according to some embodiments of the present disclosure. Figure 7 and Figure 6 The problem is that, Figure 10 The timing diagram of the data mask circuit 200, in which the loading timing signal ADD<2:0> is "000", is shown. Figure 11 The timing diagram of the data mask circuit 200, in which the loading timing signal ADD<2:0> is "100", is shown. Figure 11 In the example, the load timing signal ADD<2:0> is "100", and the timing patterns of the first write clock signal wt_x1, the second write clock signal wt_x2, and the third write clock signal wt_x4 are generated based on the load timing signal ADD<2:0>, as shown in 1110.

[0149] exist Figure 11In the example, the output stage 340 of the serial-to-parallel converter circuit structure 300, which performs serial-to-parallel conversion on the eight bit streams DQ<7:0> respectively in response to the first rising edge of the third write clock signal wt_x4, can output 64 parallel bits in DATA<63:0>, for example, as shown by "H3H2H1H000000000"; and the output stage 340 of the serial-to-parallel converter circuit structure 300, which performs serial-to-parallel conversion on the serial mask pattern in response to the first rising edge of the third write clock signal wt_x4, can output 8 bits in DMASK_N<7:0>, for example, as shown by "F0". The 64 parallel bits in DATA<63:0> and the 8 bits in DMASK_N<7:0> are combined to generate 64 parallel bits in DATA_BF<63:0>, as shown by "H3H2H1H000000000". For example, DMASK_N <4> Associated with H0(DATA<39:32>), and can be executed with DMASK_N on each bit of DATA<39:32> individually. <4> The logical AND operation.

[0150] exist Figure 11 In the example, the output stage 340 of the serial-to-parallel converter circuit structure 300, which performs serial-to-parallel conversion on the eight bit streams DQ<7:0> respectively in response to the second rising edge of the third write clock signal wt_x4, can output 64 parallel bits in DATA<63:0>, for example, as shown by "H11H10H9H8H7H6H5H4"; and the output stage 340 of the serial-to-parallel converter circuit structure 300, which performs serial-to-parallel conversion on the serial mask pattern in response to the second rising edge of the third write clock signal wt_x4, can output 8 bits in DMASK_N<7:0>, for example, as shown by "FF". The 64 parallel bits in DATA<63:0> and the 8 bits in DMASK_N<7:0> are combined to generate 64 parallel bits in DATA_BF<63:0>, as shown by "H11H10H9H8H7H6H5H4". For example, DMASK_N <0> Associated with H4, and each bit in H4 can be processed separately with DMASK_N. <0> The logical AND operation.

[0151] Furthermore, the loading timing signal ADD<2:0> can also be “001”, “010”, “011”, “101”, “110”, or “111”. According to some embodiments of this disclosure, for example, at the first rising edge of the third write clock signal WT_x4, the relationship between ADD<2:0>, DATA<63:0>, and DMASK_N<7:0> can be as shown in Table 1 below. In Table 1, each of “H0”, “H1”, “H2”, “H3”, “H4”, “H5”, “H6”, “H7”, and “H8” represents eight parallel bits from the eight parallel input bit streams DQ<7:0>. In some examples, “H0”, “H1”, “H2”, “H3”, “H4”, “H5”, “H6”, “H7”, and “H8” are extracted with reference to the settling time of ADD<2:0>. For example, H0 is the first eight parallel bits from the eight parallel input bit streams DQ<7:0> in response to the settling of ADD<2:0>. Furthermore, “00”, “FF”, “FE”, “FC”, “F8”, “F0”, “E0”, “C0”, and “80” are hexadecimal values ​​(HEX). As shown in Table 1, in some examples, ADD<2:0> can be used to control the start bit in the bit stream (e.g., each of 8 parallel bit streams) used to load into the memory cell, and the bits preceding the start bit do not need to be loaded into the page buffer. Additionally, in some examples, a mask pattern can be generated accordingly.

[0152] Then, the third write clock signal wt_x4 generates a clock signal clk_pb for the 64-bit parallel data to be written, which is converted by the write data converter 103, through the write clock driver 111. Based on the clock signal clk_pb and the address signal, the 64-bit parallel data to be written is written to the page buffer.

[0153] Table 1

[0154]

[0155]

[0156] After the write operation cycle is complete, in order to write the remaining data to the page buffer, the post-write operation is initiated according to the steps and components described above. For details on how to write the data to the page buffer based on the post-write clock signal, please refer to [link to documentation]. Figure 12 and Figure 13 .

[0157] Figure 12 The embodiments of the present invention are based on Figure 10The timing diagram shown represents a timing diagram for writing the remaining data to the page buffer. It should be noted that a set of post-write clock signals is required here: a second write clock signal wt_x2 synchronized with the post-write clock signal, and a third write clock signal wt_x4 whose period is twice that of the post-write clock signal, as detailed below. Figure 12 As shown in 1201, this differs from the write operation. Otherwise, the process of loading data into the page cache is similar and will not be elaborated further. See [example...] for details. Figure 12 As shown, during the write operation cycle, clock signals DQS_T and DQS_C are present. The data to be written is written normally, and a masking operation is performed. For details, please refer to the documentation on... Figure 10 The timing diagram is described. Due to the reasons described above, during the write operation cycle, the masking operation consumes the effective levels of DQS_T and DQS_C. This results in the remaining data in the data to be written not being loaded into the page buffer. At this time, DQS_T and DQS_C have also stopped. Therefore, based on the post-write operation provided by the embodiment of the present invention, post-write clock information is generated, and a set of write clock signals (e.g., Figure 12 The second write clock signal wt_x2 and the third write clock signal wt_x4 shown in Figure 1201 are used to write the remaining data into the page buffer. The specific writing process is the same as described above. Figure 10 The operations are similar to those in the sequence diagram, differing only in the timing of data extraction, and will not be elaborated upon here. Figure 12 In this context, HX represents the remaining data.

[0158] It should be noted that during the post-write operation, due to the characteristics of the serial-to-parallel conversion circuit and other reasons, the remaining parallel data after conversion contains redundant data. To eliminate the influence of redundant data, a masking operation is required. The masking data at this time is different from the masking data in the aforementioned write operation. Based on experience, there are at most 8 bytes of remaining data in the data to be written. Therefore, the correspondence between the masking data of the post-write operation and the loading timing signal ADD<2:0> is shown in Table 2 below.

[0159] Table 2

[0160]

[0161] In other words, for example, Figure 12 In the context of ADD<2:0> being 000, the mask data for subsequent write operations is 00h.

[0162] Figure 13 The embodiments of the present invention are based on Figure 11This is another timing diagram based on the aforementioned timing diagram, where the remaining data is written to the page buffer. The write operation and subsequent write operation here are basically similar to the processes described above, and will not be repeated here. It should be noted that, unlike the previous diagrams, here, 1301 represents a set of write clock signals; ADD<2:0> is 100, and the corresponding mask data is 0fh.

[0163] This invention provides a data transmission device. After a certain write operation cycle ends, when there is no clock signal required for data loading, a post-write generator is set to generate a post-write clock signal. With this post-write clock signal, the remaining data that could not be loaded into the page buffer after the end of a certain write operation cycle is loaded into the page buffer, thus ensuring the accuracy and integrity of the data written into the page buffer.

[0164] Based on the same inventive concept, such as Figure 14 As shown in the figure, this embodiment of the invention also provides a data transmission method, which may include:

[0165] S1401: Generates a write clock signal after a certain write operation cycle ends;

[0166] S1402: Load the remaining data in the data to be written into the page cache of the memory based on the post-write clock signal;

[0167] The data to be written is the data expected to be loaded into the page cache during the write operation cycle; the remaining data is the data that failed to be loaded into the page cache during the write operation cycle.

[0168] In some embodiments, the step of generating and writing the clock signal includes:

[0169] After a certain write operation cycle ends, a valid write-after enable signal is generated; the write-after clock signal is generated based on the valid write-after enable signal.

[0170] The effective write enable signal is generated based on the command latch clock signal and the write enable signal; the command latch clock signal is generated by the command latch enable signal and the command / address sampling clock signal; the command / address sampling clock signal is a clock signal that samples the commands and addresses on the data bus of the memory.

[0171] In some embodiments, generating the post-write clock signal based on the valid post-write enable signal includes:

[0172] A trigger instruction is generated based on the effective post-write enable signal;

[0173] The post-write clock signal is generated based on the trigger instruction;

[0174] When the post-write clock signal meets the requirements, an exit signal is generated;

[0175] When a failed write enable signal is obtained based on an exit signal, the generation of the write clock signal is stopped; wherein the write clock signal satisfies the requirement that the number of rising or falling edges of the write clock signal reaches a preset threshold.

[0176] In some embodiments, the method further includes:

[0177] The remaining serial data is converted into first parallel data with a first timing alignment with respect to a set of write clock signals; the set of write clock signals is generated by the subsequent write clock signals.

[0178] The first parallel data is transferred to the page cache.

[0179] In some embodiments, the method further includes:

[0180] Generate parallel mask data with a second timing alignment with respect to the set of write clock signals; send the mask data to the write data converter;

[0181] When the first parallel data contains redundant data, the mask data is received; the mask data is used to hide the redundant data in the first parallel data to obtain valid data;

[0182] Send the valid data to the page cache.

[0183] In some embodiments, the method further includes:

[0184] Loading timing signals are generated based on address signals;

[0185] The set of write clock signals with timing patterns is generated based on the post-write clock signal and the load timing signal; the timing pattern is used to control the loading time of loading the first parallel data and the mask data into the write data converter.

[0186] It should be noted that the data transmission method described here is the same invention as the aforementioned data transmission device. All the terms used here have been explained in detail in the aforementioned data transmission device and are equally applicable here, so they will not be repeated here.

[0187] This invention also provides a memory, including: a memory cell array;

[0188] and peripheral circuitry configured to write data to the memory cell array in parallel; wherein,

[0189] The peripheral circuit includes: the data transmission device described in any of the preceding claims.

[0190] In some embodiments, the memory cell array is a three-dimensional NAND flash memory array.

[0191] It should be noted that, as Figure 15 As shown, memory 150 may include a memory cell array 1501 and peripheral circuitry 1502 coupled to the memory cell array 1501. The memory cell array 1501 may be a NAND flash memory cell array, wherein storage transistors 1506 are provided in the form of an array of NAND memory cell strings 1508, each NAND memory cell string 1508 extending vertically above a substrate (not shown). In some embodiments, each NAND memory cell string 1508 includes a plurality of storage transistors 1506 (also simply referred to as storage cells) that are series-coupled and vertically stacked. Each storage transistor 1506 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the storage transistor 1506. Each storage transistor 1506 may be a floating-gate type storage transistor including a floating-gate transistor, or a charge-trapping type storage transistor including a charge-trapping transistor.

[0192] Each of the storage transistors 1506 discussed above can be a single-level storage cell or a multi-level storage cell. A single-level storage cell can be a single-level cell (SLC) capable of storing 1 bit; a multi-level storage cell can be a multi-level cell (MLC) capable of storing 2 bits, a three-level cell (TLC) capable of storing 3 bits, a four-level cell (QLC) capable of storing 4 bits, a five-level cell (PLC) capable of storing 5 bits, and so on.

[0193] Return to Figure 15As shown, each NAND cell string 1508 may include a source select gate (SSG) 1510 at its source end and a drain select gate (DSG) 1512 at its drain end. SSG 1510 and DSG 1512 can be configured to activate a selected NAND cell string 1508 (column of the array) during read and program operations. In some embodiments, the sources of NAND cell strings 1508 in the same block 1504 are coupled via the same source line (SL) 1514 (e.g., common SL). In other words, according to some embodiments, all NAND cell strings 1508 in the same block 1504 have an array common source (ACS). According to some embodiments, the DSG 1512 of each NAND cell string 1508 is coupled to a corresponding bit line 1516, from which data can be read or written via an output bus (not shown). In some implementations, each NAND memory cell string 1508 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having DSG 1512) or a deselection voltage (e.g., 0V) to the corresponding DSG 1512 via one or more DSG lines 1513 and / or by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having SSG 1510) or a deselection voltage (e.g., 0V) to the corresponding SSG 1510 via one or more SSG lines 1514.

[0194] For example Figure 15As shown, the NAND memory cell string 1508 can be organized into multiple blocks 1504, each of which can have a common source line 1514 (e.g., coupled to ground). In some implementations, each block 1504 is the basic data unit for an erase operation, i.e., all memory transistors 1506 on the same block 1504 are erased simultaneously. To erase the memory transistors 1506 in a selected block 1504, an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)) can be biased and coupled to the source line 1514 of the selected block 1504 and the unselected blocks 1504 on the same plane as the selected block 1504. It should be understood that in some examples, the erase operation can be performed at the half-block level, at the quarter-block level, or at any suitable number of blocks or any suitable fraction of blocks. The memory transistors 1506 of the NAND memory cell string 1508 in the same layer can be coupled via word lines 1518, and all memory cells coupled to a word line 1518 form a memory cell layer. Word line 1518 selects which row of storage transistor 1506 is affected by read and program operations. In some embodiments, each word line 1518 is coupled to a page 1520 of storage transistor 1506, which is the basic data unit used for programming operations. The size of a page 1520, in bits, can be related to the number of NAND memory cell strings 1508 coupled by word lines 1518 in a block 1504. Each word line 1518 may include multiple control gates (gate electrodes) at each storage transistor 1506 in the corresponding page 1520 and gate lines coupled to the control gates.

[0195] Return to reference Figure 15 The peripheral circuitry 1502 can be coupled to the memory cell array 1501 via bit line 1516, word line 1518, source line 1514, SSG line 1514, and DSG line 1513. The peripheral circuitry 1502 can include any suitable analog, digital, and mixed-signal circuitry for facilitating the operation of the memory cell array 1501 by applying voltage and / or current signals to each target memory transistor 1506 via bit line 1516, word line 1518, source line 1514, SSG line 1514, and DSG line 1513, and by sensing voltage and / or current signals from each target memory transistor 1506. The peripheral circuitry 1502 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 16Some exemplary peripheral circuitry is shown. Peripheral circuitry 1502 includes a page buffer / sensor amplifier 1604, a column decoder / bit line driver 1606, a row decoder / word line driver 1608, a voltage generator 1610, a control logic unit 1612, a register 1614, an interface 1616, and a data bus 1618. It should be understood that in some examples, additional peripheral circuitry may be included. Figure 16 Additional peripheral circuitry not shown.

[0196] Page buffer / sensor amplifier 1604 can be configured to read data from memory cell array 1501 and program (write) data to memory cell array 1501 according to control signals from control logic unit 1612. In one example, page buffer / sensor amplifier 1604 can store a page of programming data (write data) to be programmed into a page 1520 of memory cell array 1501. In another example, page buffer / sensor amplifier 1604 can perform a programming verification operation to ensure that data has been correctly programmed into memory transistor 1506 coupled to selected word line 1518. In yet another example, page buffer / sensor amplifier 1604 can also sense a low-power signal from bit line 1516 representing a data bit stored in memory transistor 1506 and amplify a small voltage swing to a recognizable logic level during read operations. Column decoder / bit line driver 1606 can be configured to be controlled by control logic unit 1612 and select one or more NAND memory cell strings 1508 by applying a bit line voltage generated from voltage generator 1610.

[0197] The line decoder / word line driver 1608 can be configured to be controlled by the control logic unit 1612 and to select / deselect block 1504 of the memory cell array 1501 and select / deselect word line 1518 of block 1504. The line decoder / word line driver 1608 can also be configured to drive word line 1518 using word line voltages generated from the voltage generator 1610. In some embodiments, the line decoder / word line driver 1608 can also select / deselect and drive SSG line 1514 and DSG line 1513. As described in detail below, the line decoder / word line driver 1608 is configured to perform an erase operation on memory transistor 1506 coupled to one or more selected word lines 1518. The voltage generator 1610 can be configured to be controlled by the control logic unit 1612 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 1501.

[0198] Control logic unit 1612 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. Register 1614 can be coupled to control logic unit 1612 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Interface 1616 can be coupled to control logic unit 1612 and acts as a control buffer to buffer control commands received from a host (not shown) and relay them to control logic unit 1612, and to buffer status information received from control logic unit 1612 and relay it to the host. Interface 1616 can also be coupled to column decoder / bitline driver 1606 via data bus 1618 and acts as a data I / O interface and data buffer to buffer data and relay it to or from memory cell array 1501. It should be noted that embodiments of the present invention provide a data transmission device included in the peripheral circuitry of the memory and located at the aforementioned interface 1616.

[0199] It should be noted that the memory mentioned here includes the aforementioned data transmission device and method. Therefore, the two have the same technical features. The terms appearing in this memory have been explained in detail in the aforementioned data transmission device and method, and are equally applicable here, and will not be repeated here.

[0200] like Figure 17 As shown, an embodiment of the present invention also provides a storage system 170, including: one or more of the aforementioned memory 150; and a memory controller 1701 coupled to the memory; the memory controller is configured to control various operations of the memory.

[0201] It should be noted that the memory can be any type of memory, such as NAND flash memory (e.g., 3D NAND flash memory). A memory controller is coupled to the memory and configured to control the memory; for example, the memory controller can manage data stored in the memory and communicate with a host coupled to the storage system. In some embodiments, the memory controller is designed to operate in low duty cycle environments, such as in Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in low duty cycle electronic devices such as personal calculators, digital cameras, and mobile phones. In some embodiments, the memory controller is designed to operate in high duty cycle environments, such as SSDs or embedded multimedia cards (eMMC), where SSDs or eMMCs serve as data storage for mobile devices in high duty cycle environments such as smartphones, tablets, and laptops, as well as enterprise memory cell arrays. The memory controller can be configured to control operations of the memory, such as read, erase, and program operations. The memory controller can also be configured to manage various functions related to data stored or to be stored in the memory, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some implementations, the memory controller is also configured to process error correction codes (ECC) regarding data read from or written to the memory. The memory controller may also perform any other suitable functions, such as formatting the memory. The memory controller may communicate with external devices (e.g., coupled hosts) according to specific communication protocols. For example, the memory controller may communicate with external devices via at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Firewire, etc.

[0202] The memory controller and one or more memories can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the storage system can be implemented and packaged into different types of end electronic products. In one example, the memory controller and a single memory can be integrated into a memory card. Memory cards can include PC cards (PCMCIA, Personal Computer Memory Card International Association), CF cards, Smart Media (SM) cards, memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), UFS, etc. The memory card may also include a memory card connector that couples the memory card to a host. In another example, the memory controller and multiple memories can be integrated into an SSD. The SSD may also include an SSD connector that couples the SSD to a host (e.g., a coupled host). In some implementations, the storage capacity and / or operating speed of the SSD is greater than that of the memory card.

[0203] It should be noted that the storage system provided in this embodiment of the invention belongs to the same inventive concept as the memory, data transmission device and method provided above. The terms used here have been described in detail above and will not be repeated here.

[0204] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention.

Claims

1. A data transmission device, characterized in that, include: A write-after generator is configured to generate a write-after clock signal after a certain write operation cycle has ended. The write-after clock signal is used to enable the remaining data in the data to be written to be loaded into the page cache in the memory. The masking operation is performed during the write cycle; the data to be written is the data that is expected to be loaded into the page cache during the write operation cycle; the remaining data is the data that was not loaded into the page cache during the write operation cycle.

2. The data transmission device according to claim 1, characterized in that, The post-write generator includes a post-write enable component and a post-write clock generation component, wherein, The post-write enable component is used to generate a valid post-write enable signal after a certain write operation cycle ends, and send the valid post-write enable signal to the post-write clock generation component. The post-write clock generation component is used to receive the valid post-write enable signal, turn on based on the valid post-write enable signal, and generate the post-write clock signal.

3. The data transmission device according to claim 2, characterized in that, The post-write enable component is further configured to generate a failed post-write enable signal when the post-write clock signal meets the requirements, and send the failed post-write enable signal to the post-write clock generation component. The post-write clock generation component is also configured to receive the failed post-write enable signal, and based on the failed post-write enable signal, to close and stop generating the post-write clock signal.

4. The data transmission device according to claim 3, characterized in that, The post-write enable component includes a D-type flip-flop; the D-type flip-flop includes a first input terminal, a second input terminal, and an output terminal, wherein; The first input terminal is used to input a command latch clock signal; the command latch clock signal is generated by a command latch enable signal and a command / address sampling clock signal. The command / address sampling clock signal is a clock signal that samples the commands and addresses on the data bus of the memory; The second input terminal is used to input the write enable signal; The output terminal is used to generate a valid post-write enable signal under the action of the command latch clock signal and the write enable signal, and send the valid post-write enable signal to the post-write clock generation component.

5. The data transmission device according to claim 3, characterized in that, The post-write clock generation component includes: a state machine and a post-write clock oscillator, wherein; The state machine is used to receive the valid write-back enable signal, generate a trigger command based on the valid write-back enable signal, and send the trigger command to the write-back clock oscillator. The post-write clock oscillator is used to start generating the post-write clock signal when the trigger instruction sent by the state machine is received.

6. The data transmission device according to claim 5, characterized in that, The state machine is further configured to generate an exit signal when the post-write clock signal meets the requirements; send the exit signal to the post-write enable component; the exit signal is configured to cause the post-write enable component to generate a failed post-write enable signal; the failed post-write enable signal causes the state machine to shut down. The post-write clock oscillator is further configured to: stop generating the post-write clock signal after the state machine is turned off; wherein the post-write clock signal satisfies the requirement that the number of rising or falling edges of the post-write clock signal reaches a preset threshold.

7. The data transmission device according to claim 1, characterized in that, The data transmission device further includes: a data serial-to-parallel converter and a write data converter; wherein... The data serial-to-parallel converter is used to convert the serial remaining data into first parallel data having a first timing alignment with a first set of write clock signals; and to send the first parallel data to the write data converter; the set of write clock signals is generated by the subsequent write clock signal. The write data converter, coupled to the data serial-to-parallel converter, is used to receive the first parallel data and transmit the first parallel data to the page buffer.

8. The data transmission device according to claim 7, characterized in that, The data transmission device further includes a mask serial-to-parallel converter for generating parallel mask data having a second timing alignment with respect to the set of write clock signals; and sending the mask data to the write data converter. The write data converter, coupled to the mask serial-to-parallel converter, is further configured to: receive the mask data when the first parallel data generated by the data serial-to-parallel converter contains redundant data; use the mask data to hide the redundant data in the first parallel data to obtain valid data; and send the valid data to the page buffer.

9. The data transmission device according to claim 8, characterized in that, The data transmission device further includes a clock driver, which is coupled to the data serial-to-parallel converter and the mask serial-to-parallel converter, and is used to generate the set of write clock signals based on the post-write clock signal.

10. The data transmission apparatus according to claim 9, characterized in that, The data transmission device further includes: an address generator, used to generate loading timing signals based on address signals; The clock driver is further configured to: generate the set of write clock signals with timing patterns based on the post-write clock signal and the load timing signal; the timing pattern is used to control the loading time of loading the first parallel data and the mask data into the write data converter.

11. The data transmission apparatus according to claim 8, characterized in that, The data serial-to-parallel converter has the same structure as the mask serial-to-parallel converter, with matched transistor delays and matched line delays.

12. A data transmission method, characterized in that, The method includes: After a certain write operation cycle ends, a write clock signal is generated; The remaining data in the data to be written is loaded into the page cache of the memory based on the post-write clock signal; The masking operation is performed during the write operation cycle; the data to be written is the data expected to be loaded into the page cache during the write operation cycle; and the remaining data is the data that failed to be loaded into the page cache during the write operation cycle.

13. The data transmission method according to claim 12, characterized in that, The generated and written clock signal includes: After a certain write operation cycle ends, a valid write-after enable signal is generated; the write-after clock signal is generated based on the valid write-after enable signal. The effective write enable signal is generated based on the command latch clock signal and the write enable signal; the command latch clock signal is generated by the command latch enable signal and the command / address sampling clock signal; the command / address sampling clock signal is a clock signal that samples the commands and addresses on the data bus of the memory.

14. The data transmission method according to claim 13, characterized in that, The generation of the post-write clock signal based on the valid post-write enable signal includes: A trigger instruction is generated based on the effective post-write enable signal; The post-write clock signal is generated based on the trigger instruction; When the post-write clock signal meets the requirements, an exit signal is generated; When a failed write enable signal is obtained based on an exit signal, the generation of the write clock signal is stopped; wherein the write clock signal satisfies the requirement that the number of rising or falling edges of the write clock signal reaches a preset threshold.

15. The data transmission method according to claim 13, characterized in that, The method further includes: The remaining serial data is converted into first parallel data with a first timing alignment with respect to a set of write clock signals; the set of write clock signals is generated by the subsequent write clock signals. The first parallel data is transferred to the page cache.

16. The data transmission method according to claim 15, characterized in that, The method further includes: Generate parallel mask data with a second timing alignment with respect to the set of write clock signals; send the mask data to the write data converter; When the first parallel data contains redundant data, the mask data is received; the mask data is used to hide the redundant data in the first parallel data to obtain valid data; Send the valid data to the page cache.

17. The data transmission method according to claim 16, characterized in that, The method further includes: Load timing signals are generated based on address signals; The set of write clock signals with timing patterns is generated based on the post-write clock signal and the load timing signal; the timing pattern is used to control the loading time of loading the first parallel data and the mask data into the write data converter.

18. A memory, characterized in that, include: Memory cell array; and peripheral circuitry configured to write data to the memory cell array in parallel; wherein, The peripheral circuit includes: the data transmission device according to any one of claims 1 to 11.

19. A storage system, characterized in that, include: One or more of the memories described in claim 18; and a memory controller coupled to the memory; The memory controller is configured to control various operations of the memory.

20. The storage system according to claim 19, characterized in that, The storage system is a solid-state drive or a memory card.

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