Memory device and programming operations thereof

Abstract

A memory device includes an array of memory cells in columns and rows, word lines coupled to the rows, respectively, bit lines coupled to the columns, respectively, and a peripheral circuit coupled to the array of memory cells through the bit lines and the word lines and configured to program a selected row based on a current data page. The peripheral circuit includes page buffer circuits coupled to the bit lines, respectively. Each page buffer circuit includes a cache storage cell, a multipurpose storage cell, and N-1 data storage cells. The cache storage cell is configured to sequentially receive N bits of the current data page and N bits of a next data page and sequentially store one of the N bits of the current data page and each of the N bits of the next data page. The multipurpose storage cell is configured to sequentially store non-data page information and one of the N bits of the next data page. The data storage cells are each configured to store a respective one of the N bits of the current data page.

Description

[0001] This application is a divisional application with application date of June 2, 2021, application number 202180001813.0, and invention name as memory device and programming operation thereof. Background Art

[0002] The present disclosure relates to memory devices and methods of operating the same.

[0003] Flash memory is a low-cost, high-density, non-volatile solid-state storage medium that can be electrically erased and reprogrammed. Flash memory includes NOR flash memory and NAND flash memory. Various operations can be performed on flash memory, such as reading, programming (writing), and erasing, to change the threshold voltage of each memory cell to a desired level. For NAND flash memory, erase operations can be performed at the block level, and programming or reading operations can be performed at the page level. Summary of the Invention

[0004] In one aspect, a memory device includes an array of memory cells in a plurality of columns and a plurality of rows, a plurality of word lines respectively coupled to the rows of memory cells, a plurality of bit lines respectively coupled to the columns of memory cells, and a peripheral circuit coupled to the memory cell array through the bit lines and word lines and configured to program selected rows of memory cells based on a current data page. Each memory cell is configured to be 2 N One of the levels stores a fragment of N-bit data, where N is an integer greater than 1. The peripheral circuit includes a plurality of page buffer circuits coupled to the bit lines, respectively. Each page buffer circuit includes a cache memory cell, a multi-purpose memory cell, and N-1 data storage cells. The cache memory cell is configured to sequentially receive N bits of the current data page and N bits of the next data page when programming a selected row based on the current data page, and sequentially store one of the N bits of the current data page and each of the N bits of the next data page. The multi-purpose memory cell is configured to sequentially store non-data page information and one of the N bits of the next data page when programming a selected row based on the current data page. The data storage cells are each configured to store a corresponding one of the N bits of the current data page when programming a selected row based on the current data page.

[0005] In another aspect, a system includes a memory device configured to store data and a memory controller coupled to the memory device and configured to control the memory device. The memory device includes an array of memory cells in a plurality of columns and a plurality of rows, a plurality of word lines respectively coupled to the rows of memory cells, a plurality of bit lines respectively coupled to the columns of memory cells, and a peripheral circuit coupled to the memory cell array through the bit lines and word lines and configured to program selected rows of memory cells based on a current data page. Each memory cell is configured to be 2 N One of the levels stores a fragment of N-bit data, where N is an integer greater than 1. The peripheral circuit includes a plurality of page buffer circuits coupled to the bit lines, respectively. Each page buffer circuit includes a cache memory cell, a multi-purpose memory cell, and N-1 data storage cells. The cache memory cell is configured to sequentially receive N bits of the current data page and N bits of the next data page when programming a selected row based on the current data page, and sequentially store one of the N bits of the current data page and each of the N bits of the next data page. The multi-purpose memory cell is configured to sequentially store non-data page information and one of the N bits of the next data page when programming a selected row based on the current data page. The data storage cells are each configured to store a corresponding one of the N bits of the current data page when programming a selected row based on the current data page.

[0006] In yet another aspect, a method for operating a memory device is provided. The memory device includes a plurality of rows of memory cells. N bits of a current data page are received. One of the N bits of the current data page is stored in a cache memory cell, and a corresponding one of the N bits of the current data page is stored in each of N-1 data storage cells. Non-data page information is stored in a multi-purpose memory cell. Selected rows of the rows of memory cells are programmed based on the current data page. The selected rows are sequentially verified until 2 N The Nth last level among the N levels. Receive the N bits of the next data page. N After verifying the corresponding one of the last N levels of the 2 levels, each of the N bits of the next data page is stored in the cache memory cell in sequence. N After the last of the N levels is verified, one of the N bits of the next data page is stored in the multi-purpose memory cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate aspects of the disclosure and, together with the description, further serve to explain the principles of the disclosure and to enable one skilled in the relevant art to make and use the disclosure.

[0008] Figure 1 A block diagram of a system having a memory device according to some aspects of the present disclosure is shown.

[0009] Figure 2A A diagram illustrating a memory card having a memory device according to some aspects of the present disclosure is shown.

[0010] Figure 2B A diagram illustrating a solid-state drive (SSD) having a memory device according to some aspects of the present disclosure is shown.

[0011] Figure 3 A schematic diagram of a memory device including peripheral circuits according to some aspects of the present disclosure is shown.

[0012] Figure 4 A side view of a cross section of a memory cell array including NAND memory strings is shown according to some aspects of the present disclosure.

[0013] Figure 5 A block diagram of a memory device including a memory cell array and peripheral circuits according to some aspects of the present disclosure is shown.

[0014] Figure 6 Threshold voltage distributions of memory cells in a programming operation according to some aspects of the present disclosure are shown.

[0015] Figure 7 A detailed block diagram of a page buffer in a programming operation according to some aspects of the present disclosure is shown.

[0016] Figure 8 A timing diagram illustrating multi-cache data loading in a program operation according to aspects of the present disclosure is shown.

[0017] Figure 9A and Figure 9B A waveform of a word line voltage applied to a selected word line in a program operation according to some aspects of the present disclosure is shown.

[0018] Figure 10 A schematic diagram illustrating multi-cache data loading in a program operation according to aspects of the present disclosure is shown.

[0019] Figure 11 A flowchart of a method for operating a memory device according to some aspects of the present disclosure is shown.

[0020] The present disclosure will be described with reference to the accompanying drawings. DETAILED DESCRIPTION

[0021] Although specific configurations and arrangements have been discussed, it should be understood that this is done for illustrative purposes only. Thus, other configurations and arrangements may be used without departing from the scope of this disclosure. In addition, the present disclosure may also be used in various other applications. The functions and structural features described in this disclosure may be combined, adjusted, and modified with one another, and in a manner not specifically depicted in the accompanying drawings, such combinations, adjustments, and modifications are within the scope of this disclosure.

[0022] Generally, terms can be understood, at least in part, from their use in context. For example, depending at least in part on the context, as used herein, the term "one or more" can be used to describe any feature, structure, or characteristic in a singular sense, or can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a" or "the" can also be understood to convey singular usage or to convey plural usage, depending at least in part on the context. Additionally, the term "based on" can be understood as not necessarily intended to convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described, again depending at least in part on the context.

[0023] Memory devices (e.g., NAND flash memory devices) can store more than a single bit of information in each memory cell in multiple levels (also known as states) in order to increase storage capacity and reduce per-bit cost. In a programming operation, data can be programmed (written) into xLC (e.g., multi-level cell (MLC), triple-level cell (TLC), quad-level cell (QLC), etc.). For some memory devices with xLC, a cache programming command can be used to allow data to be inserted into another data page while programming of one data page is currently being performed. In order to reduce the size of the peripheral circuits, memory devices typically include only one cache latch for each bit line (BL), which allows only one bit of data from the next data page (e.g., referred to as the lower page "LP") to be inserted while programming with the current data page. After the current data page program is executed, the other bits of data in the next data page (e.g., the middle page "MP" and the upper page "UP") need to be inserted. As a result, an additional window is required between programming adjacent data pages to load part of the next data page, which affects the performance of sequential programming operations, for example, increasing programming speed.

[0024] Although some multi-cache data loading schemes can reduce or even avoid the data loading window by utilizing not only cache latches but also some data latches to cache more bits of data from the next data page, those schemes still require at least the same number of data latches as the number of data bits in each xLC (e.g., three data latches for TLC and four data latches for QLC) as well as dedicated cache latches. As the total number of data latches and cache latches increases proportionally with the number of bit lines, the size of the page buffer with latches becomes a major burden in shrinking the size of memory devices as the memory cell density increases.

[0025] To address one or more of the above problems, the present disclosure introduces a solution that reuses some latches in the page buffer for multi-cache data loading in programming operations. As a result, the number of latches required for each bit line can be further reduced to, for example, 5 latches, while still reducing or even avoiding the data loading window for sequential programming operations. The cache latch can be used not only to cache the next data page, but also to store part of the current data page, thereby replacing one of the dedicated data latches. In some embodiments, in order to avoid the data loading window, another latch in the page buffer (e.g., a latch for storing bit line voltage level information) is also reused to cache part of the next data page at a certain stage while programming with the current data page. Therefore, sequential programming performance can be improved (e.g., with a fast programming speed) without any circuit size cost.

[0026] Figure 1 A block diagram of a system 100 having a memory device according to some aspects of the present disclosure is shown. The system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 1 As shown in , system 100 may include a host 108 and a memory system 102, wherein the memory system 102 has one or more memory devices 104 and a memory controller 106. The host 108 may be a processor (e.g., a central processing unit (CPU)) or a system on a chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host 108 may be configured to send data to the memory device 104 or receive data from the memory device 104.

[0027] The memory device 104 may be any memory device disclosed in the present disclosure. As disclosed in detail below, the memory device 104 (e.g., a NAND flash memory device) may be configured to store xLCs based on a data page having N bits of data for each xLC (i.e., configured to store data in 2 N The programming operation is performed on a memory cell in which one of the levels stores a fragment of N bits of data, where N is an integer greater than 1. Consistent with the scope of the present disclosure, a multi-cache data loading scheme can be implemented with a page buffer (e.g., having a 5-latch configuration) of the memory device 104, the page buffer having one cache storage cell (e.g., a cache latch) and multi-purpose storage cells (e.g., 3 bit line (BL) latches), the one cache storage cell being configured to sequentially store one bit of the current data page and each bit of the next data page, and the multi-purpose storage cells being configured to sequentially store non-data page information and one bit of the next data page.

[0028] According to some embodiments, the memory controller 106 is coupled to the memory device 104 and the host 108 and is configured to control the memory device 104. The memory controller 106 can manage data stored in the memory device 104 and communicate with the host 108. In some embodiments, the memory controller 106 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 106 is designed to operate in a high duty cycle environment, such as an SSD or an embedded multimedia card (eMMC), which is used as data storage for mobile devices such as smartphones, tablet computers, laptop computers, etc., as well as enterprise storage arrays. The memory controller 106 can be configured to control the operations of the memory device 104 (e.g., read, erase, and program operations). The memory controller 106 may also be configured to manage various functions regarding data stored or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, and the like. In some embodiments, the memory controller 106 may also be configured to process error correction code (ECC) for data read from or written to the memory device 104. The memory controller 106 may also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 may communicate with an external device (e.g., the host 108) according to a particular communication protocol. For example, the memory controller 106 may communicate with the external device using at least one of various interface protocols, such as a USB protocol, a MultiMediaCard (MMC) protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial ATA protocol, a Parallel ATA protocol, a Small Computer Small Form Factor Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a Firewire protocol, and the like.

[0029] The memory controller 106 and the one or more memory devices 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., Universal Flash Storage (UFS) package or eMMC package). That is, the memory system 102 can be implemented and packaged into different types of terminal electronic products. Figure 2AIn one example shown in FIG, the memory controller 106 and the single memory device 104 may be integrated into a memory card 202. The memory card 202 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 may also include a memory card that connects the memory card 202 to a host (e.g., Figure 1 The memory card connector 204 is coupled to the host 108 in FIG. Figure 2B In another example shown in , the memory controller 106 and the plurality of memory devices 104 may be integrated into an SSD 206. The SSD 206 may also include a processor that interfaces the SSD 206 with a host (e.g., Figure 1 In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0030] Figure 3 Schematic circuit diagram of a memory device 300 including peripheral circuits according to some aspects of the present disclosure is shown. The memory device 300 may be Figure 1 3. An example of a memory device 104 in FIG. Memory device 300 may include a memory cell array 301 and peripheral circuitry 302 coupled to memory cell array 301. Memory cell array 301 may be a NAND flash memory cell array in which memory cells 306 are provided in an array of NAND memory strings 308, each NAND memory string 308 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 may hold a continuous analog value, such as a voltage or charge, that depends on the number of electrons trapped within the region of the memory cell 306. Each memory cell 306 may be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor.

[0031] In some embodiments, each memory cell 306 is a single-level cell (SLC) that has two possible memory states (levels) and can therefore store one bit of data. For example, a first memory state "0" can correspond to a first threshold voltage range, and a second memory state "1" can correspond to a second threshold voltage range. In some embodiments, each memory cell 306 is an xLC that can store more than a single bit of data in more than four memory states (levels). For example, an xLC can store two bits per cell (MLC), three bits per cell (TLC), or four bits per cell (QLC). Each xLC can be programmed to take a range of possible nominal storage values ​​(i.e., 2 out of N bits of data). N In one example, an MLC can be programmed to take one of three possible programming levels from an erased state by writing one of three possible nominal storage values ​​to the cell. A fourth nominal storage value can be used for the erased state.

[0032] like Figure 3 As shown in FIG, each NAND memory string 308 may also include a source select gate (SSG) transistor 310 at its source terminal and a drain select gate (DSG) transistor 312 at its drain terminal. The SSG transistor 310 and the DSG transistor 312 may be configured to activate a selected NAND memory string 308 (column of the array) during read and program operations. In some embodiments, the sources of the NAND memory strings 308 in the same block 304 are coupled via the same source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all NAND memory strings 308 in the same block 304 have an array common source (ACS). According to some embodiments, the drain of each NAND memory string 308 is coupled to a corresponding bit line 316, from which data can be read or written via an output bus (not shown). In some embodiments, each NAND memory string 308 is configured to be selected or deselected by applying a select voltage or a deselect voltage to the gate of a corresponding DSG transistor 312 via one or more DSG lines 313 and / or by applying a select voltage or a deselect voltage to the gate of a corresponding SSG transistor 310 via one or more SSG lines 315.

[0033] like Figure 3As shown in FIG, a NAND memory string 308 can be organized into a plurality of blocks 304, each of which can have a common source line 314 (e.g., coupled to ground). In some embodiments, each block 304 is a basic unit of data for erase operations, i.e., all memory cells 306 on the same block 304 are erased simultaneously. To erase memory cells 306 in a selected block 304, the source lines 314 coupled to the selected block 304 and to unselected blocks 304 in the same plane as the selected block 304 can be biased with an erase voltage (Vers) (e.g., a high positive bias voltage (e.g., 20V or higher)). Memory cells 306 of adjacent NAND memory strings 308 can be coupled via word lines 318, which select which row of memory cells 306 is affected by read and program operations. In some embodiments, each word line 318 is coupled to a page 320 of memory cells 306, which is a basic unit of data for read and program operations. The size of a page 320 in bits may be related to the number of NAND memory strings 308 coupled by word lines 318 in a block 304. Each word line 318 may include a plurality of control gates (gate electrodes) at each memory cell 306 in a corresponding page 320 and a gate line coupling the control gates.

[0034] like Figure 3 , the memory cell array 301 may include an array of memory cells 306 in a plurality of rows and a plurality of columns in each block 304. In some embodiments, a row of memory cells 306 corresponds to one or more pages 320, and a column of memory cells corresponds to one NAND memory string 308. Rows of memory cells 306 may be coupled to word lines 318, respectively, and columns of memory cells 306 may be coupled to bit lines 316, respectively. Peripheral circuitry 302 may be coupled to the memory cell array 301 via bit lines 316 and word lines 318.

[0035] Figure 4 1 shows a side view of a cross section of a memory cell array 301 including NAND memory strings 308 according to some aspects of the present disclosure. Figure 4 As shown in FIG, NAND memory strings 308 can extend vertically through a memory stack layer 404 above a substrate 402. The substrate 402 can include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0036] The memory stack 404 may include interleaved gate conductive layers 406 and gate-to-gate dielectric layers 408. The number of pairs of gate conductive layers 406 and gate-to-gate dielectric layers 408 in the memory stack 404 may determine the number of memory cells 306 in the memory cell array 301. The gate conductive layers 406 may include a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate conductive layer 406 includes a metal layer, such as a tungsten layer. In some embodiments, each gate conductive layer 406 includes a doped polysilicon layer. Each gate conductive layer 406 may include a control gate surrounding the memory cell 306, a gate of the DSG transistor 312, or a gate of the SSG transistor 310, and may extend laterally at the top of the memory stack layer 404 as a DSG line 313, extend laterally at the bottom of the memory stack layer 404 as an SSG line 315, or extend laterally between the DSG line 313 and the SSG line 315 as a word line 318.

[0037] like Figure 4 As shown in FIG, NAND memory string 308 includes a channel structure 412 extending vertically through memory stack layer 404. In some embodiments, channel structure 412 includes a channel hole filled with one or more semiconductor materials (e.g., as semiconductor channel 420) and one or more dielectric materials (e.g., as memory film 418). In some embodiments, semiconductor channel 420 includes silicon, such as polysilicon. In some embodiments, memory film 418 is a composite dielectric layer including a tunneling layer 426, a storage layer 424 (also referred to as a "charge trapping / storage layer"), and a barrier layer 422. Channel structure 412 can have a cylindrical shape (e.g., a pillar shape). According to some embodiments, semiconductor channel 420, tunneling layer 426, storage layer 424, and barrier layer 422 are arranged radially in this order from the center of the pillar toward the outer surface of the pillar. Tunneling layer 426 can include silicon oxide, silicon oxynitride, or any combination thereof. Storage layer 424 can include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer 422 may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film 418 may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0038] According to some embodiments, Figure 4As shown in FIG, a well 414 (e.g., a P-well and / or an N-well) is formed in the substrate 402, and the source terminal of the NAND memory string 308 is in contact with the well 414. For example, a source line 314 can be coupled to the well 414 to apply an erase voltage to the well 414 (i.e., the source of the NAND memory string 308) during an erase operation. In some embodiments, the NAND memory string 308 also includes a channel plug 416 at the drain terminal of the NAND memory string 308. It should be understood that although Figure 4 Not shown, but additional features of the memory cell array 301 may be formed, including but not limited to gate line gaps / source contacts, local contacts, interconnect layers, etc.

[0039] Return Reference Figure 3 , the peripheral circuit 302 may be coupled to the memory cell array 301 through the bit lines 316, word lines 318, source lines 314, SSG lines 315, and DSG lines 313. The peripheral circuit 302 may include any suitable analog, digital, and mixed signal circuits for facilitating the operation of the memory cell array 301 by applying a voltage signal and / or a current signal to each target memory cell 306 and sensing a voltage signal and / or a current signal from each selected memory cell 306 via the bit lines 316, word lines 318, source lines 314, SSG lines 315, and DSG lines 313. The peripheral circuit 302 may include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 5 Some exemplary peripheral circuits are shown, and the peripheral circuit 302 includes a page buffer / sense amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, a control logic 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, the peripheral circuit 302 may also include Figure 5 Additional peripheral circuits not shown.

[0040] The page buffer / sense amplifier 504 can be configured to read data from the memory cell array 301 and program (write) data to the memory cell array 301 according to a control signal from the control logic 512. In one example, the page buffer / sense amplifier 504 can store a page of programming data (write data, also referred to herein as a "data page") to be programmed into one page 320 of the memory cell array 301. In another example, the page buffer / sense amplifier 504 can verify the programmed selected memory cell 306 in each program / verify loop (cycle) of the programming operation to ensure that the data has been correctly programmed into the memory cell 306 coupled to the selected word line 318. In yet another example, the page buffer / sense amplifier 504 can also sense a low-power signal from the bit line 316 representing a data bit stored in the memory cell 306 and amplify the small voltage swing to a recognizable logic level in a read operation. As described in detail below and consistent with the scope of the present disclosure, in a programming operation, the page buffer / sense amplifier 504 may include a plurality of page buffer circuits respectively coupled to the bit lines 316, and each page buffer circuit includes a set of storage cells (e.g., latches) for temporarily storing a segment of N-bit data received from the data bus 518 (e.g., in the form of Gray code) and providing the segment of N-bit data to a corresponding selected memory cell 306 via the corresponding bit line 316 in a programming operation using a multi-cache loading scheme.

[0041] The column decoder / bit line driver 506 can be configured to be controlled by control logic 512 and select one or more NAND memory strings 308 by applying a bit line voltage generated from a voltage generator 510. The row decoder / word line driver 508 can be configured to be controlled by control logic 512 and select / deselect a block 304 of the memory cell array 301 and select / deselect a word line 318 of the block 304. The row decoder / word line driver 508 can also be configured to drive the word line 318 using the word line voltage generated from the voltage generator 510. In some embodiments, the row decoder / word line driver 508 can also select / deselect and drive the SSG line 315 and the DSG line 313. The voltage generator 510 can be configured to be controlled by control logic 512 and generate word line voltages (e.g., read voltage, program voltage, channel pass voltage, local voltage, verify voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 301.

[0042] The control logic 512 may be coupled to each of the peripheral circuits described above and configured to control the operation of each peripheral circuit. The register 514 may be coupled to the control logic 512 and include a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit. The interface 516 may be coupled to the control logic 512 and act as a control buffer to buffer data received from a memory controller (e.g., Figure 1 106) and / or a host (e.g., Figure 1 The interface 516 receives control commands from the memory cell array 301 and relays the control commands to the control logic 512, and buffers status information received from the control logic 512 and relays the status information to the memory controller and / or the host. The interface 516 can also be coupled to the column decoder / bit line driver 506 via the data bus 518 and acts as a data input / output (I / O) interface and a data buffer to buffer data and relay data to or from the memory cell array 301.

[0043] Figure 6 1 shows an exemplary threshold voltage distribution of memory cells in a programming operation according to some aspects of the present disclosure. As described above, each memory cell 306 can be configured to have a 2 N Each level stores a fragment of N bits of data, where N is an integer greater than 1 (e.g., N=2 for MLC, N=3 for TLC, N=4 for QLC, etc.). Each level may correspond to 2 bits of memory cell 306. N One of the threshold voltage (Vth) ranges. Taking TLC (where N=3) as an example, Figure 6 As shown in FIG, the memory cell 306 can be programmed to one of eight levels, including one level for an erased state and seven levels for a programmed state. Each level can correspond to a corresponding threshold voltage (Vth) range of the memory cell 306. For example, the lowest threshold voltage range ( Figure 6 The level of the leftmost threshold voltage distribution in the ) can be regarded as level 0, corresponding to the second lowest threshold voltage range ( Figure 6 The level of the second threshold voltage distribution from the left in the ) can be regarded as level 1, and so on, until the level corresponding to the highest threshold voltage range ( Figure 6 Level 7 of the rightmost threshold voltage distribution).

[0044] On the other hand, each level may correspond to 2 of the N-bit data to be stored in the selected memory cell 306. N In some embodiments, 2 of the N-bit data NThe segments can be represented by Gray code (in the form of Gray code). Gray code (also known as reflected binary code (RBC) or reflected binary) is an ordering of the binary number system so that two consecutive values ​​differ in only one bit (binary digit). For example, Table 1 below shows the representation of Figure 6 An example of a binary code that uses a one-to-one mapping between eight levels (LV 0 to LV 7) and eight segments of 3-bit data is shown in Table 1. As shown in Table 1, each segment of 3-bit data can be composed of three binary values ​​(b1, b2, and b3). In one example, level 1 can correspond to a segment of 3-bit data with a value of 000. In another example, level 7 can correspond to another segment of 3-bit data with a value of 101.

[0045] Table 1

[0046] LV 0 1 2 3 4 5 6 7 b1 1 0 1 0 0 1 0 1 b2 1 0 0 1 0 1 1 0 b3 1 0 0 0 1 0 1 1

[0047] Also refer to Figure 5 In a programming operation, a data page having N pages (also referred to as a portion) of N-bit data can be used to program the memory cells 306 of a selected row coupled to a select word line 318. In other words, the peripheral circuit 302 can be configured to program the memory cells 306 of the selected row based on the current data page (having N pages of N-bit data). In some embodiments, user data is transmitted to the page buffer / sense amplifier 504 via the data bus 518, and the page buffer / sense amplifier 504 is configured to convert the user data into each data page to be programmed into the memory cells 306 of the corresponding row based on a preset Gray code. According to some embodiments, based on the preset Gray code that defines the mapping of each programming level to a corresponding segment of the N-bit data, the control logic 512 is configured to send a control signal (e.g., an enable signal) to the page buffer / sense amplifier 504 to allow the page buffer / sense amplifier 504 to generate sequential data pages for the sequential programming operation. Depending on the number N (e.g., whether the memory cells 306 are MLC, TLC, QLC, etc.), each data page can include N pages (also referred to as portions), which can be separately loaded into the page buffer / sense amplifier 504 and moved around within the page buffer / sense amplifier 504, as described in detail below. During an ongoing programming operation, the current data page can be temporarily stored in the page buffer / sense amplifier 504, and the page buffer / sense amplifier 504 can be configured to provide a corresponding segment of N bits of data to each memory cell 306 coupled to the select word line 318 via a corresponding bit line 316.

[0048] For example, Figure 7A detailed block diagram of the page buffer / sense amplifier 504 during a programming operation is shown, according to some aspects of the present disclosure. In some embodiments, the page buffer / sense amplifier 504 includes a plurality of page buffer circuits 702, each coupled to a corresponding one of the bit lines 316. In other words, each page buffer circuit 702 can be coupled to a corresponding column of memory cells 306 (e.g., a NAND memory string 308) via a corresponding bit line 316 and is configured to temporarily store a fragment of N bits of data (i.e., N bits of a current data page) for programming a corresponding selected memory cell 306 (coupled to a selected word line 318 and a corresponding bit line 316) during a programming operation. All page buffer circuits 702 together can temporarily store N pages of the entire current data page, which are used to program a selected row of memory cells 306 (e.g., a page 320 of memory cells 306) coupled to the selected word line 318 during a programming operation. As described above, in some embodiments, the page buffer circuit 702 is further configured to pre-process a corresponding portion of the user data received from the data bus 518 and convert it into corresponding N bits of the current data page based on a preset Gray code. For example, for TLC (where N=3), each page buffer circuit 702 can be configured to temporarily store a corresponding one of eight groups of three bits of the current data page as shown in Table 1 above, where the eight groups of three bits correspond to eight levels, respectively.

[0049] In order to reduce or even avoid data loading windows between adjacent data pages for programming memory cells 306 in different rows during a sequential programming operation, each page buffer circuit 702 can also be configured to cache part or all of a fragment of N bits of data (i.e., the N bits of the next data page) for programming the next selected memory cell 306 in the next programming operation while programming the currently selected memory cell 306 in the ongoing programming operation. All page buffer circuits 702 together can follow a multi-cache data loading scheme to cache one or more of the N pages of the entire next data page for programming the memory cells 306 of the next selected row coupled to the next selected word line 318 (e.g., the memory cells 306 of the next page 320) in the current programming operation.

[0050] For example, Figure 8 FIG. 1 shows a timing diagram of multi-cache data loading in a programming operation according to some aspects of the present disclosure. Figure 8As shown in FIG, still taking TLC (where N=3) as an example, the three pages (PG 0, PG 1, and PG 2) of the first data page can be loaded and stored in the page buffer / sense amplifier 504 and used to program the memory cells 306 of the first row. During the time period (tPROG 1) for programming the memory cells 306 of the first row, the three pages (PG 3, PG 4, and PG 5) of the second data page can also be loaded and cached in the page buffer / sense amplifier 504. In other words, the second data page can be ready before the end of tPROG 1, so that programming of the memory cells 306 of the second row can start immediately after programming of the memory cells 306 of the first row without any window for loading the second data page. Similarly, during the time period (tPROG 2) for programming the memory cells 306 of row 2, the three pages (PG 6, PG 7, and PG 8) of the third data page can also be loaded and cached in the page buffer / sense amplifier 504. As a result, the performance of sequential programming operations can be improved by the multi-cache data loading scheme.

[0051] Return Reference Figure 7 To implement a multi-cache data loading scheme for sequential programming operations, each page buffer circuit 702 may include a set of data storage cells 706 and a cache storage cell (DC) 708. During a currently ongoing programming operation to program memory cells 306 of a selected row based on a current data page, each data storage cell 706 may be configured to store a corresponding one of the N bits of the current data page, and the cache storage cell 708 may be configured to sequentially store each of the N bits of the next data page (i.e., cache the N bits of the next data page). According to some embodiments, to reduce the number of storage cells and the size of the page buffer circuit 702, the number of cache storage cells 708 is limited to one, i.e., a single cache storage cell 708 that can only store a single data bit at a time. Thus, the single cache storage cell 708 is configured to sequentially store each of the N bits of the next data page at different time periods during the current programming operation, as described in detail below. Furthermore, due to the limited number (e.g., one) of the cache memory cells 708, one or more of the data storage cells 706 can be configured to also store one of the N bits of the next data page during the current programming operation when the stored bit of the current data page is no longer needed (i.e., also perform a cache function). For example, at least one data storage cell 706 can be configured to sequentially store a corresponding one of the N bits of the current data page and a corresponding one of the N bits of the next data page.

[0052] The existing multi-cache data loading scheme requires that the number of data storage cells in each page buffer circuit 702 is at least the same as the number of bits of the fragment of data used to program the corresponding selected memory cell 306, that is, N data storage cells, because a single cache memory cell is dedicated to caching the data of the next data page. Unlike the existing scheme and consistent with the scope of the present disclosure, Figure 7 The single cache memory cell 708 in the page buffer circuit 702 in the embodiment can also be configured to store one of the N bits of the current data page. That is, according to some embodiments, the cache memory cell 708 is configured to sequentially store one of the N bits of the current data page and each of the N bits of the next data page. In other words, the cache memory cell 708 can act as both a data storage cell and a cache memory cell in a time-division manner to replace one of the data storage cells 706 in each page buffer circuit 702. In some embodiments, as Figure 7 As shown in , the number of data storage units 706 in each page buffer circuit 702 thus becomes N-1 (D1-Dn-1). Therefore, compared with the existing multi-cache data loading scheme, the total number of data storage units 706 and cache storage units 708 can be reduced from N+1 to N.

[0053] It should be understood that the total of N data storage units 706 and cache storage units 708 can reduce the data loading window by caching N-1 bits of the N bits of the next data page when programming the memory cells of the currently selected row based on the current data page, but it may not be possible to completely avoid the data loading window. Therefore, consistent with the scope of the present disclosure, in some embodiments, another storage unit in each page buffer circuit 702 for storing non-data page information is configured to sequentially store the non-data page information and one of the N bits of the next data page, thereby enabling all N-1 bits of the next data page to be cached during the current programming operation to avoid the data loading window. That is, the page buffer circuit 702 can include multi-purpose storage units that can store non-data page information and cache data of the next data page in a time-division manner.

[0054] Each page buffer circuit 702 may include a plurality of storage cells for storing non-data page information (ie, any information other than the data bits in the data page). Figure 7As shown in , in some embodiments, the page buffer circuit 702 includes a sense / program memory cell (DS) 712 configured to store information indicating whether the current operation performed by the page buffer / sense amplifier 504 is a read operation or a program operation, and a 3BL memory cell (DL) 710 configured to store bias information of a corresponding bit line 316 coupled to the page buffer circuit 702. In some embodiments, the 3BL memory cell 710 is a multi-purpose memory cell that acts as both a 3BL memory cell and a cache memory cell in a time-division manner. Figure 7 As shown in , each page buffer circuit 702 may further include a bias circuit 704 that is coupled to a corresponding bit line 316 and configured to apply a bit line voltage to a corresponding selected memory cell 306 coupled to the corresponding bit line 316 during a programming operation. Depending on whether the corresponding selected memory cell 306 passes verification at a corresponding level according to N-bit data for programming the selected memory cell 306, for example, a high voltage level and a low voltage level may be used as the bit line voltage to bias the corresponding bit line 316. In some embodiments, to optimize the threshold voltage distribution (e.g., as Figure 6 ), for example, to expand the read margin between adjacent levels and reduce the width of each level, a medium voltage level may also be used to bias the bit line voltage. That is, three voltage levels (e.g., high, medium, and low) may be applied to the corresponding bit line 316 (referred to herein as 3BL). In some embodiments, the voltage level applied to the corresponding bit line 316 (e.g., 3BL bias) is non-data page information stored in the 3BL memory cell 710.

[0055] It should be understood that although the 3BL memory cell 710 is described herein as an example of a multi-purpose memory cell for implementing the multi-cache data loading scheme disclosed in the present disclosure, any suitable non-data page memory cell (e.g., sense / program memory cell 712) or Figure 7Any other non-data page memory cells not shown can, in some examples, be used as multi-purpose memory cells without adding additional memory cells to page buffer circuit 702. It should also be understood that each memory cell in page buffer circuit 702 (including each data storage cell 706, cache memory cell 708, 3BL memory cell 710, and sense / program memory cell 712) can be any circuit with two stable states for storing a single data bit, such as a latch or flip-flop. In one example, each of data storage cell 706, cache memory cell 708, 3BL memory cell 710, and sense / program memory cell 712 includes a latch. In some embodiments, page buffer circuit 702 has a five-latch configuration including one cache latch, two data latches, one 3BL latch, and one sense / program latch. In some embodiments, cache memory cell 708 includes one cache latch, data storage cell 706 includes two data latches, and the multi-purpose memory cell includes one 3BL latch.

[0056] To perform a programming operation, in addition to the page buffer / sense amplifier 504 providing a corresponding segment of N-bit data to each selected memory cell 306, the row decoder / word line driver 508 can be configured to apply a program voltage and a verify voltage to the selected word line 318 coupled to the memory cells 306 of the selected row in one or more program / verify cycles to raise the threshold voltage of each selected memory cell 306 to a desired level (into a desired threshold voltage range) based on the corresponding segment of N-bit data. For example, Figure 9A and Figure 9B FIG. 2 shows a waveform of a word line voltage applied to a selected word line in a programming operation. Figure 9A As shown in , a programming operation includes one or more program / verify cycles 902. Figure 9B As shown in FIG, in each program / verify cycle 902, the row decoder / word line driver 508 may be configured to apply a program voltage (Vpgm) on the selected word line 318 and sequentially apply two voltage levels with incremental changes. N -1 verification voltage (Vvf). 2 N -1 verification voltage can correspond to 2 N levels (eg, 2 in addition to an erase level) N -1 programming level) of 2 N -1 level. That is, the peripheral circuit 302 can be configured to N 2 of the levels N-1 level sequentially verifies the memory cells 306 of the selected row. Based on the corresponding N bits of data to be stored in the selected memory cell 306 (i.e., the N bits of the current data page stored in the corresponding page buffer circuit 702), each selected memory cell 306 can be programmed to 2 N Still taking TLC (where N=3) as an example, by applying 7 verification voltages (each verification voltage corresponds to one of the 7 programming levels), the selected memory cell 306 can be programmed to 8 levels in sequence (for example, Figure 6 ) of a level.

[0057] The following describes in detail a multi-cache data loading scheme implemented based on a memory device disclosed herein (eg, memory device 300 including page buffer circuit 702). For example, Figure 11 A flow chart of a method 1100 for operating a memory device according to some aspects of the present disclosure is shown. The memory device can be any suitable memory device disclosed herein, for example, the memory device 300. The method 1100 can be implemented by the peripheral circuit 302 (e.g., the row decoder / word line driver 508 and the page buffer / sense amplifier 504). It should be understood that the operations shown in the method 1100 are not exhaustive, and other operations can be performed before, after, or between any of the operations shown. In addition, some operations can be performed simultaneously or in parallel. Figure 11 The different orders shown in .

[0058] refer to Figure 11 , method 1100 begins at operation 1102, in which N bits of a current data page are received when programming memory cells of a selected row. Figure 7 As shown in , the control logic 512 can send control signals to the cache memory cells 708 of each page buffer circuit 702 to control the cache memory cells 708 to sequentially receive data pages each having N bits of data in a sequential programming operation. In a current programming operation, that is, when programming the memory cells 306 of a selected row coupled to the selected word line 318 based on the current data page, the cache memory cells 708 can be configured to sequentially receive the N bits of the current data page and the N bits of the next data page immediately following the current data page.

[0059] Method 1100 proceeds to operation 1104, as shown in FIG. Figure 11 As shown in , in operation 1104, one of the N bits of the current data page is stored in one cache memory cell, and a corresponding one of the N bits of the current data page is stored in each of the N-1 data storage cells. Figure 7As shown in FIG, the control logic 512 can send control signals to a single cache memory cell 708 and a group of N-1 data storage cells 706 of each page buffer circuit 702 to control the single cache memory cell 708 and the N-1 data storage cells 706 to respectively store N bits of the current data page. In other words, the cache memory cell 708 can also first act as a data storage cell, so that a total of N data storage cells can respectively store N bits of the current data page. In one example, the cache memory cell 708 can be configured to be stored in a 2 N Before verifying the Nth last level of the 2 levels, one of the N bits of the current data page is stored, and at least one data storage unit 706 can be configured to store the N bits of the current data page at 2 N Before the last (N-1)th level among the N levels is verified, a corresponding one of the N bits of the current data page is stored.

[0060] Method 1100 proceeds to operation 1106, as shown in FIG. Figure 11 As shown in FIG, in operation 1106, non-data page information is stored in a multi-purpose memory cell. The non-data page information may include a voltage level applied to a corresponding bit line. For example, Figure 7 As shown in FIG, the control logic 512 can send a control signal to a single 3BL memory cell 710 to control the single 3BL memory cell 710 to store bit line bias information, for example, one of three voltage levels applied to the corresponding bit line 316. In one example, the 3BL memory cell 710 can be configured to store a bit line bias information at 2 N Before the last level of the three levels is verified, non-data page information is stored.

[0061] Method 1100 proceeds to operation 1108, as Figure 11 As shown in FIG, in operation 1108, the memory cells of the selected row are programmed based on the current data page. Figure 5 and Figure 9B As shown in , control logic 512 may send control signals to row decoder / word line driver 508 to apply a programming voltage (Vpgm) to a select word line 318 coupled to the memory cells 306 of a selected row.

[0062] Method 1100 proceeds to operation 1110, as shown in FIG. Figure 11 As shown in FIG, in operation 1110, the selected rows are verified in sequence until 2 N The Nth to last level among the levels. For example, Figure 5 and Figure 9B As shown in FIG, the control logic 512 can send a control signal to the page buffer / sense amplifier 504 to sequentially apply 2 on the selected word line 318.N -1 verification voltage (Vvf). 2 N -1 verification voltage can correspond to 2 N 2 of the levels N For example, for TLC (where N=3), 7 verification voltages may correspond to 7 segments of 3-bit data, each segment corresponding to a corresponding level in 7 programming levels (LV 1 to LV 7) out of 8 levels, as shown in Table 1 above.

[0063] Still taking TLC (where N=3) as an example, Figure 10 As shown in FIG, before verification is performed at the third-to-last level (i.e., level 6 (LV5)) among the eight levels, a cache memory cell (DC) may store one of the three bits of the current data page (current UP), a first data storage cell (D1) may store the corresponding bit of the current data page (current LP), and a second data storage cell (D2) may store the corresponding bit of the current data page (current MP). Verification at each of levels 1 (LV0) through 5 (LV4) may follow a Gray code as shown in Table 1 based on the three bits of data stored in DC, D1, and D2, e.g., 111 for LV0 and 001 for LV4, where b1, b2, and b3 may correspond to LP, MP, and UP, respectively. Other memory cells may store non-data page information. For example, a 3BL memory cell (DL) may store the voltage level applied to the corresponding bit line (3BL bias), and a sense / program memory cell (DS) may store programming or read operation information (e.g., indicating whether the current operation is a programming operation).

[0064] Method 1100 proceeds to operation 1112, as shown in FIG. Figure 11 As shown in FIG, in operation 1112, N bits of the next data page are received. For example, during the current programming operation, the page buffer circuit 702 can begin caching the next data page for the next programming operation by sequentially receiving the N bits of the next data page at the cache memory cell 708. The method 1100 proceeds to operation 1114, as shown in FIG. Figure 11 As shown in FIG, in operation 1114, at 2 N After verifying the corresponding one of the last N levels of the 2 levels, each of the N bits of the next data page is sequentially stored in the cache memory unit. N Before verifying the (N-1)th level from the last of the N levels, a corresponding one of the N bits of the current data page is stored in one of the data storage units. NAfter the last (N-1)th level among the N levels is verified, a corresponding one of the N bits of the next data page is stored in the data storage unit.

[0065] For example, Figure 10 As shown in FIG, after verifying at a corresponding one of the last three levels (LV 5, LV 6, and LV 7), DC can sequentially store each of the three bits of the next data page (next LP, next MP, and next UP). Before verifying at the second-to-last level (i.e., the seventh level (LV6)), D1 can store the corresponding bit of the current data page (current LP), and then after verifying at the second-to-last level (i.e., LV6), store the corresponding bit of the next data page (next LP). When verifying at each level, D2 can store the corresponding bit of the current data page (current MP).

[0066] After verification is performed at the third-to-last level among the eight levels (i.e., the sixth level (LV5) has been verified), the binary code of Table 1 can be updated as shown in Table 2 below, wherein all data bits in LV0 to LV5 can be updated to 1 because they are no longer needed in the current programming operation. As shown in Table 2, since b3 in the last two levels LV6 and LV7 is always 1, the DC used to store the bit of b3 (current UP) can no longer be needed, and thus the DC can be reused to cache the data bits of the next data page. For example, Figure 10 As shown in , after verification at LV5, DC can be released to replace the current UP with the first bit of the next data page (next LP).

[0067] Table 2

[0068] LV 0 1 2 3 4 5 6 7 b1 1 1 1 1 1 1 0 1 b2 1 1 1 1 1 1 1 0 b3 1 1 1 1 1 1 1 1

[0069] After verifying at the second-to-last level among the 8 levels (i.e., the 7th level (LV6) has been verified), the binary code of Table 2 can be updated as shown in Table 3 below, wherein all data bits in LV6 can be updated to 1 because they are no longer needed in the current programming operation. As shown in Table 3, since only b2 is 0 in the last level LV7, D1 used to store the bit of b1 (current LP) can no longer be needed, and thus D1 can be reused to cache the data bits of the next data page. For example, Figure 10As shown in , after verification at LV 6, D1 can be released to replace the current LP with the first bit of the next data page (next LP), so that DC can be released again to cache the second bit of the next data page (next MP). That is, after verification at LV 6, the next LP can be transferred from DC to D1, and the next MP can be cached in DC.

[0070] Table 3

[0071] LV 0 1 2 3 4 5 6 7 b1 1 1 1 1 1 1 1 1 b2 1 1 1 1 1 1 1 0 b3 1 1 1 1 1 1 1 1

[0072] Method 1100 proceeds to operation 1116, as shown in FIG. Figure 11 As shown in FIG, in operation 1116, at 2 N After the last level of the N levels is verified, one of the N bits of the next data page is stored in the multi-purpose storage unit. Figure 10 As shown in , before verifying at the last level (i.e., the 8th level (LV7)), the DL can store a 3BL bias, and then store one bit of the next data page (next MP) after verifying at LV7. In some embodiments, after verifying at the last level, the 3BL bias may no longer be needed, for example, because the read margin and distribution width of the last level may be less critical than other levels. Therefore, the DL can be released to replace the 3BL bias with the second bit of the next data page (next MP), so that the DC can be released again to cache the third bit of the next data page (next UP). That is, after verifying at LV 7, the next MP can be passed from the DC to the DL, and the next UP can be cached in the DC.

[0073] Method 1100 proceeds to operation 1118, as Figure 11 As shown in FIG, in operation 1118, a next selected row of rows of memory cells is programmed based on the next page of data. Figure 10 As shown in , since all 3 bits of the next data page (next LP, next MP, and next UP) can be cached after verification at LV 7, the next data page can become ready during the current programming operation. Therefore, at the end of the current programming operation, the next programming operation based on the next data page can be seamlessly triggered without a data loading window. For example, during the transition, the next MP can be transferred from DL to D2, so that the 3 bits of the next data page (next LP, next MP, and next UP) can be stored in D1, D2, and DC, respectively, for the next programming operation, and the DL can be released again to also store the 3BL bias for the next programming operation.

[0074] According to one aspect of the present disclosure, a memory device includes an array of memory cells in a plurality of columns and a plurality of rows, a plurality of word lines respectively coupled to the rows of memory cells, a plurality of bit lines respectively coupled to the columns of memory cells, and a peripheral circuit coupled to the memory cell array through the bit lines and word lines and configured to program a selected row of the rows of memory cells based on a current data page. Each memory cell is configured to be 2 N One of the levels stores a fragment of N-bit data, where N is an integer greater than 1. The peripheral circuit includes a plurality of page buffer circuits coupled to the bit lines, respectively. Each page buffer circuit includes a cache memory cell, a multi-purpose memory cell, and N-1 data storage cells. The cache memory cell is configured to sequentially receive N bits of the current data page and N bits of the next data page when programming a selected row based on the current data page, and sequentially store one of the N bits of the current data page and each of the N bits of the next data page. The multi-purpose memory cell is configured to sequentially store non-data page information and one of the N bits of the next data page when programming a selected row based on the current data page. The data storage cells are each configured to store a corresponding one of the N bits of the current data page when programming a selected row based on the current data page.

[0075] In some embodiments, the non-data page information includes voltage levels applied to corresponding bit lines.

[0076] In some embodiments, to program a selected row based on the current data page, the peripheral circuit is configured to sequentially N 2 of the levels N -1 level verification to select the row.

[0077] In some embodiments, the cache memory unit is configured to N Before verifying the Nth last level in the N levels, one of the N bits of the current data page is stored and the N After verifying a corresponding one of the last N levels of the N levels, each of the N bits of the next data page is stored in sequence.

[0078] In some embodiments, the multi-purpose storage unit is configured to N Before the last level of the 2 levels is verified, the non-data page information is stored and N After the last of the N levels is verified, one of the N bits of the next data page is stored.

[0079] In some embodiments, at least one of the data storage units is configured to sequentially store a corresponding one of the N bits of a current data page and a corresponding one of the N bits of a next data page.

[0080] In some embodiments, one of at least one of the data storage units is configured to store data in 2 N Before verifying the last (N-1)th level in the N levels, store the corresponding one of the N bits of the current data page and N After the last (N-1)th level among the N levels is verified, a corresponding one of the N bits of the next data page is stored.

[0081] In some embodiments, the peripheral circuit further includes a word line driver coupled to the word lines and configured to apply a program voltage to a selected word line among the word lines coupled to the selected row, and sequentially apply a 2-bit program voltage to the selected word line. N -1 verification voltage, 2 N -1 verification voltage corresponds to 2 N 2 of the levels N -1 level.

[0082] In some embodiments, each of the cache memory unit, the multipurpose memory unit, and the data memory unit includes a latch.

[0083] In some embodiments, the peripheral circuitry is further configured to program a next selected row of the rows of memory cells based on a next page of data after programming the selected row based on the current page of data.

[0084] In some implementations, the page buffer circuit includes one cache latch, two data latches, one 3-bit line latch, and one sense / program latch.

[0085] In some embodiments, one cache memory unit includes one cache latch, N-1 data memory units include two data latches, and the multi-purpose memory unit includes 3 bit line latches.

[0086] According to another aspect of the present disclosure, a system includes a memory device configured to store data and a memory controller coupled to the memory device and configured to control the memory device. The memory device includes an array of memory cells in a plurality of columns and a plurality of rows, a plurality of word lines respectively coupled to the rows of memory cells, a plurality of bit lines respectively coupled to the columns of memory cells, and a peripheral circuit coupled to the memory cell array through the bit lines and word lines and configured to program selected rows of memory cells based on a current data page. Each memory cell is configured to store data in 2 NOne of the levels stores a fragment of N-bit data, where N is an integer greater than 1. The peripheral circuit includes a plurality of page buffer circuits coupled to the bit lines, respectively. Each page buffer circuit includes a cache memory cell, a multi-purpose memory cell, and N-1 data storage cells. The cache memory cell is configured to sequentially receive N bits of the current data page and N bits of the next data page when programming a selected row based on the current data page, and sequentially store one of the N bits of the current data page and each of the N bits of the next data page. The multi-purpose memory cell is configured to sequentially store non-data page information and one of the N bits of the next data page when programming a selected row based on the current data page. The data storage cells are each configured to store a corresponding one of the N bits of the current data page when programming a selected row based on the current data page.

[0087] In some embodiments, the non-data page information includes voltage levels applied to corresponding bit lines.

[0088] In some embodiments, to program a selected row based on the current data page, the peripheral circuit is configured to sequentially N 2 of the levels N -1 level verification to select the row.

[0089] In some embodiments, the cache memory unit is configured to N Before verifying the Nth last level in the N levels, one of the N bits of the current data page is stored and the N After verifying a corresponding one of the last N levels of the N levels, each of the N bits of the next data page is stored in sequence.

[0090] In some embodiments, the multi-purpose storage unit is configured to N Before the last level of the 2 levels is verified, the non-data page information is stored and N After the last of the N levels is verified, one of the N bits of the next data page is stored.

[0091] In some embodiments, at least one of the data storage units is configured to sequentially store a corresponding one of the N bits of a current data page and a corresponding one of the N bits of a next data page.

[0092] In some embodiments, at least one of the data storage units is configured to store data in 2 N Before verifying the last (N-1)th level in the N levels, store the corresponding one of the N bits of the current data page and NAfter the last (N-1)th level among the N levels is verified, a corresponding one of the N bits of the next data page is stored.

[0093] In some embodiments, the peripheral circuit further includes a word line driver coupled to the word lines and configured to apply a program voltage to a selected word line among the word lines coupled to the selected row, and sequentially apply a 2-bit program voltage to the selected word line. N -1 verification voltage, 2 N -1 verification voltage corresponds to 2 N 2 of the levels N -1 level.

[0094] In some embodiments, each of the cache memory unit, the multipurpose memory unit, and the data memory unit includes a latch.

[0095] In some embodiments, the peripheral circuitry is further configured to program a next selected row of the rows of memory cells based on a next page of data after programming the selected row based on the current page of data.

[0096] According to another aspect of the present disclosure, a method for operating a memory device is provided. The memory device includes a plurality of rows of memory cells. N bits of a current data page are received. One of the N bits of the current data page is stored in a cache memory cell, and a corresponding one of the N bits of the current data page is stored in each of N-1 data storage cells. Non-data page information is stored in a multi-purpose memory cell. A selected row of the rows of memory cells is programmed based on the current data page. The selected rows are sequentially verified until 2 N The Nth last level among the N levels. Receive the N bits of the next data page. N After verifying the corresponding one of the last N levels of the 2 levels, each of the N bits of the next data page is sequentially stored in the cache memory cell. N After the last of the N levels is verified, one of the N bits of the next data page is stored in the multi-purpose memory cell.

[0097] In some embodiments, at 2 N Before verifying the (N-1)th level from the last of the N levels, a corresponding one of the N bits of the current data page is stored in one of the data storage units. N After the last (N-1)th level among the N levels is verified, a corresponding one of the N bits of the next data page is stored in the data storage unit.

[0098] In some implementations, a next selected row of rows of memory cells is programmed based on the next page of data.

[0099] In some embodiments, the non-data page information includes voltage levels applied to corresponding bit lines.

[0100] In some embodiments, each of the cache memory unit, the multipurpose memory unit, and the data memory unit includes a latch.

[0101] The foregoing description of specific embodiments can be readily modified and / or adapted to various applications. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein.

[0102] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A memory device, characterized in that: include: an array of memory cells in a plurality of columns and a plurality of rows; a plurality of word lines, the plurality of word lines being respectively coupled to the rows of the memory cells; a plurality of bit lines, the plurality of bit lines being respectively coupled to the columns of the memory cells; as well as a peripheral circuit coupled to the memory cell array through the bit lines and the word lines and configured to program a selected row of the rows of the memory cells based on a current data page, the data page comprising 2 N N bits of data corresponding to a level; the peripheral circuit includes a plurality of page buffer circuits respectively coupled to the bit lines, each page buffer circuit including: a cache memory unit configured to sequentially receive and store each bit of a next data page when programming the selected row based on the current data page; a multi-purpose memory cell configured to store one bit of the next data page when programming the selected row based on the current data page; and N-1 data storage units, each data storage unit being configured to store a corresponding bit in the current data page when programming the selected row based on the current data page.

2. The memory device according to claim 1, wherein The multi-purpose memory unit is further configured to store non-data page information before storing the next data page.

3. The memory device according to claim 2, wherein: The non-data page information includes voltage levels applied to corresponding bit lines.

4. The memory device according to claim 2, wherein: The selected row is programmed based on the current data page, and the peripheral circuit is configured to program the selected row based on 2 N -1 level verifies the selected row.

5. The memory device according to claim 4, wherein: The cache storage unit is configured to: In the selected row by based on the 2 N Before performing verification on the Nth to last level of the N levels, storing one of the N bits of the current data page; and In the selected row by based on the 2 N After verification is performed on the Nth to last level of the N levels, each of the N bits of the next data page is stored in sequence.

6. The memory device according to claim 4, wherein: The multi-purpose storage unit is configured to: In the selected row by based on the 2 N Before the verification is performed at the second-to-last level in the first level, the non-data page information is stored; and In the selected row by based on the 2 N After verification is performed on the second-to-last level among the N levels, one of the N bits of the next data page is stored.

7. The memory device according to any one of claims 4 to 6, wherein: At least one of the data storage units is configured to store a corresponding one of the N bits of the current data page or a corresponding one of the N bits of the next data page.

8. The memory device according to claim 7, wherein: One of the at least one of the data storage units is configured to: In the selected row by based on the 2 N Before verifying the N-th (N-1)th level among the N levels, storing the corresponding one of the N bits of the current data page; and In the selected row by based on the 2 N After verification is performed on the last (N-1)th level among the N levels, the corresponding one of the N bits of the next data page is stored.

9. The memory device according to any one of claims 4 to 6, wherein: The peripheral circuit further includes a word line driver coupled to the word line and configured to: applying a program voltage to a selected word line among the word lines coupled to the selected row; and Regarding the 2 N For each of the levels, a verification voltage is applied to the selected word line, the verification voltage corresponding to each of the levels.

10. The memory device according to any one of claims 1 to 6, wherein: Each of the cache memory unit, the multi-purpose memory unit, and the data memory unit includes a latch.

11. The memory device according to any one of claims 1 to 6, wherein: The peripheral circuitry is further configured to program a next selected row of the rows of memory cells based on the next page of data after programming the selected row based on the current page of data.

12. The memory device according to any one of claims 1 to 6, wherein: The page buffer circuit includes a cache latch, two data latches, a 3-bit line latch, and a sense / program latch.

13. The memory device according to claim 12, wherein: The cache storage unit includes the one cache latch, the N-1 data storage units include the two data latches, and the multi-purpose storage unit includes the one 3-bit line latch.

14. A system for storing data, characterized in that include: A memory device configured to store data, the memory device comprising: an array of memory cells in a plurality of columns and a plurality of rows; a plurality of word lines, the plurality of word lines being respectively coupled to the rows of the memory cells; a plurality of bit lines, the plurality of bit lines being respectively coupled to the columns of the memory cells; and a peripheral circuit coupled to the memory cell array through the bit lines and the word lines and configured to program a selected row of the rows of the memory cells based on a current data page, the data page comprising 2 N The peripheral circuit includes a plurality of page buffer circuits respectively coupled to the bit lines, each of the page buffer circuits including: a cache memory unit configured to sequentially receive and store each bit of a next data page when programming the selected row based on the current data page; a multi-purpose memory cell configured to store one bit of the next data page when programming the selected row based on the current data page; and N-1 data storage units, each data storage unit configured to store a corresponding bit of the current data page when programming the selected row based on the current data page; and A memory controller is coupled to the memory device and configured to control the memory device.

15. The system according to claim 14, wherein: The multi-purpose memory unit is further configured to store non-data page information before storing the next data page.

16. The system according to claim 15, wherein: The non-data page information includes voltage levels applied to corresponding bit lines.

17. The system according to claim 15, wherein: The selected row is programmed based on the current data page, and the peripheral circuit is configured to program the selected row based on 2 N -1 level verifies the selected row.

18. The system according to claim 17, wherein: The cache storage unit is configured to: In the selected row by based on the 2 N Before performing verification on the Nth to last level of the N levels, storing one of the N bits of the current data page; and In the selected row by based on the 2 N After verification is performed on the Nth to last level of the N levels, each of the N bits of the next data page is stored in sequence.

19. The system according to claim 17, wherein: The multi-purpose storage unit is configured to: In the selected row by based on the 2 N Before the verification is performed at the second-to-last level in the first level, the non-data page information is stored; and In the selected row by based on the 2 N After verification is performed on the second-to-last level among the N levels, one of the N bits of the next data page is stored.

20. The system according to any one of claims 17 to 19, wherein: At least one of the data storage units is configured to store a corresponding one of the N bits of the current data page or a corresponding one of the N bits of the next data page.

21. The system according to claim 20, wherein: One of the at least one of the data storage units is configured to: In the selected row by based on the 2 N Before verifying the N-th (N-1)th level among the N levels, storing the corresponding one of the N bits of the current data page; and In the selected row by based on the 2 N After verification is performed on the last (N-1)th level among the N levels, the corresponding one of the N bits of the next data page is stored.

22. The system according to any one of claims 17 to 19, wherein: The peripheral circuit further includes a word line driver coupled to the word line and configured to: applying a program voltage to a selected word line among the word lines coupled to the selected row; and Regarding the 2 N For each of the levels, a verification voltage is applied to the selected word line, the verification voltage corresponding to each of the levels.

23. The system according to any one of claims 14 to 19, wherein: Each of the cache memory unit, the multi-purpose memory unit, and the data memory unit includes a latch.

24. The system according to any one of claims 14 to 19, wherein: The peripheral circuitry is further configured to program a next selected row of the rows of memory cells based on the next page of data after programming the selected row based on the current page of data.

25. A method for operating a memory device comprising a plurality of rows of memory cells, characterized in that The method comprises: Receive N bits of the current data page; storing the N bits of the current data page in a cache memory cell and each of N-1 data memory cells, respectively; programming memory cells in a selected row based on the current data page; In the selected row by 2-based N After verifying the Nth to last level of the N levels, each of the N bits of the next data page is sequentially stored in the cache storage unit; and In the selected row by based on the 2 N After verification of the Nth to last level among the N levels is performed, one of the N bits of the next data page is stored in a multi-purpose memory cell.

26. The method according to claim 25, characterized in that Before programming the memory cells in the selected row based on the current data page, the method further includes: storing non-data page information in the multi-purpose storage unit; After programming the memory cells in the selected row based on the current data page, the method further includes: Based on the 2 N level verifies the selected row until the 2 N The Nth to last level among the levels; N bits of the next data page are received.

27. The method according to claim 25, characterized in that Also includes: In the selected row by based on the 2 N Before performing verification on the (N-1)th to last level of the N levels, storing a corresponding one of the N bits of the current data page in one of the data storage units; as well as In the selected row by based on the 2 N After verification is performed on the (N-1)th level from the last of the N levels, a corresponding one of the N bits of the next data page is stored in the data storage unit.

28. The method according to claim 25, characterized in that Also included is programming a next selected row of the rows of memory cells based on the next page of data.

29. The method according to claim 26, wherein The non-data page information includes voltage levels applied to corresponding bit lines.

30. The method according to any one of claims 25 to 28, characterized in that Each of the cache memory unit, the multi-purpose memory unit, and the data memory unit includes a latch.

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