Method for manufacturing a semiconductor memory device

Abstract

The application provides a preparation method of a semiconductor memory device, which comprises the following steps: providing a substrate; forming a plurality of first grooves in a first direction on the substrate; depositing a conductive material in the plurality of first grooves to form a word line structure; forming a word line cap on the plurality of first grooves; forming a plurality of second grooves in a second direction on the substrate, wherein the first direction intersects with the second direction; and forming an active region in the second grooves. The application can improve the preparation efficiency of the semiconductor memory device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor processing technology, and in particular to a method for fabricating a semiconductor memory device. Background Technology

[0002] With the rapid development of science and technology, the size of semiconductor memory devices has become smaller and smaller.

[0003] However, as semiconductor memory devices become smaller and smaller, their fabrication becomes increasingly difficult. This is especially true for semiconductor memory devices with buried channel transistors (BCATs), where the fabrication is particularly challenging.

[0004] In existing processes for fabricating semiconductor memory devices with buried channel transistors, the active regions are typically formed on a substrate first, followed by the formation of buried channel transistors that intersect with multiple active regions. Bit lines, bit line node contacts, and memory node contacts are then formed. However, this method is prone to collapse during the etching of the active regions before forming the buried channel transistors. Furthermore, since the buried channel transistors traverse regions of multiple different materials, the buried channel transistors themselves are also susceptible to collapse during formation, severely reducing the yield of the semiconductor memory device. Summary of the Invention

[0005] To address the aforementioned problems, the semiconductor memory device fabrication method provided by this invention first forms a word line structure on the top of a substrate, and then forms an active region spanning the word line structure on the substrate. This avoids the collapse of the active region and word line structure during formation or etching, thereby improving the fabrication yield of the semiconductor memory device.

[0006] This invention provides a method for fabricating a semiconductor memory device, comprising:

[0007] Provide substrate;

[0008] Multiple first grooves are formed on the substrate along a first direction;

[0009] Conductive material is deposited within the plurality of first grooves to form a word line structure;

[0010] The letter lines are sealed in the plurality of first grooves;

[0011] Multiple second grooves are formed on the substrate along a second direction, wherein the first direction intersects the second direction;

[0012] An active region is formed within the second groove.

[0013] Optionally, before the step of depositing conductive material in the plurality of first grooves, the method further includes:

[0014] A gate dielectric layer is formed on the sidewalls and bottom surface of the plurality of first grooves.

[0015] Optionally, the material of the gate dielectric layer includes: a silicon oxide layer, a thermal oxide layer, or a high-k dielectric layer.

[0016] Optionally, the width of the character line covering in the third direction is not less than the width of the character line structure in the third direction, and the third direction is perpendicular to the first direction.

[0017] Optionally, the material of the word line cover includes at least one of silicon nitride, polycrystalline silicon, silicon germanium, and silicon oxide.

[0018] Optionally, the step of depositing conductive material in the plurality of first grooves to form a word line structure includes:

[0019] A first conductive material is deposited in the plurality of first grooves to form an initial word line structure;

[0020] A first sub-groove is formed on the initial word line structure, and a second conductive material is deposited in the first sub-groove to form the word line structure;

[0021] The first conductive material includes at least one of titanium and titanium nitride;

[0022] The second conductive material includes tungsten.

[0023] Optionally, before the step of forming a plurality of first grooves along a first direction on the substrate, the method further includes:

[0024] A buried layer is deposited on the substrate.

[0025] Optionally, the step of forming a plurality of first grooves on the substrate along a first direction includes:

[0026] An etched window is formed on the buried layer along the first direction;

[0027] According to the etching window, a plurality of first grooves are formed on the substrate along a first direction.

[0028] Optionally, the method further includes:

[0029] A bit line node contact is formed above an active region between two word line structures that pass through the active region;

[0030] A bit line structure is formed above the bit line node contact portion along a fourth direction, the fourth direction being perpendicular to the first direction.

[0031] Optionally, the method further includes:

[0032] A storage node contact portion is formed above the active region, and the bottom of the storage node contact portion is electrically connected to the source-drain region formed at the top of the active region;

[0033] A landing pad is formed above the storage node contact portion, and the landing pad is electrically connected to the storage node contact portion;

[0034] A data storage component is formed above the landing pad.

[0035] The semiconductor memory device fabrication method provided in this invention utilizes the characteristic that a single word line structure is relatively larger than a single active region. First, a word line structure is formed on the top of the substrate, and then an active region spanning the word line structure is formed on the substrate. This not only reduces the difficulty of etching, but also avoids the collapse of the active region and word line structure during the formation or etching process, thereby improving the fabrication yield of the semiconductor memory device. Attached Figure Description

[0036] Figures 1a to 1h This is a cross-sectional view of a semiconductor memory device according to an embodiment of this application during the fabrication process;

[0037] Figure 2 This is a structural schematic diagram illustrating the arrangement of character lines according to an embodiment of this application;

[0038] Figure 3 This is a structural schematic diagram illustrating the relative positional relationship between the word line structure and the active region according to an embodiment of this application.

[0039] Figure Labels

[0040] 1. Substrate; 11. First groove; 12. Second groove; 2. Buried layer; 21. Etching window; 3. Gate dielectric layer; 4. Word line structure; 41. First conductive material; 42. Second conductive material; 5. Word line capping; 6. Active region. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0042] This embodiment provides a method for fabricating a semiconductor memory device with buried channel transistors, combined with Figures 1a to 1h The method includes: providing a substrate 1; depositing a buried layer 2 on the substrate 1; forming an etch window 21 penetrating the buried layer 2 along a first direction on the buried layer 2; forming a plurality of first grooves 11 along the first direction on the substrate 1 according to the etch window 21; forming a gate dielectric layer 3 on the sidewalls and bottom surface of the first grooves 11 and the sidewalls of the etch window 21; depositing a conductive material in the gate dielectric layer 3 to form a word line structure 4, i.e., forming a buried channel transistor; forming a word line capping 5 in the first grooves 11 and the etch window 21; removing the buried layer 2 and the word line capping 5 in the buried layer 2; forming a plurality of second grooves 12 along a second direction on the substrate 1, wherein the first direction intersects the second direction; and forming an active region 6 in the second grooves 12.

[0043] The gate dielectric layer 3 is made of a silicon oxide layer, a thermal oxide layer, or a high-k dielectric layer. The width of the word line cap 5 in a third direction is not less than the width of the word line structure 4 in a third direction, and the third direction is perpendicular to the first direction. The material of the word line cap 5 includes at least one of silicon nitride, polysilicon, silicon germanium, and silicon oxide. By limiting the widths of the word line cap 5 and the word line structure 4, damage to the word line structure 4 can be avoided when dry etching the second groove 12.

[0044] In this embodiment, each second groove 12 passes through two adjacent word line structures 4, that is, each active region 6 passes through two adjacent word line structures 4. Specifically, the opposite ends of two adjacent active regions 6 along the first direction pass through the same word line structure 4.

[0045] The semiconductor memory device fabrication method provided in this embodiment of the invention, by etching a first groove 11 on a substrate 1 to form a word line structure 4, enables the word line structure 4 to have a uniform depth, due to subsequent cleaning of the word line structure 4; combined with Figure 2 and Figure 3 Meanwhile, by taking advantage of the fact that a single word line structure 4 is relatively larger than a single active region 6, the word line structure 4 is first formed on the top of the substrate 1, and then the active region 6 that spans the word line structure 4 is formed on the substrate 1. This not only reduces the difficulty of etching, but also allows the word line structure 4 at the bottom of the active region 6 to play a fixed support role for the active region 6, and can prevent the active region 6 and the word line structure 4 from collapsing during the formation or etching process, thereby improving the fabrication yield of semiconductor memory devices.

[0046] Further, the step of depositing conductive material in the first groove 11 to form the word line structure 4 includes: depositing a first conductive material 41 in the first groove 11 to form the initial word line structure 4; forming a first sub-groove on the initial word line structure 4; and depositing a second conductive material 42 in the first sub-groove to form the word line structure 4. The first conductive material 41 includes at least one of titanium and titanium nitride; the second conductive material 42 includes tungsten.

[0047] In addition, the method further includes: forming a bit line node contact above the center position of one of the active regions 6 between the two word line structures 4 passing through the active region 6; forming a bit line structure above the bit line node contact along the fourth direction; forming a storage node contact above the active region 6, the bottom of the storage node contact being electrically connected to the source / drain region formed at the top of the active region 6; forming a landing pad above the storage node contact, the landing pad being electrically connected to the storage node contact; and forming a data storage component above the landing pad.

[0048] In this embodiment, the fourth direction is the same as the third direction. The first direction, the second direction, and the third direction are all directions on a horizontal plane. The first direction is the left-right direction, and the third direction is the front-back direction. The substrate 1 can be, for example, a bulk silicon substrate 1, a silicon-on-insulator substrate 1, a germanium substrate 1, a germanium-on-insulator substrate 1, a silicon-germanium substrate 1, a III-V compound semiconductor substrate 1, or an epitaxial thin film substrate 1 obtained by performing selective epitaxial growth.

[0049] The source / drain regions are located on top of each active region 6, on either side of the word line structure 4, and may have a different conductivity than the substrate 1. For example, the source / drain regions may have a specific conductivity to form a transistor. In one embodiment, the source / drain regions may include a trivalent impurity element. The source / drain regions may include, for example, boron or indium. The bit line node contacts include silicon-germanium or boron-doped silicon-germanium. The bit line structure electrically connects multiple bit line node contacts in a fourth direction; each bit line structure includes bit lines sequentially stacked above the bit line node contacts. The storage node contacts include, for example, silicon-germanium or boron-doped silicon-germanium. The data storage component is a capacitor.

[0050] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for fabricating a semiconductor memory device, characterized in that, include: Provide substrate; Multiple first grooves are formed along a first direction on the upper surface of the substrate; Conductive material is deposited within the plurality of first grooves to form a word line structure; The letter lines are sealed in the plurality of first grooves; Multiple second grooves are formed along a second direction on the upper surface of the substrate, the first direction intersecting the second direction; each second groove passes through two adjacent word line structures; An active region is formed within the second groove.

2. The method for fabricating a semiconductor memory device according to claim 1, characterized in that, Prior to the step of depositing conductive material within the plurality of first grooves, the method further includes: A gate dielectric layer is formed on the sidewalls and bottom surface of the plurality of first grooves.

3. The method for fabricating a semiconductor memory device according to claim 2, characterized in that, The material of the gate dielectric layer includes: a silicon oxide layer, a thermal oxide layer, or a high-k dielectric layer.

4. The method for fabricating a semiconductor memory device according to claim 1, characterized in that, The width of the character line covering in the third direction is not less than the width of the character line structure in the third direction, and the third direction is perpendicular to the first direction.

5. The method for fabricating a semiconductor memory device according to claim 1, characterized in that, The material of the word line cover includes at least one of silicon nitride, polycrystalline silicon, silicon germanium, and silicon oxide.

6. The method for fabricating a semiconductor memory device according to claim 1, characterized in that, The step of depositing conductive material in the plurality of first grooves to form a word line structure includes: A first conductive material is deposited in the plurality of first grooves to form an initial word line structure; A first sub-groove is formed on the initial word line structure, and a second conductive material is deposited in the first sub-groove to form the word line structure; The first conductive material includes at least one of titanium and titanium nitride; The second conductive material includes tungsten.

7. The method for fabricating a semiconductor memory device according to claim 1, characterized in that, Before the step of forming a plurality of first grooves along a first direction on the substrate, the method further includes: A buried layer is deposited on the substrate.

8. The method for fabricating a semiconductor memory device according to claim 7, characterized in that, The step of forming a plurality of first grooves along a first direction on the substrate includes: An etched window is formed on the buried layer along the first direction; According to the etching window, a plurality of first grooves are formed on the substrate along a first direction.

9. The method for fabricating a semiconductor memory device according to claim 1, characterized in that, The method further includes: A bit line node contact is formed above an active region between two word line structures that pass through the active region; A bit line structure is formed above the bit line node contact portion along a fourth direction, the fourth direction being perpendicular to the first direction.

10. The method for fabricating a semiconductor memory device according to claim 9, characterized in that, The method further includes: A storage node contact portion is formed above the active region, and the bottom of the storage node contact portion is electrically connected to the source-drain region formed at the top of the active region; A landing pad is formed above the storage node contact portion, and the landing pad is electrically connected to the storage node contact portion; A data storage component is formed above the landing pad.

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