A super junction structure and manufacturing method thereof

Abstract

The present invention provides a superjunction structure and a method for manufacturing the same. The method comprises providing a semiconductor substrate; epitaxially growing a first N-type epitaxial layer, and depositing a hard mask layer on the first N-type epitaxial layer; sequentially etching the hard mask layer and the first N-type epitaxial layer according to photolithographic definitions to form trenches; filling the trenches with P-type material to form P-type pillars; removing the hard mask layer and performing a chemical mechanical polishing process; epitaxially growing a second N-type epitaxial layer on the surface of the first N-type epitaxial layer; defining a superjunction structure formation region according to photolithographic definitions, and implanting P-type impurity ions into the second N-type epitaxial layer to form a P-type injection layer; and repeating the above steps until the desired drift region thickness is achieved. A superjunction structure is formed by alternating a plurality of N-type pillars, P-type pillars, N-type pillars, and P-type injection layers. The method not only reduces the on-resistance of the superjunction device but also slows down the switching process, thereby reducing the device's electromagnetic interference performance in the application circuit.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit manufacturing technology, and specifically to a superjunction structure and its manufacturing method. Background Technology

[0002] A superjunction structure is composed of alternating N-type and P-type pillars. Currently, the industry mainly uses two methods for fabricating superjunction structures: the first is... Figure 1 As shown, multiple epitaxial growths combined with multiple ion implantations, followed by a single drive-in method to connect the implanted P-type wells into a single P-type pillar, can improve electromagnetic interference (EMI) by controlling the ion implantation concentration; the second method, as... Figure 2 As shown, one or more epitaxial layers are first grown. Then, the trenches to be filled with P-type pillars are excavated in one go using a trenching method, and finally, P-type epitaxial layers are filled in to form the P-type pillars. However, with the continuous development of semiconductor processing technology, superjunction structures still face challenges and require further optimization and improvement. Summary of the Invention

[0003] In view of this, the present invention provides a superjunction structure and its manufacturing method, which can improve the electromagnetic interference performance of the superjunction device and reduce the on-resistance of the superjunction device and meet different breakdown voltage requirements, while also delaying the switching time, thereby reducing the proportion of trench in the step.

[0004] This invention provides a method for manufacturing a superjunction structure, comprising the following steps:

[0005] Step 1: Provide a semiconductor substrate;

[0006] Step 2: Epitaxially grow a first N-type epitaxial layer, and deposit a hard mask layer on the first N-type epitaxial layer;

[0007] Step 3: Based on the photolithography definition of the superjunction structure formation region, the hard mask layer and the first N-type epitaxial layer are etched sequentially to form trenches;

[0008] Step 4: Fill the trench with P-type material to form a P-type column;

[0009] Step 5: Remove the hard mask layer and perform a chemical mechanical polishing process;

[0010] Step 6: Epitaxially grow a second N-type epitaxial layer on the surface of the first N-type epitaxial layer, and form an N-type epitaxial layer by stacking the first N-type epitaxial layer and the second N-type epitaxial layer;

[0011] Step 7: Based on the photolithography definition of the superjunction structure formation region, perform P-type impurity ion implantation on the second N-type epitaxial layer to form a P-type implantation layer;

[0012] Step 8: Repeat steps 2 to 7 until the drift region thickness required by the design target is achieved. The superjunction structure is composed of multiple alternating N-type pillars, P-type pillars, N-type pillars, and P-type injection layers.

[0013] Preferably, the semiconductor substrate in step one is a silicon substrate.

[0014] Preferably, the hard mask layer in step two is a silicon nitride layer, or a stack of silicon oxide and silicon nitride.

[0015] Preferably, the depth of the trench in step three is less than the thickness of the first N-type epitaxial layer.

[0016] Preferably, the P-type material in step four is P-type silicon.

[0017] Preferably, the P-type silicon is a P-type silicon epitaxial layer formed by epitaxial growth.

[0018] Preferably, the N-type epitaxial layer in step six is ​​an N-type silicon epitaxial layer.

[0019] Preferably, the implantation depth of the impurity ions in step seven is less than the thickness of the second N-type epitaxial layer.

[0020] The present invention also provides a superjunction structure, comprising:

[0021] The device comprises multiple alternating N-type pillars, P-type pillars, N-type pillars, and P-type implanted layers. The P-type pillars are composed of P-type material filling trenches, the P-type implanted layers are formed by P-type impurity ion implantation, and the N-type pillars are composed of N-type epitaxial layers between the P-type pillars and the P-type implanted layers. The P-type material is P-type silicon, the P-type silicon is a P-type silicon epitaxial layer formed by epitaxial growth, and the N-type epitaxial layer is an N-type silicon epitaxial layer.

[0022] This invention can manufacture superjunction structures through multiple "trench and IMP superposition" structures, so that each layer of P / N region forms a "trench and IMP superposition P / N pillar" structure. The trench depth, trench fill dose, ion implantation depth and concentration can be flexibly adjusted, which can reduce the on-resistance of superjunction devices and meet different breakdown voltage requirements, while delaying the switching time to improve the EMI of superjunction devices and reduce the proportion of trenches in the step. Attached Figure Description

[0023] The above and other objects, features and advantages of the present invention will become clearer from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0024] Figure 1 The diagram shows a superjunction structure formed by existing processes.

[0025] Figure 2 This is a schematic diagram of another superjunction structure formed by existing processes;

[0026] Figure 3 The flowchart shown is a method for manufacturing a superjunction structure according to an embodiment of the present invention.

[0027] Figure 4 The diagram shown is a structural schematic of the P-shaped column after its formation according to an embodiment of the present invention.

[0028] Figure 5 The diagram shown is a structural schematic of the P-type injection layer after formation according to an embodiment of the present invention.

[0029] Figure 6 The diagram shown is a schematic diagram of a superjunction structure formed by two trenches and two injections, as an example of an embodiment of the present invention.

[0030] Figure 7 The diagram shown is a schematic of a superjunction device formed using two trenches and two injections as an example according to an embodiment of the present invention. Detailed Implementation

[0031] The present invention is described below based on the following embodiments, but the present invention is not limited to these embodiments. In the detailed description of the present invention below, certain specific details are described in detail. Those skilled in the art can fully understand the present invention without these details. To avoid obscuring the essence of the present invention, well-known methods, processes, procedures, components, and circuits are not described in detail.

[0032] Furthermore, those skilled in the art should understand that the accompanying drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale.

[0033] Unless the context explicitly requires it, words such as "including" or "contains" throughout the application should be interpreted as including rather than exclusive or exhaustive; that is, meaning "including but not limited to".

[0034] In the description of the present invention, it should be understood that the terms "first", "second", etc. are used for descriptive purposes only and should not be understood to indicate or imply relative importance. In addition, in the description of the present invention, unless otherwise specified, "plurality" means two or more.

[0035] Figure 3 The flowchart shown is a method for manufacturing a superjunction structure according to an embodiment of the present invention. Figures 4-6The diagram shows the device structure schematics for each step of the fabrication method of the superjunction structure according to an embodiment of the present invention. Figure 3 As shown, the manufacturing method of the superjunction structure in this embodiment of the invention includes the following steps:

[0036] Step 1: Provide a semiconductor substrate.

[0037] The semiconductor substrate can be made of undoped single-crystal silicon, doped single-crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), etc. As an example, in an embodiment of the present invention, the semiconductor substrate is a silicon substrate.

[0038] Step Two, as follows Figure 4 As shown, a first N-type epitaxial layer 11 is epitaxially grown, and a hard mask layer 12 is deposited on the first N-type epitaxial layer 11.

[0039] The material of the hard mask layer 12 can include a variety of materials. In this embodiment of the invention, the hard mask layer is a silicon nitride layer, or a stack of silicon oxide and silicon nitride. The formation method can be chemical vapor deposition (CVD) or physical vapor deposition (PVD).

[0040] Step 3, as follows Figure 4 As shown, the formation region of the superjunction structure is defined by photolithography, and the hard mask layer 12 and the first N-type epitaxial layer 11 are etched sequentially to form trenches.

[0041] In this embodiment of the invention, the method for etching the hard mask layer 12 and the first N-type epitaxial layer 11 is dry etching. The dry etching process includes, but is not limited to, reactive ion etching (RIE), ion beam etching, plasma etching, laser ablation, or any combination of these methods. A single manufacturing method or more than one manufacturing method may be used. The source gas for dry etching may include HBr and / or CF4 gas. In this embodiment of the invention, the depth of the trench is less than the thickness of the first N-type epitaxial layer 11.

[0042] Step 4, as follows Figure 4 As shown, P-type material is filled into the trench to form P-type column 13.

[0043] In this embodiment of the invention, the P-type material is P-type silicon, which is a P-type silicon epitaxial layer formed by epitaxial growth. When forming the P-type pillar 13, epitaxial growth is required first, followed by chemical mechanical polishing (CMP). After CMP, the hard mask layer 12 will experience some loss.

[0044] Step 5: Remove the hard mask layer 12 and perform a chemical mechanical polishing process.

[0045] In this embodiment of the invention, the hard mask layer 12 can be removed by wet etching. The chemical mechanical polishing process uses the first N-type epitaxial layer 11 as the stop layer.

[0046] Step Six, as Figure 5 As shown, a second N-type epitaxial layer 14 is epitaxially grown on the surface of the first N-type epitaxial layer 11, and the N-type epitaxial layer is formed by stacking the first N-type epitaxial layer 11 and the second N-type epitaxial layer 14.

[0047] In this embodiment of the invention, the N-type epitaxial layer is an N-type silicon epitaxial layer.

[0048] Step 7, as follows Figure 5 As shown, the formation region of the superjunction structure is defined by photolithography, and P-type impurity ion implantation is performed on the second N-type epitaxial layer 14 to form a P-type implantation layer 16.

[0049] Specifically, a photoresist 15 with a pattern of photoresist 15 is formed in the second N-type epitaxial layer 14; using the photoresist 15 as a mask, P-type impurity ion implantation is performed on the second N-type epitaxial layer 14 to form a P-type implantation layer 16; then the photoresist is removed. In this embodiment of the invention, the implantation depth of the impurity ions is less than the thickness of the second N-type epitaxial layer.

[0050] Step 8: Repeat steps 2 through 7 until the drift zone thickness required by the design target is achieved.

[0051] like Figure 6 The diagram shown illustrates a superjunction structure formed using two trenches and two implantations as an example according to an embodiment of the present invention. It includes alternating N-type pillars, P-type pillars, N-type pillars, and a P-type implanted layer. The P-type pillars are composed of P-type material filling the trenches, the P-type implanted layers are formed by P-type impurity ion implantation, and the N-type pillars are composed of an N-type epitaxial layer between the P-type pillars and the P-type implanted layer.

[0052] Among them, the P-type material is P-type silicon, which is a P-type silicon epitaxial layer formed by epitaxial growth, and the N-type epitaxial layer is an N-type silicon epitaxial layer.

[0053] This invention manufactures devices using a multi-stage "trench and IMP superposition" structure: alternating between "N-EPI Deposition + Trench Etch + P-EPI Filling + CMP" and "N-EPI Deposition + Resin Definition + IMP + Resin Removal". The N-EPI concentration, P-EPI filling concentration, Trench Depth, and IMP injection concentration can be flexibly adjusted according to actual needs. As long as each layer is aligned and the N-EPI layer thickness is greater than the required Trench Depth, the P / N regions of each layer will form a "trench and IMP superposition P / N pillar" structure.

[0054] While the "trench and IMP superposition type" PN pillar achieves different breakdown voltages (BV) due to variations in depth / EPI concentration / IMP dosage, the different PN depletion layer widths result in a gradient variation in depletion layer recovery time. This variation can improve electromagnetic interference (EMI). Furthermore, during device design, the proportion of trenches in the pitch can be reduced, thereby lowering the on-resistance (Rdson).

[0055] Figure 7 The diagram shown illustrates a superjunction device formed using a double trenching and double implantation method as an example, according to an embodiment of the present invention. Figure 7 As shown, the superjunction device of this embodiment of the invention is formed by performing the following process on the basis of the superjunction structure of this embodiment of the invention: forming a JFET region 17 and a body region 18; defining the formation region of the gate trench using photolithography, and then etching the N-type epitaxial layer of the formation region to form the gate trench; forming a gate dielectric layer 19, such as a gate oxide layer, on the side and bottom of the gate trench; filling the gate trench with polysilicon to form a polysilicon gate 20; and forming a source region 21.

[0056] Of course, the subsequent steps also include: removing the hard mask layer to form an interlayer film, forming an opening for a contact hole through the interlayer film; filling the opening with metal to form a complete contact hole; forming a front metal layer, patterning the front metal layer to form the source and gate; thinning the N-type epitaxial layer on the back side and forming a drain region on the back side of the thinned N-type epitaxial layer, and then forming a back metal layer, which forms the drain electrode (not shown in the figure).

[0057] The superjunction device of this invention achieves the goal of improving the electromagnetic interference performance of the superjunction device and reducing the proportion of trenches in the step by using an alternating trench / injection process, thereby reducing the on-resistance of the superjunction device and meeting different breakdown voltage requirements.

[0058] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. For those skilled in the art, the present invention can be modified and varied in various ways. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principle of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for manufacturing a superjunction structure, characterized in that, Includes the following steps: Step 1: Provide a semiconductor substrate; Step 2: Epitaxially grow a first N-type epitaxial layer, and deposit a hard mask layer on the first N-type epitaxial layer; Step 3: Based on the photolithography definition of the superjunction structure formation region, the hard mask layer and the first N-type epitaxial layer are etched sequentially to form trenches; Step 4: Fill the trench with P-type material to form a P-type column; Step 5: Remove the hard mask layer and perform a chemical mechanical polishing process; Step 6: Epitaxially grow a second N-type epitaxial layer on the surface of the first N-type epitaxial layer, and form an N-type epitaxial layer by stacking the first N-type epitaxial layer and the second N-type epitaxial layer; Step 7: Based on the photolithography definition of the superjunction structure formation region, perform P-type impurity ion implantation on the second N-type epitaxial layer to form a P-type implantation layer; Step 8: Repeat steps 2 to 7 until the drift region thickness required by the design target is achieved. The superjunction structure is composed of N-type pillars, P-type pillars, N-type pillars, and P-type injection layers arranged alternately in multiple thickness directions. The bottommost N-type pillar is composed of an N-type epitaxial layer between the semiconductor substrate and the P-type pillar. The other N-type pillars are composed of an N-type epitaxial layer between the P-type pillar and the P-type injection layer.

2. The method for manufacturing a superjunction structure according to claim 1, characterized in that, The semiconductor substrate mentioned in step one is a silicon substrate.

3. The method for manufacturing a superjunction structure according to claim 1, characterized in that, The hard mask layer mentioned in step two is a silicon nitride layer, or a stack of silicon oxide and silicon nitride.

4. The method for manufacturing a superjunction structure according to claim 1, characterized in that, The depth of the trench in step three is less than the thickness of the first N-type epitaxial layer.

5. The method for manufacturing a superjunction structure according to claim 1, characterized in that, The P-type material mentioned in step four is P-type silicon.

6. The method for manufacturing a superjunction structure according to claim 5, characterized in that, P-type silicon is a P-type silicon epitaxial layer formed by epitaxial growth.

7. The method for manufacturing a superjunction structure according to claim 1, characterized in that, The N-type epitaxial layer mentioned in step six is ​​an N-type silicon epitaxial layer.

8. The method for manufacturing a superjunction structure according to claim 1, characterized in that, The implantation depth of the impurity ions in step seven is less than the thickness of the second N-type epitaxial layer.

9. A superjunction structure formed using the manufacturing method of any one of claims 1 to 8, characterized in that, include: The system comprises multiple N-type pillars, P-type pillars, N-type pillars, and P-type implantation layers arranged alternately in the thickness direction. The P-type pillars are composed of P-type material filling trenches, and the P-type implantation layers are formed by P-type impurity ion implantation. The bottommost N-type pillar is composed of an N-type epitaxial layer between the semiconductor substrate and the P-type pillars. The other N-type pillars are composed of N-type epitaxial layers between the P-type pillars and the P-type implantation layers. The P-type material is P-type silicon, which is an epitaxially grown P-type silicon epitaxial layer, and the N-type epitaxial layers are N-type silicon epitaxial layers.

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