Silicon carbide umosfet device integrated with hjd and method of fabricating the same

Abstract

The application discloses a silicon carbide UMOSFET device integrated with HJD and a preparation method thereof, and relates to the technical field of semiconductors.The device comprises a substrate, an epitaxial layer located on one side of the substrate, first and second injection areas arranged at intervals and located on one side of the epitaxial layer away from the substrate, a polysilicon layer located between the first and second injection areas and on one side of the epitaxial layer away from the substrate, and a heterojunction contact between the polysilicon layer and the epitaxial layer, and a source located on one side of the first, second and polysilicon layers away from the substrate and covering at least part of the first, second and polysilicon layers. The application can reduce the switching loss and improve the energy conversion efficiency of the device.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of semiconductors, and particularly relates to a silicon carbide UMOSFET device integrated with an HJD and a preparation method thereof. BACKGROUND

[0002] Silicon carbide (SiC) is a wide-bandgap semiconductor material, which has a wider band gap, a larger saturated electron drift velocity and a higher thermal conductivity than traditional silicon materials, and is more suitable for high-temperature, high-pressure and high-frequency environments.

[0003] Metal oxide semiconductor field effect transistors (MOSFETs) have a series of advantages such as high integration density, good thermal stability and strong radiation resistance, and are widely used in power electronic systems. Silicon carbide MOSFETs, as a new type of third-generation semiconductor device, have lower conduction loss, higher voltage resistance and greater power density than silicon MOSFETs and even silicon IGBT (Insulated Gate Bipolar Transistor) devices, that is, silicon carbide MOSFETs have significant performance advantages and great development potential.

[0004] U-shaped trench gate metal oxide semiconductor field effect transistors (UMOSFETs) have the advantages of small on-resistance and small cell size compared with DMOSFETs.

[0005] Silicon carbide MOSFETs mainly act as electronic switches in power electronic systems; when they are in the on state, the lifetime of the parasitic PIN diode in the drift region increases, and the reverse recovery deteriorates sharply, which can lead to increased switching power consumption and reduced energy transmission efficiency. Therefore, a diode needs to be connected in parallel outside the silicon carbide MOSFET or integrated inside the silicon carbide MOSFET to improve the performance of the silicon carbide MOSFET body diode and improve the working efficiency of the silicon carbide MOSFET.

[0006] The silicon carbide MOSFET body reverse parallel diode can greatly improve the performance of the silicon carbide MOSFET body diode, but will increase the area of the whole module, improve the packaging cost of the device, and introduce parasitic capacitance and parasitic inductance, therefore, the existing technology integrates a Schottky barrier diode (SBD) or a junction barrier Schottky diode (JBS) in the silicon carbide MOSFET, but the internal integration of the SBD or the JBS still has a large opening voltage, therefore, it is urgent to improve the opening voltage of the silicon carbide MOSFET in the prior art. SUMMARY

[0007] In order to solve the above problems existing in the prior art, the application provides a silicon carbide UMOSFET device integrated with an HJD and a preparation method thereof. The technical problems to be solved by the application are solved by the following technical solutions.

[0008] In a first aspect, the application provides a silicon carbide UMOSFET device integrated with an HJD, comprising:

[0009] a substrate;

[0010] an epitaxial layer located on one side of the substrate;

[0011] a first implantation region and a second implantation region arranged at intervals and located on a side of the epitaxial layer away from the substrate;

[0012] a polysilicon layer located between the first implantation region and the second implantation region and on a side of the epitaxial layer away from the substrate, and a heterojunction contact between the polysilicon layer and the epitaxial layer;

[0013] a source located on a side of the first implantation region, the second implantation region and the polysilicon layer away from the substrate, and the source at least partially covering the first implantation region, the second implantation region and the polysilicon layer.

[0014] Optionally, further comprising:

[0015] a P-base region located on a side of the epitaxial layer away from the substrate;

[0016] an N+ implantation region located on a side of the P-base region away from the substrate, and at least partially covering the source on a side of the N+ implantation region away from the substrate.

[0017] Optionally, further comprising:

[0018] a second trench located on a side of the epitaxial layer away from the substrate and recessed in a direction towards the substrate, a gate dielectric layer arranged in the second trench, and a gate arranged on a side of the gate dielectric layer away from the substrate.

[0019] Optionally, along a direction perpendicular to the substrate, the second trench overlaps at least part of the first implantation region, and a distance between the second trench and the substrate near a side edge of the substrate is greater than a distance between the first implantation region and the substrate near the side edge of the substrate.

[0020] Optionally, along a direction perpendicular to the substrate, a distance between the first implantation region and the substrate near a side edge of the substrate is greater than a distance between the second implantation region and the substrate near the side edge of the substrate.

[0021] Optionally, further comprising:

[0022] a drain located on a side of the substrate away from the epitaxial layer, the drain being in ohmic contact with the substrate.

[0023] In a second aspect, the present application further provides a method for manufacturing a silicon carbide UMOSFET device integrated with a HJD, the silicon carbide UMOSFET device integrated with the HJD comprising:

[0024] a substrate;

[0025] an epitaxial layer located on a side of the substrate;

[0026] a first implantation region and a second implantation region arranged in intervals, respectively located on a side of the epitaxial layer away from the substrate;

[0027] a polysilicon layer located between the first implantation region and the second implantation region and on the side of the epitaxial layer away from the substrate, the polysilicon layer being in heterojunction contact with the epitaxial layer;

[0028] a source located on the side of the first implantation region, the second implantation region and the polysilicon layer away from the substrate, and the source at least partially covering the first implantation region, the second implantation region and the polysilicon layer;

[0029] The method comprises:

[0030] providing a substrate;

[0031] forming an epitaxial layer on a side of the substrate by epitaxial growth;

[0032] performing ion implantation on a surface of the epitaxial layer away from the substrate to form a first implantation region and a second implantation region arranged in intervals;

[0033] performing slotting between the first implantation region and the second implantation region to form a first trench;

[0034] depositing a polysilicon layer in the first trench;

[0035] depositing a source on the side of the first implantation region, the second implantation region and the polysilicon layer away from the substrate.

[0036] Optionally, further comprising:

[0037] Ion implantation is performed on the surface of the side of the epitaxial layer away from the substrate to form a P-base region;

[0038] Ion implantation is performed on the surface of the side of the P-base region away from the substrate to form an N+ injection region.

[0039] Optionally, further comprising:

[0040] Grooving is performed between the first injection region and the P-base to form a second trench; and the second trench digs away at least part of the first injection region.

[0041] Optionally, further comprising:

[0042] A gate dielectric layer and a gate electrode are sequentially formed in the second trench.

[0043] Advantages of the present application:

[0044] The present application provides a silicon carbide UMOSFET device integrated with an HJD and a preparation method thereof. The silicon carbide UMOSFET device integrated with an HJD comprises a substrate, an epitaxial layer, a first injection region and a second injection region arranged in the same layer, a polysilicon layer located between the first injection region and the second injection region, and a source electrode covering the first injection region, the second injection region and the polysilicon layer. The substrate is an N+ substrate region, the epitaxial layer is an N- epitaxial region, the first injection region and the second injection region are both P+ injection regions, and the first injection region and the second injection region have the same shape. The polysilicon layer is an N-PolySi region, and the polysilicon layer and the epitaxial layer are heterojunction contact, which is equivalent to integrating an HJD structure in the silicon carbide UMOSFET device, instead of integrating an SBD structure or a JBS structure in the silicon carbide UMOSFET device in the prior art. The present application has a smaller potential barrier difference between the polysilicon layer and the epitaxial layer, and the silicon carbide UMOSFET device of the present application needs a lower turn-on voltage, which further reduces the switching loss and improves the energy conversion efficiency of the device.

[0045] The present application will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0046] Figure 1 is a structural schematic diagram of the silicon carbide UMOSFET device integrated with an HJD provided by the embodiments of the present application;

[0047] Figure 2 is a flowchart of the preparation method of the silicon carbide UMOSFET device integrated with an HJD provided by the embodiments of the present application;

[0048] Figure 3 is another flowchart of the preparation method of the silicon carbide UMOSFET device integrated with an HJD provided by the embodiments of the present application;

[0049] Figure 4 is another flow chart of the preparation method of the integrated HJD silicon carbide UMOSFET device provided by the embodiment of the present application;

[0050] Figure 5 is another flow chart of the preparation method of the integrated HJD silicon carbide UMOSFET device provided by the embodiment of the present application;

[0051] Figure 6 is another flow chart of the preparation method of the integrated HJD silicon carbide UMOSFET device provided by the embodiment of the present application;

[0052] Figure 7 is another flow chart of the preparation method of the integrated HJD silicon carbide UMOSFET device provided by the embodiment of the present application;

[0053] Figure 8 is another flow chart of the preparation method of the integrated HJD silicon carbide UMOSFET device provided by the embodiment of the present application;

[0054] Figure 9 is another flow chart of the preparation method of the integrated HJD silicon carbide UMOSFET device provided by the embodiment of the present application. DETAILED DESCRIPTION

[0055] The present application will be further described in details below in combination with specific embodiments, but the embodiments of the present application are not limited thereto.

[0056] Please refer to Figure 1 , Figure 1 is a structural schematic diagram of the integrated HJD silicon carbide UMOSFET device provided by the embodiment of the present application, please refer to Figure 1 , the integrated HJD silicon carbide UMOSFET device provided by the present application comprises:

[0057] a substrate 1;

[0058] an epitaxial layer 2 located on one side of the substrate 1;

[0059] a first implantation region 5 and a second implantation region 6 arranged at intervals and respectively located on the side of the epitaxial layer 2 away from the substrate 1;

[0060] a polysilicon layer 11 located between the first implantation region 5 and the second implantation region 6 and on the side of the epitaxial layer 2 away from the substrate 1, and the polysilicon layer 11 and the epitaxial layer 2 are heterojunction contact;

[0061] a source electrode 13 located on the side of the first implantation region 5, the second implantation region 6 and the polysilicon layer 11 away from the substrate 1, and the source electrode 13 at least partially covers the first implantation region 5, the second implantation region 6 and the polysilicon layer 11.

[0062] Specifically, the integrated HJD silicon carbide UMOSFET device provided in the embodiment is sequentially stacked with a substrate 1 and an epitaxial layer 2, a first injection area 5 and a second injection area 6 arranged in the same layer, and a polysilicon layer 11 located between the first injection area 5 and the second injection area 6, and a source 13 covering the first injection area 5, the second injection area 6 and the polysilicon layer 11; wherein the substrate 1 is an N+ substrate area, the epitaxial layer 2 is an N- epitaxial area, the first injection area 5 and the second injection area 6 are both P+ injection areas, and the first injection area 5 and the second injection area 6 are of the same shape, the polysilicon layer 11 is an N-PolySi area, and the polysilicon layer 11 and the epitaxial layer 2 are heterojunction contact, which is equivalent to integrating an HJD structure inside the silicon carbide UMOSFET device, instead of integrating an SBD structure or a JBS structure inside the silicon carbide UMOSFET device in the prior art; so that the potential barrier difference between the polysilicon layer 11 and the epitaxial layer 2 in the present application is smaller, the silicon carbide UMOSFET device in the present application requires a lower turn-on voltage, and further reduces the switching loss and improves the energy conversion efficiency of the device.

[0063] It should be noted that the first trench 7 is arranged between the first injection area 5 and the second injection area 6, and the polysilicon layer 11 is located in the first trench 7, so that the first injection area 5 and the second injection area 6 have a joint shielding effect, which can protect the heterojunction interface and avoid the influence of high electric field on the U-shaped trench gate, thereby improving the withstand voltage capability of the device.

[0064] It should be further noted that the source 13 is at least partially filled in the first trench 7 and respectively contacts the first injection area 5 and the second injection area 6.

[0065] It should be noted that, Figure 1 The embodiment shown only schematically shows the structure of the integrated HJD silicon carbide UMOSFET device, and does not represent the actual size of each film layer.

[0066] Please continue to see Figure 1 As shown, in an optional embodiment of the present application, further comprising:

[0067] A P-base area 3 located on the side of the epitaxial layer 2 away from the substrate 1;

[0068] An N+ injection area 4 located on the side of the P-base area 3 away from the substrate 1, and at least partially covering the source 13 on the side of the N+ injection area 4 away from the substrate 1.

[0069] Specifically, please continue to see Figure 1As shown, in the embodiment, the P-base region 3 and the N+ implantation region 4 are arranged in a stack on the side of the epitaxial layer 2 away from the substrate 1; the P-base region 3 and the N+ implantation region 4 are both located on the side of the first implantation region 5 away from the second implantation region 6, and the source electrode 13 is arranged on the side of the N+ implantation region 4 away from the substrate 1, and the source electrode 13 only covers the surface of the N+ implantation region 4 away from the second trench 8, and does not extend into the second trench 8, nor does it contact the gate dielectric layer 9; the source electrode 13 covering the first implantation region 5 also does not contact the gate dielectric layer 9.

[0070] It should be noted that, in the direction perpendicular to the substrate, the thickness of the N+ implantation region 4 is less than the depth of the P-base region 3.

[0071] It should be noted that, Figure 1 The embodiment shown only shows the positional relationship of the N+ implantation region 4 and the P-base region 3, and does not represent the actual size.

[0072] Please continue to see Figure 1 As shown, in an optional embodiment of the present application, further comprising:

[0073] The second trench 8 is located on the side of the epitaxial layer 2 away from the substrate 1, and is recessed in the direction pointing to the substrate 1, and the gate dielectric layer 9 is arranged in the second trench 8, and the gate electrode 10 is arranged on the side of the gate dielectric layer 9 away from the substrate 1.

[0074] Specifically, please continue to see Figure 1 As shown, in the embodiment, the second trench 8 is arranged between the P-base region 3 and the first implantation region 5, and a layer of gate dielectric layer 9 is covered in the second trench 8, and the gate electrode 10 is arranged on the gate dielectric layer 9, so as to protect the gate electrode 10.

[0075] Please continue to see Figure 1 As shown, in an optional embodiment of the present application, in the direction perpendicular to the substrate, the second trench 8 overlaps at least part of the first implantation region 5, and the distance between the side edge of the second trench 8 close to the substrate 1 and the substrate 1 is greater than the distance between the side edge of the first implantation region 5 close to the substrate 1 and the substrate 1.

[0076] Specifically, please continue to see Figure 1 As shown, in the embodiment, in the direction perpendicular to the substrate, the depth of the second trench 8 is less than the depth of the first implantation region 5, the depth of the second trench 8 is greater than the P-base region 3, and the second trench 8 can dig away part of the first implantation region 5, or part of the P-base region 3 and the N+ implantation region 4; in this way, the second trench 8 can achieve good protection of the gate electrode 10.

[0077] Please continue to see Figure 1As shown in an optional embodiment of the present application, the distance between the first implantation region 5 and the second implantation region 6 and the substrate 1 along the direction perpendicular to the substrate 1 is greater than the distance between the polysilicon layer 11 and the substrate 1 along the direction perpendicular to the substrate 1.

[0078] Specifically, please continue to refer to Figure 2 As shown in the embodiment, the depth of the first implantation region 5 and the second implantation region 6 is greater than the depth of the first trench 7 along the direction perpendicular to the substrate 1, so that the first implantation region 5 and the second implantation region 6 achieve good shielding effect.

[0079] In an optional embodiment of the present application, further comprising: a drain 12 located on the side of the substrate 1 away from the epitaxial layer 2, and the drain 12 is in ohmic contact with the substrate 1.

[0080] In an optional embodiment of the present application, the contact between the source 13 and the N+ implantation region 4, the first implantation region 5, the second implantation region 6 and the polysilicon layer 11 is ohmic contact.

[0081] In an optional embodiment of the present application, the material of the source 13 and the drain 12 includes but is not limited to one of titanium, nickel, molybdenum or tungsten.

[0082] In an optional embodiment of the present application, along the direction perpendicular to the substrate 1,

[0083] The thickness of the substrate 1 is 1 μm-100 μm; optionally, the thickness of the substrate 1 is 3 μm, and the doping concentration is 5×10 18 cm -3 ;

[0084] The thickness of the epitaxial layer 2 is 10 μm-500 μm; optionally, the thickness of the epitaxial layer 2 is 25 μm, and the doping concentration is 8×10 15 cm -3 ;

[0085] The thickness of the P-base region 3 is 0.5 μm-5 μm; optionally, the thickness of the P-base region 3 is 0.8 μm, the width is 2 μm, and the doping concentration is 3×10 17 cm -3 ;

[0086] The thickness of the N+ implantation region 4 is 0.1 μm-2 μm; optionally, the thickness of the N+ implantation region 4 is 0.2 μm, the width is 2 μm, and the doping concentration is 1×10 19 cm -3 ;

[0087] The thickness of the first implantation region 5 and the second implantation region 6 is 1-10 μm; optionally, the thickness of the first implantation region 5 and the second implantation region 6 is 1.5 μm, the width is 2 μm, and the doping concentration is 1×1018 cm-3. 19 -3 ;

[0088] The thickness of the polysilicon is 0.1-5 μm; optionally, the thickness of the polysilicon is 1 μm, the width is 1 μm, and the doping concentration is 1×1018 cm-3. 20 -3 ;

[0089] The thickness of the gate 10 is 0.8-5 μm; optionally, the thickness of the gate 10 is 1 μm, the width is 2 μm, and the doping concentration is 1×1018 cm-3. 20 -3 ;

[0090] The thickness of the gate dielectric layer 9 is 0.1-2 μm; optionally, the thickness of the gate dielectric layer 9 is 0.1 μm, and the gate dielectric layer 9 can be a SiO2 layer.

[0091] Based on the same inventive concept, please refer to Figure 2 , Figures 3-9 is a flow chart of a preparation method of a silicon carbide UMOSFET device integrated with an HJD provided by an embodiment of the present application, and the present application further provides a preparation method of a silicon carbide UMOSFET device integrated with an HJD, wherein the silicon carbide UMOSFET device integrated with an HJD can refer to the above-mentioned embodiments, and the repeated parts will not be described herein. The preparation device comprises:

[0092] S101, providing a substrate 1;

[0093] S102, forming an epitaxial layer 2 on one side of the substrate 1 by using an epitaxial growth method;

[0094] S103, performing ion implantation on the surface of the side of the epitaxial layer 2 away from the substrate 1 to form first implantation regions 5 and second implantation regions 6 arranged at intervals;

[0095] S104, performing groove etching between the first implantation regions 5 and the second implantation regions 6 to form first grooves 7;

[0096] S105, depositing a polysilicon layer 11 in the first grooves 7;

[0097] S106, depositing a source 13 on the side of the first implantation regions 5, the second implantation regions 6, and the polysilicon layer 11 away from the substrate 1.

[0098] In an optional embodiment of the present application, the preparation method further comprises:

[0099] ​​​Ion implantation is performed on the surface of the side of the epitaxial layer 2 away from the substrate 1 to form a P-base region 3.

[0100] Ion implantation is performed on the surface of the side of the P-base region 3 away from the substrate 1 to form an N+ implant region 4.

[0101] In an alternative embodiment of the present application, further comprising:

[0102] Grooving is performed between the first implant region 5 and the P-base to form a second trench 8; and the second trench 8 digs away at least part of the first implant region 5.

[0103] In an alternative embodiment of the present application, further comprising:

[0104] A gate dielectric layer 9 and a gate 10 are formed in the second trench 8 in sequence.

[0105] In an alternative embodiment of the present application, please refer to Figure 3 , Figure 4 is another flow chart of the preparation method of the integrated HJD silicon carbide UMOSFET device provided by the embodiment of the present application, Figure 5 is another flow chart of the preparation method of the integrated HJD silicon carbide UMOSFET device provided by the embodiment of the present application, Figure 6 is another flow chart of the preparation method of the integrated HJD silicon carbide UMOSFET device provided by the embodiment of the present application, Figure 7 is another flow chart of the preparation method of the integrated HJD silicon carbide UMOSFET device provided by the embodiment of the present application, Figure 8 is another flow chart of the preparation method of the integrated HJD silicon carbide UMOSFET device provided by the embodiment of the present application, Figure 9 is another flow chart of the preparation method of the integrated HJD silicon carbide UMOSFET device provided by the embodiment of the present application, ​ is another flow chart of the preparation method of the integrated HJD silicon carbide UMOSFET device provided by the embodiment of the present application, the preparation method of the HJD silicon carbide UMOSFET device provided by the embodiment includes the following steps:

[0106] Step a: forming an epitaxial layer 2 on a substrate 1 by epitaxial growth.

[0107] First, RCA standard cleaning is performed on a SiC substrate 1 with a thickness of 3 μm and a doping concentration of 5×10 18 cm -3 -1 15 cm -3 -1

[0108] Step b: Ion implantation on the surface of the epitaxial layer 2 to form P-base region 3.

[0109] A layer of SiO2 is deposited on the surface of the epitaxial layer 2, photoresist is applied, a mask with a length of 2 μm is placed on the leftmost side of the epitaxial layer 2, after exposure, development, etching and photoresist removal, aluminum ion implantation is performed on the epitaxial layer 2, the implantation depth is 0.8 μm, and the doping concentration is 3×10 17 cm -3 After implantation, annealing is performed, and the first layer of SiO2 is removed, finally forming P-base region 3 on the left side of the epitaxial layer 2.

[0110] Step c: Ion implantation on the surface of the P-base region 3 to form N+ implantation region 4.

[0111] A layer of SiO2 is deposited on the surface of the epitaxial layer 2 and the P-base region 3, photoresist is applied, a mask with a length of 2 μm is placed on the P-base region 3, after exposure, development, etching and photoresist removal, phosphorus ion implantation is performed, the implantation depth is 0.2, and the doping concentration is 1×10 19 cm -3 After implantation, annealing is performed, and the second layer of SiO2 is removed, finally forming N+ implantation region 4 above the P-base region 3.

[0112] Step d: Ion implantation on the surface of the epitaxial layer 2 to form first implantation region 5 and second implantation region 6.

[0113] A layer of SiO2 is deposited on the surface of the epitaxial layer 2 and N+ implantation region 4, photoresist is applied, a mask with a length of 2.2 μm is placed on the upper middle and rightmost side of the epitaxial layer 2, after exposure, development, etching and photoresist removal, aluminum ion implantation is performed on the epitaxial layer 2, the implantation depth is 1.5 μm, and the doping concentration is 1×10 19 cm -3 After implantation, annealing is performed, and the third layer of SiO2 is removed, finally forming first implantation region 5 and second implantation region 6 on the upper end of the epitaxial layer 2.

[0114] Step e: Grooving on the surface of N+ implantation region 4, epitaxial layer 2 and first implantation region 5 to form first trench 7 and second trench 8.

[0115] A layer of SiO2 is deposited on the surface of N+ implantation region 4, epitaxial layer 2, first implantation region 5 and second implantation region 6, photoresist is applied, a mask with a length of 2 μm is placed between N+ implantation region 4 and first implantation region 5, and between first implantation region 5 and second implantation region 6, after exposure, development, etching and photoresist removal, the fourth layer of SiO2 is removed, finally forming second trench 8 between N+ implantation region 4 and first implantation region 5, and first trench 7 between first implantation region 5 and second implantation region 6.

[0116] Step f: depositing a gate dielectric layer 9 on the surface of the device first, and then depositing a gate 10 and a polysilicon layer 11.

[0117] A layer of SiO2 is deposited on the surface of the N+ injection region 4, the epitaxial layer 2, the first injection region 5, the second injection region 6, the first trench 7 and the second trench 8, and then photoresist is applied, and the mask is left with a gap on the surface of the second trench 8. After exposure, development, etching and removal of photoresist, a layer of N-PolySi is deposited on the surface of the device, and then a layer of SiO2 is deposited on the N-PolySi. Photoresist is applied, and the mask is left with a gap on the SiO2 layer of the second trench 8 and the central part of the first trench 7. After exposure, development, etching and removal of photoresist, the SiO2 layer is removed, and finally the gate dielectric layer 9 and the gate 10 are formed on the surface of the second trench 8, and the polysilicon layer 11 is formed in the first trench 7. The contact between the polysilicon layer 11 and the epitaxial layer 2 is a heterojunction contact.

[0118] Step g: continue to deposit the gate dielectric layer 9 on the top surface of the device, and deposit a drain 12 and a source 13.

[0119] Titanium metal is deposited on the bottom of the device to form the drain 12, and is deposited on the surface of the N+ injection region 4, the first injection region 5 on the right side, the polysilicon layer 11 and the second injection region 6. After high-temperature annealing, the source 13 is formed. The contact between the drain 12 and the substrate 1 is an ohmic contact, the contact between the source 13 and the N+ injection region 4, the first injection region 5, the second P injection region and the polysilicon layer 11 is an ohmic contact, and finally the surface planarization process is completed.

[0120] The integrated HJD silicon carbide UMOSFET device and its preparation method provided by the application are characterized in that the substrate 1 and the epitaxial layer 2 are sequentially stacked, the first injection region 5 and the second injection region 6 are arranged in the same layer, the polysilicon layer 11 is located between the first injection region 5 and the second injection region 6, and the source 13 is covered on the first injection region 5, the second injection region 6 and the polysilicon layer 11. The substrate 1 is an N+ substrate region, the epitaxial layer 2 is an N- epitaxial region, the first injection region 5 and the second injection region 6 are both P+ injection regions, and the shapes of the first injection region 5 and the second injection region 6 are the same. The polysilicon layer 11 is an N-PolySi region, and the contact between the polysilicon layer 11 and the epitaxial layer 2 is a heterojunction contact, which is equivalent to integrating an HJD structure inside the silicon carbide UMOSFET device, instead of integrating an SBD structure or a JBS structure inside the N+ substrate region of the silicon carbide UMOSFET device in the prior art. The potential barrier difference between the polysilicon layer 11 and the epitaxial layer 2 in the application is smaller, the silicon carbide UMOSFET device in the application requires a lower turn-on voltage, and the switching loss is further reduced, thereby improving the energy conversion efficiency of the device.

[0121] The above description is further detailed in connection with specific preferred embodiments of the present application, and it is not to be construed that the specific implementation of the present application is limited to these descriptions. For those skilled in the art to which the present application belongs, without departing from the concept of the present application, a number of simple deductions or substitutions can be made, and all of them should be considered as falling within the protection scope of the present application.

Claims

1. A method for fabricating a silicon carbide UMOSFET device with integrated HJD, characterized in that, The preparation method includes: Provide substrate; An epitaxial layer is formed on one side of the substrate by epitaxial growth. Ion implantation is performed on the surface of the epitaxial layer on the side opposite to the substrate to form a P-base region; Ion implantation is performed on the surface of the P-base region on the side opposite to the substrate to form an N+ implantation region; Ion implantation is performed on the surface of the epitaxial layer on the side opposite to the substrate to form a first implantation region and a second implantation region arranged at intervals. A groove is formed between the first injection area and the second injection area to form a first trench; at the same time, a groove is formed between the first injection area and the P-base to form a second trench; and the second trench removes at least a portion of the first injection area. A polysilicon layer is deposited in the first trench; a gate dielectric layer and a gate are sequentially formed in the second trench; Source electrodes are deposited in the first injection region, the second injection region, and the side of the polysilicon layer away from the substrate, and source electrodes are deposited on a portion of the side of the first injection region and the second injection region, and a source electrode is deposited on the side of a portion of the N+ injection region away from the substrate.

2. A silicon carbide UMOSFET device with integrated HJD, characterized in that, include: Substrate; An epitaxial layer is located on one side of the substrate; The first and second injection regions, which are spaced apart, are located on the side of the epitaxial layer away from the substrate, respectively. A polysilicon layer is located between the first implantation region and the second implantation region, and is located on the side of the epitaxial layer away from the substrate. The polysilicon layer and the epitaxial layer are in heterojunction contact. The source electrode is located on the side of the first implantation region, the second implantation region, and the polysilicon layer away from the substrate, and the source electrode at least partially covers the first implantation region, the second implantation region, and the polysilicon layer, as well as covering a portion of the side surfaces of the first implantation region and the second implantation region. The P-base region is located on the side of the epitaxial layer opposite to the substrate; The N+ implantation region is located on the side of the P-base region away from the substrate, and the side of the N+ implantation region away from the substrate at least partially covers the source electrode; The second trench is located on the side of the epitaxial layer away from the substrate and is recessed in the direction pointing towards the substrate. A gate dielectric layer is disposed in the second trench, and a gate electrode is disposed on the side of the gate dielectric layer away from the substrate.

3. The silicon carbide UMOSFET device with integrated HJD according to claim 2, characterized in that, Along a direction perpendicular to the substrate, the second trench overlaps with at least a portion of the first injection region, and the distance between the side of the second trench near the substrate and the substrate is greater than the distance between the side of the first injection region near the substrate and the substrate.

4. The silicon carbide UMOSFET device with integrated HJD according to claim 2, characterized in that, Along a direction perpendicular to the substrate, the distance between the side of the first implantation region and the second implantation region closest to the substrate and the substrate is greater than the distance between the side of the polysilicon layer closest to the substrate and the substrate.

5. The silicon carbide UMOSFET device with integrated HJD according to claim 2, characterized in that, Also includes: The drain is located on the side of the substrate away from the epitaxial layer, and the drain is in ohmic contact with the substrate.

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