An infrared detection chip based on a CMOS process and a preparation method and application thereof

Abstract

The application discloses an infrared detection chip based on a CMOS process and a preparation method and application thereof. The infrared detection chip comprises a silicon substrate, a CMOS readout circuit, an electron transport layer, a Se x Te 1‑x thin film layer, an electron transport layer, a Se x Te 1‑x thin film layer, wherein the range of x is 0<=x<=1, and a second electrode layer arranged on the Se x Te 1‑x thin film layer. Compared with the prior art, the preparation of the CMOS integrated infrared detection chip is low in cost and simple in process.

Description

Technical Field

[0001] This application relates to an infrared detection chip based on CMOS technology, its fabrication method and application, belonging to the field of optical detection technology. Background Technology

[0002] Current infrared detector chips are mainly based on materials such as InGaAs and HgCdTe, and are mostly fabricated using techniques such as high-temperature solid-state and molecular beam epitaxy. They are then integrated with CMOS circuits via flip-chip bonding, resulting in complex processes, low yields, and high manufacturing costs. For example, InGaAs imaging chips primarily connect InGaAs pixel units epitaxially grown on an InP substrate to the CMOS readout circuitry through indium pillar growth and flip-chip bonding.

[0003] Tellurium (Te) has a band gap of 0.35 eV, a melting point of 450℃, and band edge absorption up to 3.5 μm, making it an excellent infrared detection material. Furthermore, it can also be co-fired with selenium (Se) to form an alloy, Se. x Te 1-x (0≤x≤1), the absorption band edge can be adjusted from 0.66 to 3.5 μm. Se x Te 1-x Thin films can be grown on the surface of CMOS readout circuits using thermal evaporation processes, but currently, including Se... x Te 1-x Research on thin-film infrared photodetectors and their compatibility with CMOS integration processes is still in its early stages. Summary of the Invention

[0004] This application provides a Se based on CMOS technology. x Te 1-x The infrared detection chip solves the problem that traditional infrared detection chips require complex processes such as molecular beam epitaxy and flip-chip integration, which are costly.

[0005] One aspect of this application provides an infrared detection chip based on CMOS technology, comprising:

[0006] A silicon substrate, including a CMOS readout circuit, the CMOS readout circuit including lead electrodes;

[0007] An electron transport layer, wherein the electron egress layer is disposed on the lead-out electrode;

[0008] Se x Te 1-x Thin film layer, the Se x Te 1-x A thin film layer is disposed on the electron transport layer, wherein the range of x is 0 ≤ x ≤ 1;

[0009] and a second electrode layer, the second electrode layer being disposed on the Se x Te 1-x thin film layer.

[0010] Optionally, the CMOS readout circuit can use a commercial 16000 (128x128) pixel CMOS readout circuit, or can be designed and flow by itself, and the CMOS circuit needs to be windowed to expose the lead electrode.

[0011] Optionally, the second electrode layer is a transparent electrode.

[0012] Optionally, the Se x Te 1-x The thickness of the thin film layer is 1-10 μm;

[0013] Optionally, the Se x Te 1-x The thickness of the thin film layer is independently selected from any value in 1 μm, 2 μm, 4 μm, 6 μm, 8 μm, 10 μm or a range value between any two of the above.

[0014] Optionally, the CMOS process-based infrared detection chip can respond to a wavelength range of 700-3500 nm. The longer the response wavelength is when the tellurium content is the highest, and the response wavelength decreases as the tellurium content decreases.

[0015] Optionally, the Se x Te 1-x The thin film layer can respond to a wavelength of 1500 nm.

[0016] Optionally, the electron transport layer is selected from at least one of ZnO, ZnMgO, SnO2, TiO2, but is not limited to the above several or several combinations;

[0017] The thickness of the electron transport layer is 100-400 nm;

[0018] Optionally, the thickness of the electron transport layer is independently selected from any value in 100 nm, 200 nm, 300 nm, 400 nm or a range value between any two of the above.

[0019] Optionally, the CMOS process-based infrared detection chip further comprises a hole transport layer, the hole transport layer being located between the Se x Te 1-x thin film layer and the second electrode layer;

[0020] Optionally, the hole transport layer is selected from at least one of NiO y , CuSCN, P3HT, but is not limited to the above several or several combinations;

[0021] Optionally, the thickness of the hole transport layer is independently selected from any value or range between any two values of 0, 100 nm, 200 nm, 300 nm, 400 nm.

[0022] Optionally, the thickness of the hole transport layer is independently selected from any value or range between any two values of 0, 100 nm, 200 nm, 300 nm, 400 nm.

[0023] Optionally, the second electrode layer is selected from at least one of ITO, IWO, FTO, IHO, but is not limited to the above several or several combinations.

[0024] The thickness of the second electrode layer is 100-400 nm.

[0025] Optionally, the thickness of the second electrode layer is independently selected from any value or range between any two values of 100 nm, 200 nm, 300 nm, 400 nm.

[0026] Another aspect of the present application provides a preparation method of the above-mentioned infrared detection chip based on CMOS process, comprising:

[0027] (1) preparing the electron transport layer on the lead-out electrode of the silicon substrate;

[0028] (2) obtaining the Se x Te 1-x thin film layer on the electron transport layer by using a thermal evaporation method.

[0029] (3) obtaining the second electrode layer on the Se x Te 1-x thin film layer by using a magnetron sputtering process.

[0030] Optionally, the step (3) specifically comprises the following steps:

[0031] (3-1) preparing the hole transport layer on the Se x Te 1-x thin film layer; and

[0032] Optionally, the thermal evaporation method is at least one of a single-source thermal evaporation method and a double-source thermal evaporation method.

[0033] Optionally, the single-source thermal evaporation method specifically comprises:

[0034] using Se x Te 1-x alloy powder as raw material, an evaporation temperature of 350-500°C, an evaporation speed of 1-5 nm / s, an evaporation time of 30-90 mins, and a vacuum degree in the evaporation chamber of 10 -6 -6 x 10 -5Torr;

[0035] Optionally, the evaporation temperature is independently selected from any value or a range between any two values of 350℃, 400℃, 450℃, 500℃;

[0036] Optionally, the evaporation speed is independently selected from any value or a range between any two values of 1nm / s, 2nm / s, 3nm / s, 4nm / s, 5nm / s;

[0037] Optionally, the evaporation duration is independently selected from any value or a range between any two values of 30mins, 60mins, 90mins;

[0038] Optionally, the dual-source thermal evaporation method specifically comprises:

[0039] using a raw material containing at least one of a tellurium source and a selenium source to perform thermal evaporation, wherein the evaporation temperature of the tellurium source is 350-500℃, the evaporation speed is 1-5nm / s, the vacuum degree in the evaporation chamber is 10 -6 -6x10 -5 Torr, and the evaporation duration is 30-90mins; the evaporation temperature of the selenium source is 200-250℃, the evaporation speed is 1-5nm / s, the vacuum degree in the evaporation chamber is 10 -6 -6x10 -5 Torr, and the evaporation duration is 30-90mins;

[0040] Optionally, the evaporation temperature of the tellurium source is independently selected from any value or a range between any two values of 350℃, 400℃, 450℃, 500℃; and the evaporation speed is independently selected from any value or a range between any two values of 1nm / s, 2nm / s, 3nm / s, 4nm / s, 5nm / s;

[0041] Optionally, the evaporation temperature of the selenium source is any value or a range between any two values of 200℃, 230℃, 250℃; and the evaporation speed is independently selected from any value or a range between any two values of 1nm / s, 2nm / s, 3nm / s, 4nm / s, 5nm / s.

[0042] Optionally, after the thermal evaporation in step (2), annealing is further included, which can be selected according to the component variation; the annealing is performed after the thermal evaporation of Se x Te 1-x ;

[0043] Optionally, the temperature of the annealing is 180-300℃; and the time of the annealing is 5-30mins;

[0044] Optionally, the annealing temperature is independently selected from any value of 180℃, 220℃, 260℃, 300℃ or a range between any two of the above values.

[0045] Optionally, the annealing time is dependent on the value of x. x Te 1-x .

[0046] Optionally, the tellurium source is tellurium powder and the selenium source is selenium powder.

[0047] As a specific embodiment, the method for preparing the CMOS process-based infrared detection chip comprises the following steps:

[0048] (1) using radio frequency magnetron sputtering process I to obtain the electron transport layer on the lead-out electrode of the silicon substrate;

[0049] (2) using thermal evaporation method to obtain the Se x Te 1-x thin film layer on the electron transport layer;

[0050] (3) using radio frequency magnetron sputtering process II to obtain the hole transport layer on the Se x Te 1-x thin film layer;

[0051] (4) using magnetron sputtering process to obtain the second electrode layer on the hole transport layer.

[0052] As a specific embodiment, in the radio frequency magnetron sputtering process I, the process I parameters are: sputtering power is 50-200W, sputtering time is 30-90mins, and sputtering atmosphere is O2:Ar=0:100-2:98. In the radio frequency magnetron sputtering process II, the process II parameters are: sputtering power is 50-200W, sputtering time is 30-90mins, and sputtering atmosphere is O2:Ar=0:100-2:98.

[0053] Optionally, the process parameters of the magnetron sputtering process are: sputtering power is 50-200W, sputtering time is 10-30mins, and sputtering atmosphere is O2:Ar=0:33-1:33.

[0054] Optionally, the sputtering power is independently selected from any value of 50W, 100W, 150W, 200W or a range between any two of the above values.

[0055] Optionally, the sputtering time is independently selected from any value of 10mins, 20mins, 30mins or a range between any two of the above values.

[0056] In still another aspect of the present application, an infrared detector is provided, comprising:

[0057] The CMOS process-based infrared detection chip or the CMOS process-based infrared detection chip obtained according to the preparation method described above is arranged in the shell.

[0058] The present application can produce beneficial effects, including:

[0059] The Se x Te 1-x alloy infrared detector can be directly prepared on a CMOS circuit substrate by a process such as thermal evaporation; the Se x Te 1-x During the preparation of the thin film layer, annealing after thermal evaporation does not require high-temperature (> 300℃) treatment, does not require molecular beam epitaxy, and does not require complex processes such as flip-chip bonding, thereby reducing the cost of the infrared detection chip and simplifying the production process flow. Compared with the prior art, the present application realizes the preparation of a CMOS integrated infrared detection chip with low cost and simple process. BRIEF DESCRIPTION OF DRAWINGS

[0060] Figure 1 The CMOS process-based infrared detection chip obtained in Example 1 of the present application;

[0061] Figure 2 The Se x Te 1-x alloy thin film layer prepared in Example 1 and Example 2 of the present application; and

[0062] Among them:

[0063] 1, CMOS circuit and lead electrode; 2, electron transport layer; 3, Se x Te 1-x thin film layer; 4, hole transport layer; 5, second electrode layer. DETAILED DESCRIPTION

[0064] The present application will be described in detail below in conjunction with examples, but the present application is not limited to these examples.

[0065] In the examples of the present application, the raw materials were purchased through commercial channels, and the tellurium powder and selenium powder were purchased from Aladdin.

[0066] In the examples, the Se x Te 1-x thin film was prepared by thermal evaporation using a Corte Laisko thermal evaporation plating system COSMO.

[0067] ITO, ZnO and NiO by magnetron sputtering X The thin film was prepared by a high vacuum multi-target magnetron sputtering coating system JCP500 produced by Beijing Techno-Sciences Technology Co., Ltd.

[0068] Se x Te 1-x The alloy was prepared in a muffle furnace, using a Kecheng 1200℃ small well type furnace VBF-1200X.

[0069] Preparation Example 1

[0070] Se 0.3 Te 0.7 The specific preparation method of the alloy is as follows:

[0071] After the raw materials 1.18g of tellurium powder and 4.47g of selenium powder were sealed into a quartz tube, they were placed in a muffle furnace and heated to 560℃ within one hour, sintered for 12 hours, and then cooled to room temperature for 12 hours, to obtain Se 0.3 Te 0.7 alloy.

[0072] Example 1

[0073] (1) Prepare a silicon substrate, including a CMOS readout circuit, which is a commercial 16000 (128x128) pixel CMOS readout circuit, including a windowed exposed lead electrode;

[0074] (2) Prepare a zinc oxide electron transport layer on the lead electrode: the zinc oxide layer is prepared by radio frequency magnetron sputtering process, using zinc oxide as the sputtering raw material, the sputtering power is 200W, the sputtering time is 30mins, the sputtering atmosphere is O2:Ar=1:99, and the obtained zinc oxide layer thickness is 400nm.

[0075] (3) Prepare a Se 0.3 Te 0.7 thin film layer on the zinc oxide electron transport layer: using single-source thermal evaporation Se 0.3 Te 0.7 alloy process (single-source thermal evaporation process see Figure 2 b figure), using the Se 0.3 Te 0.7 alloy obtained in Preparation Example 1 as the raw material, the evaporation temperature is 400℃, the evaporation speed is 2nm / s, the total evaporation time is about 90mins, and the vacuum degree in the evaporation chamber is 2x10 -6 Torr. After evaporation, annealing was performed at a temperature of 260℃ for 5mins in a nitrogen atmosphere.

[0076] Se x Te 1-xA thin film layer with a thickness of 1 μm, wherein x is 0.3, can respond to the 1500 nm wavelength band.

[0077] (4) In Se x Te 1-x Hole transport layer (NiO thin film) was prepared on the thin film layer: The NiO layer was prepared by radio frequency magnetron sputtering, using NiO as the sputtering material, sputtering power of 200W, sputtering time of 30mins, and sputtering atmosphere of O2:Ar = 0:99. The thickness of the NiO layer was 100nm.

[0078] (5) Fabrication of a second electrode layer (ITO thin film) on the hole transport layer: The second electrode layer was fabricated using DC magnetron sputtering with a bulk mixture of indium oxide and tin oxide as the sputtering material. The sputtering power was 100W, the sputtering time was 10mins, and the sputtering atmosphere was O2:Ar = 0:33. The thickness of the second electrode layer was 200nm.

[0079] The obtained infrared detection chip based on CMOS technology is shown below. Figure 1 The chip structure, from bottom to top, includes, in sequence, CMOS circuitry and lead-out electrode 1, electron transport layer 2, and Se... x Te 1-x Thin film layer 3, hole transport layer 4, and second electrode layer 5—this chip structure incorporates the photosensitive layer (Se). x Te 1-x Thin film layer, namely Se 0.3 Te 0.7 The thin film layer is integrated with the CMOS circuit without the need for flip-chip bonding, molecular beam epitaxy and other processes, which reduces the cost and process difficulty of infrared detection chips.

[0080] Example 2

[0081] (1) Prepare a silicon substrate, including a CMOS readout circuit. The CMOS readout circuit is a commercial 16,000 (128×128) pixel CMOS readout circuit, including the lead-out electrodes exposed by the window.

[0082] (2) Preparation of zinc oxide electron transport layer on lead-out electrode: The zinc oxide layer is prepared by radio frequency magnetron sputtering process, with ZnO bulk as sputtering material, sputtering power of 100W, sputtering time of 30mins, sputtering atmosphere O2:Ar=1:99, and the thickness of the obtained zinc oxide layer is about 200nm.

[0083] (3) Preparation of Se on zinc oxide electron transport layer x Te 1-x Thin film layer: prepared using a dual-source thermal evaporation process (see dual-source thermal evaporation process). Figure 2In Fig. a, 2g of Te source is Te powder, the evaporation temperature is 450°C, the evaporation speed is 3nm / s, and the vacuum degree in the chamber is <10 -6 Torr; 2g of Se source is Se powder, the evaporation temperature is 200°C, the evaporation speed is 1.28nm / s, and the vacuum degree in the chamber is 10 -6 Torr. After the evaporation, annealing is performed at a temperature of 260°C for 5min under a nitrogen atmosphere.

[0084] The Se x Te 1-x thin film layer is Se 0.3 Te 0.7 , and the thickness is 1μm, which can respond to a wavelength band of 1500nm.

[0085] (4) A hole transport layer (NiO thin film) is prepared on the Se x Te 1-x thin film layer: NiO y layer is prepared by using a radio frequency magnetron sputtering process, with a nickel oxide target as the sputtering raw material, a sputtering power of 200W, a sputtering time of 30min, and a sputtering atmosphere of O2:Ar=0:99. The thickness of the NiO y layer is 100nm.

[0086] (5) A second electrode layer (ITO thin film) is prepared on the hole transport layer: the second electrode layer is prepared by using a direct current magnetron sputtering process, with a mixture block of indium oxide and tin oxide as the sputtering raw material, a sputtering power of 100W, a sputtering time of 10min, and a sputtering atmosphere of O2:Ar=0:33. The thickness of the second electrode layer is 200nm.

[0087] Figure 2 The two kinds of thermal evaporation processes for preparing the Se 0.3 Te 0.7 thin film layer in Example 1 and Example 2 are shown in Fig. a and Fig. b. When the double-source co-evaporation process is used, it is convenient to adjust the film composition, but the instrument requirement is higher; when the Se 0.3 Te 0.7 alloy single-source evaporation process is used, the process is simple, but due to the different saturated vapor pressures of selenium and tellurium, there may be a problem of uneven distribution of film composition.

[0088] The above description is only several embodiments of the present application, and does not limit the present application in any form. Although the above preferred embodiments are disclosed, the present application is not limited thereto. Any person skilled in the art can make some changes or modifications to the above disclosed technical contents without departing from the scope of the technical solution of the present application, which are equivalent to the equivalent embodiments, and all of them belong to the scope of the technical solution.

Claims

1. A method for fabricating an infrared detection chip based on CMOS technology, characterized in that, (1) An electron transport layer is fabricated on the lead-out electrode of a silicon substrate; (2) Se was obtained on the electron transport layer by thermal evaporation. x Te 1-x Thin film layer; (3) Using magnetron sputtering process, in the Se x Te 1-x A second electrode layer is obtained on the thin film layer; The thermal evaporation method is selected from at least one of single-source thermal evaporation method and dual-source thermal evaporation method; Step (2) includes annealing after thermal evaporation, wherein the annealing temperature is 180~300℃ and the annealing time is 5~30mins; Step (3) specifically includes the following steps: In the Se x Te 1-x A hole transport layer is prepared on the thin film layer; the second electrode layer is obtained on the hole transport layer by magnetron sputtering. The CMOS-based infrared detection chip includes: A silicon substrate, including a CMOS readout circuit, the CMOS readout circuit including lead electrodes; An electron transport layer is disposed on the lead-out electrode; Se x Te 1-x Thin film layer, the Se x Te 1-x A thin film layer is disposed on the electron transport layer, wherein the range of x is 0 < x < 1; The second electrode layer is disposed on the Se x Te 1-x On the thin film layer; The CMOS-based infrared detection chip also includes a hole transport layer, which is located in the Se... x Te 1-x Between the thin film layer and the second electrode layer.

2. The preparation method according to claim 1, characterized in that, The Se x Te 1-x The thickness of the thin film layer is 1~10μm.

3. The preparation method according to claim 1, characterized in that, The Se x Te 1-x The wavelength range that the thin film layer can respond to is 700~3500nm.

4. The preparation method according to claim 1, characterized in that, The Se x Te 1-x The wavelength range that the thin film layer can respond to is 1500nm.

5. The preparation method according to claim 1, characterized in that, The electron transport layer is selected from at least one of ZnO, ZnMgO, SnO2, and TiO2; The thickness of the electron transport layer is 100~400nm.

6. The preparation method according to claim 1, characterized in that, The hole transport layer is selected from NiO. y At least one of CuSCN and P3HT, wherein the range of y is 1≤y≤2.

7. The preparation method according to claim 1, characterized in that, The thickness of the hole transport layer is 0~400 nm.

8. The preparation method according to claim 1, characterized in that, The second electrode layer is selected from at least one of ITO, IWO, FTO, and IHO; The thickness of the second electrode layer is 100~400 nm.

9. The preparation method according to claim 1, characterized in that, The single-source thermal evaporation method specifically includes: With Se x Te 1-x Using alloy powder as raw material, the evaporation temperature is 350~500℃, the evaporation rate is 1~5nm / s, the evaporation time is 30~90 mins, and the vacuum degree in the evaporation chamber is 10. -6 ~6×10 -5 Torr.

10. The preparation method according to claim 1, characterized in that, The dual-source thermal evaporation method specifically includes: Thermal evaporation is performed using raw materials containing at least one of tellurium and selenium sources. The tellurium source evaporation temperature is 350–500°C, the evaporation rate is 1–5 nm / s, and the vacuum level within the evaporation chamber is 10⁻⁶. -6 ~ 6×10 -5 Torr, evaporation time 30~90 mins; selenium source evaporation temperature 200~250℃, evaporation rate 1~5nm / s, vacuum degree in evaporation chamber 10 -6 ~6×10 -5 Torr, evaporation time is 30~90 mins.

11. The preparation method according to claim 10, characterized in that, The tellurium source is tellurium powder, and the selenium source is selenium powder.

12. The preparation method according to claim 1, characterized in that, The process parameters for the magnetron sputtering process are: sputtering power of 50~200W, sputtering time of 10~30 mins, and sputtering atmosphere O2:Ar=0:33~1:

33.

13. An infrared detector, characterized in that, include: An infrared detection chip based on CMOS technology obtained by the preparation method according to any one of claims 1 to 12.

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