A light-emitting chip and a method for preparing the same

Abstract

The present invention provides a light-emitting chip and a preparation method thereof. The preparation method comprises: providing a first substrate, and sequentially growing an N-type buffer layer, an N-type functional layer, an active layer, and a P-type functional layer on the first substrate, wherein the P-type functional layer comprises, in a growth order, a P-type confinement layer, a P-type current spreading layer, and a roughening layer, wherein the P-type current spreading layer has multiple layers, each layer containing an Al component of different contents, and by growing a P-type current spreading layer having a lattice constant slightly different from that of the P-type confinement layer on the P-type confinement layer, the problem of increased warping of the light-emitting chip due to mismatch stress between the P-type confinement layer and the P-type current spreading layer during subsequent grinding is avoided, thereby avoiding damage to the light-emitting chip, thereby achieving the purposes of improving the yield rate of the light-emitting chip, optimizing the current spreading of the light-emitting chip, and improving the light-emitting effect of the light-emitting chip.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a light-emitting chip and a preparation method thereof. Background Art

[0002] Mini LED (sub-millimeter light-emitting diode) chip is an LED chip with a size of about 100μm×100μm. With the development of display technology, Mini LED chip is widely used in backlight display devices as an upgraded version of traditional LCD backlight source. Therefore, Mini LED chip is required to have good light output effect.

[0003] In the existing technology, the P-type current spreading layer in the Mini LED chip generally adopts GaP (gallium phosphide) material, and the remaining layers adopt AlGaInP or AlInP materials that match the substrate lattice.

[0004] To ensure the thickness of the Mini LED chip, the substrate of the Mini LED chip is usually thinned. However, as the substrate becomes thinner, the mismatch stress between the P-type current spreading layer of the GaP material and the P-type confinement layer of the AlInP material will cause the Mini LED chip to warp more, leading to damage to the Mini LED chip during subsequent grinding, cutting and other process preparations, which not only affects the light output effect of the Mini LED chip, but also reduces the yield rate of the Mini LED chip. Summary of the Invention

[0005] In view of this, an embodiment of the present invention provides a light-emitting chip and a preparation method thereof to solve the problem that the light-emitting chip is easily damaged when prepared using the existing method, resulting in poor light output effect of the light-emitting chip and reducing the yield rate of the light-emitting chip.

[0006] To solve the above problems, the embodiments of the present invention provide the following technical solutions:

[0007] A first aspect of an embodiment of the present invention discloses a method for preparing a light-emitting chip, comprising:

[0008] Providing a first substrate having a predetermined crystal orientation;

[0009] An N-type buffer layer, an N-type functional layer, an active layer, and a P-type functional layer are sequentially grown on the first substrate, wherein the N-type functional layer comprises, in order of growth, an N-type corrosion stop layer, an N-type ohmic contact layer, an N-type current spreading layer, and an N-type confinement layer; the P-type functional layer comprises, in order of growth, a P-type confinement layer, a P-type current spreading layer, and a roughening layer; the P-type current spreading layer comprises an N layer, each layer comprising an Al component of different contents, and the value of N ranges from 1 to 10;

[0010] Roughening a side of the roughening layer away from the P-type current spreading layer;

[0011] Vapor-depositing a silicon compound or an oxygen compound on the roughened side of the roughened layer, and polishing the roughened layer;

[0012] providing a second substrate;

[0013] vapor-depositing a silicon compound or an oxygen compound on the second substrate;

[0014] bonding the silicon compound or oxygen compound on the second substrate to the silicon compound or oxygen compound on the roughened layer;

[0015] sequentially etching the first substrate, the N-type buffer layer, and the N-type etching stop layer;

[0016] Forming a P electrode, an N electrode, an ISO isolation layer and a double electrode based on an electrode construction process;

[0017] The side of the second substrate on which the silicon compound is not evaporated is ground to obtain a light-emitting chip with a chip thickness ranging from 1 μm to 100 μm.

[0018] Preferably, N Al2O3 layers are grown on the side of the P-type confinement layer away from the active layer. x Ga 1-x InP / Al y Ga 1-y InP layer, to obtain a P-type current spreading layer;

[0019] Among them, Al x Ga 1-x InP and Al y Ga 1-y The Al content in InP ranges from 0.2 to 0.9, the value of x is 0.3, and the value of y is 0.7.

[0020] Preferably, N Al2O3 layers are grown on the side of the P-type confinement layer away from the active layer. x Ga 1-x InP / Al y Ga 1-y As layer, P-type current expansion is obtained;

[0021] Among them, Al x Ga 1-x The Al content in InP ranges from 0.2 to 0.9. y Ga 1-y The Al component content in As ranges from 0.3 to 1, the value of x is 0.3, and the value of y is 0.6.

[0022] Preferably, N Al2O3 layers are grown on the side of the P-type confinement layer away from the active layer.x Ga 1-x As / Al y Ga 1-y As layer, a P-type current spreading layer is obtained;

[0023] Among them, Al x Ga 1-x As and Al y Ga 1-y The Al component content in As ranges from 0.3 to 1, the value of x is 0.2, and the value of y is 0.6.

[0024] Preferably, when growing a P-type current spreading layer having an N-layer structure on the side of the P-type confinement layer away from the active layer, the growth is performed in such a way that the Al component content in the latter layer structure is greater than the Al component in the former layer structure;

[0025] Alternatively, when growing a P-type current spreading layer having an N-layer structure on the side of the P-type confinement layer away from the active layer, the growth is performed in such a manner that the thickness of the latter layer is greater than the thickness of the former layer;

[0026] Alternatively, when growing a P-type current spreading layer having an N-layer structure on the side of the P-type confinement layer away from the active layer, the growth is performed in such a way that the Mg doping concentration in the latter layer is greater than that in the former layer.

[0027] Preferably, the crystal orientation is (100) <111> , N-type GaAs with an angle of 2 degrees to 15 degrees is used as the first substrate.

[0028] Preferably, an N-type GaAs buffer layer doped with Si is grown on one side of the first substrate within a temperature range of 650°C to 750°C.

[0029] Preferably, an active layer of a superlattice multi-quantum well structure is grown on a side of the N-type functional layer away from the N-type buffer layer.

[0030] Preferably, a roughening layer is grown on a side of the P-type current spreading layer away from the P-type confinement layer, and the roughening layer is roughened to obtain a roughening layer with a roughening depth ranging from 0.2 um to 4 um.

[0031] A second aspect of the embodiments of the present invention discloses a light-emitting chip. The light-emitting chip is a light-emitting chip prepared according to the method for preparing a light-emitting chip disclosed in the first aspect of the embodiments of the present invention.

[0032] Based on the above-mentioned method for preparing a light-emitting chip provided by the embodiment of the present invention, the method for preparing a light-emitting chip includes: providing a first substrate with a preset crystal orientation; sequentially growing an N-type buffer layer, an N-type functional layer, an active layer, and a P-type functional layer on the first substrate, wherein the N-type functional layer includes, in the order of growth, an N-type corrosion stop layer, an N-type ohmic contact layer, an N-type current spreading layer, and an N-type limiting layer; the P-type functional layer includes, in the order of growth, a P-type limiting layer, a P-type current spreading layer, and a roughening layer; the P-type current spreading layer has an N layer, each layer contains an Al component of different contents, and the value of N ranges from 1 to 10; the roughening layer is subjected to the treatment of the N-type buffer layer; ... current spreading layer includes, in the order of growth, an N-type current spreading layer, and a roughening layer; the P-type current spreading layer includes an N layer, each layer contains an Al component of different contents, and the value of N ranges from 1 to 10; the roughening layer is subjected to the treatment of the N-type buffer layer; the N-type functional layer includes, in the order of growth, an N-type corrosion stop layer, an N-type oh The method comprises the following steps: roughening the side of the roughened layer away from the P-type current spreading layer; vapor-depositing a silicon compound or an oxygen compound on the roughened side of the roughened layer and polishing the roughened layer; providing a second substrate; vapor-depositing a silicon compound or an oxygen compound on the second substrate; bonding the silicon compound on the second substrate to the silicon compound on the roughened layer; sequentially etching the first substrate, the N-type buffer layer and the N-type etching stop layer; forming a P electrode, an N electrode, an ISO isolation layer and a double electrode based on an electrode construction process; and grinding the side of the second substrate on which the silicon compound or oxygen compound is not vapor-deposited to obtain a light-emitting chip with a chip thickness ranging from 1 μm to 100 μm.

[0033] In this embodiment of the present invention, by growing a P-type current spreading layer on the P-type confinement layer with a lattice constant that is slightly different from that of the P-type confinement layer, the subsequent polishing of the second substrate avoids the problem of increased warping of the light-emitting chip due to mismatch stress between the P-type confinement layer and the P-type current spreading layer, thereby preventing damage to the light-emitting chip, ensuring the light extraction efficiency of the light-emitting chip, and improving the yield rate of the light-emitting chip. Furthermore, the P-type current spreading layer has a multilayer structure, and during the growth process, each layer contains a different content of Al components, effectively enhancing the lateral current expansion capability of the P-type current spreading layer, further improving the light extraction efficiency of the light-emitting chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0035] Figure 1 A flowchart of a method for preparing a light-emitting chip provided in an embodiment of the present invention;

[0036] Figure 2 A schematic structural diagram of a light-emitting chip provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0037] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0038] In the following description, many specific details are set forth to facilitate a full understanding of the present application. However, the present application may also be implemented in other ways different from those described herein. Those skilled in the art may make similar generalizations without violating the connotation of the present application. Therefore, the present application is not limited to the specific embodiments disclosed below.

[0039] Next, the present invention is described in detail with reference to schematic diagrams. For ease of illustration, when describing embodiments of the present invention, cross-sectional views illustrating device structures may be partially enlarged and not to scale. Furthermore, these schematic diagrams are merely illustrative and should not limit the scope of protection of the present invention. Furthermore, in actual production, three-dimensional dimensions, including length, width, and depth, should be included.

[0040] Example 1:

[0041] Figure 1 A schematic diagram of a process for preparing a light-emitting chip according to an embodiment of the present invention is provided. Figure 2 Based on Figure 1 A schematic structural diagram of a light-emitting chip obtained by the disclosed method for preparing the light-emitting chip.

[0042] The method for preparing the light-emitting chip includes:

[0043] S11: providing a first substrate having a preset crystal orientation.

[0044] In one embodiment of the present invention, the first substrate may be a substrate with a crystal orientation of (100) <111> , an N-type GaAs substrate with an included angle of 2 degrees to 15 degrees, but the embodiments of the present invention are not limited to this. GaAs has a zinc blende structure, and different crystal orientations have different interplanar spacing, atomic density, growth rate during epitaxial growth and crystal growth quality. Based on this characteristic, the crystal orientation and included angle are set to obtain good crystal quality and specific electrical properties.

[0045] In one embodiment of the present invention, the first substrate may also be a silicon substrate.

[0046] S12: sequentially growing an N-type buffer layer, an N-type functional layer, an active layer, and a P-type functional layer on the first substrate.

[0047] In one embodiment of the present invention, an N-type GaAs buffer layer doped with Si is grown on one side of the first substrate at a temperature ranging from 650 degrees to 750 degrees.

[0048] In S12 , the N-type functional layer includes, in order of growth, an N-type corrosion stop layer, an N-type ohmic contact layer, an N-type current spreading layer, and an N-type confinement layer.

[0049] In one embodiment of the present invention, first, the N-type etching stop layer is grown on a side of the N-type GaAs buffer layer facing away from the first substrate.

[0050] The N-type etching stop layer may be made of AlGaInP material doped with Si element.

[0051] Alternatively, the N-type etching stop layer may be made of GaInP material doped with Si.

[0052] Secondly, the N-type ohmic contact layer is grown on a side of the N-type etching stop layer away from the N-type GaAs buffer layer.

[0053] The N-type ohmic contact layer may be made of GaAs material doped with Si element.

[0054] Secondly, the N-type current spreading layer is grown on a side of the N-type ohmic contact layer away from the N-type corrosion stop layer.

[0055] The N-type current spreading layer may be made of AlGaInP material doped with Si element.

[0056] Finally, the N-type confinement layer is grown on a side of the N-type current spreading layer away from the N-type ohmic contact layer.

[0057] The N-type confinement layer may be made of AlInP material doped with Si element.

[0058] In one embodiment of the present invention, an active layer of a superlattice multi-quantum well structure is grown on a side of the N-type functional layer away from the N-type buffer layer. The active layer may be made of AlGaInP material.

[0059] Specifically, an active layer of a superlattice multi-quantum well structure is grown on a side of the N-type confinement layer away from the N-type current spreading layer.

[0060] In one embodiment of the present invention, the P-type functional layer is grown on a side of the active layer away from the N-type functional layer.

[0061] In S12 , the P-type functional layer includes, in a growth order, a P-type confinement layer, a P-type current spreading layer, and a roughening layer.

[0062] The P-type current spreading layer has N layers, each layer contains Al components with different contents, and the value of N ranges from 1 to 10.

[0063] In one embodiment of the present invention, first, the P-type confinement layer is grown on a side of the active layer away from the N-type functional layer.

[0064] The P-type confinement layer may be made of Mg-doped AlInP material.

[0065] Secondly, the P-type current spreading layer is grown on a side of the P-type confinement layer away from the active layer.

[0066] The P-type current spreading layer may be made of Mg-doped AlGaInP material and / or AlGaAs material.

[0067] When specifically growing the P-type current spreading layer, it should be noted that the number of layers of the P-type current spreading layer and the Al component contained in each layer are set according to the size and performance requirements of the current chip.

[0068] In one embodiment of the present invention, when a P-type current spreading layer having an N-layer structure is grown on the side of the P-type confinement layer away from the active layer, the growth is performed in such a way that the Al component content in the latter layer is greater or less than the Al component in the former layer.

[0069] It should be noted that the thickness of each layer of the P-type current spreading layer having an N-layer structure can be the same or different, and the Mg doping concentration in each layer can be the same or different. Those skilled in the art can select the Al component content, thickness, and Mg doping concentration of each layer of the P-type current spreading layer according to actual needs, and are not limited here.

[0070] In one embodiment of the present invention, when a P-type current spreading layer having an N-layer structure is grown on the side of the P-type confinement layer away from the active layer, the growth is performed in such a way that the thickness of the latter layer is greater or less than that of the former layer.

[0071] In one embodiment of the present invention, when a P-type current spreading layer having an N-layer structure is grown on the side of the P-type confinement layer away from the active layer, the growth is performed in such a way that the Mg doping concentration in the latter layer is greater or less than the Mg doping concentration in the former layer.

[0072] Finally, the roughening layer is grown on a side of the P-type current spreading layer away from the P-type confinement layer.

[0073] The roughening layer may be made of Mg-doped AlGaInP material or AlGaAs material. Specifically, the Mg doping concentration in the roughening layer is 5E17 to 1.5E18.

[0074] In one embodiment of the present invention, the Al component content in the roughened layer is 0.2 to 0.4.

[0075] In one embodiment of the present invention, the thickness of the roughening layer is 1.5 um to 3 um.

[0076] In one embodiment of the present invention, the roughening layer is a P-type roughening layer.

[0077] S13: roughening a side of the roughening layer away from the P-type current spreading layer.

[0078] The roughening layer is roughened with an acidic solution to obtain a roughening layer with a roughening depth of 0.2 μm to 4 μm.

[0079] The acidic solution may be hydrochloric acid or nitric acid. By roughening one side of the roughened layer, the adhesion of the roughened layer may be improved.

[0080] S14: evaporating a silicon compound or an oxygen compound on the roughened side of the roughened layer, and polishing the roughened layer.

[0081] In S14, the silicon compound includes SiO2 or Si3N4.

[0082] In one embodiment of the present invention, after SiO 2 is evaporated on the roughened side of the roughening layer, the surface of the evaporated SiO 2 is polished for subsequent bonding.

[0083] S15: providing a second substrate, and evaporating a silicon compound or an oxygen compound on the second substrate.

[0084] In S15, the silicon compound includes SiO2 or Si3N4.

[0085] In one embodiment of the present invention, the second substrate may be an Al2O3 substrate or glass.

[0086] S16: Bonding the silicon compound or oxygen compound on the second substrate with the silicon compound or oxygen compound on the roughened layer.

[0087] In one embodiment of the present invention, SiO 2 on the second substrate is bonded to SiO 2 on the roughened layer.

[0088] In one embodiment of the present invention, Si 3 N 4 on the second substrate is bonded to Si 3 N 4 on the roughened layer.

[0089] S17: etching the first substrate, the N-type buffer layer, and the N-type etching stop layer in sequence.

[0090] In one embodiment of the present invention, ammonia mixed with hydrogen peroxide is used to etch the first substrate and the N-type buffer layer, and hydrochloric acid mixed with phosphoric acid is used to etch the N-type etching stop layer.

[0091] S18: forming a P electrode, an N electrode, an ISO isolation layer and a double electrode based on an electrode construction process.

[0092] exist Figure 2 In the embodiment, the P electrode includes P-Pad, the N electrode includes N-Pad, and the double electrode includes N-Metal.

[0093] In S18, based on the structure obtained after executing S17, a P electrode, an N electrode, an ISO isolation layer, and a double electrode can be formed through existing electrode construction processes. The electrode construction process includes but is not limited to a series of processes such as photolithography, evaporation, etching, and cutting at the chip end.

[0094] In one embodiment of the present invention, first, photolithography combined with ICP technology is used to etch from the N-type ohmic contact layer to the P-type current spreading layer. Specifically, photolithography combined with ICP technology is used to sequentially etch the N-type ohmic contact layer, the N-type current spreading layer, the N-type confinement layer, the active layer, the P-type confinement layer, and finally the P-type current spreading layer.

[0095] Wherein, the etching depth of the P-type current spreading layer is 0.5um to 3um.

[0096] Then, photolithography is combined with evaporation process to deposit P electrode, N electrode, ISO isolation layer and double electrode in sequence.

[0097] S19: Grinding the side of the second substrate on which the silicon compound or oxygen compound is not evaporated to obtain a light-emitting chip with a chip thickness ranging from 1 um to 100 um.

[0098] After the light-emitting chip having a thickness ranging from 1 μm to 100 μm is obtained by grinding, the light-emitting chip can be cut, split, and tested.

[0099] In one embodiment of the present invention, a light-emitting chip with a chip thickness ranging from 1 um to 50 um can be obtained by grinding the side of the second substrate on which the silicon compound or oxygen compound is not evaporated.

[0100] In this embodiment of the present invention, by growing a P-type current spreading layer on the P-type confinement layer with a lattice constant that is slightly different from that of the P-type confinement layer, the subsequent polishing of the second substrate avoids the problem of increased warping of the light-emitting chip due to mismatch stress between the P-type confinement layer and the P-type current spreading layer, thereby preventing damage to the light-emitting chip, ensuring the light extraction efficiency of the light-emitting chip, and improving the yield rate of the light-emitting chip. Furthermore, the P-type current spreading layer has a multilayer structure, and during the growth process, each layer contains a different content of Al components, effectively enhancing the lateral current expansion capability of the P-type current spreading layer, further improving the light extraction efficiency of the light-emitting chip.

[0101] Example 2:

[0102] Based on the growth process of the P current spreading layer in S12 disclosed in Example 1, in this embodiment, N Al x Ga 1-x InP / Al y Ga 1-y InP layer, a P-type current spreading layer is obtained.

[0103] The value range of N can be 1 to 10. Each layer of Al x Ga 1-x InP / Al y Ga 1-y The Al content in InP can be different. x Ga 1-x InP / Al y Ga 1-y The Al component content in the InP layer can be selected as needed.

[0104] Al x Ga 1-x InP / Al y Ga 1-y The value of x in the InP layer is 0.3, and the value of y is 0.7.

[0105] In one embodiment of the present invention, each Al x Ga 1-x InP / Al y Ga 1-y The thickness of the InP layer and the Mg content can also be different or the same as required.

[0106] In one embodiment of the present invention, each Al x Ga 1-x InP / Al y Ga 1-y The InP layer is composed of an Al x Ga1-x Al-SiO2 is grown on the InP layer y Ga 1-y The InP layer is obtained.

[0107] Among them, each Al x Ga 1-x InP / Al y Ga 1-y Al in the InP layer x Ga 1-x InP layer and Al y Ga 1-y The Al component content in the InP layer can also be selected according to actual needs.

[0108] In one embodiment of the present invention, each Al x Ga 1-x InP / Al y Ga 1-y Al in the InP layer x Ga 1-x The Al composition content in the InP layer ranges from 0.2 to 0.9.

[0109] Each Al x Ga 1-x InP / Al y Ga 1-y Al in the InP layer y Ga 1-y The Al composition content in the InP layer ranges from 0.2 to 0.9.

[0110] In one embodiment of the present invention, if N is 1, an Al2O3 layer is grown on the side of the P-type confinement layer away from the active layer. x Ga 1-x InP / Al y Ga 1-y InP layer, a P-type current spreading layer is obtained. x Ga 1-x InP / Al y Ga 1-y The Al component contained in the InP layer can be set according to current needs.

[0111] If N is 3, three layers of Al are grown on the side of the P-type confinement layer away from the active layer. x Ga 1-x InP / Al y Ga 1-y InP layer, a P-type current spreading layer is obtained.

[0112] Specifically, 3 layers of Al x Ga 1-x InP / Aly Ga 1-y The InP layer includes the first Al x Ga 1-x InP / Al y Ga 1-y InP layer, second Al x Ga 1-x InP / Al y Ga 1-y InP layer and the third Al x Ga 1-x InP / Al y Ga 1-y InP layer.

[0113] The first Al x Ga 1-x InP / Al y Ga 1-y The InP layer contains a first Al x Ga 1-x InP layer and the first Al y Ga 1-y InP layer.

[0114] The second Al x Ga 1-x InP / Al y Ga 1-y The InP layer contains a second Al x Ga 1-x InP layer and the second Al y Ga 1-y InP layer.

[0115] The third Al x Ga 1-x InP / Al y Ga 1-y The InP layer contains a third Al x Ga 1-x InP layer and the third Al y Ga 1-y InP layer.

[0116] Among them, the first Al x Ga 1-x InP layer, first Al y Ga 1-y InP layer, second Al x Ga 1-x InP layer, second Al y Ga 1-y InP layer, third Al x Ga 1-x InP layer and the third Aly Ga 1-y The Al composition in the InP layers is different, and the thickness and Mg doping concentration can be the same or different.

[0117] In one embodiment of the present invention, the P-type current spreading layer is 10 layers of Al x Ga 1-x InP / Al y Ga 1-y InP layer structure.

[0118] According to the growth order, each Al x Ga 1-x InP / Al y Ga 1-y The doping concentration of the InP layer gradually increases, and the thickness gradually thickens, guiding the current to expand laterally. In order to ensure that the roughening morphology is controllable, a thick layer of Al is grown on the outermost layer. y Ga 1-y InP layer, thickness is 1.5um to 3um.

[0119] Table 1 gives the first Al x Ga 1-x InP layer, first Al y Ga 1-y InP layer, second Al x Ga 1-x InP layer, second Al y Ga 1-y InP layer, third Al x Ga 1-x InP layer, third Al y Ga 1-y InP layer and the tenth Al y Ga 1-y The Al composition, Mg doping concentration, and thickness ranges of the InP layer. Each layer can be grown with reference to the values ​​in Table 1.

[0120] Table 1:

[0121]

[0122] In the embodiment provided by the present invention, by growing a P-type current spreading layer with a lattice constant smaller than that of the P-type confinement layer on the P-type confinement layer, the problem of increased warping of the light-emitting chip caused by the mismatch stress between the P-type confinement layer and the P-type current spreading layer is avoided during the subsequent grinding of the second substrate, thereby avoiding damage to the light-emitting chip, ensuring the light-emitting effect of the light-emitting chip, and improving the yield rate of the light-emitting chip. At the same time, the P-type current spreading layer has multiple layers of Al x Ga 1-x InP / Al y Ga 1-yDuring the growth process of the InP layer, each layer contains a different content of Al components, which effectively enhances the current lateral expansion capability of the P-type current expansion layer and further improves the light-emitting effect of the light-emitting chip.

[0123] Example 3:

[0124] Based on the growth process of the P current spreading layer in S12 disclosed in Example 1, in this embodiment, N Al x Ga 1-x InP / Al y Ga 1-y As layer, a P-type current spreading layer is obtained.

[0125] The value range of N can be 1 to 10. Each layer of Al x Ga 1-x InP / Al y Ga 1-y The content of the Al component contained in As may vary.

[0126] Among them, each Al x Ga 1-x InP / Al y Ga 1-y The Al component content in the As layer can be selected as needed.

[0127] Al x Ga 1-x InP / Al y Ga 1-y The value of x in the As layer is 0.3, and the value of y is 0.6.

[0128] In one embodiment of the present invention, each Al x Ga 1-x InP / Al y Ga 1-y The thickness of the As layer and the Mg content can also be different or the same as required.

[0129] In one embodiment of the present invention, each Al x Ga 1-x InP / Al y Ga 1-y As layer is composed of Al x Ga 1-x Al-SiO2 is grown on the InP layer y Ga 1-y As layer obtained.

[0130] Among them, each Al x Ga 1-x InP / Aly Ga 1-y Al in As layer x Ga 1-x InP layer and Al y Ga 1-y The Al component content in the As layer can also be selected according to actual needs.

[0131] In one embodiment of the present invention, each Al x Ga 1-x InP / Al y Ga 1-y Al in As layer x Ga 1-x The Al composition content in the InP layer ranges from 0.2 to 0.9.

[0132] Each Al x Ga 1-x InP / Al y Ga 1-y Al in As layer y Ga 1-y The Al component content in the As layer ranges from 0.3 to 1.

[0133] In one embodiment of the present invention, if N is 1, an Al2O3 layer is grown on the side of the P-type confinement layer away from the active layer. x Ga 1-x InP / Al y Ga 1-y As layer, a P-type current spreading layer is obtained. x Ga 1-x InP / Al y Ga 1-y The Al component contained in the As layer can be set according to current needs.

[0134] If N is 3, three layers of Al are grown on the side of the P-type confinement layer away from the active layer. x Ga 1-x InP / Al y Ga 1-y As layer, a P-type current spreading layer is obtained.

[0135] Specifically, 3 layers of Al x Ga 1-x InP / Al y Ga 1-y The As layer includes the first Al x Ga 1-x InP / Al y Ga 1-y As layer, second Al x Ga1-x InP / Al y Ga 1-y As layer and third Al x Ga 1-x InP / Al y Ga 1-y As layer.

[0136] The first Al x Ga 1-x InP / Al y Ga 1-y The As layer contains the first Al x Ga 1-x InP layer and the first Al y Ga 1-y As layer.

[0137] The second Al x Ga 1-x InP / Al y Ga 1-y As layer contains the second Al x Ga 1-x InP layer and the second Al y Ga 1-y As layer.

[0138] The third Al x Ga 1-x InP / Al y Ga 1-y As layer contains the third Al x Ga 1-x InP layer and the third Al y Ga 1-y As layer.

[0139] Among them, the first Al x Ga 1-x InP layer, first Al y Ga 1-y As layer, second Al x Ga 1-x InP layer, second Al y Ga 1-y As layer, third Al x Ga 1-x InP layer and the third Al y Ga 1-y The Al composition in the As layers is different, and the thickness and Mg doping concentration can be the same or different.

[0140] In one embodiment of the present invention, the P-type current spreading layer is 10 layers of Al x Ga 1-x InP / Aly Ga 1-y As structure.

[0141] According to the growth order, each Al x Ga 1-x InP / Al y Ga 1-y As layer doping concentration gradually increases, thickness gradually thickens, guides the current to expand laterally. y Ga 1-y As layer absorption ratio, under the premise of ensuring the current expansion effect, Al y Ga 1-y The thickness of the As layer is greater than that of the Al x Ga 1-x The InP layer is significantly thinner.

[0142] In order to ensure the controllable coarsening morphology, a thick layer of Al is grown on the outermost layer. y Ga 1-y As layer, thickness is 1.5um to 3um.

[0143] Table 2 gives the first Al x Ga 1-x InP layer, first Al y Ga 1-y As layer, second Al x Ga 1-x InP layer, second Al y Ga 1- y As layer, third Al x Ga 1-x InP layer, third Al y Ga 1-y As layer and the tenth Al y Ga 1-y The Al composition, Mg doping concentration, and thickness ranges of the As layer. Each layer can be grown with reference to the values ​​in Table 2.

[0144] Table 2:

[0145]

[0146] In the embodiment provided by the present invention, by growing a P-type current spreading layer with a lattice constant smaller than that of the P-type confinement layer on the P-type confinement layer, the problem of increased warping of the light-emitting chip caused by the mismatch stress between the P-type confinement layer and the P-type current spreading layer is avoided during the subsequent grinding of the second substrate, thereby avoiding damage to the light-emitting chip, ensuring the light-emitting effect of the light-emitting chip, and improving the yield rate of the light-emitting chip. At the same time, the P-type current spreading layer has multiple layers of Al x Ga 1-x InP / Aly Ga 1-y During the growth process, each As layer contains different contents of Al components, which effectively enhances the current lateral expansion capability of the P-type current expansion layer and further improves the light-emitting effect of the light-emitting chip.

[0147] Example 4:

[0148] Based on the growth process of the P current spreading layer in S12 disclosed in Example 1, in this embodiment, N Al x Ga 1-x As / Al y Ga 1-y As layer, a P-type current spreading layer is obtained.

[0149] The value range of N can be 1 to 10. Each layer of Al x Ga 1-x As / Al y Ga 1-y The content of the Al component contained in As may vary.

[0150] Among them, each Al x Ga 1-x As / Al y Ga 1-y The Al component content in the As layer can be selected as needed.

[0151] Al x Ga 1-x As / Al y Ga 1-y The value of x in the As layer is 0.2, and the value of y is 0.6.

[0152] In one embodiment of the present invention, each Al x Ga 1-x As / Al y Ga 1-y The thickness of the As layer and the Mg content can also be different or the same as required.

[0153] In one embodiment of the present invention, each Al x Ga 1-x As / Al y Ga 1-y As layer is composed of Al x Ga 1-x Al-Si-Al-Si ... y Ga 1-y As layer obtained.

[0154] Among them, each Al x Ga1-x As / Al y Ga 1-y Al in As layer x Ga 1-x As layer and Al y Ga 1-y The Al component content in the As layer can also be selected according to actual needs.

[0155] In one embodiment of the present invention, each Al x Ga 1-x As / Al y Ga 1-y Al in As layer x Ga 1-x As layer and Al y Ga 1- y The Al component content in the As layer ranges from 0.3 to 1.

[0156] In one embodiment of the present invention, if N is 1, an Al2O3 layer is grown on the side of the P-type confinement layer away from the active layer. x Ga 1-x As / Al y Ga 1-y As layer, a P-type current spreading layer is obtained. x Ga 1-x As / Al y Ga 1-y The Al component contained in the As layer can be set according to current needs.

[0157] If N is 3, three layers of Al are grown on the side of the P-type confinement layer away from the active layer. x Ga 1-x As / Al y Ga 1-y As layer, a P-type current spreading layer is obtained.

[0158] Specifically, 3 layers of Al x Ga 1-x As / Al y Ga 1-y The As layer includes the first Al x Ga 1-x As / Al y Ga 1-y As layer, second Al x Ga 1-x As / Al y Ga 1-y As layer and third Al x Ga 1-x As / Al yGa 1-y As layer.

[0159] The first Al x Ga 1-x As / Al y Ga 1-y The As layer contains the first Al x Ga 1-x As layer and first Al y Ga 1-y As layer.

[0160] The second Al x Ga 1-x As / Al y Ga 1-y As layer contains the second Al x Ga 1-x As layer and the second Al y Ga 1-y As layer.

[0161] The third Al x Ga 1-x As / Al y Ga 1-y As layer contains the third Al x Ga 1-x As layer and third Al y Ga 1-y As layer.

[0162] Among them, the first Al x Ga 1-x As layer, first Al y Ga 1-y As layer, second Al x Ga 1-x As layer, second Al y Ga 1-y As layer, third Al x Ga 1-x As layer and third Al y Ga 1-y The Al composition in the As layers is different, and the thickness and Mg doping concentration can be the same or different.

[0163] In the embodiment provided by the present invention, by growing a P-type current spreading layer with a lattice constant smaller than that of the P-type confinement layer on the P-type confinement layer, the problem of increased warping of the light-emitting chip caused by the mismatch stress between the P-type confinement layer and the P-type current spreading layer is avoided during the subsequent grinding of the second substrate, thereby avoiding damage to the light-emitting chip, ensuring the light-emitting effect of the light-emitting chip, and improving the yield rate of the light-emitting chip. At the same time, the P-type current spreading layer has multiple layers of Al x Ga 1-xAs / Al y Ga 1-y During the growth process, each As layer contains different contents of Al components, which effectively enhances the current lateral expansion capability of the P-type current expansion layer and further improves the light-emitting effect of the light-emitting chip.

[0164] Example 5:

[0165] The present invention also provides a light emitting chip, the specific structure of which is as follows Figure 2 As shown, the light-emitting chip is manufactured according to the above-mentioned method for manufacturing a light-emitting chip. The P-type current spreading layer of the light-emitting chip has N layers, each layer contains a different content of Al component, and the value range of N is 1 to 10. Of course, the value range of N can be expanded according to actual needs.

[0166] It should be noted that in the description of this application, it should be understood that the terms "upper", "lower", "top", "bottom", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore should not be understood as limiting this application. When a component is considered to be "connected" to another component, it can be directly connected to the other component or there may be a centrally located component.

[0167] It should also be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that an article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such article or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the article or device comprising the aforementioned elements.

[0168] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present application. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application is not limited to the embodiments shown herein, but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for preparing a light-emitting chip, characterized in that: include: Providing a first substrate having a predetermined crystal orientation; An N-type buffer layer, an N-type functional layer, an active layer, and a P-type functional layer are sequentially grown on the first substrate, wherein the N-type functional layer comprises, in order of growth, an N-type corrosion stop layer, an N-type ohmic contact layer, an N-type current spreading layer, and an N-type confinement layer; the P-type functional layer comprises, in order of growth, a P-type confinement layer, a P-type current spreading layer, and a roughening layer; the P-type current spreading layer comprises an N-layer, each layer comprising an Al component of varying content, with N ranging from 2 to 10; wherein the roughening layer is grown on a side of the P-type current spreading layer facing away from the P-type confinement layer, and the side of the roughening layer facing away from the P-type current spreading layer is roughened to obtain a roughening layer having a roughening depth ranging from 0.2 μm to 4 μm; Vapor-depositing a silicon compound or an oxygen compound on the roughened side of the roughened layer, and polishing the roughened layer; providing a second substrate; vapor-depositing a silicon compound or an oxygen compound on the second substrate; bonding the silicon compound or oxygen compound on the second substrate to the silicon compound or oxygen compound on the roughened layer; sequentially etching the first substrate, the N-type buffer layer, and the N-type etching stop layer; Forming a P electrode, an N electrode, an ISO isolation layer and a double electrode based on an electrode construction process; Grinding the side of the second substrate on which the silicon compound or oxygen compound is not evaporated to obtain a light-emitting chip with a chip thickness ranging from 1 μm to 100 μm; Wherein, when growing a P-type current spreading layer having an N-layer structure on the side of the P-type confinement layer away from the active layer, the growth is performed in such a way that the Al component content in the latter layer structure is greater than the Al component in the former layer structure; Alternatively, when growing a P-type current spreading layer having an N-layer structure on the side of the P-type confinement layer away from the active layer, the growth is performed in such a manner that the thickness of the latter layer is greater than the thickness of the former layer; Alternatively, when growing a P-type current spreading layer having an N-layer structure on the side of the P-type confinement layer away from the active layer, the growth is performed in such a way that the Mg doping concentration in the latter layer is greater than that in the former layer.

2. The method according to claim 1, characterized in that N Al layers are grown on the side of the P-type confinement layer away from the active layer. x Ga 1-x InP / Al y Ga 1-y InP layer, to obtain P-type current expansion; Among them, Al x Ga 1-x InP and Al y Ga 1-y The Al content in InP ranges from 0.2 to 0.9, the value of x is 0.3, and the value of y is 0.

7.

3. The method according to claim 1, characterized in that N Al layers are grown on the side of the P-type confinement layer away from the active layer. x Ga 1-x InP / Al y Ga 1-y As layer, a P-type current spreading layer is obtained; Among them, Al x Ga 1-x The Al content in InP ranges from 0.2 to 0.

9. y Ga 1-y The Al component content in As ranges from 0.3 to 1, the value of x is 0.3, and the value of y is 0.

6.

4. The method according to claim 1, wherein N Al layers are grown on the side of the P-type confinement layer away from the active layer. x Ga 1-x As / Al y Ga 1-y As layer, a P-type current spreading layer is obtained; Among them, Al x Ga 1-x As and Al y Ga 1-y The Al component content in As ranges from 0.3 to 1, the value of x is 0.2, and the value of y is 0.

6.

5. The method according to any one of claims 1 to 4, characterized in that Provides a (100) orientation <111> , N-type GaAs with an angle of 2 degrees to 15 degrees is used as the first substrate.

6. The method according to any one of claims 1 to 4, characterized in that An N-type GaAs buffer layer doped with Si is grown on one side of the first substrate within a temperature range of 650 degrees to 750 degrees.

7. The method according to any one of claims 1 to 4, characterized in that An active layer of a superlattice multi-quantum well structure is grown on a side of the N-type functional layer away from the N-type buffer layer.

8. A light-emitting chip, characterized in that: The light-emitting chip is a light-emitting chip prepared by the method for preparing a light-emitting chip according to any one of claims 1 to 7.

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