signal detection circuit

Abstract

A signal detection circuit includes an input switching circuit, an amplitude detection circuit, a clock generation circuit, and an integration circuit. The input switching circuit receives a reference voltage and an input voltage, and is controlled by a set of switching signals to selectively output the reference voltage or the input voltage. The amplitude detection circuit detects the output of the input switching circuit to correspondingly generate an amplitude voltage. The clock generation circuit generates the set of switching signals for controlling the input switching circuit to alternately enter a first phase and a second phase, and the input switching circuit is controlled to output the reference voltage in the first phase and the input voltage in the second phase. The integration circuit is configured to take the amplitude voltage as an input and accumulate, and generate an integration voltage corresponding to the accumulated result within a predetermined time interval. The predetermined time interval includes a plurality of periods with the first phase and the second phase as a cycle.

Description

Technical Field

[0001] This invention relates to a signal detection circuit, and more particularly to a signal detection circuit that can reduce the impact of process offset. Background Technology

[0002] In existing signal detection circuits, in order to detect the magnitude of the signal to be measured, two independent current paths are often set up for the signal to be measured and the reference voltage. After being filtered into DC voltages by an amplitude detector, the signal magnitudes are compared by a comparator.

[0003] However, in the above architecture, when creating two independent current paths, the difference in process offset often leads to a large error after the comparator comparison.

[0004] Therefore, how to reduce the impact of process offset through circuit design improvements to overcome the above-mentioned defects has become one of the important issues that need to be addressed in this field. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a signal detection circuit that can reduce the impact of process offset, in order to address the shortcomings of the prior art.

[0006] To address the aforementioned technical problems, the present invention provides a signal detection circuit comprising an input switch circuit, an amplitude detection circuit, a clock generation circuit, and an integrator circuit. The input switch circuit is configured to receive a reference voltage and an input voltage, and is controlled by a switching signal group to selectively output either the reference voltage or the input voltage. The amplitude detection circuit is configured to detect the output of the input switch circuit to generate an amplitude voltage accordingly. The clock generation circuit is configured to generate the switching signal group. The switching signal group controls the input switch circuit to alternately enter a first stage and a second stage, and the input switch circuit is controlled to output the reference voltage in the first stage and the input voltage in the second stage. The integrator circuit is configured to use the amplitude voltage as input and accumulate it, generating an integrated voltage corresponding to an accumulated result within a predetermined time interval. The predetermined time interval includes multiple cycles that loop between the first stage and the second stage.

[0007] One beneficial effect of the present invention is that the signal detection circuit provided by the present invention selects the input signal and the reference voltage to enter the amplitude detection circuit and the integration circuit at different stages by using an input switch circuit. Since the circuit shares the same back end, the input signal and the reference voltage will experience the same circuit offset. Therefore, the error caused by process bias when using different paths can be reduced.

[0008] To further understand the features and technical content of the present invention, please refer to the following detailed description and illustrations of the present invention. However, the illustrations provided are for reference and illustration only and are not intended to limit the present invention. Attached Figure Description

[0009] Figure 1 This is a functional block diagram of the signal detection circuit in an embodiment of the present invention.

[0010] Figure 2 This is a circuit layout diagram of the signal detection circuit according to an embodiment of the present invention.

[0011] Figure 3 This is a first signal timing diagram of the signal detection circuit in an embodiment of the present invention.

[0012] Figure 4 This is a second signal timing diagram of the signal detection circuit in an embodiment of the present invention.

[0013] Figure 5 This is a circuit layout diagram of a signal detection circuit according to another embodiment of the present invention. Detailed Implementation

[0014] The following specific embodiments illustrate the implementation of the "signal detection circuit" disclosed in this invention. Those skilled in the art can understand the advantages and effects of this invention from the content disclosed in this specification. This invention can be implemented or applied through other different specific embodiments, and the details in this specification can also be modified and changed based on different viewpoints and applications without departing from the concept of this invention. Furthermore, it should be stated in advance that the accompanying drawings of this invention are for simple illustrative purposes only and are not depicted according to actual dimensions. The following embodiments will further describe the relevant technical content of this invention in detail, but the disclosed content is not intended to limit the scope of protection of this invention. In addition, the term "or" as used herein may include, depending on the actual situation, any combination of any one or more of the associated listed items.

[0015] Figure 1 This is a functional block diagram of the signal detection circuit according to an embodiment of the present invention. (See attached diagram.) Figure 1 As shown, an embodiment of the present invention provides a signal detection circuit 1, which includes an input switch circuit 10, an amplitude detection circuit 12, a clock generation circuit 14, and an integration circuit 16.

[0016] The input switching circuit 10 is configured to receive the reference voltage VREF and the input voltage VIN, and is controlled by the switching signal group SS to selectively output the reference voltage VREF or the input voltage VIN.

[0017] Please refer to the following first. Figure 2 , Figure 2This is a circuit layout diagram of the signal detection circuit according to an embodiment of the present invention. For example, the reference voltage VREF is a pair of differential reference voltages, including a first reference voltage VREFP and a second reference voltage VREFN, and the input voltage VIN is a pair of differential input voltages, including a first input voltage VINP and a second input voltage VINN.

[0018] exist Figure 2 In this embodiment, in response to the input voltage VIN being a differential signal, the input switching circuit 10 can be, for example, a multiplexer, whose circuitry can be simplified as follows: Figure 2 The diagram includes a first switch S1, a second switch S2, a third switch S3, and a fourth switch S4, and has a first output terminal o1 and a second output terminal o2. The first switch S1, the second switch S2, the third switch S3, and the fourth switch S4 can be N-type or P-type metal-oxide-semiconductor field-effect transistors (MOSFETs), but the invention is not limited thereto.

[0019] The first switch S1 is connected to the first output terminal o1 and receives the first reference voltage VREFP; the second switch S2 is connected to the first output terminal o1 and receives the first input voltage VINP; the third switch S3 is connected to the second output terminal o2 and receives the second input voltage VINN; and the fourth switch S4 is connected to the second input terminal o2 and receives the second reference voltage VREFN.

[0020] Please refer to this again. Figure 1 The amplitude detection circuit 12 is used to detect the output of the input switching circuit 10 to generate an amplitude voltage VA accordingly. For example, the amplitude detection circuit 12 can be... Figure 2 The rectifier 120, or any circuit that can convert an input signal into a simple output high or low potential depending on its magnitude, is not limited thereto.

[0021] like Figure 2 As shown, the rectifier 120 may have a first detection output terminal do1 and a second detection output terminal do2, and is configured to generate an amplitude voltage VA including a first amplitude voltage Va1 and a second amplitude voltage Va2 at the first detection output terminal do1 and the second detection output terminal do2 corresponding to the outputs of the first output terminal o1 and the second output terminal o2.

[0022] On the other hand, clock generation circuit 14 is used to generate switching signal group SS (such as... Figure 1 (As shown). The switching signal group SS is mainly used to control the input switching circuit 10 to alternately enter the first stage and the second stage. Specifically, in the first stage, the input switching circuit 10 is controlled to output a reference voltage VREF, and in the second stage, it outputs an input voltage VIN.

[0023] Furthermore, when the above switching method is applied Figure 2 In an embodiment, the switching signal group SS may include a first switching signal φ1 and a second switching signal φ2. The first switching signal φ1 is used to control the first switch S1 and the fourth switch S4 to be turned on in the first stage, and the second switching signal φ2 is used to control the second switch S2 and the third switch S3 to be turned on in the second stage, so that the input switching circuit 10 outputs a first reference voltage VREFP and a second reference voltage VREFN at the first output terminal o1 and the second output terminal o2 respectively in the first stage, and outputs a first input voltage VINP and a second input voltage VINN at the first output terminal o1 and the second output terminal o2 respectively in the second stage.

[0024] Please refer to this again. Figure 1 The integrator circuit 16 is used to take the amplitude voltage VA as input and accumulate it, and generate an integrated voltage VINT corresponding to the accumulated result within a predetermined time interval. The predetermined time interval covers multiple cycles with the first stage and the second stage as the loop.

[0025] For example, the integrator circuit 16 can sample the amplitude voltage VA in the first stage (generated based on the reference voltage VREF) and the amplitude voltage VA in the second stage (generated based on the input voltage VIN) in a single cycle and then perform subtraction. Therefore, after multiple cycles equivalent to the predetermined time interval, it can be determined whether the input voltage VIN is higher or lower than the reference voltage VREF based on the accumulated integrated voltage VINT.

[0026] Please refer to this method. Figure 2 The integrating circuit 16 may include a sampling circuit 160 and an integrating amplifier 162. The sampling circuit 160 is used to sample the first amplitude voltage Va1 and the second amplitude voltage Va2 in the first stage.

[0027] like Figure 2 As shown, the sampling circuit 160 may include a first sampling capacitor C1, a second sampling capacitor C2, a fifth switch S5, a sixth switch S6, a seventh switch S7, and an eighth switch S8. The fifth switch S5, the sixth switch S6, the seventh switch S7, and the eighth switch S8 may be N-type or P-type metal-oxide-semiconductor field-effect transistors (MOSFETs), but the present invention is not limited thereto.

[0028] The first sampling capacitor C1 is connected between the first detection output terminal do1 and the first node N1, and the second sampling capacitor C2 is connected between the second detection output terminal do2 and the second node N2. One end of the fifth switch S5 is connected to the first node N1, and the other end receives the common-mode voltage Vcm. One end of the sixth switch S6 is connected to the second node N2, and the other end receives the common-mode voltage Vcm. The seventh switch S7 is connected between the first node N1 and the third node N3, and the eighth switch S8 is connected between the second node N2 and the fourth node N4.

[0029] On the other hand, the integrating amplifier 162 is used to hold the first amplitude voltage Va1 and the second amplitude voltage Va2 sampled by the sampling circuit 160 in the second stage for accumulation.

[0030] Therefore, as Figure 2 As shown, the integrating amplifier 162 may include a fully differential amplifier FDA, a first feedback capacitor Cfb1, and a second feedback capacitor Cfb2.

[0031] The fully differential amplifier FDA has a non-inverting input (left positive terminal), an inverting input (left negative terminal), an inverting output (right positive terminal), and a non-inverting output (right negative terminal). The non-inverting input is connected to the third node N3, and the inverting input is connected to the fourth node N4. A first feedback capacitor Cfb1 is connected between the non-inverting input and the inverting output, and a second feedback capacitor Cfb2 is connected between the inverting input and the non-inverting output.

[0032] like Figure 2 As shown, the fifth switch S5 and the sixth switch S6 are controlled by the first switching signal φ1 to be turned on in the first stage and turned off in the second stage. The seventh switch S7 and the eighth switch S8 are controlled by the second switching signal φ2 to be turned on in the second stage and turned off in the first stage. In embodiments of the present invention, the integrator circuit 16 can be replaced by a low-pass filter or a capacitor, but the present invention is not limited thereto.

[0033] The following will be referred to Figure 3 illustrate Figure 2 The detection mechanism of the signal detection circuit. Figure 3 This is a first signal timing diagram of the signal detection circuit according to an embodiment of the present invention. As shown in the figure, a timing diagram including time points t1 to t9 is presented. Specifically, in... Figure 3 In this embodiment, the reference voltage VREF is less than the input voltage VIN in the interval from time t1 to t5, and greater than the input voltage VIN in the interval from time t5 to time t9.

[0034] Starting from time point t2, between time points t2 and t3, the first stage begins. The first switching signal φ1 is high, and the second switching signal φ2 is low, indicating that switches S1, S4, S5, and S6 are all on, while switches S2, S3, S7, and S8 are all off. At this time, the reference voltage VREF is input to rectifier 120, generating a low-level amplitude voltage VA. For this amplitude voltage VA, the first sampling capacitor C1 samples the difference between the first amplitude voltage Va1 and the common-mode voltage Vcm, and the second sampling capacitor C2 samples the difference between the second amplitude voltage Va2 and the common-mode voltage Vcm. Based on this, the amplitude voltage VA can be sampled.

[0035] Next, between time points t3 and t4, the second stage begins. The first switching signal φ1 is at a low potential, and the second switching signal φ2 is at a high potential, indicating that the first switch S1, the fourth switch S4, the fifth switch S5, and the sixth switch S6 are all off, while the second switch S2, the third switch S3, the seventh switch S7, and the eighth switch S8 are all on. At this time, the input voltage VIN is input to the rectifier 120, generating a high-potential amplitude voltage VA. This high-potential amplitude voltage VA is subtracted from the low-potential amplitude voltage VA sampled in the first stage. The result of this subtraction is then amplified by the fully differential amplifier FDA and stored in the first feedback capacitor Cfb1 and the second feedback capacitor Cfb2 to generate the integral voltage VINT.

[0036] Depend on Figure 3 As can be seen, since the reference voltage VREF is less than the input voltage VIN in the interval from time t2 to t5, the integral voltage VINT gradually decreases from time t2 to t5. Therefore, after multiple cycles with the first and second stages as the loop, for example at time t5, the integral voltage VINT can be output as the cumulative result, and the relationship between the reference voltage VREF and the input voltage VIN can be determined accordingly.

[0037] On the other hand, since the reference voltage VREF is greater than the input voltage VIN in the time interval from t6 to t9, the integral voltage VINT gradually increases from t6 to t9. The increased integral voltage VINT can also be output as the cumulative result after multiple cycles.

[0038] Additionally, it should be noted that, Figure 2 The integrating amplifier 162 also includes a first reset switch Sr1, a second reset switch Sr2, and a third reset switch Sr3. The first reset switch Sr1 is connected between the non-inverting input and the inverting output of the fully differential amplifier FDA, the second reset switch Sr2 is connected between the inverting input and the non-inverting output of the fully differential amplifier FDA, and the third reset switch Sr3 is connected between the third node N3 and the fourth node N4.

[0039] Correspondingly, the clock generation circuit 14 also generates a reset signal Rst to control the first reset switch Sr1, the second reset switch Sr2, and the third reset switch Sr3 to be turned on during a reset time interval before and after the predetermined time interval, and to be turned off during the predetermined time interval. For example, the reset time interval could be... Figure 3 The predetermined time interval can be, for example, between time points t1 and t2 and between t5 and t6. After the first reset switch Sr1, the second reset switch Sr2, and the third reset switch Sr3 are turned on, the held integral voltage VINT can be reset for re-detection.

[0040] The following will be referred to Figure 4 To illustrate with another embodiment Figure 2 The detection mechanism of the signal detection circuit. Figure 4 This is a second signal timing diagram of the signal detection circuit according to an embodiment of the present invention. As shown in the figure, a timing diagram including time points t1 to t9 is presented. Specifically, in... Figure 4 In this embodiment, the reference voltage VREF remains constant, while the input voltage is less than the reference voltage VREF in the time interval from t1 to t5, and greater than the reference voltage VREF in the time interval from t5 to t9.

[0041] Starting from time point t2, between time points t2 and t3, the first stage begins. The first switching signal φ1 is high, and the second switching signal φ2 is low, indicating that switches S1, S4, S5, and S6 are all on, while switches S2, S3, S7, and S8 are all off. At this time, the reference voltage VREF is input to rectifier 120, generating a high-level amplitude voltage VA. For this amplitude voltage VA, the first sampling capacitor C1 samples the difference between the first amplitude voltage Va1 and the common-mode voltage Vcm, and the second sampling capacitor C2 samples the difference between the second amplitude voltage Va2 and the common-mode voltage Vcm. Based on this, the amplitude voltage VA can be sampled.

[0042] Next, between time points t3 and t4, the second stage begins. The first switching signal φ1 is at a low potential, and the second switching signal φ2 is at a high potential, indicating that the first switch S1, the fourth switch S4, the fifth switch S5, and the sixth switch S6 are all off, while the second switch S2, the third switch S3, the seventh switch S7, and the eighth switch S8 are all on. At this time, the input voltage VIN is input to the rectifier 120, generating a low-potential amplitude voltage VA. This low-potential amplitude voltage VA is subtracted from the high-potential amplitude voltage VA sampled in the first stage. The result of this subtraction is then amplified by the fully differential amplifier FDA and stored in the first feedback capacitor Cfb1 and the second feedback capacitor Cfb2 to generate the integral voltage VINT.

[0043] Depend on Figure 4 It can be seen that since the reference voltage VREF is greater than the input voltage VIN in the interval from time t2 to t5, the integral voltage VINT gradually increases from time t2 to t5. Therefore, after multiple cycles with the first and second stages as the loop, for example at time t5, the integral voltage VINT can be output as the cumulative result, and the relationship between the reference voltage VREF and the input voltage VIN can be determined accordingly.

[0044] Therefore, the above embodiment uses the input switch circuit 10 to select the input voltage VIN and the reference voltage VREF to enter the amplitude detection circuit 12 and the integration circuit 16 at different stages. Since they share the same back-end circuit, the input voltage VIN and the reference voltage VREF will experience the same circuit offset. Therefore, the error caused by process bias when using different paths can be reduced.

[0045] In some embodiments, the signal detection circuit 1 may also selectively include a comparator circuit 18, configured to receive the integrated voltage VINT generated by the integrator circuit 16 (i.e., ...) through its first and second input terminals. Figure 2 The voltages at the inverted and non-inverted output terminals are compared to generate a comparison result signal Vcomp as the cumulative result. Correspondingly, in this embodiment, the clock generation circuit 14 is also used to generate a comparison clock signal comclk to accumulate the signal within a predetermined time interval (e.g., ...). Figure 3 , 4 At the end of the time period from t2 to t5, the comparator circuit 18 is controlled to generate and output the comparison result signal Vcomp.

[0046] Please refer to the following first. Figure 5 , Figure 5This is a circuit layout diagram of a signal detection circuit according to another embodiment of the present invention. In another embodiment, the integrating amplifier 162 may also selectively include a chopping circuit, such as a first chopping circuit CC1 and a second chopping circuit CC2 connected to the input and output terminals of the fully differential amplifier FDA, respectively, which may be designed to operate at specific time points. The first chopping circuit CC1 has two input terminals connected to the third node N3 and the fourth node N4, respectively, and two output terminals connected to the non-inverting input terminal (left + terminal) and the inverting input terminal (left - terminal), respectively. The second chopping circuit CC2 has two input terminals connected to the inverting output terminal (right - terminal) and the non-inverting output terminal (right + terminal), respectively, and two output terminals connected to the first input terminal and the second input terminal of the comparator circuit 18, respectively.

[0047] For example, the first chopper circuit CC1 and the second chopper circuit CC2 can operate together in a predetermined number of cycles, so that the comparator circuit 18 can cancel the offset on the signal transmission path and optimize the comparison result signal Vcomp.

[0048] For example, the aforementioned offset can be the offset generated by the fully differential amplifier FDA, and the specific number of cycles can be four cycles. In the first interval of the four cycles, for example, in the first two cycles, the first chopper circuit CC1 and the second chopper circuit CC2 can be configured to compare the signal at the inverted output terminal (right-side - terminal) with the signal at the non-inverted output terminal (right-side + terminal) according to the first switching signal φ1 and the second switching signal φ2. In the second interval of the four cycles, for example, in the last two cycles, the first chopper circuit CC1 and the second chopper circuit CC2 are configured to switch the comparator circuit 18 to compare the signal at the non-inverted output terminal (right-side + terminal) with the signal at the inverted output terminal (right-side - terminal) according to the first switching signal φ1 and the second switching signal φ2. This achieves the effect of averaging and canceling the offset of the two output terminals, thus optimizing the comparison result signal Vcomp.

[0049] Beneficial effects of the embodiments:

[0050] One beneficial effect of the present invention is that the signal detection circuit provided by the present invention selects the input signal and the reference voltage to enter the amplitude detection circuit and the integration circuit at different stages by using an input switch circuit. Since the circuit shares the same back end, the input signal and the reference voltage will experience the same circuit offset. Therefore, the error caused by process bias when using different paths can be reduced.

[0051] On the other hand, the signal detection circuit provided by the present invention may selectively include a comparator circuit and a chopper circuit to achieve the effect of averaging the offset of the two output terminals and generating an optimized comparison result signal Vcomp as the cumulative result.

[0052] The above-disclosed content is only a preferred embodiment of the present invention, and the scope of patent protection claimed by the present invention is not limited thereto. Therefore, all equivalent technical changes made using the content of the present invention specification and illustrations are within the scope of patent protection claimed by the present invention.

[0053] Explanation of reference numerals in the attached figures:

[0054] 1: Signal detection circuit

[0055] 10: Input switch circuit

[0056] 12: Amplitude Detection Circuit

[0057] 120: Rectifier

[0058] 14: Clock generation circuit

[0059] 16: Integrating Circuit

[0060] 18: Comparator Circuit

[0061] 160: Sampling circuit

[0062] 162: Integrating Amplifier

[0063] C1: First sampling capacitor

[0064] C2: Second sampling capacitor

[0065] CC1: First chopper circuit

[0066] CC2: Second chopper circuit

[0067] Cfb1: First feedback capacitor

[0068] Cfb2: Second feedback capacitor

[0069] comclk: Compare clock signals

[0070] do1: First detection output terminal

[0071] do2: Second detection output terminal

[0072] FDA: Fully Differential Amplifier

[0073] N1: First node

[0074] N2: Second node

[0075] N3: Third Node

[0076] N4: Fourth Node

[0077] o1: First output terminal

[0078] o2: Second output terminal

[0079] Rst: Reset signal

[0080] S1: First switch

[0081] S2: Second switch

[0082] S3: Third switch

[0083] S4: Fourth Switch

[0084] S5: Fifth Switch

[0085] S6: Sixth Switch

[0086] S7: Seventh Switch

[0087] S8: Eighth Switch

[0088] Sr1: First reset switch

[0089] Sr2: Second reset switch

[0090] Sr3: Third reset switch

[0091] SS: Switching signal group

[0092] t1 to t9: Time

[0093] VA: Amplitude Voltage

[0094] Va1: First amplitude voltage

[0095] Va2: Second amplitude voltage

[0096] Vcm: Common-mode voltage

[0097] Vcomp: Comparison result signal

[0098] VIN: Input voltage

[0099] VINN: Second input voltage

[0100] VINP: First input voltage

[0101] VINT: Integral voltage

[0102] VREF: Reference Voltage

[0103] VREFN: Second reference voltage

[0104] VREFP: First reference voltage

[0105] φ1: First switching signal

[0106] φ2: Second switching signal

Claims

1. A signal detection circuit, comprising: An input switching circuit is configured to receive a reference voltage and an input voltage, and is controlled by a switching signal group to selectively output the reference voltage or the input voltage; An amplitude detection circuit is configured to detect the output of the input switch circuit in order to generate a corresponding amplitude voltage. A clock generating circuit is configured to generate the switching signal group, wherein the switching signal group is used to control the input switching circuit to alternately enter a first stage and a second stage, and the input switching circuit is controlled to output the reference voltage in the first stage and output the input voltage in the second stage. An integrating circuit is configured to take the amplitude voltage as input and accumulate it, and generate an integrated voltage corresponding to an accumulation result within a predetermined time interval. The predetermined time interval includes at least one cycle that loops between the first stage and the second stage. The reference voltage is a pair of differential reference voltages, including a first reference voltage and a second reference voltage, and the input voltage is a pair of differential input voltages, including a first input voltage and a second input voltage.

2. The signal detection circuit according to claim 1, characterized in that, The input switch circuit has a first output terminal and a second output terminal, and includes: A first switch is connected to the first output terminal and receives the first reference voltage; A second switch is connected to the first output terminal and receives the first input voltage; A third switch is connected to the second output terminal and receives the second input voltage; A fourth switch is connected to the second output terminal and receives the second reference voltage.

3. The signal detection circuit according to claim 2, characterized in that, The switching signal group includes a first switching signal and a second switching signal. The first switching signal is used to control the first switch and the fourth switch to be turned on in the first stage, and the second switching signal is used to control the second switch and the fourth switch to be turned on in the second stage, so that the input switch circuit outputs the first reference voltage and the second reference voltage at the first output terminal and the second output terminal respectively in the first stage, and outputs the first input voltage and the second input voltage at the first output terminal and the second output terminal respectively in the second stage.

4. The signal detection circuit according to claim 3, characterized in that, The amplitude detection circuit has a first detection output terminal and a second detection output terminal, and is configured to generate amplitude voltages including a first amplitude voltage and a second amplitude voltage at the first detection output terminal and the second detection output terminal respectively, corresponding to the outputs of the first output terminal and the second detection output terminal. The integrating circuit includes: A sampling circuit, configured to sample the first amplitude voltage and the second amplitude voltage in the first phase; and An integrating amplifier is configured to hold the first amplitude voltage and the second amplitude voltage sampled by the sampling circuit in the second stage for accumulation, respectively.

5. The signal detection circuit according to claim 4, characterized in that, The sampling circuit includes: A first sampling capacitor is connected between the first detection output terminal and a first node; A second sampling capacitor is connected between the second detection output terminal and a second node; A fifth switch, one end of which is connected to the first node, and the other end of which receives a common-mode voltage; A sixth switch, one end of which is connected to the second node, and the other end of which receives the common-mode voltage; A seventh switch is connected between the first node and a third node; and An eighth switch is connected between the second node and a fourth node; The integrating amplifier includes: A fully differential amplifier has a non-inverting input, an inverting input, an inverting output, and a non-inverting output, wherein the non-inverting input is connected to the third node, and the inverting input is connected to the fourth node. A first feedback capacitor is connected between the non-inverting input terminal and the inverting output terminal; and A second feedback capacitor is connected between the inverting input terminal and the non-inverting output terminal.

6. The signal detection circuit according to claim 5, characterized in that, The fifth and sixth switches are configured to be controlled by the first switching signal to be turned on in the first stage and turned off in the second stage; the seventh and eighth switches are configured to be controlled by the second switching signal to be turned on in the second stage and turned off in the first stage.

7. The signal detection circuit according to claim 6, characterized in that, The integrating amplifier further includes: A first reset switch is connected between the non-inverting input terminal and the inverting output terminal; A second reset switch is connected between the inverting input terminal and the non-inverting output terminal; and A third reset switch is connected between the third node and the fourth node. The clock generating circuit is further configured to generate a reset signal to control the first reset switch, the second reset switch, and the third reset switch to be turned on during a reset time interval before and after the predetermined time interval, and to be turned off during the predetermined time interval.

8. The signal detection circuit according to claim 7, characterized in that, It also includes a comparator circuit configured to receive and compare the voltages of the inverted output terminal and the non-inverted output terminal through a first input terminal and a second input terminal of the comparator circuit, respectively, to generate a comparison result signal as the cumulative result. The clock generation circuit is further configured to generate a comparison clock signal to control the comparator circuit to generate and output the comparison result signal at the end of the predetermined time interval.

9. The signal detection circuit according to claim 8, characterized in that, Also includes: A first chopper circuit has two input terminals respectively connected to the third node and the fourth node, and two output terminals respectively connected to the non-inverting input terminal and the inverting input terminal; A second chopper circuit has two input terminals respectively connected to the inverting output terminal and the non-inverting output terminal, and two output terminals respectively connected to the first input terminal and the second input terminal of the comparator circuit. The first chopper circuit and the second chopper circuit are configured to cause the comparator circuit to compare the voltage of the inverted output terminal with the voltage of the non-inverted output terminal in a first interval within a predetermined number of the at least one cycle, and to cause the comparator circuit to switch to comparing the voltage of the non-inverted output terminal with the voltage of the inverted output terminal in a second interval within the predetermined number of the at least one cycle.

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