A silicon-based liquid crystal panel and a pixel circuit thereof

Abstract

The application discloses a silicon-based liquid crystal panel and a pixel circuit thereof. The silicon-based liquid crystal panel comprises a plurality of pixel units, and the pixel circuit comprises: a pixel storage array circuit comprising a plurality of Flash memory units connected in one-to-one correspondence with the plurality of pixel units, the Flash memory unit providing a pixel display voltage for the corresponding pixel unit; a driving circuit connected with the Flash memory unit, used for providing a driving signal and a voltage control signal for the Flash memory unit; wherein the Flash memory unit works under the driving of the driving signal and generates the pixel display voltage according to the voltage control signal. In this way, the pixel size can be reduced, and the signal crosstalk problem between adjacent pixels can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits and display technology, in particular to a silicon-based liquid crystal panel and a pixel circuit thereof. BACKGROUND

[0002] Liquid Crystal on Silicon (LCoS) is a reflective projection display device, which controls the deflection of liquid crystal by using semiconductor silicon technology, and then controls the phase distribution of incident light to perform image modulation. Compared with traditional display structures, LCoS has the characteristics of high light utilization efficiency, small size, high aperture ratio, mature manufacturing technology, etc., and can easily achieve high resolution and full color performance. The above advantages make LCoS have great advantages in the field of display applications in the future.

[0003] The LCoS panel includes a CMOS substrate of a complementary metal oxide semiconductor (CMOS) dot matrix arranged on a silicon substrate, and the CMOS substrate is integrated with a memory unit and a driving circuit of a pixel unit. The memory unit of the pixel unit is arranged below a liquid crystal pixel. The existing LCoS panel usually uses a static random access memory (SRAM) or a dynamic random access memory (DRAM) as a storage unit. However, the SRAM and DRAM structures are complex and large in size, resulting in a large size of the pixel unit. Moreover, for the SRAM which usually adopts a digital modulation mode, the difference in modulation signals between adjacent pixel units is easy to cause signal crosstalk. SUMMARY

[0004] The technical problem solved by the present application is to provide a silicon-based liquid crystal panel and a pixel circuit thereof to reduce the size of the pixel and improve the signal crosstalk problem between adjacent pixels.

[0005] To solve the above technical problem, one technical solution adopted by the present application is to provide a pixel circuit of a silicon-based liquid crystal panel. The silicon-based liquid crystal panel includes a plurality of pixel units, and the pixel circuit includes: a pixel storage array circuit including a plurality of Flash memory units connected one-to-one with the plurality of pixel units, the Flash memory unit providing a pixel display voltage for the corresponding pixel unit; a driving circuit connected with the Flash memory unit, used to provide a driving signal and a voltage control signal for the Flash memory unit; wherein the Flash memory unit works under the driving of the driving signal and generates the pixel display voltage according to the voltage control signal.

[0006] In one embodiment, the Flash memory cell includes a substrate and a first gate, a second gate, a source and a drain disposed on the substrate; wherein a driving circuit is connected to the second gate, the source and the drain respectively, the driving circuit provides a voltage control signal to the first gate through the source, the drain and the second gate, and the driving circuit provides a driving signal to the source, the drain and the second gate.

[0007] In one embodiment, the voltage control signal includes a charging voltage, and the driving circuit adjusts a charging time length and / or a charging voltage value of the charging voltage to the first gate to achieve a pixel display voltage.

[0008] In one embodiment, the second gate is disposed on a side of the first gate away from the substrate, the first gate and the second gate are located between the source and the drain, and a projection of the second gate on the substrate is located within a projection of the first gate on the substrate.

[0009] In one embodiment, the silicon-based liquid crystal panel further includes a reflective electrode layer disposed on a side of the second gate away from the substrate, and the first gate is connected to the reflective electrode layer.

[0010] In one embodiment, the silicon-based liquid crystal panel further includes a dielectric layer disposed between the reflective electrode layer and the first gate, the dielectric layer is provided with a through hole, and the first gate is connected to the reflective electrode layer through the through hole.

[0011] In one embodiment, a projection of the pixel storage array circuit on the substrate of the silicon-based liquid crystal panel is located within a projection of the plurality of pixel units on the substrate.

[0012] In one embodiment, the driving signal includes a row driving signal and a column driving signal, and the driving circuit includes a row driving circuit connected to the Flash memory cell, for selectively providing the row driving signal to the Flash memory cell according to a row addressing signal; a column driving circuit connected to the Flash memory cell, for selectively providing the column driving signal and the voltage control signal to the Flash memory cell according to a column addressing signal; and a peripheral logic circuit connected to the row driving circuit and the column driving circuit respectively, for providing the row addressing signal and the row driving signal to the row driving circuit, and providing the column addressing signal, the column driving signal and the voltage control signal to the column driving circuit.

[0013] In one specific embodiment, the plurality of pixel units form an M*N sub-pixel array, the column driving circuit includes M*N column drivers, the row driving circuit includes M*N row drivers, the column drivers are arranged in one-to-one correspondence with the sub-pixel array, and the row drivers are arranged in one-to-one correspondence with the sub-pixel array; all the Flash memory units corresponding to the sub-pixel array are connected to the column driver corresponding thereto through a wire, and the wire of each column driver is electrically isolated from the wires of other column drivers; all the Flash memory units corresponding to the sub-pixel array are connected to the row driver corresponding thereto through a wire, and the wire of each row driver is electrically isolated from the wires of other row drivers; wherein M is a natural number greater than 1, and N is a natural number greater than 1.

[0014] To solve the above technical problems, one technical scheme adopted by the present application is to provide a silicon-based liquid crystal panel. The silicon-based liquid crystal panel comprises a CMOS substrate, a liquid crystal layer, an ITO layer and a cover plate which are sequentially stacked, wherein the CMOS substrate is integrated with the pixel circuit of each of the above embodiments.

[0015] The beneficial effects of the present application are that: the pixel memory unit in the pixel circuit of the silicon-based liquid crystal panel of the present application adopts a Flash memory unit, compared with an SRAM, without needing to control the voltage fluctuation through a pulse width modulation signal by using multiple transistors as the SRAM memory unit to obtain a pixel display voltage, and without needing to obtain an analog voltage signal through a digital-to-analog converter as the DRAM memory unit, the Flash memory unit only needs to control the (floating gate) charging duration to achieve an analog voltage signal; the structure of the Flash memory unit is simple, and the signal interference between adjacent pixels is small, so the pixel size corresponding to the Flash memory unit of the present application is small, so the area of the pixel unit can be designed to be smaller, thereby the size of the silicon-based liquid crystal panel can be reduced, the panel yield of a single wafer can be improved, or a higher resolution panel can be manufactured under the same size, and the signal interference between adjacent pixels can be reduced. BRIEF DESCRIPTION OF DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0017] Figure 1 is a structural schematic diagram of an embodiment of the LCoS panel of the present application;

[0018] Figure 2 is Figure 1 is a structural schematic diagram of an embodiment of the pixel circuit of the LCoS panel of the embodiment;

[0019] Figure 3 is Figure 2 Structure diagram of the flash memory unit and the reflective electrode layer in the pixel circuit of the embodiment;

[0020] Figure 4 is Figure 3 Front view diagram of the partial structure of the flash memory unit and the reflective electrode layer of the embodiment;

[0021] Figure 5 is Figure 3 Side view diagram of the partial structure of the flash memory unit and the reflective electrode layer of the embodiment;

[0022] Figure 6 is Figure 2 Circuit structure diagram of the flash memory unit in the pixel circuit of the embodiment;

[0023] Figure 7 is the circuit structure diagram of the DRAM unit in the existing LCoS panel;

[0024] Figure 8 is the circuit structure diagram of the SRAM unit in the existing LCoS panel;

[0025] Figure 9 is Figure 1 Circuit structure diagram of the LCoS panel of the embodiment. DETAILED DESCRIPTION

[0026] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work are within the scope of protection of the present application.

[0027] The terms “first”, “second” in the present application are only for descriptive purpose, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. In the description of the present application, the meaning of “multiple” is at least two, for example, two, three, etc., unless otherwise explicitly and specifically limited. In addition, the terms “include” and “have” and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device including a series of steps or units is not limited to the listed steps or units, but can optionally include steps or units not listed, or can optionally include other steps or units inherent to the process, method, product or device.

[0028] This application first proposes an LCoS panel comprising multiple pixel units, such as... Figures 1 to 6 As shown, Figure 1 This is a schematic diagram of the structure of an embodiment of the LCoS panel of this application; Figure 2 yes Figure 1 A schematic diagram of the pixel circuit of an embodiment of the LCoS panel; Figure 3 yes Figure 2 A schematic diagram of the structure of the Flash memory cell and reflective electrode layer in the pixel circuit of the embodiment; Figure 4 yes Figure 3 A schematic diagram of a partial structure of a Flash memory cell and a front view of the reflective electrode layer in an embodiment; Figure 5 yes Figure 3 A side view of a portion of the structure of a Flash memory cell and a reflective electrode layer, as shown in the embodiment.

[0029] Figure 6 yes Figure 2 A schematic diagram of the circuit structure of the Flash memory cell in the pixel circuit of this embodiment. The LCoS panel (not shown) of this embodiment includes: a CMOS substrate (not shown), a liquid crystal layer 120, a transparent conductive layer 130, and a light-transmitting cover plate 140 stacked sequentially. The CMOS substrate integrates the pixel circuit 150. The transparent conductive layer 130 is made of, for example, indium tin oxide (ITO), fluorine-doped tin oxide (SnO2:F, FTO), aluminum-doped zinc oxide (ZnO:Al, ZAO), or an indium / antimony / zinc / cadmium oxide.

[0030] LCoS panels replace traditional TFT dot matrices with CMOS dot matrices on a single-crystal silicon substrate; specifically, pixel circuits 150 are integrated on the single-crystal silicon wafer, including driving circuits 151 (including CMOS) and pixel storage array circuits 152 (including CMOS).

[0031] Furthermore, the LCoS panel in this embodiment also includes a reflective electrode layer 170, disposed between the CMOS substrate and the liquid crystal layer 120. The reflective electrode layer 170 can be an aluminum electrode layer, and the pixel electrode layer is made of aluminum to form the reflective electrode layer 170. To prevent strong light from illuminating the channel, a light-blocking layer (not shown) can also be added to the CMOS substrate.

[0032] In one application scenario, the LCoS panel is on a silicon wafer, and the pixel circuit 150 is formed by depositing and etching layers of dielectric and metal layer by layer, and the reflective electrode layer 170 is on the uppermost metal layer, forming a CMOS active matrix substrate, i.e., a CMOS substrate; then the CMOS substrate is bonded with the cover plate 140 (which can be glass) containing the ITO layer 130; then the liquid crystal is pumped in to form the liquid crystal layer 120 between the CMOS substrate and the transparent conductive layer 130, so as to realize the LCoS panel. In other embodiments, the liquid crystal can also be dropped first, and then the cover plate is bonded.

[0033] Further, the LCoS panel further comprises a frame 160 arranged between the ITO layer 130 and the CMOS substrate and located in the peripheral region of the liquid crystal layer 120. The frame 160 is used for encapsulation, support and region separation.

[0034] The LCoS panel is divided into a pixel region (not labeled in the figure), a peripheral region (not labeled in the figure) located at the periphery of the pixel region, and a plurality of pixel units (not labeled in the figure) arranged in the pixel region; the liquid crystal layer 120 is arranged corresponding to the pixel region, and the frame 160 is arranged corresponding to the peripheral region.

[0035] Further, the LCoS panel of the embodiment further comprises a first alignment layer 181 and a second alignment layer 191, the first alignment layer 181 is arranged between the reflective electrode layer 170 and the liquid crystal layer 120, and the second alignment layer 191 is arranged between the liquid crystal layer 120 and the transparent conductive layer 130. The alignment layer is used to give the liquid crystal molecules an initial orientation, so that the orientations of the liquid crystal molecules at different positions in the non-working state are consistent. The material of the alignment layer can be, for example, silicon oxide (SiOx), which is prepared by electron beam evaporation (Electron Beam Evaporation); or the material of the alignment layer can be, for example, polyimide, which is first formed into a coating layer by spraying, chemical vapor deposition or atomic layer deposition, and then a plurality of orientation grooves are formed on the surface of the alignment material coating layer by rubbing process or laser processing process, so as to obtain the alignment layer with alignment ability.

[0036] In the embodiment, the pixel circuit 150 comprises a driving circuit 151 and a pixel storage array circuit 152; the pixel storage array circuit 152 comprises a plurality of Flash memory units 153 corresponding to a plurality of pixel units, and the Flash memory unit 153 provides a pixel display voltage for the corresponding pixel unit; the driving circuit 151 is connected with the Flash memory unit 153, and is used to provide a driving signal and a voltage control signal for the Flash memory unit 153; the Flash memory unit 153 works under the driving of the driving signal, and generates the pixel display voltage according to the voltage control signal.

[0037] The specific structure and working principle of the pixel circuit 150 will be described in detail below.

[0038] Compared with the prior art, the pixel memory unit in the pixel circuit 150 of the LCoS panel in the embodiment adopts a Flash memory unit 153. Unlike an SRAM memory unit, the Flash memory unit 153 does not need to control voltage fluctuations by using multiple transistors through a pulse width modulation signal to obtain a pixel display voltage, and does not need to obtain an analog voltage signal through a digital-to-analog converter like a DRAM memory unit. The Flash memory unit 153 only needs to control the (floating gate) charging time to achieve an analog voltage signal. The structure of the Flash memory unit 153 is simple, and the signal interference between adjacent pixels is small. Therefore, the pixel size corresponding to the Flash memory unit 153 in the present application is small, so that the area of the pixel unit can be designed to be smaller, thereby reducing the size of the LCoS panel, improving the panel yield of a single wafer, or manufacturing a higher resolution panel under the same size, and reducing the signal interference between adjacent pixels.

[0039] Optionally, the Flash memory unit 153 in the embodiment includes a substrate 154, and a first gate 155, a second gate 156, a source 157, and a drain 158 disposed on the substrate 154. The driving circuit 151 is connected with the second gate 156, the source 157, and the drain 158, respectively. The driving circuit 151 provides a voltage control signal for the first gate 155 through the second gate 156, the source 157, and the drain 158. The driving circuit 151 provides a driving signal for the source 157, the drain 158, and the second gate 156.

[0040] The first gate 155 is provided with an insulating layer between the substrate 154 and the second gate 156.

[0041] The second gate 156 is a control gate of the Flash memory unit 153, used to control the working of the Flash memory unit 153. The first gate 155 is a floating gate of the Flash memory unit 153, surrounded by a dielectric layer to form an independent electrode layer, so that the voltage control signal charges and discharges the independent electrode layer to achieve different voltage values of the Flash memory unit 153, i.e., the pixel display voltage.

[0042] The first gate 155 is connected with the fourth metal layer 50 through a conductive column (not labeled in the figure), and the first gate 155 is connected with the reflective electrode layer 170 through the fourth metal layer 50.

[0043] The substrate 154 can be a silicon wafer substrate of a CMOS substrate.

[0044] The voltage control signal of the embodiment includes a charging voltage and a charging time length, and the driving circuit 151 adjusts the charging time length of the charging voltage to the first gate 155 to realize the pixel display voltage. Different voltage controls are realized by adjusting the charging time length of the charging voltage to the first gate 155, so as to control the Flash memory unit 153 to output analog voltage signals with different voltage values.

[0045] In other embodiments, the driving circuit can adjust the charging voltage value of the charging voltage to the first gate 155 to realize the pixel display voltage.

[0046] The data writing time of the Flash memory unit 153 is between microseconds and milliseconds, and the data writing time depends on the driving voltage (voltage value of the driving signal) of the driving circuit 151.

[0047] Optionally, the second gate 156 of the embodiment is arranged on the side of the first gate 155 away from the substrate 154, the first gate 155 and the second gate 156 are located between the source 157 and the drain 158, and the projection of the second gate 156 on the substrate 154 is located within the projection of the first gate 155 on the substrate 154.

[0048] The size of the second gate 156 is smaller than the size of the first gate 155, and the second gate 156 is arranged in an overlapping and spaced manner with the first gate 155.

[0049] Optionally, the LCoS panel of the embodiment further includes: a first metal layer 20 (i.e., a source electrode) connected with the source 157, a second metal layer 30 (i.e., a drain electrode) connected with the drain 158, a third metal layer 40 (i.e., a second gate electrode) connected with the second gate 156, and a fourth metal layer 50 (i.e., a first gate electrode) connected with the first gate 155; wherein the first metal layer 20, the second metal layer 30, the third metal layer 40 and the fourth metal layer 50 can be arranged in the same layer.

[0050] The reflective electrode layer 170 (aluminum electrode layer) of the LCoS panel is arranged on the side of the second gate 156 away from the substrate 154, and the first gate 155 is connected with the reflective electrode layer 170 through the fourth metal layer 50.

[0051] From the above analysis, the size of the second gate 156 is smaller than the size of the first gate 155, the part of the first gate 155 not covered by the second gate 156 is connected with the reflective electrode layer 170, which avoids signal interference or avoids punching of the second gate 156.

[0052] This embodiment of the LCoS panel further includes: a dielectric layer (not shown) disposed between the reflective electrode layer 170 and the first gate electrode 155; the dielectric layer has a via (not shown), and the first gate electrode 155 is connected to the reflective electrode layer 170 through the via. A conductive post (not shown) is provided within the via, and this conductive post can be integrally disposed with the first gate electrode 155 or the reflective electrode layer 170.

[0053] Specifically, the dielectric layer extends between the first gate 155 and the fourth metal layer 50 and between the fourth metal layer 50 and the reflective electrode layer 170. The dielectric layer is provided with a first via (not shown) and a second via (not shown). The first gate 155 and the fourth metal layer 50 are connected through the first via, and the fourth metal layer 50 and the reflective electrode layer 170 are connected through the second via.

[0054] The LCoS panel in this embodiment further includes: other dielectric layers disposed between the source 157 and the first metal layer 20, between the drain 158 and the second metal layer 30, and between the second gate 156 and the third metal layer 40; and multiple dielectric layers and metal layers can be stacked between the reflective electrode layer 170 and the fourth metal layer 50 to realize other structures of the LCoS panel, specifically referring to the structure of existing LCoS panels.

[0055] During their long-term research and development, the inventors of this application discovered that LCoS panels have two main driving methods: analog driving and digital driving. The analog driving method utilizes a DRAM structure to display different grayscale levels of pixels. The input display signal needs to be converted into an analog voltage signal by a digital-to-analog converter (DAC). By controlling the output voltage of the DAC, the pixel voltage is modulated, thereby achieving grayscale display control. The main problems faced by the analog driving method in LCoS display applications are: under CMOS technology, the leakage current of the pixel switching transistors in the off-state is not negligible, resulting in excessively large holding capacitors in the DRAM structure. This leads to a decrease in image refresh rate and occupies too much chip area, reducing screen resolution.

[0056] Digital driving methods typically utilize SRAM structures to display different grayscale levels of pixels by modulating the conduction time of the pixel switching transistors. Since SRAM outputs only maximum and minimum voltage values, the grayscale level of the output image needs to be adjusted by controlling the duty cycle of these maximum and minimum values. While SRAM-based digital driving methods do not require analog-to-digital conversion via a digital-to-analog converter, they do require a very complex and high-speed control interface, thus increasing design complexity and technical costs.

[0057] like Figures 6 to 8 As shown, compared to the Flash memory unit 153 in this embodiment ( Figure 6 ), DRAM Figure 7) has one more capacitor, and its pixel size is larger; and the SRAM has 6 transistors, and its pixel size is larger, and the SRAM needs to use pulse width modulation to obtain an equivalent voltage, and the voltage fluctuates high and low in the operation process, and the voltage difference between adjacent pixels is too large, and crosstalk is easily caused. Figure 8

[0058] Optionally, as shown in Figures 1 to 6 、 Figure 9 The driving signal of the embodiment includes a row driving signal and a column driving signal, and the driving circuit 151 of the embodiment includes a row driving circuit (not shown in the figure), a column driving circuit (not shown in the figure), and a peripheral logic circuit 161; the row driving circuit is connected with the Flash memory unit 153, and is used for selectively providing the Flash memory unit 153 with the row driving signal according to a row addressing signal; the column driving circuit is connected with the Flash memory unit 153, and is used for selectively providing the Flash memory unit 153 with the column driving signal and a voltage control signal according to a column addressing signal; and the peripheral logic circuit 161 is connected with the row driving circuit and the column driving circuit respectively, and is used for providing the row driving circuit with the row addressing signal and the row driving signal, and providing the column driving circuit with the column addressing signal, the column driving signal, and the voltage control signal.

[0059] The projection of the pixel storage array circuit 152 of the embodiment on the substrate (i.e. the substrate of the CMOS substrate) of the LCoS panel is located within the projection of the pixel region on the substrate, and the projection of the Flash memory unit 153 on the substrate overlaps with the projection of the pixel unit on the substrate; the projection of the driving circuit 151 on the substrate is located outside the projection of the pixel region on the substrate, so as to reduce the size of the pixel unit; and the projections of the row driving circuit, the column driving circuit, and the peripheral logic circuit 161 on the substrate are uniformly arranged outside the periphery of the projection of the pixel region on the substrate.

[0060] The pixel region of the embodiment is provided with a pixel array (not shown in the figure), and the pixel array includes a plurality of pixel units (not shown in the figure); the pixel storage array circuit 152 of the embodiment is an array composed of a plurality of Flash memory units 153, and each pixel unit corresponds to one Flash memory unit 153.

[0061] ​Optionally, the column drive circuit of the embodiment comprises a data register 103, an amplifier 104, a high-voltage generating circuit 106 and a column driver 105; the data register 103 is connected with the peripheral logic circuit 161, the column driver 105 and the amplifier 104 respectively, and is used for registering a column addressing signal and a column drive signal; the column driver 105 is further connected with the high-voltage generating circuit 106 and the Flash memory unit 153, and is used for obtaining the column addressing signal and the column drive signal from the data register 103 and obtaining a voltage control signal from the high-voltage generating circuit 106; the Flash memory unit 153 obtains the column addressing signal, the column drive signal and the voltage control signal from the column driver 105; the high-voltage generating circuit 106 is further connected with the peripheral logic circuit 161, and is used for obtaining a control signal from the peripheral logic circuit 161 to generate the voltage control signal; and the amplifier 104 is further connected with the peripheral logic circuit 161, and is used for amplifying at least the column drive signal.

[0062] Optionally, the row drive circuit of the embodiment further comprises a row driver 111 connected with the peripheral logic circuit 161, and used for obtaining a row drive signal and a row addressing signal from the peripheral logic circuit 161.

[0063] The plurality of pixel units of the embodiment form M*N sub-pixel arrays, the column drive circuit comprises M*N column drivers 105, the row drive circuit comprises M*N row drivers 111, the column drivers 105 are arranged in one-to-one correspondence with the sub-pixel arrays, and the row drivers 111 are arranged in one-to-one correspondence with the sub-pixel arrays; all Flash memory units 153 corresponding to a sub-pixel array are connected with the column driver 105 corresponding thereto through a wire, and the wire of each column driver 105 is electrically isolated from the wires of other column drivers 105; and all Flash memory units 153 corresponding to a sub-pixel array are connected with the row driver 111 corresponding thereto through a wire, and the wire of each row driver 111 is electrically isolated from the wires of other row drivers 111.

[0064] Wherein, M is a natural number greater than 1, and N is a natural number greater than 1. Specifically, M of the embodiment is 2, and N is 2; in other embodiments, M and N can be set according to actual needs.

[0065] In other embodiments, one row driver can correspond to multiple sub-pixel arrays, or one column driver can correspond to multiple sub-pixel arrays, or multiple peripheral logic circuits are adopted, etc.

[0066] The source 157 of the Flash memory unit 153 is connected with the row driver 111, and the drain 158 is connected with the column driver 105.

[0067] In other embodiments, the drain of the flash memory cell is connected to the row driver and the source is connected to the column driver.

[0068] Compared with the prior art, the pixel memory unit in the pixel circuit of the LCoS panel of the present application adopts a flash memory unit. Compared with an SRAM memory unit, the flash memory unit does not need to control voltage fluctuations by using multiple transistors through a pulse width modulation signal to obtain a pixel display voltage, nor does it need to obtain an analog voltage signal through a digital-to-analog converter as in a DRAM memory unit. The flash memory unit only needs to control the charging time (of the floating gate) to achieve an analog voltage signal. The structure of the flash memory unit is simple, and the signal interference between adjacent pixels is small. Therefore, the pixel size corresponding to the flash memory unit is small, so the area of the pixel unit can be designed to be smaller, thereby reducing the size of the LCoS panel, improving the panel yield of a single wafer, or manufacturing a higher resolution panel under the same size, and reducing the signal interference between adjacent pixels.

[0069] The above description is merely an embodiment of the present application and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation using the content of the specification and drawings, or direct or indirect application in other related technical fields, is also included in the patent protection scope of the present application.

Claims

1. A pixel circuit of a liquid crystal on silicon panel, characterized by, The silicon-based liquid crystal panel comprises a plurality of pixel units, and the pixel circuit comprises: a pixel storage array circuit comprising a plurality of Flash memory units connected one-to-one with the plurality of pixel units, the Flash memory units providing pixel display voltages for the corresponding pixel units; a driving circuit connected with the Flash memory units, for providing driving signals and voltage control signals for the Flash memory units; wherein the Flash memory units operate under the driving of the driving signals and generate the pixel display voltages according to the voltage control signals.

2. The pixel circuit of claim 1, wherein, The Flash memory unit comprises a substrate and a first gate, a second gate, a source and a drain provided on the substrate; wherein the driving circuit is connected with the second gate, the source and the drain respectively, the driving circuit provides the voltage control signal for the first gate through the source, the drain and the second gate, and the driving circuit provides the driving signal for the source, the drain and the second gate.

3. The pixel circuit of claim 2, wherein, The voltage control signal comprises a charging voltage, and the driving circuit adjusts the charging time and / or the charging voltage value of the charging voltage on the first gate to realize the pixel display voltage.

4. The pixel circuit of claim 2, wherein, The second gate is provided on the side of the first gate away from the substrate, the first gate and the second gate are located between the source and the drain, and the projection of the second gate on the substrate is located within the projection of the first gate on the substrate.

5. The pixel circuit of claim 2, wherein, The silicon-based liquid crystal panel further comprises a reflective electrode layer provided on the side of the second gate away from the substrate, and the first gate is connected with the reflective electrode layer.

6. The pixel circuit of claim 5, wherein, The silicon-based liquid crystal panel comprises a dielectric layer provided between the reflective electrode layer and the first gate, and the dielectric layer is provided with a through hole, and the first gate is connected with the reflective electrode layer through the through hole.

7. The pixel circuit of claim 2, wherein, The projection of the pixel storage array circuit on the substrate of the silicon-based liquid crystal panel is located within the projection of the plurality of pixel units on the substrate.

8. The pixel circuit according to any one of claims 1 to 7, characterized by, The driving signal comprises a row driving signal and a column driving signal, and the driving circuit comprises: a row driving circuit connected with the Flash memory units, for selectively providing the row driving signal for the Flash memory units according to a row addressing signal; a column driving circuit connected with the Flash memory units, for selectively providing the column driving signal and the voltage control signal for the Flash memory units according to a column addressing signal; a peripheral logic circuit connected with the row driving circuit and the column driving circuit respectively, for providing the row addressing signal and the row driving signal for the row driving circuit, and providing the column addressing signal, the column driving signal and the voltage control signal for the column driving circuit.

9. The pixel circuit of claim 8, wherein, The plurality of pixel units form M*N sub-pixel arrays, the column driving circuit comprises M*N column drivers, the row driving circuit comprises M*N row drivers, the column drivers are arranged in one-to-one correspondence with the sub-pixel arrays, and the row drivers are arranged in one-to-one correspondence with the sub-pixel arrays; all the Flash memory units corresponding to the sub-pixel arrays are connected with the column drivers corresponding thereto through wires, and the wires of each column driver are electrically isolated from the wires of other column drivers; all the Flash memory units corresponding to the sub-pixel arrays are connected with the row drivers corresponding thereto through wires, and the wires of each row driver are electrically isolated from the wires of other row drivers. M is a natural number greater than 1, and N is a natural number greater than 1.

10. A silicon-based liquid crystal panel, characterized by, The pixel circuit comprises a CMOS substrate, a liquid crystal layer, an ITO layer and a cover plate which are sequentially stacked, wherein the CMOS substrate is integrated with the pixel circuit according to any one of claims 1 to 9.

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