Semiconductor structure and manufacturing method thereof

Abstract

A semiconductor structure and a method of fabricating the same are disclosed. The semiconductor structure includes a substrate, a stack structure on the substrate, an insulating layer on the stack structure, a passivation layer on the insulating layer, and a contact structure through the passivation layer and the insulating layer and directly contacting the stack structure, wherein the insulating layer includes an extension protruding from a sidewall of the passivation layer and abutting a surface of the stack structure contacted by the contact structure.

Description

Technical Field

[0001] The present invention relates to a semiconductor structure and a manufacturing method thereof, and in particular to a high electron mobility transistor (HEMT) structure and a manufacturing method thereof. Background Art

[0002] High electron mobility transistors (HEMTs) are an emerging type of field-effect transistor (FET). They utilize a potential well formed at a heterojunction by joining semiconductor materials of different band gaps. This well gathers electrons, forming a two-dimensional electron gas (2DEG) that serves as the channel for current flow. Gallium nitride (GaN) compounds, a family of III-V semiconductor compounds, exhibit wide band gaps, high breakdown voltages, strong bonding strengths, thermal stability, and unique spontaneous and piezoelectric polarization properties. These compounds can form a 2DEG with high electron concentration and high electron mobility even in the undoped state, achieving high switching speeds and response frequencies. As a result, they have gradually replaced silicon-based transistors and are widely used in power converters, low-noise amplifiers, and radio frequency (RF) and millimeter wave (MMW) technologies.

[0003] However, existing high electron mobility transistors still encounter some problems. For example, when etching the insulating layer to form the contact structure opening, insufficient etching may result in the insulating layer not being etched through or the insulating layer remaining on the semiconductor material at the bottom of the opening. Excessive etching may cause damage to the semiconductor material, both of which may lead to poor contact problems. Summary of the Invention

[0004] In order to overcome the above problems, an object of the present invention is to provide a semiconductor structure and a manufacturing method thereof, which can have improved contact quality and yield.

[0005] According to one embodiment of the present invention, a semiconductor structure includes a substrate, a stacked structure located on the substrate, an insulating layer located on the stacked structure, a passivation layer located on the insulating layer, and a contact structure passing through the passivation layer and the insulating layer and directly contacting the stacked structure, wherein the insulating layer includes an extension protruding from a side wall of the passivation layer and adjacent to a surface of the stacked structure in contact with the contact structure.

[0006] A method for fabricating a semiconductor structure according to one embodiment of the present invention includes the following steps: First, a stacked structure is formed on a substrate, followed by forming an insulating layer and a passivation layer on the stacked structure. Next, an etching process is performed to form an opening through the passivation layer and the insulating layer, exposing a portion of the stacked structure and an extension of the insulating layer. Next, a contact structure is formed to fill the opening and directly contact the stacked structure, wherein the extension of the insulating layer is adjacent to a surface of the stacked structure that contacts the contact structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 、 Figure 2 and Figure 3 Schematic cross-sectional view of the steps of a method for manufacturing a semiconductor structure according to a first embodiment of the present invention;

[0008] Figure 3A for Figure 3 A partially enlarged schematic diagram of the semiconductor structure shown;

[0009] Figure 3B For semiconductor structures Figure 3 A partially enlarged schematic diagram of another embodiment of the steps shown;

[0010] Figure 4 、 Figure 5 and Figure 6 A schematic cross-sectional view of steps of a method for manufacturing a semiconductor structure according to a second embodiment of the present invention;

[0011] Figure 6A for Figure 6 A partially enlarged schematic diagram of the semiconductor structure shown;

[0012] Figure 6B For semiconductor structures Figure 6 A partially enlarged schematic diagram of another embodiment of the steps shown;

[0013] Figure 7 、 Figure 8 、 Figure 9 、 Figure 10 、 Figure 11 A schematic cross-sectional view of steps of a method for manufacturing a semiconductor structure according to a third embodiment of the present invention;

[0014] Figure 8A for Figure 8 A partially enlarged schematic diagram of the semiconductor structure shown;

[0015] Figure 8B For semiconductor structures Figure 8 A partially enlarged schematic diagram of another embodiment of the steps shown.

[0016] Description of main component symbols

[0017] 101 laminated structure

[0018] 102 base

[0019] 103 buffer layer

[0020] 104 Channel Layer

[0021] 106 Barrier layer

[0022] 108 gate layer

[0023] 126 insulation layer

[0024] 128 passivation layer

[0025] 132 contact structure

[0026] 140 Opening

[0027] 142 Contact structure

[0028] 152 passivation layer

[0029] 160 Opening

[0030] 162 electrodes

[0031] 106S surface

[0032] 106T top surface

[0033] 108a semiconductor gate layer

[0034] 108b Metal gate layer

[0035] 108S surface

[0036] 108T top surface

[0037] 126a Extension

[0038] 128W sidewall

[0039] 132a Lining

[0040] 132b Metal layer

[0041] 142a Lining

[0042] 142b Metal layer

[0043] 162a Lining

[0044] 162b Metal layer

[0045] E1 Etching Process

[0046] R1 gate region

[0047] R2 source / drain region DETAILED DESCRIPTION

[0048] To help those skilled in the art better understand the present invention, the following lists preferred embodiments of the present invention and, in conjunction with the accompanying drawings, details the components and intended effects of the present invention. It should be noted that the features of the following embodiments may be replaced, recombined, or combined to create other embodiments without departing from the spirit of the present disclosure.

[0049] Figure 1 、 Figure 2 and Figure 3 Illustrated is a schematic cross-sectional view of steps in a method for manufacturing a semiconductor structure according to a first embodiment of the present invention. Figure 3A for Figure 3 A partially enlarged schematic diagram of the semiconductor structure shown. Figure 3B For semiconductor structures Figure 3 A partially enlarged schematic diagram of another embodiment of the steps shown. Figure 1 First, a substrate 102 is provided, such as a silicon substrate, a silicon carbide (SiC) substrate, a sapphire substrate, a gallium nitride substrate, an aluminum nitride substrate, or a substrate formed of other suitable materials. Subsequently, a stacked structure 101 is formed on the substrate 102, which may include a buffer layer 103, a channel layer 104, and a barrier layer 106 in order from the bottom (close to the substrate 102) to the top (away from the substrate). The stacked structure 101 may include a gate region R1 and source / drain (S / D) regions R2 located on both sides of the gate region R1. In some embodiments, when the semiconductor structure is an enhancement mode high electron mobility transistor, the gate region R1 of the stacked structure 101 may further include a gate layer 108.

[0050] The buffer layer 103, the channel layer 104, the barrier layer 106 and the gate layer 108 are sequentially formed on the substrate 102 by a heteroepitaxy growth process, and then the gate layer 108 is patterned, for example, by a photolithography and etching process, to remove the gate layer 108 outside the gate region R1, to obtain the following: Figure 1Applicable heteroepitaxial growth techniques include, but are not limited to, molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), and hydride vapor phase deposition (HVPE).

[0051] The buffer layer 103, channel layer 104, barrier layer 106, and gate layer 108 may each comprise a III-V semiconductor compound material, such as, but not limited to, gallium nitride (GaN), aluminum gallium nitride (AlGaN), graded aluminum gallium nitride (graded AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), aluminum gallium indium nitride (AlGaInN), doped gallium nitride (dopedGaN), aluminum nitride (AlN), or a combination thereof. According to one embodiment of the present invention, the buffer layer 103 may comprise aluminum gallium nitride (AlGaN), the channel layer 104 may comprise gallium nitride (GaN), the barrier layer 106 may comprise aluminum gallium nitride (AlGaN), and the gate layer 108 may comprise magnesium (Mg), iron (Fe), or other suitably doped p-type gallium nitride (p-GaN). The thickness of the gate layer 108 may be between three and twelve times the thickness of the barrier layer 106. For example, in some embodiments, the thickness of the gate layer 108 may be between 60 nm and 100 nm, and the thickness of the barrier layer 106 may be between 8 nm and 20 nm, but the present invention is not limited thereto.

[0052] Please continue to refer to Figure 1After patterning the gate layer 108, an insulating layer 126 is then formed on the stacked structure 101 to conformally cover the sidewalls and top surface 108T of the gate layer 108. A passivation layer 128 is then formed on the insulating layer 126. The materials of the insulating layer 126 and the passivation layer 128 may include insulating materials, such as, but not limited to, aluminum nitride (AlN), aluminum oxide (Al2O3), boron nitride (BN), silicon nitride (Si3N4), silicon oxide (SiO2), zirconium oxide (ZrO2), hafnium oxide (HfO2), lanthanum oxide (La2O3), lutetium oxide (Lu2O3), lanthanum lutetium oxide (LaLuO3), high-k dielectric materials, or other suitable insulating materials. By combining the materials of the insulating layer 126 and the passivation layer 128, the leakage current of the high electron mobility transistor can be reduced and the breakdown voltage and output power can be improved. According to one embodiment of the present invention, the insulating layer 126 may be made of aluminum oxide (Al2O3) with a thickness ranging from approximately 2.5 nm to 10 nm. The passivation layer 128 may be made of silicon oxide (SiO2) and / or silicon nitride (Si3N4) with a thickness ranging from approximately 150 nm to 2500 nm, but is not limited thereto.

[0053] Please refer to Figure 2 A patterned mask layer (not shown) may then be formed on the passivation layer 128. An etching process E1, such as reactive-ion etching (RIE) or inductively coupled plasma (ICP) etching, may then be performed using the patterned mask layer as a mask to form an opening 130 that penetrates the passivation layer 128 and the insulating layer 126 and exposes a surface 108S of the gate layer 108. It is worth noting that to avoid poor contact caused by the insulating layer 126 not being etched through or the insulating layer 126 remaining at the bottom of the opening 130, and to reduce damage to the gate layer 108 caused by overetching of the gate layer 108 by the etching process E1, the present invention particularly utilizes a fluorine (F)-containing gas, such as, but not limited to, at least one of SF6, CF4, CHF3, C3F6, C2F6, and NF3, as the etching gas in the etching process E1, and does not utilize a chlorine (Cl)-containing gas, to achieve better etching results. According to an embodiment of the present invention, the process temperature of the etching process E1 is preferably controlled between -15° C. and 35° C., and the pressure of the etching chamber is preferably controlled between 30 mtorr and 1300 mtorr.

[0054] like Figure 2As shown, the surface 108S of the gate layer 108 exposed from the opening 130 has a recessed profile lower than the top surface 108T, and the depth of the recess can be controlled to be within a range of no more than 5 nm, for example, between 1 nm and 2 nm. It is worth noting that, through the selection of etching gas in the aforementioned etching process E1, an extension 126a is formed in the portion of the insulating layer 126 adjacent to the bottom edge of the opening 130, protruding from the sidewall 128W of the passivation layer 128 and extending along the top surface 108T.

[0055] Please refer to Figure 3 Then, a conductive layer (not shown) is formed on the passivation layer 128 and the conductive layer is filled into the opening 130 so as to be in direct contact with the gate layer 108. The conductive layer is then patterned to obtain the contact structure 132. According to one embodiment of the present invention, the contact structure 132 may include a liner 132a and a metal layer 132b located on the liner 132a. The liner 132a is in direct contact with the gate layer 108, the insulating layer 126, and the passivation layer 128. This improves the bonding between the metal layer 132b and the passivation layer 128, the insulating layer 126, and the gate layer 108, and can also be used to prevent the material of the metal layer 132b from being squeezed out or diffused to the outside, thereby affecting the reliability of the device. The materials of the liner 132a and the metal layer 132b may include, but are not limited to, aluminum (Al), silver (Ag), gold (Au), copper (Cu), nickel (Ni), titanium (Ti), tantalum (Ta), tungsten (W), cobalt (Co), molybdenum (Mo), palladium (Pd), platinum (Pt), compounds of the above materials, composite layers, or alloys. According to one embodiment of the present invention, the liner 132a may include titanium nitride (TiN), and the metal layer 132b may include aluminum (Al). In this embodiment, a Schottky contact is formed between the contact structure 132 and the gate layer 108.

[0056] Please continue to refer to Figure 3 The semiconductor structure provided in the first embodiment of the present invention may include a substrate 102, a stacked structure 101 located on the substrate 102, an insulating layer 126 located on the stacked structure 101, and a passivation layer 128 located on the insulating layer 126. The stacked structure 101 includes, from bottom (adjacent to the substrate 102) to top (away from the substrate 102), a buffer layer 103, a channel layer 104, a barrier layer 106, and a gate layer 108. A contact structure 132 passes through the passivation layer 128 and the insulating layer 126 and directly contacts the gate layer 108 of the stacked structure 101.

[0057] Please refer to Figure 3A. Looking at the details in detail, the surface 108S of the gate layer 108 in contact with the contact structure 132 has a recessed profile that is lower than the top surface 108T. The extension 126a of the insulating layer 126 is adjacent to the bottom edge of the contact structure 132 and protrudes from the sidewall 128W of the passivation layer 128, extending along the top surface 108T of the gate layer 108 to the edge of the surface 108S adjacent to the gate layer 108 (i.e., the junction between the top surface 108T and the surface 108S). In other words, the profile of the surface 108S of the gate layer 108 generally starts from the end point of the extension 126a and is recessed downward and is lower than the top surface 108T and the extension 126a. According to one embodiment of the present invention, the surface of the extension 126a in contact with the contact structure 132 and the surface 108S of the gate layer 108 may have a continuous arc-shaped profile.

[0058] According to another embodiment of the present invention, Figure 3B As shown, the etch selectivity of the etching process E1 for the insulating layer 126 can be further adjusted so that the extension 126a protrudes further from the sidewall 128W of the passivation layer 128 and extends beyond the interface between the top surface 108T and the surface 108S of the gate layer 108. The liner 132a can be configured to completely fill the gap 127 between the extension 126a and the surface 108S of the gate layer 108, or it can be configured to partially fill the gap 127, forming an air gap (not shown). The extension 126a can modulate the electric field in the surrounding area, thereby increasing the device's threshold voltage and reducing gate leakage current, thereby improving the device's high-frequency performance.

[0059] The following describes various embodiments of the present invention. To simplify the description, the following description focuses on the differences between the embodiments and does not reiterate the similarities. Identical elements in each embodiment are designated with the same reference numerals to facilitate comparison between the embodiments.

[0060] Figure 4 、 Figure 5 and Figure 6 Illustrated is a schematic cross-sectional view of steps in a method for manufacturing a semiconductor structure according to a second embodiment of the present invention. Figure 6A for Figure 6 A partially enlarged schematic diagram of the semiconductor structure shown. Figure 6B For semiconductor structures Figure 6 A partially enlarged schematic diagram of another embodiment of the steps shown. The main difference between this embodiment and the first embodiment is that the gate layer may include a semiconductor gate layer and a metal gate layer located on the semiconductor gate layer.

[0061] Please refer to Figure 4The semiconductor structure may include a substrate 102, a stacked structure 101 located on the substrate 102, an insulating layer 126 located on the stacked structure 101, and a passivation layer 128 located on the insulating layer 126. The stacked structure 101 may include a buffer layer 103, a channel layer 104, a barrier layer 106, and a gate layer 108, wherein the gate layer 108 includes a semiconductor gate layer 108a and a metal gate layer 108b located on the semiconductor gate layer 108a. The material of the semiconductor gate layer 108a may include a III-V semiconductor compound material, for example, p-type gallium nitride (p-GaN) containing magnesium (Mg), iron (Fe), or other suitable doping. The material of the metal gate layer 108b may include aluminum (Al), silver (Ag), gold (Au), copper (Cu), nickel (Ni), titanium (Ti), tantalum (Ta), tungsten (W), cobalt (Co), molybdenum (Mo), palladium (Pd), platinum (Pt), compounds of the above materials, composite layers, or alloys, but is not limited thereto. According to one embodiment of the present invention, the metal gate layer 108b may include titanium nitride (TiN). The thickness ratio of the semiconductor gate layer 108a and the metal gate layer 108b can be adjusted as needed. Preferably, the thickness of the semiconductor gate layer 108a is approximately 1.5 times to 10 times the thickness of the metal gate layer 108b. For example, in some embodiments, the thickness of the semiconductor gate layer 108a may be between 60nm and 100nm, and the thickness of the metal gate layer 108b may be between 10nm and 40nm, but is not limited thereto. The metal gate layer 108b may be formed on the semiconductor gate layer 108a by chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD) manufacturing process, and then the metal gate layer 108b and the semiconductor gate layer 108a are simultaneously patterned by a patterning process (such as a photolithography and etching process) to obtain the following. Figure 4 In this embodiment, the top surface 108T of the gate layer 108 is equal to the top surface of the metal gate layer 108b.

[0062] Please refer to Figure 5An etching process E1 is then performed to form an opening 130 that penetrates the passivation layer 128 and the insulating layer 126 over the gate region R1 and exposes the surface 108S of the gate layer 108 (in this embodiment, the surface 108S also serves as the surface of the metal gate layer 108b). By using a fluorine (F)-containing gas as the etching gas in etching process E1 and omitting a chlorine (Cl)-containing gas, the surface 108S of the metal gate layer 108b exposed through the opening 130 can have a recessed profile that is lower than the top surface 108T. The depth of the recess can be controlled to be within a range of no greater than 5 nm, for example, between 1 nm and 2 nm. In this embodiment, the portion of the insulating layer 126 adjacent to the bottom edge of the opening 130 may also have an extension 126a that protrudes from the sidewall 128W of the passivation layer 128 and extends along the top surface 108T (in this embodiment, the top surface 108T also serves as the top surface of the metal gate layer 108b).

[0063] Please refer to Figure 6 and Figure 6A Then, a conductive layer (not shown) is formed on the passivation layer 128 and fills the opening 130 to directly contact the metal gate layer 108b. Then, the excess portion of the conductive layer (not shown) is removed by a patterning process to obtain a contact structure 132. Figure 6A As shown, the surface 108S of the metal gate layer 108b in contact with the contact structure 132 has a concave profile lower than the top surface 108T. The extension 126a of the insulating layer 126 is adjacent to the bottom edge of the contact structure 132 and protrudes from the side wall 128W of the passivation layer 128, extending along the top surface 108T of the metal gate layer 108b to the edge of the surface 108S adjacent to the metal gate layer 108b. According to one embodiment of the present invention, the surface of the extension 126a in contact with the contact structure 132 and the top surface 108T of the metal gate layer 108b may have a continuous arc profile. In this embodiment, a metal gate layer 108b is provided on the semiconductor gate layer 108a as a bonding layer between the contact structure 132, which can improve the quality of the electrical connection with the contact structure 132, and can also provide protection for the semiconductor gate layer 108a during the etching process E1. More importantly, compared to Figure 3 The Schottky contact of the first embodiment is formed between the etched surface 108S of the gate layer 108 and the contact structure 132. The Schottky contact of this embodiment is formed between the deposition surfaces of the semiconductor gate layer 108a and the metal gate layer 108b, and can have more stable quality.

[0064] In other embodiments, Figure 6BAs shown, the etch selectivity of the etching process E1 for the insulating layer 126 can be further adjusted so that the extension 126a protrudes further from the sidewalls 128W of the passivation layer 128 and extends beyond the interface between the top surface 108T and the surface 108S of the metal gate layer 108b. The liner 132a can be configured to completely fill the gap 127 between the extension 126a and the surface 108S of the metal gate layer 108b, or it can be configured to partially fill the gap 127, forming an air gap (not shown). The extension 126a can modulate the electric field in the surrounding area, thereby increasing the device's threshold voltage and reducing gate leakage current.

[0065] Figure 7 、 Figure 8 、 Figure 9 、 Figure 10 、 Figure 11 Illustrated is a schematic cross-sectional view of steps in a method for manufacturing a semiconductor structure according to a third embodiment of the present invention. Figure 8A for Figure 8 A partially enlarged schematic diagram of the semiconductor structure shown. Figure 8B For semiconductor structures Figure 8 A partially enlarged schematic diagram of another embodiment of the steps shown. The main difference between this embodiment and the first embodiment is that the semiconductor structure further includes a source / drain contact structure provided in the source / drain region.

[0066] Please refer to Figure 7 After forming the stacked structure 101, the insulating layer 126, and the passivation layer 128 on the substrate 102, an etching process E1 is then performed to form openings 140 on both sides of the gate layer 108, penetrating the passivation layer 128 and the insulating layer 126 on the source / drain region R2 and exposing a surface 106S of the barrier layer 106. By using a fluorine (F)-containing gas as an etching gas and not using a chlorine (Cl)-containing gas in the etching process E1, the surface 106S of the barrier layer 106 exposed from the opening 140 can have a concave profile lower than the top surface 106T of the barrier layer 106, and the depth of the concave can be controlled to be within a range of no more than 5 nm, for example, between 1 nm and 2 nm. By selecting the etching gas in the etching process E1 , an extension portion 126 a is obtained in the portion of the insulating layer 126 adjacent to the bottom edge of the opening 140 , protruding from the sidewall 128W of the passivation layer 128 and extending along the top surface 106T of the barrier layer 106 .

[0067] Please refer to Figure 8 and Figure 8A, then a conductive layer (not shown) is formed on the passivation layer 128 and fills the opening 140 to directly contact the barrier layer 106, and then the excess portion of the conductive layer (not shown) is removed using a patterning process to obtain a contact structure 142. According to one embodiment of the present invention, the contact structure 142 may include a liner 142a and a metal layer 142b located on the liner 142a, wherein the liner 142a is in direct contact with the barrier layer 106, the insulating layer 126, and the passivation layer 128, which can improve the bonding between the metal layer 142b and the passivation layer 128, the insulating layer 126, and the barrier layer 106, and can also be used to inhibit the material of the metal layer 142b from being squeezed out or diffused to the outside and affecting the reliability of the device. The materials of the liner 142a and the metal layer 142b can refer to the materials of the liner 132a and the metal layer 132b mentioned above and will not be repeated here. In this embodiment, an ohmic contact is included between the contact structure 132 and the barrier layer 106. Zoom in to see the details, Figure 8A As shown, a surface 106S of the barrier layer 106 in contact with the contact structure 142 has a recessed profile that is lower than the top surface 106T. An extension 126a of the insulating layer 126 is located adjacent to the bottom edge of the contact structure 142 and protrudes from the sidewall 128W of the passivation layer 128, extending along the top surface 106T of the barrier layer 106 to the edge of the adjacent surface 106S. According to one embodiment of the present invention, the surface of the extension 126a in contact with the contact structure 142 and the top surface 106T of the barrier layer 106 may have a continuous curved profile.

[0068] In other embodiments, Figure 8B As shown, the etch selectivity of the etching process E1 on the insulating layer 126 can be further adjusted so that the extension 126a protrudes further from the sidewall 128W of the passivation layer 128 and extends beyond the interface between the top surface 106T and the surface 106S of the barrier layer 106. The liner 142a can be configured to completely fill the gap 127 between the extension 126a and the surface 106S of the barrier layer 106, or it can be configured to partially fill the gap 127, forming an air gap (not shown). The extension 126a can modulate the electric field in the surrounding area, thereby reducing source / drain leakage current and improving the high-frequency performance of the device.

[0069] Please refer to Figure 9 Then, another passivation layer 152 is formed on the passivation layer 128 and covers the contact structure 142. The material of the passivation layer 152 is described above with reference to the passivation layer 128 and will not be repeated here. The materials of the passivation layer 152 and the passivation layer 128 can be the same or different.

[0070] Please refer to Figure 10. Then, the etching process E1 is performed again to form an opening 130 that passes through the passivation layer 152, the passivation layer 128, and the insulating layer 126 on the gate region R1 and exposes a surface 108S of the gate layer 108. At the same time, openings 160 are formed on both sides of the opening 130 that pass through the passivation layer 152 on the source / drain region R2 and expose the surface of the contact structure 142. With reference to the foregoing, the surface 108S of the gate layer 108 has a recessed profile that is lower than the top surface 108T. The portion of the insulating layer 126 adjacent to the bottom edge of the opening 130 may have an extension 126a that protrudes from the sidewall 128W of the passivation layer 128 and extends along the top surface 108T.

[0071] Please refer to Figure 11 Then, another conductive layer (not shown) is formed on the passivation layer 152 and the conductive layer is filled into the opening 130 and the opening 160, and is in direct contact with the gate layer 108 and the contact structure 142, respectively. Then, the conductive layer is patterned to form the contact structure 132 and the electrode 162 in the gate region R1 and the source / drain region R2, respectively. Figure 11 As shown, electrode 162 may include a liner 162a and a metal layer 162b located on liner 162a. The materials of liner 162a and metal layer 162b can refer to the description of liner 132a and metal layer 132b above, and will not be repeated here. According to one embodiment of the present invention, liner 132a and liner 162a may include the same material, and metal layer 162b and metal layer 132b may include the same material.

[0072] In summary, the semiconductor structure and its fabrication method provided by the present invention utilize a fluorine (F)-containing gas as the etching gas during the etching step for forming the contact structure opening, rather than a chlorine (Cl)-containing gas. This ensures that the insulating layer at the bottom of the opening can be completely removed without overetching or damaging the material layers of the stacked structure (e.g., gate layer 108, gate conductive layer 108b, and barrier layer 106), thereby reducing contact failures caused by incomplete etching of the insulating layer or residual insulating layer at the bottom of the opening. Furthermore, an extension of the insulating layer can be formed adjacent to the bottom edge of the contact structure 132, thereby reducing leakage current and improving the high-frequency performance of the device.

[0073] The above descriptions are merely preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A semiconductor structure, characterized in that include: substrate; a laminated structure located on the substrate; an insulating layer located on the laminate structure; a passivation layer located on the insulating layer; as well as An opening is formed through the passivation layer and the insulating layer and exposing the stacked structure by an etching process containing fluorine (F) gas and not containing chlorine (Cl) gas, A contact structure is located in the opening and directly contacts the stacked structure, wherein the insulating layer includes an extension portion protruding from the sidewall of the passivation layer and adjacent to the surface of the stacked structure in contact with the contact structure, wherein the liner of the contact structure directly covers the bottom and top surfaces of the extension portion. 2 . The semiconductor structure as claimed in claim 1 , wherein a material of the insulating layer comprises aluminum oxide, and a material of the passivation layer comprises silicon oxide or silicon nitride.

3. The semiconductor structure according to claim 1 , wherein the stacked structure comprises: buffer layer; a channel layer located on the buffer layer; a barrier layer, located on the channel layer; as well as The gate layer is located on the barrier layer and directly contacts the contact structure. 4 . The semiconductor structure as claimed in claim 3 , wherein materials of the buffer layer, the channel layer, and the barrier layer respectively comprise Group III-V semiconductor compounds. 5 . The semiconductor structure of claim 3 , wherein a material of the buffer layer comprises carbon-doped gallium nitride (GaN:C), a material of the channel layer comprises gallium nitride (GaN), and a material of the barrier layer comprises aluminum gallium nitride (AlGaN). 6 . The semiconductor structure according to claim 3 , wherein the gate layer comprises a semiconductor gate layer directly contacting the extension portion and the contact structure, and a material of the semiconductor gate layer comprises a P-type doped Group III-V semiconductor compound.

7. The semiconductor structure according to claim 3 , wherein the gate layer comprises: a semiconductor gate layer located on the barrier layer; and The metal gate layer is located on the semiconductor gate layer and directly contacts the extension portion and the contact structure. 8 . The semiconductor structure as claimed in claim 7 , wherein a material of the semiconductor gate layer comprises a P-type doped Group III-V semiconductor compound, and a material of the metal gate layer comprises titanium nitride (TiN).

9. The semiconductor structure according to claim 1 , wherein the stacked structure comprises: buffer layer; a channel layer located on the buffer layer; as well as The barrier layer is located on the channel layer and directly contacts the contact structure. 10 . The semiconductor structure as claimed in claim 1 , wherein the surface of the stacked structure is lower than the extending portion of the insulating layer.

11. A method for manufacturing a semiconductor structure, comprising: forming a laminated structure on a substrate; forming an insulating layer on the laminated structure; forming a passivation layer on the insulating layer; Performing an etching process to form an opening through the passivation layer and the insulating layer and exposing a portion of the stacked structure and an extension of the insulating layer; forming a liner to conformally cover the sidewalls of the opening, the top and bottom surfaces of the extension, and the top surface of the stacked structure; as well as forming a metal layer on the liner and filling the opening, The etching process uses a fluorine (F)-containing gas and does not use a chlorine (Cl)-containing gas.

12. The method for fabricating a semiconductor structure according to claim 11, wherein the etching process comprises using at least one of SF6, CF4, CHF3, C3F6, C2F6, and NF3 as an etching gas. 13 . The method for manufacturing a semiconductor structure according to claim 11 , wherein a material of the insulating layer comprises aluminum oxide, and a material of the passivation layer comprises silicon oxide or silicon nitride.

14. The method for manufacturing a semiconductor structure according to claim 11 , wherein the step of forming the stacked structure comprises: forming a buffer layer on the substrate; forming a channel layer on the buffer layer; and A barrier layer is formed on the channel layer, wherein the barrier layer directly contacts the extension portion and the liner. 15 . The method for fabricating a semiconductor structure according to claim 14 , wherein materials of the buffer layer, the channel layer, and the barrier layer respectively comprise Group III-V semiconductor compounds.

16. The method for manufacturing a semiconductor structure according to claim 11 , wherein the step of forming the stacked structure comprises: forming a buffer layer on the substrate; forming a channel layer on the buffer layer; forming a barrier layer on the channel layer; as well as A gate layer is formed on the barrier layer, wherein the gate layer directly contacts the extension portion and the liner. 17 . The method for manufacturing a semiconductor structure according to claim 16 , wherein the gate layer comprises a semiconductor gate layer, and a material of the semiconductor gate layer comprises a P-type doped Group III-V semiconductor compound.

18. The method for manufacturing a semiconductor structure according to claim 16, wherein the gate layer comprises: a semiconductor gate layer located on the barrier layer; and The metal gate layer is located on the semiconductor gate layer and directly contacts the extension portion and the liner. 19 . The method for fabricating a semiconductor structure according to claim 18 , wherein a material of the semiconductor gate layer comprises a P-type doped Group III-V semiconductor compound, and a material of the metal gate layer comprises titanium nitride (TiN).

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