Voltage multiplier circuit

Abstract

Embodiments of this disclosure relate to a voltage multiplier circuit. In one embodiment, the voltage multiplier includes an input node, an output node, and first and second control nodes for receiving first and second clock signals defining two commutation states. An ordered sequence of intermediate nodes is coupled between the input and output nodes and includes two ordered subsequences. Capacitors are coupled: between each odd-numbered intermediate node in the first subsequence and the first control node; between each even-numbered intermediate node in the first subsequence and the second control node; between each odd-numbered intermediate node in the second subsequence and the corresponding odd-numbered intermediate node in the first subsequence; and between each even-numbered intermediate node in the second subsequence and the corresponding even-numbered intermediate node in the first subsequence. The circuit includes selectively conductive electronic components coupled to the intermediate nodes.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Italian patent application No. 102021000012167 entitled “Voltage Multiplier Circuit”, filed on May 12, 2021, which is incorporated herein by reference. Technical Field

[0003] This disclosure generally relates to electronic systems and methods, and in certain embodiments, to voltage multiplier circuits. Background Technology

[0004] Voltage multiplier circuits are known in the art and have been the subject of extensive work disclosed, for example, by the documents cited in the following list of references:

[0005] [Schenkel] M.Schenkel, "Eine neue schaltung fur die erzeugung holdergleichspannungen," Elektrotechnische Zeitschrift, vol.40, no.28, pp.333-335, July1919;

[0006] [Cockcroft]JD Cockcroft and ET Walton, "Experiments with HighVelocity Positive Ions.-(I)Further Developments in the Method of ObtainingHigh Velocity Positive Ions," Proc.Roy.Soc.,A,vol.136,pp.619-630,1932;

[0007] [Luscher] J. Luscher, "Arrangements for biasing the substrate of anintegrated circuit," USPatent 3 845 331, 1974;

[0008] [Dickson] J.F. Dickson, “On-chip high-voltage generation in MNOS integrated circuits using an improved voltage multiplier technique,” IEEE J. Solid-State Circuits, vol. SC-11, pp. 374-378, June 1976;

[0009] [Storti] S. Storti, F. Consiglieri and M. Paparo, “A 30-A 30-V motor controller and driver,” IEEE J. Solid-State Circuits, vol. 23, no. 6, pp. 1394-1401, Dec. 1988;

[0010] [Hobrecht] S. Hobrecht, “An intelligent BiCMOS / DMOS quad 1-A high-side switch,” IEEE J. Solid-State Circuits, vol. 25, no. 6, pp. 1395-1402, Dec. 1990;

[0011] [Wong] S.L. Wong, S. Venkitasubrahmanian, M.J. Kim and J.C. Young, “Design of a 60-V 10-A intelligent power switch using standard cells,” IEEE J. Solid-State Circuits, vol. 27, no. 3, pp. 429-432, March 1992;

[0012] [Gariboldi 94] R. Gariboldi and F. Pulvirenti, “A monolithic quad line driver for industrial applications,” IEEE J. Solid-State Circuits, vol. 29, no. 8, pp. 957-962, Aug. 1994;

[0013] [Gariboldi 96]R. Gariboldi and F. Pulvirenti, “A 70mohm intelligent highside switch with full diagnostics,” IEEE J. Solid-State Circuits, vol. 31, no. 7, pp. 915-923, July 1996;

[0014] [Baveno]F. Pulvirenti, P. Milazzo and R. Ursino, “Charger power switch for mobile phones,” in Proc. 2 nd IEEE-CAS R8 Workshop, 1997, pp. 97-100;

[0015] [Gerber]B. Gerber, J. C. Martin and J. Fellrath, “A 1.5V single-supply one-transistor CMOS EEPROM,” IEEE J. Solid-State Circuits, vol. SC-16, no. 3, pp. 195-200, June 1981;

[0016] [Witters]J. S. Witters, G. Groeseneken and H. E. Maes, “Analysis and modeling of on-chip high voltage generator circuits for use in EEPROM circuits,” IEEE J. Solid-State Circuits, vol. 24, no. 5, pp. 1342-1380, October 1989;

[0017] [Umezawa]A. Umezawa et al. “A 5-V-only operation 0.6-um flash EEPROM with row decoder scheme in triple-well structure,” IEEE J. Solid-State Circuits, vol. 27, no. 11, pp. 1540-1546, November 1992;

[0018] [Jinbo]T. Jinbo et al., “A 5-V-only 16-Mb flash memory with sector erase mode,” IEEE J. Solid-State Circuits, vol. 27, no. 11, pp. 1547-1554, November 1992;

[0019] [Atsumi]S. Atsumi et al., “A 16-Mb flash EEPROM with new self-data-refresh scheme for a sector erase operation,” IEEE J. Solid-State Circuits, vol. 29, no. 4, pp. 461-469, April 1994;

[0020] [Calligaro 1]C. Calligaro, P. Malcovati and G. Torrelli, “Voltage multiplier with output stabilization,” in Proc. 2 nd IEEE-CAS R8 Workshop, 1997, pp. 97-100;

[0021] [Calligaro 2]C. Calligaro et al., “Positive and negative CMOS voltage multiplier for 5-V-only flash memories,” in Proc. 2 nd IEEE-CAS R8 Workshop, 1997, pp. 97-100;

[0022] [Monna]G. L. E. Monna et al, “Charge pump for optimal dynamic range filters,” in Proc. Iscas’94, 1994, pp. 747-750;

[0023] [Berkhout]M. Berkhout, G. van Steenwijk and A. J. M. van Tuijl, “A low-ripple charge pump circuit for high voltage applications,” in Proc. ESSCIRC’93, 1993, pp. 290-293;

[0024] [Wang]C.C. Wang and J.C. Wu, “Efficiency improvement in charge pump circuits,” IEEE J. Solid - State Circuits, vol. 32, no. 6, pp. 852 - 860, June 1997;

[0025] [Steenwijk]G. van Steenwijk, K. Hoen and Hans Wallinga, “Analysis and design of a charge pump circuit for high output current applications,” in Proc. ESSCIRC’93, 1993, pp. 118 - 121;

[0026] [Gasparini]F. Gasparini and G. Zingales, “Sul funzionamento dei moltiplicatori di tensione a raddrizzatori e condensatori,” L’Elettrotecnica, vol. 46, no. 11, pp. 742 - 753, November 1959;

[0027] [Weiner]M.M. Weiner, “Analysis of Cockcroft - Walton voltage multipliers with an arbitrary number of stages,” The Review of Scientific Instruments, vol. 40, no. 2, pp. 330 - 333, February 1969;

[0028] [Brugler]J.S. Brugler, “Theoretical performance of voltage multiplier circuits,” IEEE J. Solid - State Circuits, pp. 132 - 135, June 1971;

[0029] [Lin] PMLin and LOChua, “Topological generation and analysis of voltage multipliers circuits,” IEEE Trans. Circuits Syst., vol. cas-24, no. 10, pp. 517-530, October 1977; and

[0030] [Pulvirenti] F. Pulvirenti and R. Gariboldi, "Voltage elevator on the charge pump type," European Patent 0 696 839.

[0031] Specifically, the document [Schenkel] discloses a voltage multiplier with discrete capacitors and valve diodes.

[0032] The [Cockcroft] paper discloses a voltage multiplier that generates voltages up to several million volts higher than those achievable with capacitors having a lower operating range than the circuit disclosed in the [Schenkel] paper. However, in the application disclosed in the [Cockcroft] paper, the coupling capacitor can be made large enough to achieve effective multiplication and sufficient current capacity, while the on-chip capacitor has a value of several hundred pF and a relatively high stray capacitance. Therefore, the voltage multiplier disclosed in the [Cockcroft] paper is often referred to as the Cockcroft-Walton voltage multiplier because it is sensitive to stray capacitance and is not widely used in integrated circuits.

[0033] The paper [Luscher] discloses a voltage multiplier based on the Schenkel topology, which is highly insensitive to parasitic capacitance and is implemented monolithically by replacing the valve with a MOS diode. A similar voltage multiplier circuit is also disclosed in the paper [Dickson], and it is commonly referred to as the Dickson multiplier.

[0034] On-chip voltage multipliers based on the Dickson architecture are used in smart power integrated circuits to drive output power transistors, such as those disclosed in [Storti], [Hobrecht], [Wong], [Gariboldi 94], and [Baveno]; for programming and erasing memory cells in non-volatile memory circuits, such as those disclosed in [Gerber], [Witters], [Umezawa], [Jinbo], [Atsumi], [Calligaro 1], and [Calligaro 2]; and for optimizing dynamic voltage range in low-voltage applications, such as those disclosed in [Monna].

[0035] For example, on-chip voltage multipliers based on the Dickson architecture disclosed in [Storti], [Hobrecht], [Gerber], [Monna], and [Berkhout] utilize capacitors interconnected by diodes and coupled in parallel with two inverted clock signals. Implementations of these circuits with MOS transistors that function as diodes are disclosed, for example, in [Witters], [Wong], [Calligaro 1], and [Calligaro 2].

[0036] For example, voltage multipliers of MOS transistors that function like switches, as disclosed in documents [Umezawa], [Jinbo], [Atsumi], [Gariboldi 94], [Gariboldi 96] and [Wang], are also known in the art, particularly for low-voltage applications as disclosed in documents [Baveno] and [Steenwijk].

[0037] Examples of charge pump circuits used in Cockcroft-Walton voltage multipliers are disclosed in the literature [Gasparini], [Weiner], [Brugler], and [Lin]. Summary of the Invention

[0038] Despite the extensive activity in this field, known on-chip fully integrated voltage multipliers may still have the drawback of occupying a large silicon area.

[0039] Therefore, there is a need in the art to provide improved voltage multiplier circuits conceived for high multiplication factors and low silicon area occupancy with integrated capacitors.

[0040] Some embodiments help to provide such improved voltage multiplier circuits.

[0041] According to one or more embodiments, such an improved voltage multiplier circuit can be implemented by a circuit having the features set forth in the appended claims.

[0042] The claims are an integral part of the technical teachings provided herein regarding the embodiments.

[0043] Some embodiments involve voltage multiplier circuits that include a charge pump architecture.

[0044] One or more embodiments can be applied to smart power integrated circuits, memory integrated circuits, low-voltage applications, controllers and drivers for microelectromechanical systems (MEMS), etc.

[0045] In one embodiment, the voltage multiplier includes an input node, an output node, and first and second control nodes for receiving first and second clock signals defining two commutation states. An ordered sequence of intermediate nodes is coupled between the input and output nodes and includes two ordered subsequences. Capacitors are coupled between: each odd-numbered intermediate node in the first subsequence and a first control node; each even-numbered intermediate node in the first subsequence and a second control node; each odd-numbered intermediate node in the second subsequence and a corresponding odd-numbered intermediate node in the first subsequence; and each even-numbered intermediate node in the second subsequence and a corresponding even-numbered intermediate node in the first subsequence. The circuitry includes selectively conductive electronic components coupled to the intermediate nodes. In a first commutation state, the electronic components provide conductive paths between each even-numbered intermediate node and the corresponding next odd-numbered intermediate node, between the input node and the first intermediate node, and between the last intermediate node and the output node. In a second commutation state, the electronic components provide conductive paths between each odd-numbered intermediate node and the corresponding next even-numbered intermediate node.

[0046] In one or more embodiments, the voltage multiplier circuit may include a first input node and a second input node configured to receive an input voltage from a voltage source between them. The voltage multiplier circuit may include a first output node and a second output node configured to couple to an output capacitor to generate an output voltage across the output capacitor. The voltage multiplier circuit may include a first input control node configured to receive a first clock signal and a second input control node configured to receive a second clock signal, the second clock signal being inverted compared to the first clock signal. The voltage multiplier circuit can therefore switch between a first commutation state and a second commutation state based on the values ​​of the first and second clock signals. The voltage multiplier circuit may include an ordered sequence of intermediate voltage nodes arranged between the first input node and the first output node. The ordered sequence may include a first ordered subsequence and a second ordered subsequence of intermediate voltage nodes (e.g., at least two ordered subsequences). Each ordered subsequence may include the same number of intermediate voltage nodes. For example, the number may be even. For example, the number may be equal to or greater than four. The voltage multiplier circuit may include a corresponding capacitor connected between each odd number of intermediate voltage nodes in the first ordered subsequence of the ordered sequence and the first input control node. A first intermediate voltage node in a first ordered subsequence can be selectively coupled to a first input node. The voltage multiplier circuit may include a corresponding capacitor connected between each even-numbered intermediate voltage node in the first ordered subsequence of the ordered sequence and a second input control node. The voltage multiplier circuit may include a corresponding capacitor connected between each odd-numbered intermediate voltage node in the second ordered subsequence of the ordered sequence and a corresponding odd-numbered intermediate voltage node in the first ordered subsequence of the ordered sequence. The voltage multiplier circuit may include a first plurality of selectively conductive electronic components coupled to the intermediate voltage nodes of the ordered sequence. In a first commutation state of the voltage multiplier circuit, the electronic components may be configured to provide a conductive path between each even-numbered intermediate voltage node in the ordered sequence and a corresponding next odd-numbered intermediate voltage node in the ordered sequence, a conductive path between the first input node and the first intermediate voltage node of the ordered sequence, and a conductive path between the last intermediate voltage node of the ordered sequence and the first output node. In the second commutation state of the voltage multiplier circuit, the electronic components can be configured to provide a conductive path between each odd intermediate voltage node in the ordered sequence and the corresponding next even intermediate voltage node in the ordered sequence.

[0047] In one or more embodiments, the voltage multiplier circuit may include other ordered sequences of intermediate voltage nodes arranged between the first input node and the first output node. These other ordered sequences may include corresponding first ordered subsequences and corresponding second ordered subsequences of intermediate voltage nodes (e.g., at least two ordered subsequences). Each ordered subsequence may include the same number of intermediate voltage nodes. For example, the number may be even. For example, the number may be equal to or greater than four. The voltage multiplier circuit may include a corresponding capacitor connected between each odd-numbered intermediate voltage node in the first ordered subsequence of the other ordered sequence and the second input control node. The first intermediate voltage node in the first ordered subsequence of the other ordered sequence may be selectively coupled to the first input node. The voltage multiplier circuit may include a corresponding capacitor connected between each even-numbered intermediate voltage node in the first ordered subsequence of the other ordered sequence and the first input control node. The voltage multiplier circuit may include a corresponding capacitor connected between each odd-numbered intermediate voltage node in the second ordered subsequence of the other ordered sequence and the corresponding odd-numbered intermediate voltage node in the first ordered subsequence of the other ordered sequence. A voltage multiplier circuit may include a corresponding capacitor connected between each even-numbered intermediate voltage node in a second ordered subsequence of another ordered sequence and a corresponding even-numbered intermediate voltage node in a first ordered subsequence of another ordered sequence. The voltage multiplier circuit may also include a plurality of other selectively conductive electronic components coupled to intermediate voltage nodes of other ordered sequences. In a first commutation state of the voltage multiplier circuit, the other electronic components may be configured to provide a conductive path between each odd-numbered intermediate voltage node in an odd-numbered intermediate voltage node of another ordered sequence and a corresponding next even-numbered intermediate voltage node of the other ordered sequence. In a second commutation state of the voltage multiplier circuit, the other electronic components may be configured to provide a conductive path between each even-numbered intermediate voltage node in an even-numbered intermediate voltage node of another ordered sequence and a corresponding next odd-numbered intermediate voltage node of the other ordered sequence, a conductive path between a first input node and a first intermediate voltage node of another ordered sequence, and a conductive path between the last intermediate voltage node of another ordered sequence and a first output node.

[0048] In one or more embodiments, the ordered sequence of intermediate voltage nodes and other ordered sequences of intermediate voltage nodes may include at least one corresponding third ordered subsequence of intermediate voltage nodes. Each ordered subsequence may include the same number of intermediate voltage nodes. For example, the number may be even. For example, the number may be equal to or greater than four.

[0049] One or more embodiments can therefore help reduce the silicon area footprint of voltage multiplier circuits. Attached Figure Description

[0050] One or more embodiments will now be described by way of example only, with reference to the accompanying drawings, in which:

[0051] Figure 1 This is an example circuit diagram of a conventional N-stage voltage multiplier circuit based on the Cockcroft-Walton architecture;

[0052] Figure 2 This is an example circuit diagram of a conventional N-stage voltage multiplier based on the Dickson architecture;

[0053] Figure 3 This is an exemplary circuit diagram of the equivalent circuit of a voltage multiplier circuit;

[0054] Figure 4 This is an exemplary circuit diagram of a voltage multiplier circuit having a single-branch architecture for generating a positive voltage, according to one or more embodiments of this specification.

[0055] Figure 5 and Figure 6 It is based on Figure 4 A circuit diagram illustrating exemplary operation of a voltage multiplier circuit;

[0056] Figure 7 This is an exemplary circuit diagram of a voltage multiplier circuit having a dual-branch architecture for generating a positive voltage, according to one or more embodiments of this specification.

[0057] Figure 8 This is an exemplary circuit diagram of a voltage multiplier circuit with a single-branch architecture according to one or more embodiments of this specification;

[0058] Figure 9 and Figure 10 It is based on Figure 8 A circuit diagram illustrating exemplary operation of a voltage multiplier circuit;

[0059] Figure 11 This is an exemplary circuit diagram of a voltage multiplier circuit with a dual-branch architecture according to one or more embodiments of this specification;

[0060] Figure 12 This is an exemplary circuit diagram of a voltage multiplier circuit having a dual-branch architecture for generating a positive voltage, according to one or more embodiments of this specification.

[0061] Figure 13 and Figure 14 It is based on Figure 12 An exemplary circuit diagram showing the implementation details of a voltage multiplier circuit;

[0062] Figure 15This is an exemplary circuit diagram of a voltage multiplier circuit having a single-branch architecture for generating a negative voltage, according to one or more embodiments of this specification.

[0063] Figure 16 This is an exemplary circuit diagram of a voltage multiplier circuit having a dual-branch architecture for generating a negative voltage, according to one or more embodiments of this specification; and

[0064] Figure 17 This is an exemplary circuit diagram of a voltage multiplier circuit having a dual-branch architecture for generating a negative voltage, according to one or more embodiments of this specification. Detailed Implementation

[0065] In the following description, one or more specific details are illustrated to provide a thorough understanding of examples of embodiments described herein. Embodiments may be obtained without one or more specific details, or by utilizing other methods, components, materials, etc. In other instances, known structures, materials, or operations are not illustrated or described in detail so that certain aspects of the embodiments are not obscured.

[0066] References to "embodiment" or "one embodiment" within the framework of this specification are intended to indicate that a particular configuration, structure, or feature described with respect to that embodiment is included in at least one embodiment. Therefore, phrases such as "in an embodiment" or "in one embodiment" that may appear at one or more points in this specification do not necessarily refer to the same embodiment. Furthermore, particular constructions, structures, or features may be combined in any suitable manner in one or more embodiments.

[0067] The headings and reference numerals used herein are provided for convenience only and therefore do not limit the scope of protection or the scope of the embodiments.

[0068] Throughout the accompanying figures, unless the context otherwise requires, the same parts or elements are represented by the same reference numerals / numbers and corresponding descriptions will not be repeated for the sake of brevity.

[0069] Through the detailed description of the exemplary embodiments, one can first refer to Figure 1 , Figure 2 and Figure 3 .

[0070] Figure 1 This is an exemplary circuit diagram of a conventional N-stage voltage multiplier 10 based on the Cockcroft-Walton architecture. The voltage multiplier circuit 10 includes components configured to receive an input voltage V from a voltage source 12. IN Input node 10a is configured to cross storage capacitor C OUT Generate output voltage V OUTThe output node 10b, and the N+1 diodes D1,...,D1 coupled (e.g., in series) between the input node 10a and the output node 10b and conducting from the input node 10a to the output node 10b. N+1 A chain (or string). For example, the first diode D1 has an anode terminal coupled to the input node 10a and a cathode terminal coupled to the anode terminal of the second diode D2, and intermediate diodes D2,...,D... N Each diode in the array has a corresponding anode terminal coupled to the cathode terminal of the preceding diode and a corresponding cathode terminal coupled to the anode terminal of the next (following) diode, and the last diode D... N+1 With the penultimate diode D N The cathode terminal is coupled to the anode terminal, and the cathode terminal is coupled to the output node 10b. The voltage multiplier circuit 10 includes components configured to receive a first drive clock signal v. CK The first drive input node 14a is configured to receive the first drive clock signal v CK Inverted second drive clock signal The second drive input node 14b (e.g., v) CK and It can be two square wave clock signals with a 50% duty cycle and offset by half a clock cycle. The voltage multiplier circuit 10 includes N pump (or coupling) capacitors C. P First pump capacitor C P It has a first terminal coupled to a node between the first and second diodes of the diode chain (i.e., the cathode terminal coupled to the first diode D1 of the chain) and a second terminal coupled to the first drive input node 14a. The second pump capacitor C... P It has a first terminal coupled to the node between the second and third diodes of the diode chain (i.e., coupled to the cathode terminal of the second diode D2 of the chain) and a second terminal coupled to the second drive input node 14b. For other pump capacitors, the general j-th pump capacitor has a corresponding first terminal coupled to the cathode terminal of the j-th diode of the chain and a corresponding second terminal coupled to the cathode terminal of the (j-2)-th diode of the chain.

[0071] Figure 2 This is an example circuit diagram of a conventional N-stage voltage multiplier 20 based on the Dickson architecture. Essentially, it is based on... Figure 1 In the same manner as shown, the voltage multiplier circuit 20 includes components configured to receive an input voltage V from the voltage source 22. IN Input node 20a is configured to cross storage capacitor C OUT Generate output voltage V OUTThe output node 20b, and the N+1 diodes D1,...,D1 coupled (e.g., in series) between the input node 20a and the output node 20b and conducting from the input node 20a to the output node 20b. N+1 A chain (or string). Voltage multiplier circuit 20 includes components configured to receive a first drive clock signal v. CK The first drive input node 24a is configured to receive the first drive clock signal v CK Inverted second drive clock signal The second drive input node 24b (e.g., v) CK and It can be two square wave clock signals with a 50% duty cycle and offset by half a clock cycle. The voltage multiplier circuit 20 includes N pump (or coupling) capacitors C. P Each pump capacitor C P The circuit has a first terminal coupled to a node between two diodes in the diode chain and a second terminal coupled to either a first drive input node 24a or a second drive input node 24b. Specifically, two pump capacitors (i.e., one coupled to the anode of a diode and the other to the cathode of a diode) whose first terminal is coupled to the same diode in the diode chain have second terminals coupled to two different drive input nodes, such that during operation of the voltage multiplier circuit 20, the anode and cathode of each diode in the diode chain are driven at different voltage levels. In other words, the second terminal of the pump capacitor whose first terminal is coupled to the cathode of the odd-numbered diode in the diode chain is coupled to the first drive input node 24a, and the second terminal of the pump capacitor whose first terminal is coupled to the cathode of the even-numbered diode in the diode chain is coupled to the second drive input node 24b.

[0072] exist Figure 1 and Figure 2 In the two circuits illustrated, the storage capacitor C OUT Configured to store charge and provide a stable output voltage V OUT N pump capacitors C P The diode is configured to pump charge, and it is configured to transfer charge only in one direction, from the input node to the output node. For example... Figure 1 and Figure 2 The operation of the multiplier circuit illustrated herein is known to those skilled in the art: it is based on the voltage amplitude V CK Pump capacitor C driven by two inverted clock signals P The clock signal alternates between charging and discharging in each half-cycle, causing the charge "packet" to pull the output voltage V high. OUT Diode chain pumping.

[0073] Figure 3This is an exemplary circuit diagram of the equivalent circuits of voltage multiplier circuits 10 and 20, where V O It is the voltage generated by the multiplier circuit under open-circuit load conditions, and R OUT It is the equivalent output resistance. According to... Figure 3 The equivalent circuit shown in the figure has an output voltage V. OUT It can be calculated according to the following equation (1):

[0074] V OUT =V O -R OUT ·I OUT (1)

[0075] Considering stray capacitance, the open-circuit load voltage V of voltage multiplier circuits 10 and 20 is reported in the literature [Dickson]. O and output resistance R OUT If the clock period is much longer than the time constant R D C P (where R) D If the diode resistor is used, then the output resistance R is defined. OUT The equations are valid. The results are summarized in the following equations (2) to (4), where equation (2) is valid for both multipliers, equation (3) is valid for Dickson multiplier 20, and equation (4) is valid for Cockcroft-Walton multiplier 10:

[0076] V O =V IN -(N+1)·V D +N·V CK (2)

[0077]

[0078]

[0079] Where V IN It is the input voltage of the multiplier circuit, V CK It is the swing voltage of the clock signal, V D is the forward voltage drop of the diode, and f is the clock frequency.

[0080] It should be noted that the Cockcroft-Walton multiplier 10 has two main limitations: effective voltage multiplication only occurs when the pump capacitor is much larger than the stray capacitor, and the output impedance increases rapidly with the number of multiplication stages. Another limitation of implementing the Cockcroft-Walton multiplier 10 in a monolithic integrated circuit is that if both circuits are designed to have the same output impedance, the silicon size increases rapidly with the number of multiplication stages compared to the Dickson multiplier 20.

[0081] On the other hand, due to the voltage limitation of the on-chip capacitors, Dickson multipliers implemented in monolithic integrated circuits cannot achieve high output voltages.

[0082] For example, a pump capacitor with an operating voltage of 12V is used in a voltage multiplier circuit to pump the voltage from the input voltage V. IN =3.3V to start generating output voltage V OUT At 70V, the Dickson multiplier will not be suitable due to the voltage limitation of the capacitor, as given by the following comparative equations (3) and (4a) for R. OUT Equation (5) obtained from the value shows that a Cockcroft-Walton multiplier with the same output impedance will have a larger size:

[0083]

[0084] Therefore, there is a need in the art to provide improved voltage multiplier circuits that rely on the maximum voltage capability of on-chip capacitors while reducing silicon area footprint.

[0085] One or more embodiments may therefore relate to, for example Figure 4 The voltage multiplier circuit 40 is illustrated in the example. Figure 4 This is an exemplary circuit diagram of a voltage multiplier circuit 40 having a single-branch architecture for generating a positive voltage.

[0086] like Figure 4 As illustrated, the voltage multiplier circuit 40 includes diodes D1,…,D1 arranged between the input node 40a and the output node 40b. N+1 The chain is basically as referenced. Figure 1 and Figure 2 The input node 40a discussed is configured to receive an input voltage V from the voltage source 42. IN Output node 40b is configured to generate output voltage V. OUT The diode chain provides an intermediate voltage between input node 40a and output node 40b at nodes A1,...,A. N An ordered sequence (e.g., a general node A) x Corresponding to general-purpose diode Dx (Cathode terminal).

[0087] Voltage multiplier circuit 40 includes components configured to receive a first drive clock signal v CK The first drive input node 44a is configured to receive the first drive clock signal v CK Inverted second drive clock signal The second drive input node 44b. The voltage multiplier circuit 40 includes N pump (or coupling) capacitors C. P .like Figure 4 As shown, N pump capacitors C P They are arranged in groups (e.g., clusters) of number K = N / M, each group consisting of M capacitors.

[0088] The first pump capacitor bank includes M pump capacitors C P Its first terminal is coupled to the odd-numbered intermediate voltage nodes A1, A3, ..., A4 in the first subsequence of 2M intermediate voltage nodes numbered from 1 to 2M (i.e., A1, ..., A2M). 2M-1 (e.g., the first node and the third node), and its second terminal is coupled to the first drive input node 44a to receive the first drive clock signal v. CK The second pump capacitor bank includes M pump capacitors C. P Its first terminal is coupled to an even number of intermediate voltage nodes A2, A4, ..., A in the first subsequence of 2M intermediate voltage nodes. 2M (e.g., the second node and the fourth node), and the second terminal is coupled to the second drive input node 44b to receive the second drive clock signal. Therefore, the pump capacitors in the first and second groups are basically arranged according to the Dickson architecture.

[0089] The third pump capacitor bank includes M pump capacitors C. P Its first terminal is coupled to numbers from 2M+1 to 4M ( Figure 4 Odd-numbered intermediate voltage nodes A in the second subsequence of 2M intermediate voltage nodes (not visible in the middle) 2M+1 A 2M+3 ,…,A 4M-1 (For example, the first node and the third node), and the second terminal is coupled to the corresponding odd-numbered intermediate voltage nodes A1, A3, ..., A in the first subsequence of 2M intermediate voltage nodes numbered from 1 to 2M. 2M-1 (For example, the first and third nodes). In other words, the third group of pump capacitors is stacked together with the first group of pump capacitors, similar to the Cockcroft-Walton architecture. The fourth group of pump capacitors consists of M pump capacitors C. PIts first terminal is coupled to numbers from 2M+1 to 4M ( Figure 4 Even-numbered intermediate voltage nodes A in the second subsequence of 2M intermediate voltage nodes (not visible in the middle) 2M+2 A 2M+4 ,…,A 4M (For example, the second node and the fourth node), and the second terminal is coupled to the corresponding odd-numbered intermediate voltage node A2, A4, ..., A in the first subsequence of 2M intermediate voltage nodes numbered from 1 to 2M. 2M (For example, the second and fourth nodes). In other words, the pump capacitors of the fourth group are stacked together with the pump capacitors of the second group, similar to the Cockcroft-Walton architecture.

[0090] In this specification, when two intermediate voltage nodes of two different subsequences occupy the same position (e.g., position 1, position 2, etc.) in the corresponding ordered subsequence, they are referred to as "corresponding".

[0091] The number of pump capacitor banks is related to the number of stages N of the voltage multiplier and the number of capacitors M in each bank. Generally, the penultimate pump capacitor bank consists of M pump capacitors C. P Its first terminal is coupled to the odd-numbered intermediate voltage node A in the last subsequence of 2M intermediate voltage nodes numbered from N-2M+1 to N. N-2M+1 A N-2M+3 ,…,A N-1 And the second terminal is coupled to numbers from N-4M+1 to N-2M ( Figure 4 The corresponding odd-numbered intermediate voltage node A in the penultimate subsequence of the intermediate voltage node (not visible in the middle) N-4M+1 A N-4M+3 A N-2M-1 In other words, the second-to-last group of pump capacitors is stacked together with the fourth-to-last group of pump capacitors, similar to the Cockcroft-Walton architecture. The last group of pump capacitors consists of M pump capacitors C. P Its first terminal is coupled to the even-numbered intermediate voltage node A in the last subsequence of 2M intermediate voltage nodes numbered from N-2M+1 to N. N-2M+2 A N-2M+4 A N And the second terminal is coupled to numbers from N-4M+1 to N-2M ( Figure 4 The even-numbered intermediate voltage node A in the penultimate subsequence of the intermediate voltage node (not visible in the middle) N-4M+2 A N-4M+4 ,…,A N-2MIn other words, the last group of pump capacitors is stacked together with the third-to-last group of pump capacitors, similar to the Cockcroft-Walton architecture.

[0092] Therefore, in such Figure 4 In the illustrated voltage multiplier circuit 40, the first two sets of pump capacitors C P Basically arranged according to the Dickson architecture, while the remaining (middle and last) groups of pump capacitors C P Stacked on top of the previous pump capacitors, similar to a Cockcroft-Walton multiplier (e.g., their lower terminals are connected to the higher terminals of the capacitors in the first two groups, which are connected to the diode chain, gradually moving towards the output). In short, pump capacitors belonging to the same group are arranged "in parallel" like Dickson charge pumps, while different groups of pump capacitors are stacked on top of each other, similar to a Cockcroft-Walton charge pump.

[0093] refer to Figure 5 and Figure 6 explain Figure 4 The operation of the voltage multiplier circuit 40 is illustrated in the figure. Figure 5 Especially when v CK =0 (low value) and At (high value), in clock signal v CK and An example of charge transfer in circuit 40 during the first half of the cycle. Figure 6 Especially when v CK =V CK (high value) and (At low values) in the clock signal v CK and An example of charge transfer in circuit 40 during the second half of the cycle.

[0094] In the first half of the clock cycle, when v CK for low and When it is high, it is due to signal v CK (That is, pump capacitors coupled to an odd number of intermediate voltage nodes) are charged with (more) positive voltage. They are charged from the signal via odd number of diodes. The driven pump capacitor (i.e., the pump capacitor coupled to the even-numbered intermediate voltage node) receives charge "packets" from the signal. The driven pump capacitor is discharged in the context. During this phase, the first pump capacitor is discharged by the input voltage V. IN Direct charging. In the second half of the clock cycle, when v CK For high and When it is low, it is determined by signal v CKThe driven pump capacitors are discharged. They supply the charge packets to the signal via even-numbered diodes. The driven pump capacitor is driven by the signal The driven pump capacitor is charged with a corrected voltage in the context.

[0095] In the signal v CK Of the first group of M pump capacitors driven, the first pump capacitor (coupled between node 44a and node A1) is V IN -V D Charging, the third pump capacitor (coupled between node 44a and node A3) at V IN +2V CK -3V D Charging, the fifth pump capacitor (coupled between node 44a and node A5) at V IN +4V CK -5V D Charging continues in this manner until the (2M-1)th pump capacitor (coupled at node 44a and node A) 2M-1 (between) with V IN +(2M-2)·V CK -(2M-1)·V D Charging. (In the process of...) In the driven second pump capacitor bank, the second pump capacitor (coupled between node 44b and node A2) is V IN +V CK -2V D Charging, the fourth pump capacitor (coupled between node 44b and node A4) at V IN +3V CK -4V D Charging, the sixth pump capacitor (coupled between node 44b and node A6) at V IN +5V CK -6V D Down-charging, and so on, until the 2M pump capacitor (coupled at node 44b and node A) 2M (between) in V IN +(2M-1)·V CK -2M·V D To charge. Pump capacitors from 2M+1 to N (i.e., those in group 3 and later) are charged at 2M·(V CK -V D ) charging; this is the voltage across the two terminals of the capacitor. As reported by the multiplier known in equation (2), the output capacitance is V IN +N·V CK -(N+1)·V D Charge.

[0096] Note that the equivalent output resistance of voltage multiplier circuit 40 can be calculated according to the following equation (6) as a combination of a 2M-stage Dickson multiplier and an N / 2M-stage Cockcroft-Walton multiplier, assuming the clock period is greater than the time constant R. D C P It is much longer, where RD is the diode resistance:

[0097]

[0098] Regarding silicon size, comparisons are used to calculate R. OUT Equations (3) and (6), note that, as Figure 4 The dimensions of the architecture (hereinafter also referred to as the "hybrid architecture") in the middle can be represented as:

[0099]

[0100] One or more embodiments may involve, for example Figure 7 The voltage multiplier circuit 70 is illustrated in the example. Figure 7 Based on reference Figure 4 , Figure 5 and Figure 6 The same concept discussed is illustrated in the exemplary circuit diagram of a voltage multiplier circuit 70 with a dual-branch architecture for generating a positive voltage.

[0101] like Figure 7 As shown, the voltage multiplier circuit 70 includes: a first chain of N+1 diodes arranged between input node 40a and output node 40b, wherein input node 40a and output node 40b are substantially defined as shown in the reference. Figure 4 The intermediate nodes A1,…,A discussed N ; and the second chain of N+1 diodes arranged between input node 40a and output node 40b, which is also basically as described in the reference. Figure 4 The input node 40a and output node 40b discussed here define intermediate voltage nodes B1,...,B N Another set. The voltage multiplier circuit 70 includes 2N pump (or coupling) capacitors C P / 2. For example... Figure 7 As shown, there are 2N pump capacitors C P / 2 is arranged in two subsets, each subset comprising K = N / M groups (e.g., clusters), each group comprising M capacitors. The first subset comprises the capacitors generated by the clock signal v. CK The pump capacitor is driven (e.g., coupled to node 44a), while the second subset includes the pump capacitor driven by the clock signal. A pump capacitor that drives (e.g., coupled to node 44b).

[0102] The first group of the first subset of pump capacitors includes pump capacitor C P / 2, whose first terminal is coupled to the first voltage node set A1,…,A N Odd-numbered intermediate voltage nodes A1, A3, ..., A in the first subsequence of M intermediate voltage nodes numbered from 1 to M. M-1 (e.g., the first node and the third node), and the second terminal is coupled to the first drive input node 44a to receive the first drive clock signal v. CK The first group of the first subset of pump capacitors also includes pump capacitor C. P / 2, whose first terminal is coupled to the second voltage node set B1,…,B N Even-numbered intermediate voltage nodes B2, B4, ..., B in the first subsequence of M intermediate voltage nodes numbered from 1 to M. M (For example, the second node and the fourth node), and the second terminal is coupled to the first drive input node 44a to receive the first drive clock signal v. CK .

[0103] The first group of the second subset of pump capacitors includes pump capacitor C. P / 2, whose first terminal is coupled to the first voltage node set A1,…,A N Even-numbered intermediate voltage nodes A2, A4, ..., A in the first subsequence of M intermediate voltage nodes numbered from 1 to M. M (e.g., the second node and the fourth node), and the second terminal is coupled to the second drive input node 44b to receive the second drive clock signal. The first group of the second subset of pump capacitors also includes pump capacitor C. P / 2, whose first terminal is coupled to the second voltage node set B1,…,B N Odd-numbered intermediate voltage nodes B1, B3, ..., B in the first subsequence of M intermediate voltage nodes numbered from 1 to M. M-1 (e.g., the first node and the third node), and the second terminal is coupled to the second drive input node 44a to receive the second drive clock signal.

[0104] The second group of the first subset of pump capacitors includes pump capacitor C. P / 2, whose first terminal is coupled to the first voltage node set A1,…,A N Odd-numbered intermediate voltage node A in the second subsequence of M intermediate voltage nodes numbered from M+1 to 2M M+1 A M+3 ,…,A 2M-1(e.g., the first node and the third node), and the second terminal is coupled to the first voltage node set A1,…,A N The odd-numbered intermediate voltage nodes A1, A3, ..., A1 in the first subsequence of M intermediate voltage nodes numbered from 1 to M. M-1 (For example, the first node and the third node). The second group of the second subset of pump capacitors also includes pump capacitor C. P / 2, whose first terminal is coupled to the second voltage node set B1,…,B N B, an even-numbered intermediate voltage node in the second subsequence of M intermediate voltage nodes numbered from M+1 to 2M. M+2 B M+4 ,…,B 2M (For example, the second node and the fourth node), and the second terminal is coupled to the second voltage node set B1,…,B N The even-numbered intermediate voltage nodes B2, B4, ..., B in the first subsequence of M intermediate voltage nodes numbered from 1 to M. M (For example, the second node and the fourth node).

[0105] The second group of the second subset of pump capacitors includes pump capacitor C P / 2, whose first terminal is coupled to the first voltage node set A1,…,A N Even-numbered intermediate voltage nodes A in the second subsequence of M intermediate voltage nodes numbered from M+1 to 2M M+2 A M+4 ,…,A 2M (For example, the second node and the fourth node), and the second terminal is coupled to the first voltage node set A1, ..., A N The even-numbered intermediate voltage nodes A2, A4, ..., A6 are in the first subsequence of M intermediate voltage nodes numbered from 1 to M. M (For example, the second node and the fourth node). The second group of the second subset of pump capacitors also includes pump capacitor C. P / 2, whose first terminal is coupled to the second voltage node set B1,…,B N Odd-numbered intermediate voltage node B in the second subsequence of M intermediate voltage nodes numbered from M+1 to 2M M+1 B M+3 ,…,B 2M-1 (e.g., the first node and the third node), and the second terminal is coupled to the second voltage node set B1,…,B N The odd-numbered intermediate voltage nodes B1, B3, ..., B in the first subsequence of M intermediate voltage nodes numbered from 1 to M. M-1 (For example, the first node and the third node).

[0106] Typically, the last group of the first subset of pump capacitors includes pump capacitor C. P / 2, whose first terminal is coupled to the first voltage node set A1,…,A N Odd-numbered intermediate voltage node A in the last subsequence of M intermediate voltage nodes numbered from N-M+1 to N N-M+1 A N-M+3 ,…,A N-1 (e.g., the first node and the third node), and the second terminal is coupled to the first voltage node set A1, ..., A N The corresponding odd-numbered intermediate voltage node A in the penultimate subsequence of the M intermediate voltage nodes numbered from N-2M+1 to NM. N-2M+1 A N-2M+3 ,…,A N-M-1 (For example, the first node and the third node). The last group of the first subset of pump capacitors also includes pump capacitor C. P / 2, whose first terminal is coupled to the second voltage node set B1,…,B N B, the even-numbered intermediate voltage node in the last subsequence of the M intermediate voltage nodes numbered from N-M+1 to N. N-M+2 B N-M+4 ,…,B N (For example, the second node and the fourth node), and the second terminal is coupled to the second voltage node set B1,…,B N The even-numbered intermediate voltage node B in the penultimate subsequence of the M intermediate voltage nodes numbered from N-2M+1 to NM. N-2M+2 , B N-2M+4 ,…,B N-M (For example, the second node and the fourth node).

[0107] Typically, the last group of the second subset of pump capacitors includes pump capacitor C. P / 2, whose first terminal is coupled to the first voltage node set A1,…,A N Even-numbered intermediate voltage node A in the last subsequence of M intermediate voltage nodes numbered from N-M+1 to N. N-M+2 A N-M+4 ,…,A N (For example, the second node and the fourth node), and the second terminal is coupled to the first voltage node set A1,…,A N The even-numbered intermediate voltage node A in the penultimate subsequence of the M intermediate voltage nodes numbered from N-2M+1 to NM. N-2M+2 A N-2M+4 ,…,A N-M(For example, the second and fourth nodes). The last group of the second subset of pump capacitors also includes pump capacitor C. P / 2, whose first terminal is coupled to the second voltage node set B1,…,B N Odd-numbered intermediate voltage node B in the last subsequence of M intermediate voltage nodes numbered from N-M+1 to N. N-M+1 B N-M+3 ,…,B N-1 (e.g., the first node and the third node), and the second terminal is coupled to the second voltage node set B1,…,B N The corresponding odd-numbered intermediate voltage node B in the penultimate subsequence of the M intermediate voltage nodes numbered from N-2M+1 to NM. N-2M+1 B N-2M+3 ,…,B N-M-1 (For example, the first node and the third node).

[0108] Note that, although Figure 7 The architecture has been described in detail with reference to the first, second, and last groups of pump capacitors in each subset, but the number of pump capacitor groups (i.e., number K = N / M) can vary according to design specifications, with each group "stacked" on top of the previous one (e.g., see [reference]). Figure 7 In and node A i+1 B i+2 A i+3 B i+M and B i+1 A i+2 B i+3 A i+M Coupled intermediate capacitor bank).

[0109] If each pump capacitor C P / 2 is the capacitance value of the pump capacitor C in a single-branch architecture. P If half of the capacitance value is applied, then the open-circuit load voltage V of the voltage multiplier circuit 70 will be... O Same as reported in Equation (2). The total capacitance remains unchanged between the single-branch and dual-branch architectures, with the dual-branch architecture comprising 2N*C. P / 2 capacitors, while the single-branch architecture includes N*C P One capacitor. Regarding the voltage ripple at the multiplier output and the current peaks in the capacitors and diodes, Figure 7 The dual-branch architecture illustrated in the example may be advantageous, as it halves the cost compared to a single-branch architecture.

[0110] The dual-branch voltage multiplier 70 operates similarly to a single-branch architecture, except that the voltage across the pump capacitor is halved because... Figure 7The architecture is symmetrical and for a given N-stage multiplier, the number of pump capacitors is doubled.

[0111] In the first pump capacitor bank of the first subset (directly connected to node 44a and controlled by signal v) CK (Drive) and in the first pump capacitor bank of the second subset (directly connected to node 44b and controlled by signal) (Drive), the first two pump capacitors (coupled between nodes 44a and A1, and between nodes 44b and B1, respectively) are connected at V IN -V D Charging, the second pump capacitor (coupled between nodes 44a and B2, and between nodes 44b and A2, respectively) at V IN +V CK -2V D Charging, the third pump capacitor (coupled between nodes 44a and A3, and between nodes 44b and B3, respectively) at V IN +2V CK -3V D Charging continues in this manner until the Mth pump capacitor (in the case of an even number, coupled to nodes 44a and B respectively). M Between, and at nodes 44b and A M Between; when M is odd, they are coupled at nodes 44a and A respectively. M Between, and between nodes 44b and B M (between) with V IN +(M-1)·V CK -M·V D Charging. The pump capacitors of the other groups coupled to the intermediate voltage nodes numbered M+1 to N are all charged at M·(V). CK -V D ) charging. As reported in equation (2) for known multipliers and single-branch architectures, the output capacitor at V IN +N·V CK -(N+1)·V D Down-to-charge.

[0112] Note that the equivalent output resistance of voltage multiplier circuit 70 can be calculated according to the following equation (8) as a combination of an M-class Dickson multiplier and an N / M-class Cockcroft-Walton multiplier, assuming the clock period is greater than the time constant R. D C P Much longer, of which R D It is a diode resistor:

[0113]

[0114] Regarding silicon size, comparisons are used to calculate R.OUT Equations (3) and (8), note that, as Figure 7 The dimensions of the architecture in the middle (hereinafter also referred to as the "hybrid dual architecture") can be represented as:

[0115]

[0116] In one or more embodiments (e.g., in an on-chip implementation), diodes D1, ..., D N+1 It can be by Figure 8 The MOS transistor illustrated in the example is used instead. It should be noted that... Figure 8 The voltage multiplier circuit 80 basically corresponds to Figure 4 The architecture, in which diodes D1,…,D N+1 MOS transistors M1,…,M N+1 Replacement. MOS transistors can be n-channel and / or p-channel, as long as they are responsive to the clock signal v. CK and The current value is appropriately driven to conduct from the input node to the output node.

[0117] refer to Figure 9 and Figure 10 explain Figure 8 The operation of the voltage multiplier circuit 80 is illustrated in the figure. Figure 9 Especially when v CK =0 (low value) and At (high value), in clock signal v CK and An example of charge transfer in circuit 80 during the first half of the cycle. Figure 10 Especially when v CK =V CK (high value) and (At low values) in the clock signal v CK and An example of charge transfer in circuit 80 during the second half of the cycle.

[0118] In the first half of the clock cycle, when v CK for low and When it is high, it is due to signal v CK The driven pump capacitor is driven by a signal The driven pump capacitor is charged with (more) positive voltage by the signal. The driven pump capacitor is discharged in context. (Due to v) CK The driven pump capacitor receives charge "packets" via odd-numbered switches (MOS transistors), which are in a conductive state (on) during this phase, while even-numbered switches (MOS transistors) are in a non-conductive state (off). During this phase, the first pump capacitor is driven by the input voltage V. INDirect charging. In the second half of the clock cycle, when v CK For high and When it is low, it is determined by signal v CK The driven pump capacitor is driven by a signal The pump capacitor is discharged by the signal. The driven pump capacitor is charged with a corrected voltage in the context. This is due to the signal v. CK The pump capacitor is driven by an even-numbered switch (MOS transistor) that provides a charge packet. The even-numbered switch is in a conductive state (on) during this phase, while the odd-numbered switch (MOS transistor) is in a non-conductive state (off).

[0119] Directly connected to node 44a and controlled by signal v CK In the first pump capacitor bank driven by the pump, the first pump capacitor (coupled between node 44a and node A1) is V IN Charging, the third pump capacitor (coupled between node 44a and node A3) at V IN +2V CK Charging, the fifth pump capacitor (coupled between node 44a and node A5) at V IN +4V CK Charging continues in this manner until the (2M-1)th pump capacitor (coupled between node 44a and node A5) reaches V IN +(2M-2)·V CK Charging. Directly connected to node 44b and controlled by a signal. In the driven second pump capacitor bank, the second pump capacitor (coupled between node 44b and node A2) is V IN +V CK Charging, the fourth pump capacitor (coupled between node 44b and node A4) at V IN +3V CK Charging, the sixth pump capacitor (coupled between node 44b and node A6) at V IN +5V CK Charging continues in this manner until the 2M pump capacitor (coupled at node 44b and node A) is reached. 2M (between) with V IN +(2M-1)·V CK Charging. All pump capacitors from 2M+1 to N operate at 2MV. CK Charging; this is the voltage across the two terminals of the capacitor. Open-circuit load output voltage V O Report in the following equation (10):

[0120] V O =V IN +N·V CK (10)

[0121] Note that, as Figure 8 The equivalent output resistance of the voltage multiplier circuit 80 shown is the same as that defined in equation (6), assuming the clock period is greater than the time constant R. M C P Much longer, of which R M It is a MOS transistor resistor.

[0122] In one or more embodiments, such as Figure 11 As illustrated, MOS transistors can also be used to replace diodes in a two-branch architecture. It should be noted that... Figure 11 The voltage multiplier circuit 110 basically corresponds to Figure 7 The architecture uses MOS transistors instead of diodes. MOS transistors can be n-channel and / or p-channel, provided they are properly driven (e.g., according to reference...). Figure 9 and Figure 10 The driving scheme discussed is if a positive output voltage is generated.

[0123] Note that, as Figure 11 The equivalent output resistance of the voltage multiplier circuit 110 illustrated in the figure is the same as that defined in equation (8), assuming that the clock period is much longer than the time constant R. M C P , where R M This is the resistor for the MOS transistor. Additionally, as... Figure 11 The open-circuit load voltage V of the voltage multiplier circuit 110 illustrated in the figure O Same as defined in equation (10). Regarding the voltage ripple on the multiplier output and the current peaks in the capacitors and MOS transistors, as... Figure 11 The dual-branch MOS architecture illustrated in the figure may be advantageous, as it reduces costs by half compared to the single-branch MOS architecture.

[0124] Typically, a two-branch voltage multiplier circuit used to generate a positive voltage can be implemented as follows: Figure 12 The circuit diagram is shown.

[0125] like Figure 12 As illustrated, the voltage multiplier circuit 120 includes a chain of N charge transfer circuit blocks 130 arranged between the input node 40a and the output node 40b. Figure 13 As shown, each charge transfer circuit block 130 has an input terminal V d Output terminal V u The first control terminal and the second control terminal. The charge transfer circuit block 130 includes electronic components (e.g., diodes and / or transistors) arranged such that when two inverted switching signals are applied to the first and second control terminals, charge flows from the input terminal V...d Transfer to output terminal V u Specifically, based on the values ​​of the control signals received at the two control terminals, circuit block 130 can operate in two different commutation states: in the first state, input terminal V... d Coupled to the first control terminal and the output terminal V u Coupled to the second control terminal; in the second state, the input terminal V d It is coupled to the second control terminal, and the output terminal V u It is coupled to the first control terminal.

[0126] like Figure 12 As illustrated, the first and second control terminals of each charge transfer circuit block 130 are configured to be connected via a corresponding pump capacitor C. P / 2 receives complementary control signals (e.g., v) CK and ).like Figure 12 As illustrated, N charge transfer circuit blocks 130 are arranged in sub-chains of number K = N / M, each sub-chain comprising a string of M blocks 130.

[0127] In the first sub-chain of block 130, the first control terminal of each block 130 is connected via a corresponding pump capacitor C. P / 2 is coupled to the first drive input node 44a, and the second control terminal of each block 130 is connected via a corresponding pump capacitor C. P / 2 is coupled to the second drive input node 44b. In the second sub-chain of block 130, the first control terminal of each block 130 is connected via a corresponding pump capacitor C. P / 2 is coupled to the first control terminal of the corresponding block 130 in the first sub-chain, and the second control terminal of each block 130 is connected via a corresponding pump capacitor C. P / 2 and is coupled to the second control terminal of the corresponding block 130 in the first sub-chain. In other words, the pump capacitor coupled to block 130 in the second sub-chain is stacked to the pump capacitor coupled to block 130 in the first sub-chain.

[0128] The number of subchains K is related to the stage N and the number of blocks M in each subchain. Typically, in the j-th subchain of block 130, the first control terminal of each block 130 is connected via a corresponding pump capacitor C. P / 2 is coupled to the first control terminal of the corresponding block 130 in the (j-1)th subchain, and the second control terminal of each block 130 is connected via the corresponding pump capacitor C. P / 2 is coupled to the second control terminal of the corresponding block 130 in the (j-1)th subchain.

[0129] For example, in one or more embodiments, each charge transfer circuit block 130 may include, for example, Figure 14 The arrangement is illustrated in the example. The arrangement includes: a first n-channel transistor N. l It has an input terminal V d The current path between the first control terminal and the second n-channel transistor N2, which has a current path between the input terminal V and the first control terminal. d The current path between the second control terminal; the first p-channel transistor P1, which has a current path between the output terminal V and the second control terminal V. u The current path between the first control terminal and the second p-channel transistor P2, which has a current path between the output terminal V and the first control terminal; and the second p-channel transistor P2, which has a current path between the output terminal V and the first control terminal. u The current path between the first n-channel transistor N1 and the first p-channel transistor P1 is coupled to the second control terminal, and the gate terminals of the second n-channel transistor N2 and the second p-channel transistor P2 are coupled to the first control terminal.

[0130] The operation of such an arrangement used in a latching charge pump is disclosed in [Pulvirenti] and [Gariboldi 96], and therefore will not be repeated here for the sake of brevity.

[0131] One or more embodiments can be used to generate negative voltages. For example... Figure 17 As shown in the circuit diagram, this can be achieved, for example, by means of... Figure 15 and Figure 16 The circuit diagrams illustrate the inversion. Figure 4 and Figure 7 The polarity of the diodes in the architecture is used to obtain, or to reverse, the polarity. Figure 8 and Figure 11 The polarity of the activation signal of the MOS transistor in the architecture is obtained by either inverting or flipping it. Figure 12 The orientation of the charge transfer circuit block 130 in the architecture (e.g., the switching terminal V) u and V d To obtain it.

[0132] Figure 15 The operation of the single-branch negative voltage multiplier circuit 150 illustrated is similar to... Figure 4 The operation of the single-branch positive voltage multiplier circuit 40 illustrated below will therefore be discussed only by way of example. In the first half of the clock cycle, when v... CK for low and When it is high, it is due to signal v CK The driven pump capacitor (i.e., coupled to the odd-numbered intermediate voltage nodes A1,…,A) N-1 They are charged. They are charged by means of an even number of diodes from the signal. Driven (i.e., coupled to an even number of intermediate voltage nodes A2,…,A)N The pump capacitor receives charge "packets" from the signal. The driven pump capacitor discharges at a more negative voltage in the context. In the second half of the clock cycle, when v... CK For high and When it is low, it is determined by signal v CK The driven pump capacitors discharge at a more negative voltage. They supply the charge packets to the signal via odd-numbered diodes. The driven pump capacitor is driven by the signal The driven pump capacitor is charged according to the context. During this phase, the first pump capacitor is directly discharged to the input voltage V. IN .

[0133] The first pump capacitor (coupled between node 44a and node A1) is V IN -V CK +V D Charging, the second pump capacitor (coupled between node 44b and node A2) at V IN -2V CK +2V D Charging, the third pump capacitor (coupled between node 44a and node A3) at V IN -3V CK +3V D Charging follows the same principle. In a single-branch architecture, pump capacitors from 2M to N all have a voltage of -2M·(V). CK -V D ) charging; in the dual-branch architecture, the pump capacitors from M to N are all charged with -M·(V CK -V D Charging. Open-circuit load output voltage V O Report in the following equation (11):

[0134] V O =V IN -N·V CK +(N+1)·V D (11)

[0135] Note that the equivalent output resistance of voltage multiplier circuit 150 is the same as that reported in equation (6).

[0136] It should also be noted that the first diode should be connected to ground, not to V. IN The output voltage becomes more negative.

[0137] like Figure 16 The operation of the dual-branch negative voltage multiplier 160 illustrated herein is similar to that of the single-branch negative architecture, except that the voltage across the pump capacitor is halved, and for the sake of simplicity, it will not be described further herein.

[0138] like Figure 8 The operation of the negative voltage multiplier circuit based on the MOS transistor architecture illustrated in the figure can be achieved by reversing the previous reference. Figure 9 and Figure 10 The operation is explained to obtain, that is, the activation phase of the inverting MOS transistor relative to the two half-cycles of the clock signal. In this case, in the first half-clock cycle, when v CK for low and When it is high, it is due to signal v CK The driven pump capacitor is driven by a signal The pump capacitor is charged by the signal. The driven pump capacitor discharges at a more negative voltage in the context. (Due to v) CK The driven pump capacitor receives charge "packets" via even-numbered switches (MOS transistors), which are in a conductive state (on) during this phase, while odd-numbered switches (MOS transistors) are in a non-conductive state (off). In the second half-clock cycle, when v... CK For the sake of the high When it is low, it is determined by signal v CK The driven pump capacitor is driven by a signal The driven pump capacitor discharges at a more negative voltage, driven by the signal. The driven pump capacitor charges according to the context. This is due to the signal v. CK The driven pump capacitor is supplied with a charge packet via odd-numbered switches (MOS transistors), which are in a conductive state (on) during this phase, while even-numbered switches (MOS transistors) are in a non-conductive state (off). During this phase, the first pump capacitor is directly discharged to the input voltage V. IN .

[0139] The first pump capacitor (coupled between node 44a and node A1) is V IN -V CK Charging, the second pump capacitor (coupled between node 44b and node A2) at V IN -2V CK During charging, the third pump capacitor (coupled between node 44a and node A3) is charged at V. IN -3V CK Down-charging, and so on. In a single-branch architecture, the pump capacitors from 2M to N all operate at -2MV. CK Charging; in the dual-branch architecture, the pump capacitors from M to N all operate at -M·V. CK Down-charging. Open-circuit load output voltage V O Report in the following equation (12):

[0140] V O =V IN-N·V CK (12)

[0141] The equivalent output resistance is the same as that defined in equation (6).

[0142] The operation of a dual-branch negative voltage multiplier with MOS transistors is similar to that of a single-branch one, so it will not be described further for the sake of simplicity.

[0143] Tables I and II, provided at the end of the description, summarize the open-circuit load voltage V of the voltage multiplier circuits discussed in this paper. O Output resistance R OUT and total capacitance C TOT The formula.

[0144] One or more embodiments may be applied, by way of example only, to a monolithic octal driver for a MEMS (Micro-Electro-Mechanical Systems) switch, wherein the driver's power supply rail V OUT =70V from power supply V DD = 3.3V to start generation. For example, one or more embodiments can be implemented using silicon-on-insulator (SOI) technology such as SOI-BCD6s technology and pump capacitors with a 12V operating voltage. Considering a 3.0V regulated power supply, such an exemplary multiplier can have almost N=24 stages. Furthermore, assuming V IN =V CK =3.0V, M can be selected to divide the operating voltage of the pump capacitor (e.g., 12V) by the regulated power supply (e.g., 3.0V). So far, M can be equal to 4 because the maximum voltage across the pump capacitor will not exceed the operating value of 12V. According to equation (9), when M=1, a 24-stage N-stage Cockcroft-Walton multiplier will be 204 times larger than a Dickson, while according to equation (9) with M=4, a multiplier with 24 N-stages and 4 M-stages according to one or more embodiments will be 15.2 times larger than a Dickson and 13.4 times smaller than a Cockcroft-Walton.

[0145] One or more embodiments can therefore provide an integrated voltage multiplier circuit with a reduced silicon area footprint.

[0146] Without prejudice to the fundamental principles and without departing from the scope of protection, the details and embodiments may vary, even significantly, relative to the content described by way of example only.

[0147] The scope of protection is determined by the appended claims.

[0148] Table 1

[0149] Multiplier type Diode multiplier Multiplier with MOS transistor positive voltage <![CDATA[V O =V IN +N·V CK -(N+1)·V D ]]> <![CDATA[V O =V IV +N·V CK ]]> negative voltage <![CDATA[V O =V IN -N·V CK +(N+1)·V D ]]> <![CDATA[V O =V IN -N·V CK ]]>

[0150] Table 2

[0151]

Claims

1. A voltage multiplier circuit, comprising: The first input node and the second input node are configured to be coupled to a voltage source to receive an input voltage between the first input node and the second input node; The first output node and the second output node are configured to be coupled to an output capacitor to generate an output voltage across the output capacitor; A first input control node and a second input control node, the first input control node being configured to receive a first clock signal and the second input control node being configured to receive a second clock signal, the second clock signal being inverted from the first clock signal, wherein the voltage multiplier circuit switches between a first commutation state and a second commutation state according to the values ​​of the first clock signal and the second clock signal. An ordered sequence of intermediate voltage nodes is arranged between the first input node and the first output node, the ordered sequence including a first ordered subsequence of intermediate voltage nodes and a second ordered subsequence of intermediate voltage nodes; A corresponding capacitor is coupled between each odd intermediate voltage node in the first ordered subsequence of the ordered sequence and the first input control node, wherein the first intermediate voltage node in the first ordered subsequence is configured to be selectively coupled to the first input node; A corresponding capacitor is coupled between each even-numbered intermediate voltage node and the second input control node in the first ordered subsequence of the ordered sequence; A corresponding capacitor is coupled between each odd-numbered intermediate voltage node in the second ordered subsequence of the ordered sequence and the corresponding odd-numbered intermediate voltage node in the first ordered subsequence of the ordered sequence; A corresponding capacitor coupled between each even-numbered intermediate voltage node in the second ordered subsequence of the ordered sequence and the corresponding even-numbered intermediate voltage node in the first ordered subsequence of the ordered sequence; and A first plurality of selectively conductive electronic components are coupled to the intermediate voltage node of the ordered sequence, wherein: In the first commutation state of the voltage multiplier circuit, the first plurality of selectively conductive electronic components are configured to provide conductive paths between each even-numbered intermediate voltage node in the ordered sequence and the corresponding next odd-numbered intermediate voltage node of the ordered sequence, a conductive path between the first input node and the first intermediate voltage node of the ordered sequence, and a conductive path between the last intermediate voltage node of the ordered sequence and the first output node. In the second commutation state of the voltage multiplier circuit, the first plurality of selectively conductive electronic components are configured to provide a conductive path between each odd intermediate voltage node in the ordered sequence and the corresponding next even intermediate voltage node of the ordered sequence.

2. The voltage multiplier circuit according to claim 1 further includes: Other ordered sequences of intermediate voltage nodes are arranged between the first input node and the first output node, and the other ordered sequences include the corresponding first ordered subsequence and the corresponding second ordered subsequence of the intermediate voltage nodes. A corresponding capacitor is coupled between each odd intermediate voltage node in the first ordered subsequence of the other ordered sequence and the second input control node, wherein the first intermediate voltage node in the first ordered subsequence of the other ordered sequence is configured to be selectively coupled to the first input node; The corresponding capacitors coupled between each even-numbered intermediate voltage node and the first input control node in the first ordered subsequence of the other ordered sequence; A corresponding capacitor is coupled between each odd-numbered intermediate voltage node in the second ordered subsequence of the other ordered sequence and the corresponding odd-numbered intermediate voltage node in the first ordered subsequence of the other ordered sequence; as well as A corresponding capacitor coupled between each even-numbered intermediate voltage node in the second ordered subsequence of the other ordered sequence and the corresponding even-numbered intermediate voltage node in the first ordered subsequence of the other ordered sequence; and Several other selectively conductive electronic components are coupled to the intermediate voltage node of the other ordered sequence, wherein: In the first commutation state of the voltage multiplier circuit, the other plurality of selectively conductive electronic components are configured to provide a conductive path between each odd-numbered intermediate voltage node in the other ordered sequence and the corresponding next even-numbered intermediate voltage node of the other ordered sequence, and In the second commutation state of the voltage multiplier circuit, the other plurality of selectively conductive electronic components are configured to provide conductive paths between each even-numbered intermediate voltage node in the other ordered sequence and the corresponding next odd-numbered intermediate voltage node of the other ordered sequence, a conductive path between the first input node and the first intermediate voltage node of the other ordered sequence, and a conductive path between the last intermediate voltage node of the other ordered sequence and the first output node.

3. The voltage multiplier circuit of claim 2, wherein the first plurality of selectively conductive electronic components and the other plurality of selectively conductive electronic components include a latching charge pump unit string arranged between the first input node and the first output node.

4. The voltage multiplier circuit of claim 2, wherein the first plurality of selectively conductive electronic components comprises p-channel transistors and n-channel transistors arranged in current paths between each subsequent intermediate voltage node pair of the ordered sequence, and wherein the other plurality of selectively conductive electronic components comprises other p-channel transistors and other n-channel transistors arranged in current paths between each subsequent other intermediate voltage node pair of the other ordered sequence.

5. The voltage multiplier circuit according to claim 4, wherein: The control terminal of the p-channel transistor is coupled to the m-th intermediate voltage node of the other ordered sequence of intermediate voltage nodes, and the control terminal of the n-channel transistor is coupled to the (m+1)-th intermediate voltage node of the other ordered sequence of intermediate voltage nodes; and The control terminals of the other p-channel transistors are coupled to the m-th intermediate voltage node of the ordered sequence of intermediate voltage nodes, and the control terminals of the other n-channel transistors are coupled to the (m+1)-th intermediate voltage node of the ordered sequence of intermediate voltage nodes.

6. The voltage multiplier circuit according to claim 4, wherein: The control terminal of the p-channel transistor is coupled to the (m+1)th intermediate voltage node of the other ordered sequence of intermediate voltage nodes, and the control terminal of the n-channel transistor is coupled to the mth intermediate voltage node of the other ordered sequence of intermediate voltage nodes; and The control terminals of the other p-channel transistors are coupled to the (m+1)th intermediate voltage node of the ordered sequence of intermediate voltage nodes, and the control terminals of the other n-channel transistors are coupled to the mth intermediate voltage node of the ordered sequence of intermediate voltage nodes.

7. The voltage multiplier circuit of claim 1, wherein the first plurality of selectively conductive electronic components includes diodes arranged in a string between the first input node and the first output node, and wherein the intermediate voltage node is located between subsequent diodes in the string.

8. The voltage multiplier circuit of claim 7, wherein the diode is arranged to selectively conduct from the first input node toward the first output node.

9. The voltage multiplier circuit of claim 7, wherein the diode is arranged to selectively conduct from the first output node toward the first input node.

10. The voltage multiplier circuit of claim 1, wherein the first plurality of selectively conductive electronic components comprises transistors arranged in a string between the first input node and the first output node, and wherein the intermediate voltage node is located between subsequent transistors in the string.

11. The voltage multiplier circuit of claim 10, further comprising a control circuit means configured to activate the transistor to conduct from the first input node toward the first output node based on the values ​​of the first clock signal and the second clock signal.

12. The voltage multiplier circuit of claim 10, further comprising a control circuit means configured to activate the transistor to conduct from the first output node toward the first input node based on the values ​​of the first clock signal and the second clock signal.

13. The voltage multiplier circuit of claim 1, wherein the ordered sequence of intermediate voltage nodes includes at least one third ordered subsequence of intermediate voltage nodes, and the voltage multiplier circuit further comprises: A corresponding capacitor coupled between each odd-numbered intermediate voltage node in the at least one third ordered subsequence of the ordered sequence and the corresponding odd-numbered intermediate voltage node in the preceding ordered subsequence of the ordered sequence; as well as A corresponding capacitor is coupled between each even-numbered intermediate voltage node in the at least one third ordered subsequence of the ordered sequence and the corresponding even-numbered intermediate voltage node in the preceding ordered subsequence of the ordered sequence.

14. The voltage multiplier circuit according to claim 1, further comprising: A first clock generator is coupled to the first input control node, and the first clock generator is configured to generate the first clock signal; as well as A second clock generator, coupled to the second input control node, is configured to generate a second clock signal that is inverted from the first clock signal.

15. The voltage multiplier circuit of claim 1, wherein the voltage multiplier circuit is implemented in a semiconductor chip, and wherein the capacitor is integrated in the semiconductor chip.

16. An integrated circuit, comprising: The input node is configured to receive the input voltage. An output node is configured to be coupled to an output capacitor and configured to generate an output voltage higher than the input voltage; The first input control node is configured to receive the first clock signal; The second input control node is configured to receive a second clock signal, which is inverted from the first clock signal, wherein the integrated circuit switches between a first commutation state and a second commutation state according to the first clock signal and the second clock signal. An ordered sequence of intermediate voltage nodes is arranged between the input node and the output node, the ordered sequence comprising a first ordered subsequence of intermediate voltage nodes and a second ordered subsequence of intermediate voltage nodes; A corresponding capacitor is coupled between each odd intermediate voltage node in the first ordered subsequence of the ordered sequence and the first input control node, wherein the first intermediate voltage node in the first ordered subsequence is configured to be selectively coupled to the input node; A corresponding capacitor is coupled between each even-numbered intermediate voltage node and the second input control node in the first ordered subsequence of the ordered sequence; A corresponding capacitor is coupled between each odd-numbered intermediate voltage node in the second ordered subsequence of the ordered sequence and the corresponding odd-numbered intermediate voltage node in the first ordered subsequence of the ordered sequence; A corresponding capacitor coupled between each even-numbered intermediate voltage node in the second ordered subsequence of the ordered sequence and the corresponding even-numbered intermediate voltage node in the first ordered subsequence of the ordered sequence; and A first plurality of selectively conductive electronic components are coupled to the intermediate voltage node of the ordered sequence, wherein: In the first commutation state, the first plurality of selectively conductive electronic components are configured to provide conductive paths between each even-numbered intermediate voltage node in the ordered sequence and the corresponding next odd-numbered intermediate voltage node of the ordered sequence, a conductive path between the input node and the first intermediate voltage node of the ordered sequence, and a conductive path between the last intermediate voltage node of the ordered sequence and the output node. In the second commutation state, the first plurality of selectively conductive electronic components are configured to provide a conductive path between each of the odd intermediate voltage nodes in the ordered sequence and the corresponding next even intermediate voltage node of the ordered sequence.

17. The integrated circuit of claim 16, wherein the first plurality of selectively conductive electronic components comprises a plurality of diodes arranged in a string between the input node and the output node.

18. The integrated circuit of claim 17, wherein each of the plurality of diodes is implemented using a transistor.

19. The integrated circuit of claim 16, wherein each of the first plurality of selectively conductive electronic components comprises: First node, second node, third node, and fourth node; A first n-channel transistor has a current path coupled between the first node and the third node; The first p-channel transistor has a current path coupled between the third node and the second node; The second n-channel transistor has a current path coupled between the first node and the fourth node; as well as The second p-channel transistor has a current path coupled between the fourth node and the second node, wherein the third node is coupled to the second input control node, and wherein the fourth node is coupled to the first input control node.

20. A method comprising: Receive the input voltage at the input node; An output voltage is generated at an output node, which is coupled to an output capacitor. The output voltage is higher than the input voltage. An ordered sequence of intermediate voltage nodes is arranged between the input node and the output node. The ordered sequence includes a first ordered subsequence of intermediate voltage nodes and a second ordered subsequence of intermediate voltage nodes. A corresponding capacitor is coupled between each odd-numbered intermediate voltage node in the second ordered subsequence of the ordered sequence and a corresponding odd-numbered intermediate voltage node in the first ordered subsequence of the ordered sequence. A corresponding capacitor is coupled between each even-numbered intermediate voltage node in the second ordered subsequence of the ordered sequence and a corresponding even-numbered intermediate voltage node in the first ordered subsequence of the ordered sequence. A first plurality of selectively conductive electronic components are coupled to the intermediate voltage nodes of the ordered sequence. A first clock signal is received at a first input control node, wherein a corresponding capacitor is coupled between each odd intermediate voltage node in the first ordered subsequence of the ordered sequence and the first input control node, wherein the first intermediate voltage node in the first ordered subsequence is selectively coupled to the input node; A second clock signal is received at the second input control node. The second clock signal is inverted compared with the first clock signal. A corresponding capacitor is coupled between each even-numbered intermediate voltage node in the first ordered subsequence of the ordered sequence and the second input control node. Based on the first clock signal and the second clock signal, switch between the first commutation state and the second commutation state; In the first commutation state, the first plurality of selectively conductive electronic components provide a conductive path between each even-numbered intermediate voltage node in the ordered sequence and the corresponding next odd-numbered intermediate voltage node of the ordered sequence, a conductive path between the input node and the first intermediate voltage node of the ordered sequence, and a conductive path between the last intermediate voltage node of the ordered sequence and the output node. as well as In the second commutation state, the first plurality of selectively conductive electronic components are used to provide a conductive path between each odd intermediate voltage node in the ordered sequence and the corresponding next even intermediate voltage node of the ordered sequence.

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