An ultra-low on-resistance flatness analog switch circuit

Abstract

The present invention belongs to the field of integrated circuits, and specifically relates to an ultra-low on-resistance flatness analog switch circuit, which includes a control circuit and a switch circuit; the control circuit includes three NPN-type transistors, three PNP-type transistors, two resistors, and a diode, and each device is connected according to a circuit diagram to control the switch circuit; the switch circuit includes three JFET field-effect transistors, and the three JFET field-effect transistors are interconnected to form a switch circuit; the control circuit is connected to the switch circuit to control the switching of the switch circuit; in the circuit of the present invention, a switch control signal is converted by the control circuit to control the switching of the switch tube; when the EN in the control circuit is at a low level, the analog switch is in an off state, and when the EN is at a high level, the analog switch is in an on state, at this time, the on-resistance flatness can be guaranteed to be within 1%, thereby improving the insertion loss and total harmonic distortion parameter performance of the analog switch.

Description

Technical Field

[0001] The present invention belongs to the field of integrated circuits, and in particular relates to an ultra-low on-resistance flatness analog switch circuit. Background Art

[0002] Analog switches, integrated circuit components that control analog signals and select specific transmission paths, are widely used in data acquisition, process control, instrumentation, audio and video systems, and other applications. When transmitting signals with high transmission quality requirements, such as audio and video, the insertion loss and total harmonic distortion (THD) performance of analog switches plays a key role in signal transmission quality. The flatness of the analog switch's on-resistance affects these parameters; the lower the on-resistance flatness, the better the insertion loss and THD performance. This means that for high-quality signal transmission, the on-resistance flatness of the analog switch should be as low as possible.

[0003] At present, in the design process of analog switch circuit, in order to reduce its on-resistance flatness, it is usually adopted to connect PMOS and NMOS devices in parallel, substrate follower, constant V GS However, even if the analog switch circuit adopts the technology of connecting PMOS and NMOS devices in parallel and substrate following, it is difficult to reduce the on-resistance to below 10%. GS Although this technology can keep the on-resistance at a fixed value, its circuit design requires the use of complex circuit structures such as gate-source voltage generation circuits and charge pumps, which brings certain challenges to the circuit's low power consumption, response speed, and reliability. Summary of the Invention

[0004] In order to solve the problem that the on-resistance flatness of analog switch circuits is difficult to reduce to below 10% even with existing technical means, the present invention proposes an ultra-low on-resistance flatness analog switch circuit, which includes a control circuit and a switch circuit, wherein the control circuit is used to control the switch circuit; the control circuit includes three NPN transistors, three PNP transistors, two resistors and a diode; the base of the NPN transistor Q1 serves as a control signal input terminal, the collector is connected to the base of the NPN transistor Q2 and the base of the NPN transistor Q6 respectively, and then connected to the power supply input terminal VDD, and the emitter is connected to the collector of the second resistor R2, the third resistor R3 and the PNP transistor Q5 respectively. The emitter-collector of the NPN transistor Q2 is connected to the other end of the second resistor R2, and the collector is respectively connected to the collector of the PNP transistor Q3, the base of the PNP transistor Q3, and the base of the PNP transistor Q4; the emitter-collector of the PNP transistor Q3 is connected to the emitter of the PNP transistor Q4 and the positive electrode of the diode D1, and then connected to the power input terminal VDD; the collector of the PNP transistor Q4 is connected to the switching circuit; the cathode of the diode D1 is respectively connected to the collector of the NPN transistor Q6 and the base of the PNP transistor Q5; the emitter-collector of the NPN transistor Q6 is connected to the other end of the third resistor R3; and the emitter of the PNP transistor Q5 is connected to the switching circuit.

[0005] Preferably, the control circuit also includes a first resistor R1, one end of the first resistor is connected to the power input terminal VDD, and the other end is respectively connected to the collector of the NPN transistor Q1, the base of the NPN transistor Q2 and the base of the NPN transistor Q6, for starting the control circuit.

[0006] Preferably, the switching circuit includes three JFET field-effect transistors, the drain of JFET transistor P1 serves as the output end of the switching circuit, the source is connected to the source of JFET transistor P3, and the gate is respectively connected to the gate of JFET transistor P2, the source of JFET transistor P2 and the gate of JFET transistor P3; the drain of JFET transistor P2 is connected to the drain of JFET transistor P3; the port after the source of JFET transistor P1 is connected to the source of JFET transistor P3 serves as the input end of the switching circuit; and the switching circuit is connected to the control circuit.

[0007] Furthermore, the connection between the switch circuit and the control circuit includes: the collector of the PNP transistor Q4 of the control circuit is connected to the source of the JFET transistor P2, and the emitter of the PNP transistor Q5 of the control circuit is connected to the drain of the JFET transistor P2.

[0008] Beneficial effects of the present invention:

[0009] The present invention designs an analog switch circuit with ultra-low on-resistance flatness. After the switch control signal EN in the circuit is converted by the control circuit, it controls the on and off of the switch tube P1. When EN in the control circuit is at a low level, the analog switch is in the off state, and when EN is at a high level, the analog switch is in the on state. At this time, its on-resistance flatness can be guaranteed to be within 1%, thereby improving the performance of parameters such as insertion loss and total harmonic distortion of the analog switch and providing high-quality signal transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 This is a circuit diagram of an ultra-low on-resistance flatness analog switch according to an embodiment of the present invention;

[0011] Figure 2 This is a simulation diagram of the on-resistance of the analog switch circuit with ultra-low on-resistance flatness of the present invention. DETAILED DESCRIPTION

[0012] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0013] An analog switch circuit with ultra-low on-resistance flatness comprises a control circuit and a switch circuit, wherein the control circuit controls the switch circuit, and the switch circuit controls the on and off of the system. The analog switch circuit with ultra-low on-resistance flatness can achieve an on-resistance flatness below 1%, improving the analog switch's performance parameters such as insertion loss and total harmonic distortion, and providing a high-quality signal transmission path.

[0014] A specific implementation of an ultra-low on-resistance flatness analog switch circuit, such as Figure 1As shown, the control circuit of the circuit includes: three NPN transistors, three PNP transistors, two resistors and a diode; the base of the NPN transistor Q1 serves as the control signal input terminal, the collector is connected to the base of the NPN transistor Q2 and the base of the NPN transistor Q6 respectively, and then connected to the power input terminal VDD, the emitter is connected to the second resistor R2, the third resistor R3 and the collector of the PNP transistor Q5 respectively, and then grounded; the emitter of the NPN transistor Q2 is connected to the other end of the second resistor R2, and the collector is connected to the PNP transistors Q5 respectively. The collector of the transistor Q3, the base of the PNP transistor Q3 and the base of the PNP transistor Q4 are connected; the emitter-collector of the PNP transistor Q3 is connected to the emitter of the PNP transistor Q4 and the positive electrode of the diode D1 and then connected to the power input terminal VDD; the collector of the PNP transistor Q4 is connected to the switching circuit; the cathode of the diode D1 is connected to the collector of the NPN transistor Q6 and the base of the PNP transistor Q5 respectively; the emitter-collector of the NPN transistor Q6 is connected to the other end of the third resistor R3; and the emitter of the PNP transistor Q5 is connected to the switching circuit.

[0015] In this embodiment, the control circuit further includes a first resistor R1, one end of which is connected to the power input terminal VDD, and the other end of which is respectively connected to the collector of the NPN transistor Q1, the base of the NPN transistor Q2, and the base of the NPN transistor Q6, for starting the control circuit.

[0016] A specific embodiment of an ultra-low on-resistance flatness analog switch circuit, the switch circuit includes three field-effect transistors (JFETs), the drain of JFET P1 serving as the output of the switch circuit, the source connected to the source of JFET P3, and the gate connected to the gate, source, and gate of JFET P2, P3, respectively; the drain of JFET P2 connected to the drain of JFET P3; the port connecting the source of JFET P1 and the source of JFET P3 serving as the input of the switch circuit; and the switch circuit connected to a control circuit.

[0017] The connection between the switch circuit and the control circuit includes: the collector of the PNP transistor Q4 of the control circuit is connected to the source of the JFET tube P2, and the emitter of the PNP transistor Q5 of the control circuit is connected to the drain of the JFET tube P2.

[0018] An ultra-low on-resistance flatness analog switch circuit includes a control circuit and a switch circuit. When the circuit operates normally, when a low level is input to the signal input terminal of the control circuit, the analog switch is in an off state; when a high level is input to the signal input terminal of the control circuit, the analog switch is in an on state.

[0019] Specifically, when the switch control signal EN is at a low level, the NPN transistor Q1 is in the cut-off state, and the base potentials V B =VDD, at this time Q2, Q6 are in the on state, at the same time PNP transistors Q3, Q4, Q5 are also in the on state, and Q3, Q4 work in the saturation region, at this time the gate point of PJFET tubes P1, P2, P3 is V G Close to VDD, as long as the signal potential of the analog input terminal S of the switch does not exceed V GS -V GS(off) (V GS(off) is the pinch-off voltage of the PJFET tube. The PJFET tube V GS(off) The analog switch is in the off state.

[0020] When the switch control signal EN is high, the NPN transistor Q1 is in the on state, and the base potentials of Q2 and Q6 are V B =GND, at this time Q2, Q6 are in the cut-off state, and at the same time PNP transistors Q3, Q4, Q5 are in the cut-off state due to the base current I B =0, so it is also in the cut-off state. At this time, the signal of the analog switch input terminal S is transmitted to the gates of P1, P2, and P3 through the PJFET tubes P3 and P2, so the V GS When it is 0, P1 is always in the on state, that is, the analog switch is in the on state.

[0021] from Figure 2 It can be seen that when the ultra-low on-resistance flatness analog switch circuit designed by the present invention is working normally, its on-resistance hardly changes with the voltage value of the analog input terminal S, that is, its on-resistance flatness can be controlled within 1%.

[0022] In summary, the present invention discloses an analog switch circuit with ultra-low on-resistance flatness, whose on-resistance flatness can be controlled within 1%, thereby improving the insertion loss, total harmonic distortion and other parameter performances of the analog switch, thereby improving the transmission quality of the analog switch device for audio and video signals and reducing the impact of the analog switch device on the transmission signal.

[0023] The above embodiments further illustrate the purpose, technical solutions and advantages of the present invention in detail. It should be understood that the above embodiments are only preferred implementation plans of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made to the present invention within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. An ultra-low on-resistance flatness analog switch circuit, the circuit comprising a control circuit and a switch circuit, wherein the control circuit is used to control the switch circuit; characterized in that: The control circuit includes three NPN transistors, three PNP transistors, two resistors and a diode; the base of the NPN transistor Q1 serves as the control signal input terminal, the collector is connected to the base of the NPN transistor Q2 and the base of the NPN transistor Q6 respectively, and then connected to the power input terminal VDD, the emitter is connected to the second resistor R2, the third resistor R3 and the collector of the PNP transistor Q5 respectively, and then grounded; the emitter of the NPN transistor Q2 is connected to the other end of the second resistor R2, and the collector is connected to the PNP transistor Q3 The collector of the PNP transistor Q3, the base of the PNP transistor Q4, and the base of the PNP transistor Q3 are connected; the emitter of the PNP transistor Q3 is connected to the emitter of the PNP transistor Q4 and the positive electrode of the diode D1, and then connected to the power input terminal VDD; the collector of the PNP transistor Q4 is connected to the switching circuit; the cathode of the diode D1 is connected to the collector of the NPN transistor Q6 and the base of the PNP transistor Q5; the emitter of the NPN transistor Q6 is connected to the other end of the third resistor R3; the emitter of the PNP transistor Q5 is connected to the switching circuit; The switching circuit includes three JFET field-effect transistors. The drain of JFET transistor P1 serves as the output end of the switching circuit, the source is connected to the source of JFET transistor P3, and the gate is connected to the gate of JFET transistor P2, the source of JFET transistor P2, and the gate of JFET transistor P3 respectively; the drain of JFET transistor P2 is connected to the drain of JFET transistor P3; the port after the source of JFET transistor P1 is connected to the source of JFET transistor P3 serves as the input end of the switching circuit; and the switching circuit is connected to the control circuit.

2. The ultra-low on-resistance flatness analog switch circuit according to claim 1, characterized in that: The control circuit also includes a first resistor R1, one end of which is connected to the power input terminal VDD, and the other end is respectively connected to the collector of the NPN transistor Q1, the base of the NPN transistor Q2 and the base of the NPN transistor Q6, for starting the control circuit.

3. The ultra-low on-resistance flatness analog switch circuit according to claim 1, characterized in that: The connection between the switch circuit and the control circuit includes: the collector of the PNP transistor Q4 of the control circuit is connected to the source of the JFET tube P2, and the emitter of the PNP transistor Q5 of the control circuit is connected to the drain of the JFET tube P2.

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