Drive acceleration circuit, LED drive circuit, and electronic device

Abstract

The present invention discloses a drive acceleration circuit, an LED drive circuit, and an electronic device. The drive acceleration circuit includes: an output circuit having a control terminal and an output terminal, the output terminal being configured to generate an output current; a bias circuit connected to the control terminal of the output circuit; the bias circuit biases the output circuit based on the bias current, thereby increasing the speed at which the output current is established. The technical solution provided by the present invention simplifies the circuit structure, enables faster output current establishment, ensures the accuracy of low output currents, and achieves more refined output dimming levels, resulting in a smoother dimming process.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and in particular to a driving acceleration circuit, an LED driving circuit and an electronic device. Background Art

[0002] In recent years, people have increasingly higher requirements for LEDs to achieve better lighting or display effects. To meet these requirements, LED driver chips are required to provide current levels with higher resolution.

[0003] Currently, LED driver chips have two drive modes: DC dimming and pulse width modulation (PWM). PWM dimming allows for finer dimming without increasing the size of the circuit board, resulting in more natural transitions between dimming levels. However, in LED driver circuits, using PWM dimming can lead to a long build-up time for the output LED current, resulting in output current loss. This can cause the light to be too dim at low brightness levels and low output current accuracy. Summary of the Invention

[0004] In view of this, the present invention provides a driving acceleration circuit, an LED driving circuit and an electronic device, which have a simple circuit structure, can establish the output current more quickly, and ensure the accuracy of the small output current, making the output dimming level more delicate and the dimming process smoother.

[0005] In order to achieve the above object, the present invention provides the following technical solutions:

[0006] A driving acceleration circuit, comprising:

[0007] An output circuit having a control terminal and an output terminal, wherein the output terminal is used to generate an output current;

[0008] A bias circuit is connected to the control terminal of the output circuit; the bias circuit performs bias control on the output circuit based on the bias current to improve the establishment speed of the output current.

[0009] Preferably, in the above-mentioned driving acceleration circuit, the bias circuit has a first switching state and a second switching state;

[0010] Preferably, in the above-mentioned driving acceleration circuit, the bias tube connected to the current loop in the bias circuit has a first gate width-to-length ratio, which is used to pre-charge the first node; in the output stage of the output circuit, in the second switching state, the bias tube connected to the current loop in the bias circuit has a second gate width-to-length ratio, which is used to accelerate the establishment speed of the output current based on the first node potential; wherein, the first width-to-length ratio is smaller than the second width-to-length ratio.

[0011] 3. The driving acceleration circuit according to claim 2, wherein the first node is connected to a supplementary capacitor for increasing a charging voltage of the first node.

[0012] Preferably, in the above-mentioned driving acceleration circuit, the bias circuit includes a first bias tube and a second bias tube;

[0013] The gates of the first bias transistor and the second bias transistor are both connected to the switch control circuit, the drains of the two are both connected to the bias current source, and the sources of the two are both connected to a preset potential;

[0014] The gate of the first bias transistor is connected to the bias current source, and the supplementary capacitor is connected between the gate and the source of the first bias transistor;

[0015] The gate of the second bias transistor is connected to the control end of the output circuit.

[0016] Preferably, in the above-mentioned driving acceleration circuit, the gate width-to-length ratios of the first bias transistor and the second bias transistor are both smaller than W / L, and the sum of their gate width-to-length ratios is W / L; wherein W and L are both set constants.

[0017] Preferably, in the above-mentioned driving acceleration circuit, the gate lengths of the first bias tube and the second bias tube are both L, the gate width of the first bias tube is (1 / M)*W, and the gate width of the second bias tube is (M-1) / M*W, where M is a proportional coefficient set greater than 1, and W is a set constant.

[0018] Preferably, in the above-mentioned driving acceleration circuit, the bias circuit includes a first bias tube and a second bias tube;

[0019] The drain of the first bias transistor is connected to a bias current source, the source is connected to a preset potential, and the gate is connected to the first plate of the supplementary capacitor through a first switch control circuit; the second plate of the supplementary capacitor is connected to the preset potential, and the first plate is connected to the bias current source;

[0020] The drain of the second bias tube is connected to the bias current source, the source is connected to the preset potential, and the gate is connected to the first plate of the supplementary capacitor through a second switch control circuit; the gate of the second bias tube is connected to the control end of the output circuit.

[0021] Preferably, in the above-mentioned driving acceleration circuit, the width-to-length ratio of the gate of the first bias tube is less than W / L, and the width-to-length ratio of the gate of the first bias tube is equal to W / L.

[0022] Preferably, in the above-mentioned driving acceleration circuit, the gate lengths of the first bias tube and the second bias tube are both L, the gate width of the second bias tube is W, and the gate width of the first bias tube is smaller than W.

[0023] Preferably, in the above-mentioned driving acceleration circuit, the first bias tube, the second bias tube and the output tube in the output circuit are all NMOS.

[0024] Preferably, in the above-mentioned driving acceleration circuit, the sources of the first bias tube, the second bias tube and the output tube are all grounded, and the preset potential is zero potential;

[0025] The bias current source is connected to a power supply.

[0026] Preferably, in the above-mentioned driving acceleration circuit, the first bias tube, the second bias tube and the output tube in the output circuit are all PMOS.

[0027] Preferably, in the above-mentioned driving acceleration circuit, the sources of the first bias tube, the second bias tube and the output tube are all connected to a power supply, and the preset potential is the power supply voltage;

[0028] The bias current source is grounded.

[0029] Preferably, in the above-mentioned driving acceleration circuit, the output circuit comprises a first-stage output tube to an n-stage output tube connected in parallel, where n is a positive integer greater than 1;

[0030] The gate width-to-length ratio of the i-th stage output tube is Ki=2 i-1 , i is a positive integer not greater than n, and W and L are both set constants.

[0031] Preferably, in the above-mentioned driving acceleration circuit, the bias circuit has at least one bias tube, the output circuit has at least one output tube, the gate lengths of the bias tube and the output tube are both L, and the gate widths are different, and L is a set constant.

[0032] The present invention further provides an LED driving circuit, the LED driving circuit comprising: a driving acceleration circuit as described in any one of the above items;

[0033] The output end of the driving acceleration circuit is connected to the LED lamp.

[0034] The present invention further provides an electronic device, which includes the LED driving circuit as described above.

[0035] As can be seen from the above description, in the drive acceleration circuit, LED drive circuit, and electronic device provided by the technical solution of the present invention, the drive acceleration circuit includes: an output circuit having a control end and an output end, the output end being used to generate an output current; a bias circuit connected to the control end of the output circuit; the bias circuit is used to bias the output circuit based on the bias current to improve the establishment speed of the output current.

[0036] Furthermore, a bias circuit can be configured to include a first bias tube and a second bias tube. Based on a PWM control signal, the gates of the first bias tube and the second bias tube are controlled to be on and off. For example, if both bias tubes are NMOS, when the PWM control signal is low, the gates of the first bias tube and the second bias tube are controlled to be disconnected, the gate of the second bias tube is grounded, and the gate and drain of the first bias tube are connected to a bias current source. The bias current source pre-charges the gate of the first bias tube and the supplementary capacitor. When the PWM control signal is high, the gates of the first bias tube and the second bias tube are controlled to be connected, turning on the output tube, thereby accelerating the establishment of the output current. By applying the technical solution provided by the present invention, the circuit structure is simple, the output current can be established more quickly, and the accuracy of the small output current can be guaranteed, making the output dimming level more refined and the dimming process smoother. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without any creative work.

[0038] The structures, proportions, sizes, etc. depicted in the drawings of this specification are only used to match the contents disclosed in the specification so as to facilitate understanding and reading by persons familiar with this technology. They are not intended to limit the conditions under which the present invention can be implemented and therefore have no substantive technical significance. Any structural modifications, changes in proportional relationships, or adjustments in size should still fall within the scope of the technical contents disclosed in the present invention without affecting the effects and objectives that can be achieved by the present invention.

[0039] Figure 1 This is a schematic diagram of an LED driver circuit based on PWM control signal dimming;

[0040] Figure 2 This is a schematic diagram of another LED driver circuit based on PWM control signal dimming;

[0041] Figure 3 A schematic diagram of a driving acceleration circuit provided by an embodiment of the present invention;

[0042] Figure 4 A schematic diagram of another driving acceleration circuit provided by an embodiment of the present invention;

[0043] Figure 5 for Figure 4 A schematic diagram of a switching state of the circuit shown;

[0044] Figure 6 for Figure 4 Another schematic diagram of the switching state of the circuit shown;

[0045] Figure 7 A schematic diagram of another driving acceleration circuit provided by an embodiment of the present invention;

[0046] Figure 8 for Figure 7 A schematic diagram of a switching state of the circuit shown;

[0047] Figure 9 for Figure 7 Another schematic diagram of the switching state of the circuit shown;

[0048] Figure 10 A graph showing a change in output-stage gate voltage according to an embodiment of the present invention;

[0049] Figure 11 A schematic diagram of another driving acceleration circuit provided by an embodiment of the present invention;

[0050] Figure 12 A schematic diagram of an LED driving circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0051] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0052] As described in the background technology, there are two driving modes in the LED driver chip, DC dimming mode and dimming mode based on PWM (pulse width modulation) control signal. Compared with the DC dimming mode, the dimming mode based on PWM control signal uses PWM control signal dimming to achieve finer dimming without increasing too much area, making the dimming level transition more natural. PWM control signal dimming uses the duty cycle of the PWM control signal in the form of a square wave to control the on-off of the output tube to adjust the output current, thereby achieving the purpose of adjusting the light intensity. When the PWM control signal is low, the gate of the output driver tube is pulled low. When the PWM control signal is high, the gate of the output tube is connected to the mirror-biased gate to obtain the output current.

[0053] The current LED driver chip uses a PWM control signal for dimming at a mainstream clock frequency of 4M / 8M. Slower clock frequencies generally have a greater tolerance for slower output stage build-up speeds. For an 8M clock frequency, the output tube conduction time is a minimum of 125ns. Under these conditions, the output current build-up needs to be accelerated.

[0054] With an 8MHz clock frequency and 8-bit PWM dimming accuracy, the PWM control signal frequency is 31.25kHz. Even if the PWM resolution is increased by only 1 bit, adopting a 9-bit PWM control signal resolution, the output PWM control signal frequency will fall into the 20Hz-20kHz range, making the capacitor whistling on the power supply audible to the human ear. This has a serious impact on products that are more concerned about sound quality, such as: speakers, headphones, etc.

[0055] To increase the PWM control signal resolution and achieve finer dimming levels without causing the power capacitor's vibration frequency to fall within the human ear's audible range, the clock frequency can be increased. Using a 16MHz clock and 9-bit PWM resolution, 512 dimming levels can be achieved while ensuring the capacitor's vibration frequency is outside the audible range. With a 16MHz clock frequency, the output stage's minimum on-time is only 62.5ns. The original speed-up circuit would result in a loss of half the current. To maintain accuracy at low output currents, the output current needs to settle even faster.

[0056] refer to Figure 1 , Figure 1 The following is a schematic diagram of a PWM control signal dimming LED driver circuit. Figure 1 As shown, the LED driving circuit includes a bias circuit 1 and an output circuit 2. The output circuit 2 has a control terminal A and an output terminal OUT, and the output terminal is used to generate an output current. The bias circuit 1 includes: a bias current source I REF And bias tube M0.

[0057] The output circuit 2 may include: n parallel output tubes, which are connected in sequence from the first-stage output tube M1 to the n-stage output tube Mn, where n is a positive integer greater than 1.

[0058] It should be noted that in the embodiment of the present application, the required output circuit 2 can be designed based on the load demand, and the output circuit 2 is not limited to Figure 1 The circuit structure of multiple parallel output tubes shown can also be other circuit structures that require bias control.

[0059] The gates of the n parallel output transistors are all connected to the control terminal A, the sources are all grounded, and the drains are all connected to the output terminal OUT. The gate and drain of the bias transistor M0 are connected and biased by the bias current source I REF The gate of the bias transistor M0 is connected to the control terminal A through a switch control circuit controlled by a PWM control signal.

[0060] The gate width-to-length ratio of the bias tube M0 is the same as that of the first-stage output tube, which is W / L. W and L are set constants. The gate lengths of all tubes are the same, which is L. The number of gates of the bias tube M0 is 1, and the number of gates of the i-th stage output tube Mi is 2. i-1 i is a positive integer not greater than n. For example, the number of gates of the first-stage output tube M1 is 1, and the number of gates of the n-stage output tube Mn is 2. n-1 , which is equivalent to the proportional increase of the gate width-to-length ratio of each level of output tube. The gate width-to-length ratio of the i-th level output tube Mi is Ki=2 i-1 .

[0061] When the PWM control signal is low, the gate of the bias tube M0 is disconnected from the control terminal A, and the gate of the bias tube M0 is connected to the bias current source I REF Gate-source capacitance C gs0 Charging is carried out, the gates of the output tubes M1-Mn are connected to the ground, and the output current is 0.

[0062] When the PWM control signal is high, the gate of the bias tube M0 and the gates of the output tubes M1-Mn are connected together, and the bias current source I REF The gate-source capacitance C of the bias tube M0 and the output tubes M1-Mn gs0 -C gsn To charge. Among them, the gate-source capacitance of bias tube M0 is C gs0 , the gate-source capacitance of the i-th stage output tube is C gsi The gate-source capacitance is the parasitic capacitance between the gate and source of the MOS tube.

[0063] At the moment the PWM signal switches to high, the gate potential of bias transistor M0 decreases due to charge averaging. After a period of charging, the gates of bias transistor M0 and output transistors M1-Mn reach the desired potential, stabilizing the output current. Because output transistors M1-Mn are hundreds of times larger than bias transistor M0, the gate voltage builds up very slowly. In this application, gate-source capacitance refers to the parasitic capacitance between the gate and source of the corresponding MOS transistor.

[0064] refer to Figure 2 , Figure 2 This is another LED driver circuit schematic diagram based on PWM control signal dimming. Figure 2 As shown, in Figure 1 The basic LED driver circuit shown in the figure has a bias circuit 3 added for acceleration. This bias circuit 3 includes two bias current sources, IBIAS1 and IBIAS2, two NMOS transistors, N1 and N2, and two PMOS transistors, P1 and PSW. The gates of transistors N1 and N2 are connected, and their sources are both grounded. The drain of transistor N1 is connected to the source of transistor PSW via bias current source IBIAS1, while the drain of transistor N2 is connected to the source of transistor PSW via bias current source IBIAS2. The gate of transistor PSW is connected to a set control signal, and its drain is connected to the source of transistor P1. The gate of transistor P1 is connected to the drain of transistor N1, and the drain of transistor P1 is connected to the gate of bias transistor M0.

[0065] Bias current sources IBIAS1 and IBIAS2 are used to turn on transistor P1. The PSW transistor is a switching transistor that closes when the PWM control signal is high. Together, transistor P1 and bias current sources IBIAS1 and IBIAS2 charge the gates of output transistors M1-Mn, accelerating the buildup of their gate voltages and accelerating the output current, allowing the current to quickly rise from 0 to the desired value. Once the gate voltages of output transistors M1-Mn are established, transistor MB conducts, grounding the gate and drain voltages of transistor N2. Bias current source IBIAS1 pulls the gate of transistor P1 to the power supply, turning it off. This prevents the addition of additional current and the resulting deviation of the output stage current from the designed value.

[0066] Figure 2 The circuit shown adds a bias current to accelerate charging of the output tube's gate when the PWM control signal jumps high, and then turns off the bias current after completion. The output stage using this structure requires a settling time of 20ns-30ns. For a duty cycle of 1 / 255, the output current loss is about 1 / 6-1 / 4, and the current accuracy is seriously reduced.

[0067] Through the above method, we can know that Figure 1 The circuit structure shown cannot improve the output current settling speed, but Figure 2Although the circuit structure shown can improve the output current establishment speed to a certain extent, it cannot guarantee the current accuracy at low currents for faster clock frequencies. When using PWM dimming, the output LED current establishment time is too long, resulting in output current loss, causing the light to be too dim at low brightness and low output current accuracy. In addition, the existing technology requires the addition of additional bias circuits and control circuits in the circuit implementation, making the design more complicated.

[0068] Therefore, in order to solve the above problems, the present invention provides a driving acceleration circuit, an LED driving circuit, and an electronic device, wherein the driving acceleration circuit includes:

[0069] An output circuit having a control terminal and an output terminal, wherein the output terminal is used to generate an output current;

[0070] A bias circuit is connected to the control terminal of the output circuit; the bias circuit performs bias control on the output circuit based on the bias current to improve the establishment speed of the output current.

[0071] The present invention aims to improve the output current accuracy at higher frequencies and higher resolutions, especially at low currents, to achieve finer output dimming levels and a smoother dimming process. Furthermore, the present invention simplifies the circuit structure of the prior art, making it easier to implement.

[0072] Optionally, the output circuit can be configured to include multiple output tubes connected in parallel, and the bias circuit can be configured to include a first bias tube and a second bias tube, with the gates of the first bias tube and the second bias tube of the bias circuit both connected to a switch control circuit. The gates of the first bias tube and the second bias tube can be controlled to be on and off based on a PWM control signal. For example, if both bias tubes are NMOS, when the PWM control signal is low, the gates of the first bias tube and the second bias tube are controlled to be disconnected, the gate of the second bias tube is grounded, and the gate and drain of the first bias tube are connected to a bias current source. The bias current source pre-charges the gate of the first bias tube and the supplementary capacitor. When the PWM control signal is high, the gates of the first bias tube and the second bias tube are controlled to be connected, turning on the output tube, thereby accelerating the establishment of the output current. By applying the technical solution provided by the present invention, the circuit structure is simple, the output current can be established more quickly, and the accuracy of small output currents can be guaranteed, making the output dimming level more refined and the dimming process smoother.

[0073] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0074] refer to Figure 3 As shown, Figure 3 A schematic diagram of a driving acceleration circuit provided in an embodiment of the present application is provided. The driving acceleration circuit includes:

[0075] an output circuit 2, the output circuit 2 having a control terminal A and an output terminal OUT, the output terminal OUT being used to generate an output current;

[0076] A bias circuit 1 is connected to the control terminal A of the output circuit 1; the bias circuit 1 performs bias control on the output circuit 2 based on the bias current to improve the establishment speed of the output current.

[0077] In the embodiment of the present application, the bias circuit 1 is provided to accelerate the establishment of the output current. By optimizing the design of the bias circuit 1, the circuit structure can be simplified, and the output current can be established more quickly, ensuring the accuracy of the small output current, making the output dimming level more refined, and making the dimming process smoother.

[0078] The design principle of the bias circuit 1 in this application is described in detail below:

[0079] For MOS tubes working in the saturation region, the following formula is satisfied:

[0080]

[0081]

[0082] In the above formulas (1) and (2), I is the source-drain current of the MOS tube, μ n is the mobility, C OX is the gate oxide capacitance of the MOS tube, W is the gate width of the MOS tube, L is the gate length of the MOS tube, W / L is the gate width-to-length ratio, V gs is the gate-source voltage of the MOS tube, V TH is the threshold voltage of the MOS tube.

[0083] For a capacitor C, let its charging time be t, charging current be i, and voltage after charging be V. Then, we have:

[0084] i*t=C*V (3)

[0085] If driven based on PWM control signal, Figure 1 In the circuit shown, when the PWM control signal is high or low, the circuit operates in the open and closed states. When the PWM control signal is low, the output is closed, and the node NGATE1 of the output tube is pulled low. When the PWM control signal is high again, the node NGATE1 is charged to a high level, thereby generating an output. The acceleration process is to speed up the process of charging the node NGATE1 high.

[0086] When the PWM control signal is low, the gate voltage of bias tube M0 is V M0G, the gate voltage of M1 is 0V, and at the moment when the PWM control signal is high, the voltage of the control terminal A is consistent with the gate voltage of the bias tube M0 and is equal to V G After stabilization, the gate voltage of bias tube M0 is equal to the gate voltage of control terminal A, which is equal to V MG Therefore, the moment when the PWM control signal jumps to high is:

[0087] C gs0 ×V M0G =V G ×(C gs0 +C gs ) (4)

[0088]

[0089] Among them. C gs is the sum of the gate-source capacitance of all output tubes in output circuit 2, which is equal to C gs1 to C gsn The sum of these n capacitors.

[0090] Based on the above formula (3), the time required for output stabilization is:

[0091]

[0092] Through the above analysis, when the output current is determined by the output tube size, the stabilized gate voltage V MG To reduce the settling time, the bias current I REF Or increase the V at the moment of conduction G , based on formula (5), if we increase V G , increase the V at the moment of conduction G Can increase the V when turning off M0G .

[0093] The bias current I REF When the size of the power tube in output circuit 2 is fixed, the gate-source capacitance C of the first-stage output tube M1 in output circuit 2 is gs1 The output current is fixed, and the proportional coefficient K of the bias circuit 1 in the output stage cannot be changed. K is the sum of K1 to Kn. When the output circuit 2 is in the output stage, the gate width-to-length ratio W / L of the bias tube connected to the current loop cannot be changed. Based on the above formula (6), the only way is to increase the V of the output circuit 2 in the off stage. M0G , that is, it can only change the gate width-to-length ratio of the bias tube connected to the current loop in the bias circuit 1 when the output circuit 2 is turned off. For NMOS, it means changing the gate width-to-length ratio of the bias tube connected to the current loop when the PWM control signal is low.

[0094] Based on this, in an embodiment of the present application, bias circuit 1 is configured to have a first switching state and a second switching state. When output circuit 2 is in the off state, bias circuit 1 is in the first switching state. At this time, the bias transistor connected to the current loop of bias circuit 1 has a first gate width-to-length ratio, which is used to charge the first node. When output circuit 2 is in the output phase, bias circuit 1 is in the second switching state. At this time, the bias transistor connected to the current loop of bias circuit 1 has a second gate width-to-length ratio, which is used to accelerate the output current establishment speed of control terminal A based on the potential of the first node. The first width-to-length ratio is smaller than the second width-to-length ratio. The first node is the gate node of the bias transistor connected to the current loop.

[0095] In the first switching state, bias circuit 1 is configured to perform pre-charging based on a smaller first gate width-to-length ratio, thereby achieving a higher charging voltage. Furthermore, the supplementary capacitor connected to the first node enables more charge to be stored during the pre-charging process. Thus, when switching to the second switching state, after averaging the charges at control terminal A and bias circuit 1 based on the higher charging voltage, a higher voltage can be maintained, ensuring that the gate voltage of the output transistor reaches the required operating voltage more quickly, thereby accelerating the buildup of the output current.

[0096] Moreover, only one bias current source I is required REF To provide bias current for the bias circuit 1, a plurality of bias current sources are not required. The bias circuit 1 only needs two bias transistors and one supplementary circuit, and the circuit structure is simple.

[0097] In order to realize the bias circuit 1 of the above two switching states, one implementation method can be as follows: Figure 4 As shown, based on Figure 1 The circuit shown splits the bias tube M0 into two small-sized tubes with a gate width-to-length ratio smaller than W / L.

[0098] refer to Figure 4 , Figure 4 A schematic diagram of another driving acceleration circuit provided by an embodiment of the present invention.

[0099] like Figure 4 As shown, the driving acceleration circuit includes: an output circuit 2 and a bias circuit 1.

[0100] The output circuit 2 has a control terminal A and an output terminal OUT. The output terminal OUT is used to generate an output current, and the control terminal A is used to connect to the bias circuit 1.

[0101] If the load is an LED lamp, the output circuit 2 can be configured to include multiple output tubes connected in parallel. The implementation is as described above. The output circuit 2 includes the first-stage output tube M1 to the n-th-stage output tube Mn, where n is a positive integer greater than 1. The gate width-to-length ratio of the i-th-stage output tube Mi is Ki=2 i-1The gate width of the i-th stage output tube Mi is 2 i-1 W, the gate length is L.

[0102] The gates of the output tubes at each level are connected to the control terminal A of the output circuit 2 , the drains of the output tubes at each level are connected to the output terminal OUT, and the sources of the output tubes at each level are connected to a preset potential.

[0103] The bias circuit 1 includes a first bias transistor M00 and a second bias transistor M01 ; the gate width-to-length ratios of the first bias transistor M00 and the second bias transistor M01 are both smaller than W / L, and the sum of their gate width-to-length ratios is W / L.

[0104] The gates of the first bias transistor M00 and the second bias transistor M01 are both connected to the switch control circuit Q, and the drains of both are connected to the bias current source I REF , the sources of both are connected to the preset potential;

[0105] The gate of the first bias transistor M00 is connected to the bias current source I REF , a supplementary capacitor C1 is connected between its gate and source;

[0106] The gate of the second bias transistor M01 is connected to the control terminal A of the output circuit 2 .

[0107] In an embodiment of the present invention, the switch control circuit Q includes a PWM switch, which is configured to control the conduction state of the two bias transistors based on a PWM control signal. Specifically, during the output circuit-off phase, the gates of the first bias transistor M00 and the second bias transistor M01 are disconnected based on the PWM control signal, and the gate of the second bias transistor M01 is connected to a preset potential, thereby precharging the gate of the first bias transistor M00 and the supplementary capacitor C1. After the precharging is completed, the output circuit 2 enters the output phase. During the output phase, the gates of the first bias transistor M00 and the second bias transistor M01 are connected based on the PWM control signal to enable each output transistor.

[0108] exist Figure 4 In the illustrated embodiment, two NMOS bias transistors are used as an example. During the output circuit-off phase, the gates of the first bias transistor M00 and the second bias transistor M01 are disconnected based on a PWM control signal, and the gate of the second bias transistor M01 is grounded. This allows the gate of the first bias transistor M00 and the supplementary capacitor C1 to be precharged. After the precharge is complete, the output circuit 2 enters the output phase. During the output phase, the gates of the first bias transistor M00 and the second bias transistor M01 are connected based on a PWM control signal to enable each output transistor.

[0109] It should be noted that in the embodiment of the present application, the implementation of the switch control circuit Q is not limited to a PWM switch, and can also be other electronic switches, so that it has two processes: pre-charging and starting.

[0110] Optionally, the gate lengths of the first bias transistor M00 and the second bias transistor M01 are both set to L, the gate width of the first bias transistor M00 is (1 / M)*W, and the gate width of the second bias transistor M01 is (M-1) / M*W, where M is a proportional coefficient set to be greater than 1, and W is a set constant. The value of M can be set based on the output current buildup time, which is not limited in this embodiment of the present application.

[0111] In the embodiment of the present invention, taking the two bias transistors as NMOS as an example, the gates of the first bias transistor M00 and the second bias transistor M01 can be controlled to be on and off based on the PWM control signal. When the PWM control signal is low, the gates of the first bias transistor M00 and the second bias transistor M01 are controlled to be disconnected. When the PWM control signal is high, the gates of the first bias transistor M00 and the second bias transistor M01 are controlled to be connected.

[0112] refer to Figure 5 , Figure 5 for Figure 4 A schematic diagram of a switching state of the circuit shown, specifically, Figure 4 When the PWM control signal is low, the driving acceleration circuit shown in FIG1 controls the gates of the first bias tube M00 and the second bias tube M01 to be disconnected through the PWM switch, and the gate and drain of the first bias tube M00 are connected to the bias current source I REF The output end is connected to the first plate of the supplementary capacitor C1, the second plate of the supplementary capacitor C1 is grounded, the gate of the second bias tube M01 is grounded, the drain is connected to the drain of the first bias tube M00, the gates of the n output tubes M1-Mn are grounded, and the drains are all connected to the output end OUT, the bias current source I REF The gate of the first bias transistor M00 and the supplementary capacitor C1 are precharged. When the PWM control signal is low, the first bias transistor M00 is turned on and connected to the current loop. Taking the gate length of each MOS transistor as an example, relative to Figure 1 The bias tube M0 with a gate width of W, Figure 4 In the manner shown, the gate width W of the first bias transistor M00 is equal to (1 / M)*W, and the gate width-to-length ratio of the first bias transistor M00 becomes 1 / M of the original. REF Under this condition, node NGATE0 can get a higher V NGATE0 .

[0113] Based on the above formula (1), we can know that under the same bias current source I REF Under the condition that the source-drain current I of the MOS tube remains unchanged, when the gate width-to-length ratio decreases, VGS -V TH Increase, V TH unchanged, V gs It can be seen that by adjusting the gate width-to-length ratio of the bias circuit during the off phase of the output circuit 2, the gate-source voltage V gs . So relative to Figure 1 As shown in the circuit, the bias circuit 1 described in the technical solution of this application includes a first bias transistor M00 and a second bias transistor M01. The bias circuit 1 is precharged when the output circuit 2 is in the off stage, and the bias circuit 1 is turned on when the output circuit 2 is in the output stage. During the precharging and turning-on processes, the conduction states of the two bias transistors are different, which is equivalent to adjusting the gate width-to-length ratio of the bias transistors in the bias circuit 1 to achieve fast charging and turning-on processes.

[0114] refer to Figure 6 , Figure 6 for Figure 4 Another switching state of the circuit shown, specifically, represents Figure 4 When the control signal PWM is high, the illustrated drive acceleration circuit uses PWM switching to connect the gates of the first bias transistor M00 and the second bias transistor M01 together. The drains of the first bias transistor M00 and the second bias transistor M01 are also connected together, along with their gates. The gates of each output transistor are connected to the gates of the first bias transistor M00 and the second bias transistor M01. The charge originally on node NGATE0 is transferred to node NGATE1, causing the voltage on node NGATE0 to drop and the voltage on node NGATE1 to rise.

[0115] (C1+C gs00 )×V NGATE0 =V NGATE0 '×(C1+C gs00 +C gs01 +C gs1 +C gs2 +…+C gsn ) (7)

[0116] Among them, V NGATE0 is the voltage of node NGATE0 when the PWM control signal is low, V NGATE0 ' is the voltage of node NGATE0 when the PWM control signal is high, C gs00 is the gate-source capacitance of the first bias transistor M00, C gs01 is the gate-source capacitance of the second bias tube M01, and the gate-source capacitance of each level of output tube is C gs1 -C gsn .

[0117] According to the above formula (7), the added supplementary capacitor C1 can better stabilize the voltage V of the node NGATE0 of the first bias transistor M00 during the charge exchange process. NGATE0 If the supplementary capacitor C1 is not added, the gate width of the first bias transistor M00 is only 1 / M of the gate width of the original bias transistor M0. The gate capacitance C gs00 is very small, which causes the instantaneous charge when the PWM control signal jumps to high to be averaged and then obtain a very small V NGATE0 and V NGATE1 , and cannot play the role of accelerating the establishment of the output current. Therefore, adding the supplementary capacitor C1 can stabilize the voltage level of the node NGATE0.

[0118] In the technical solution of the present invention, based on the PWM control signal, the gates of the first bias tube M00 and the second bias tube M01 are controlled to be on and off. When the PWM control signal is low, as shown in FIG. Figure 5 As shown, the gates of the first bias tube M00 and the second bias tube M01 are controlled to be disconnected, the gate of the second bias tube M01 is grounded, and the gate and drain of the first bias tube M00 are connected to the bias current source I REF Connection, bias current source I REF The gate of the first bias tube M00 and the supplementary capacitor C1 are precharged. After the precharging is completed, when the PWM control signal is high, as shown in FIG. Figure 6 As shown, the gate connection of the first bias tube M00 and the second bias tube M01 is controlled to turn on the output tubes of each level, thereby accelerating the establishment of the output current and ensuring the accuracy of the small output current, making the output dimming level more delicate and the dimming process smoother.

[0119] Relative to Figure 1 As shown, the present invention primarily implements the process of splitting bias transistor M0, whose gate width-to-length ratio is W / L, into a first bias transistor M00 with a channel width-to-length ratio of W1 / L and a second bias transistor M01 with a channel width-to-length ratio of W2 / L, where W1 = (1 / M)*W and W2 = (M-1) / M*W. Supplementary capacitor C1 is then added to accelerate the output current buildup. This is equivalent to splitting bias transistor M0 into first bias transistor M00 and second bias transistor M01. The gate width of first bias transistor M00 is 1 / M of the original bias transistor M0's gate width, while the gate width of second bias transistor M01 is (M-1) / M of the original bias transistor M0's gate width. Therefore, using different M values can achieve different output current buildup speeds.

[0120] It should be noted that the first bias transistor M00 is in an operating state during the entire cycle of the PWM control signal, and the second bias transistor M01 only works when the PWM control signal is high and is in an off state at other times.

[0121] In the embodiment of the present invention, the gate lengths of the first bias transistor M00, the second bias transistor M01, and the output transistors M1-Mn are all L, where L is a set constant.

[0122] The gate width of the first bias transistor M00 is (1 / M)*W, and the gate width of the second bias transistor M01 is (M-1) / M*W, where M is a set proportional coefficient and is greater than 1, and W is a set constant.

[0123] Based on the above description, we can see that Figure 4 The method shown is equivalent to Figure 1 The original bias tube M0 is split into a first bias tube M00 and a second bias tube M01. The gate width of the first bias tube M00 is 1 / M of the gate width of the original bias tube. Different M values can be used to achieve different output current build-up speeds. The gate width of the first bias tube M00 is W1, and the gate width of the second bias tube M01 is W2. The sum of the gate widths of the first bias tube M00 and the second bias tube M01 is W1+W2=W.

[0124] In the embodiment of the present invention, the preset potential can be zero potential or a power supply voltage. If the first bias transistor M00, the second bias transistor M01, and the output transistors M1-Mn are all NMOS, the preset potential is zero potential, that is, grounded; if the first bias transistor M00, the second bias transistor M01, and the output transistors M1-Mn are all PMOS, the preset potential is the power supply voltage.

[0125] Figure 4-Figure 6 In the illustrated embodiment, the first bias transistor M00 , the second bias transistor M01 , and the output transistor in the output circuit 2 are all NMOS transistors.

[0126] The sources of the first bias tube M00, the second bias tube M01 and the output tube are all grounded, and the preset potential is zero potential; the bias current source I REF Connect to the power supply VDD.

[0127] In another way, Figure 7-Figure 9 As shown, Figure 7 A schematic diagram of another driving acceleration circuit provided by an embodiment of the present invention is shown. Figure 8 for Figure 7 A switching state diagram of the circuit shown, Figure 9 for Figure 7 Another switching state diagram of the circuit shown is shown. In this embodiment, the first bias tube M00, the second bias tube M01 and the output tube in the output circuit are all PMOS.

[0128] The sources of the first bias tube M00, the second bias tube M01 and the output tube are all connected to the power supply VDD, and the preset potential is the power supply voltage; the bias current source I REF Ground.

[0129] In the embodiment of the present invention, the NMOS tube is replaced with a PMOS tube, and its control method is the same as that of the above-mentioned NMOS embodiment, and the same effect can be achieved, which will not be repeated in the embodiment of the present application.

[0130] It should be noted that, optionally, in the driving acceleration circuit, the gate lengths of all MOS tubes are the same, namely, L, so that each MOS tube can be manufactured using the same process flow.

[0131] All MOS tubes in the driving acceleration circuit can be set to be PMOS or NMOS, so as to facilitate the preparation of each MOS tube in the same process flow and the control of the switch state.

[0132] refer to Figure 10 , Figure 10 This is a graph showing the output stage gate voltage variation according to an embodiment of the present invention. Figure 10 for Figure 4 The voltage changes of the nodes NGATE0 and NGATE1 in the manner shown in FIG. 1 and FIG. 2 when the PWM control signal becomes high. Figure 2 In the manner shown, the voltage at the node NGATE0_PRE changes when the PWM control signal jumps high.

[0133] like Figure 10 As shown, Figure 2 In the method shown, when the PWM control signal is low, the gate of the bias tube M0 is precharged to the voltage required for normal operation, so that the bias current of the output stage is established. When the PWM control signal jumps high, due to the large size of the output tube, the gate-source parasitic capacitance is hundreds of times that of the bias tube, causing the node NGATE0_PRE to drop to a very low level, and the bias current source I REF It takes a long time to charge the large capacitor, causing the voltage at the node NGATE1 of the output stage to be at a very low level in the initial stage of establishment, and the output current to establish slowly. Figure 2 The output current settling time of the method shown is about 30ns. When operating at a frequency of 16M, the minimum on-time of the output stage is 62.5ns, which will cause an output current loss of more than 50% and a serious reduction in accuracy.

[0134] like Figure 10As shown, when the PWM control signal is low, only the first bias transistor M00 is used to complete the initial establishment of the node NGATE0. The sum of the gate widths W1 of the first bias transistor M00 and the gate width W2 of the second bias transistor M01 is equal to the total bias transistor width W. Since the aspect ratio W1 / L of the first bias transistor M00 is less than W / L, at the same bias current source I REF under the condition, compared with the case where both the first bias transistor M00 and the second bias transistor M01 are used for gate voltage establishment, the gate voltage of the first bias transistor M00 will be charged to a higher level. When the PWM control signal is high, the voltage of the node NGATE0 drops. However, due to its relatively high voltage and the addition of the supplementary capacitor C1, it is ensured that more charge is stored at the node NGATE0 during the pre-charge stage. After charge averaging between the node NGATE0 and the node NGATE1, they are maintained at a higher voltage value, ensuring that the gate voltage of the output transistor reaches the required operating voltage faster and accelerating the establishment of the output current.

[0135] Therefore, compared with Figure 2 the method shown, the technical solution of the embodiment of the present invention can achieve the establishment of the output current faster. Based on the method shown in Figure 2 it can reduce the establishment time by half, ensure the accuracy of small currents at a faster operating frequency, and at the same time, due to the increase in the clock frequency, a more delicate dimming level can be achieved.

[0136] As can be seen from the above description, in the drive acceleration circuit provided by the technical solution of the present invention, based on the PWM control signal, the gate on and off of the first bias transistor M00 and the second bias transistor M01 are controlled. When the PWM control signal is low, the gates of the first bias transistor M00 and the second bias transistor M01 are controlled to be open-circuited, the gate of the second bias transistor M01 is grounded, and the gate and drain of the first bias transistor M00 are connected to the bias current source I REF The bias current source I REF pre-charges the gate of the first bias transistor M00 and the supplementary capacitor C1. When the PWM control signal is high, the gates of the first bias transistor M00 and the second bias transistor M01 are controlled to be connected, and the output transistor is turned on, thereby enabling the establishment of the output current faster, ensuring the accuracy of the small output current, making the output dimming level more delicate, and making the dimming process smoother.

[0137] In other methods, without splitting the bias transistor M0 in Figure 1 using an additional small transistor for the establishment of the initial bias gate voltage, or using different bias establishment small transistors for different establishment time selections, the same effect can also be achieved.

[0138] In order to implement the bias circuit 1 with the above two switching states, another implementation method can be as shown in Figure 11 Based on Figure 1 In the circuit shown, the bias tube M0 is retained, and a bias tube with a small gate width-to-length ratio and a supplementary capacitor C1 are added in front of the bias tube M0.

[0139] refer to Figure 11 As shown, Figure 11 A schematic diagram of another driving acceleration circuit provided by an embodiment of the present invention is shown. Figure 11 In the illustrated embodiment, the bias circuit 1 includes a first bias transistor and a second bias transistor. In this embodiment, the gate lengths of the first and second bias transistors are both L. The first bias transistor is a bias transistor MB with a gate width-to-length ratio of W1 / L, and the second bias transistor is a bias transistor M0 with a gate width-to-length ratio of W / L. W1 = (1 / M) * W.

[0140] exist Figure 11 In the embodiment shown, the gate width-to-length ratio of the first bias transistor is less than W / L, and the gate width-to-length ratio of the first bias transistor is equal to W / L. The gate width-to-length ratio and gate width of the first bias transistor are not limited.

[0141] like Figure 11 As shown, the drain of the first bias tube is connected to the bias current source I REF , the source is connected to a preset potential, the gate is connected to the first plate of the supplementary capacitor C1 through the first switch control circuit Q1; the second plate of the supplementary capacitor C1 is connected to the preset potential, and the first plate is connected to the bias current source I REF .

[0142] The drain of the second bias transistor is connected to the bias current source I REF , the source is connected to the preset potential, the gate is connected to the first plate of the supplementary capacitor C1 through the second switch control circuit Q2; the gate of the second bias tube is connected to the control terminal A of the output circuit 2.

[0143] The first switch control circuit Q1 can be implemented by a first PWM switch tube, and the second switch control circuit Q2 can be implemented by a second PWM switch tube. The first switch control circuit Q1 and the second switch control circuit Q2 can be controlled respectively by two PWM control signals with opposite phases. For example, the first switch control circuit Q1 can be controlled by a first PWM control signal PWMN, and the second switch control circuit Q2 can be controlled by a second PWM control signal PWMP.

[0144] The gate width of the second bias transistor is W, and the gate width of the first bias transistor is smaller than W. As mentioned above, the gate width of the first bias transistor can be set to W1, and the gate width-to-length ratio of the first bias transistor can be It should be noted that in Figure 11In the illustrated embodiment, the gate width of the first bias transistor is not limited to W1 = (1 / M) * W, as long as the width-to-length ratio of the gate of the first bias transistor is less than W / L.

[0145] exist Figure 11 In the circuit shown, all MOS tubes are NMOS for illustration. At this time, the preset potential is 0 potential, and connecting to the preset potential represents grounding. The other end of the current source is connected to the power supply VDD.

[0146] exist Figure 11 In the circuit shown, bias circuit 1 maintains Figure 1 When the bias transistor M0 in the embodiment is used as the second bias transistor, the bias circuit 1 only needs to add a supplementary capacitor C1 and a bias transistor MB with a gate width-to-length ratio smaller than W / L as the first bias transistor.

[0147] Based on the above formula (6), as mentioned above, by adjusting the gate width-to-length ratio of the first bias tube, the V of the output circuit 2 in the off stage can be increased. M0G When the second PWM control signal PWMP is low, the first bias tube is turned on and the gate of the second bias tube is grounded. If the first bias tube with a smaller gate width and length is connected to the current loop, a higher gate-source voltage V gs When the second PWM control signal PWMP is high, the gate of the first bias transistor is grounded, and the gate of the second bias transistor is connected to the bias current source I REF , and then connected to the current loop, so as to achieve the addition and establishment of the output current.

[0148] for Figure 11 In the method shown, if no supplementary capacitance is added, then:

[0149] C gs00 ×V NGATE0 =V NGATE1 ×(C gs0 +C gs ) (8)

[0150]

[0151] Among them, V NGATE0 Represents the voltage of node NGATE0, V NGATE1 Indicates the voltage of the node NGATE1.

[0152] The output stabilization time can be expressed as:

[0153]

[0154]

[0155]

[0156] exist Figure 11 In the embodiment shown, since the gate width-to-length ratio of the first bias transistor is relatively small, the charging voltage of the node NGATE0 can be relatively high. However, the small gate width-to-length ratio of the first bias transistor results in a large gate-source capacitance C gs00 Much smaller than the gate-source capacitance C of the second bias tube gs0 , which will result in an insignificant acceleration effect. Therefore, the bias circuit 1 is further provided with a supplementary capacitor C1 having a larger capacitance, and the capacitance of the supplementary capacitor C1 is much larger than the gate-source capacitance C gs00 And the gate-source capacitance C gs0 .

[0157] When the supplementary capacitor C1 is added, the following relationship is satisfied:

[0158] (C gs00 +C1)×V NGATE0 =V NGATE1 ×(C gs0 +C gs +C1) (13)

[0159]

[0160] The time required for the output to stabilize is:

[0161]

[0162] Since the capacitance of the supplementary capacitor C1 is much larger than the gate-source capacitance C gs00 And the gate-source capacitance C gs0 , so the charging voltage increase effect of node NGATE0 will be prominent, thereby shortening the output current establishment time.

[0163] Based on the above embodiment, another embodiment of the present invention further provides an LED driving circuit, such as Figure 10 As shown, Figure 10 This is a schematic diagram of an LED driver circuit according to an embodiment of the present invention. The LED driver circuit includes the driver acceleration circuit described in the above embodiment; the output end of the driver acceleration circuit is connected to an LED lamp 100. This LED driver circuit utilizes the driver acceleration circuit provided in the above embodiment, resulting in a simple circuit structure, faster output current establishment, and guaranteed accuracy of low output currents, resulting in more refined output dimming levels and a smoother dimming process.

[0164] Based on the above embodiment, another embodiment of the present invention further provides an electronic device, which includes the LED driving circuit described in the above embodiment.

[0165] The electronic device can be a speaker or a keyboard. The electronic device uses the LED driver circuit provided in the above embodiment. The circuit structure is simple, and the output current can be established more quickly while ensuring the accuracy of the small output current, making the output dimming level more delicate and the dimming process smoother.

[0166] The various embodiments in this specification are described in a progressive, parallel, or combined manner. Each embodiment focuses on the differences from other embodiments, and reference can be made to the common and similar parts between the various embodiments. The LED driver circuit and electronic device disclosed in the embodiments correspond to the drive acceleration circuit disclosed in the embodiments, so the description is relatively simple. For relevant details, refer to the description of the drive acceleration circuit.

[0167] It should be noted that in the description of the present invention, it should be understood that the terms "upper," "lower," "top," "bottom," "inner," "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate the description of the present invention and simplify the description. They do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present invention. When a component is considered to be "connected" to another component, it may be directly connected to the other component or there may be a centrally located component.

[0168] It should also be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that an article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such article or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the article or device comprising the aforementioned elements.

[0169] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present application. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application is not limited to the embodiments shown herein, but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A driving acceleration circuit, characterized in that: The driving acceleration circuit includes: An output circuit having a control terminal and an output terminal, wherein the output terminal is used to generate an output current; a bias circuit connected to the control terminal of the output circuit; the bias circuit performs bias control on the output circuit based on a bias current to improve a settling speed of the output current, the bias circuit having a first switching state and a second switching state; In the output circuit shutdown phase, in the first switching state, the bias transistor connected to the current loop in the bias circuit has a first gate width-to-length ratio, which is used to pre-charge the first node; in the output phase of the output circuit, in the second switching state, the bias transistor connected to the current loop in the bias circuit has a second gate width-to-length ratio, which is used to accelerate the establishment speed of the output current based on the first node potential; wherein the first gate width-to-length ratio is smaller than the second gate width-to-length ratio.

2. The driving acceleration circuit according to claim 1, wherein: The first node is connected to a supplementary capacitor for increasing a charging voltage of the first node.

3. The driving acceleration circuit according to claim 2, wherein: The bias circuit includes a first bias tube and a second bias tube; The gates of the first bias transistor and the second bias transistor are both connected to the switch control circuit, the drains of the two are both connected to the bias current source, and the sources of the two are both connected to a preset potential; The gate of the first bias transistor is connected to the bias current source, and the supplementary capacitor is connected between the gate and the source of the first bias transistor; The gate of the second bias transistor is connected to the control end of the output circuit.

4. The driving acceleration circuit according to claim 3, characterized in that: The gate width-to-length ratios of the first bias transistor and the second bias transistor are both smaller than W / L, and the sum of their gate width-to-length ratios is W / L; wherein W and L are both set constants.

5. The driving acceleration circuit according to claim 4, characterized in that: The gate lengths of the first bias tube and the second bias tube are both L, the gate width of the first bias tube is (1 / M)*W, and the gate width of the second bias tube is (M-1) / M*W, where M is a proportional coefficient set to be greater than 1.

6. The driving acceleration circuit according to claim 2, wherein: The bias circuit includes a first bias tube and a second bias tube; The drain of the first bias transistor is connected to a bias current source, the source is connected to a preset potential, and the gate is connected to the first plate of the supplementary capacitor through a first switch control circuit; the second plate of the supplementary capacitor is connected to the preset potential, and the first plate is connected to the bias current source; The drain of the second bias tube is connected to the bias current source, the source is connected to the preset potential, and the gate is connected to the first plate of the supplementary capacitor through a second switch control circuit; the gate of the second bias tube is connected to the control end of the output circuit.

7. The driving acceleration circuit according to claim 6, characterized in that: The width-to-length ratio of the gate of the first bias tube is less than W / L, and the width-to-length ratio of the gate of the first bias tube is equal to W / L; wherein W and L are both set constants.

8. The driving acceleration circuit according to claim 7, wherein: The gate lengths of the first bias tube and the second bias tube are both L, the gate width of the second bias tube is W, and the gate width of the first bias tube is smaller than W.

9. The driving acceleration circuit according to any one of claims 3 to 8, characterized in that: The first bias tube, the second bias tube and the output tube in the output circuit are all NMOS.

10. The driving acceleration circuit according to claim 9, characterized in that: The sources of the first bias tube, the second bias tube and the output tube are all grounded, and the preset potential is zero potential; The bias current source is connected to a power supply.

11. The driving acceleration circuit according to any one of claims 3 to 8, characterized in that: The first bias tube, the second bias tube and the output tube in the output circuit are all PMOS.

12. The driving acceleration circuit according to claim 11, wherein: The sources of the first bias tube, the second bias tube and the output tube are all connected to a power supply, and the preset potential is the power supply voltage; The bias current source is grounded.

13. The driving acceleration circuit according to claim 1, wherein: The output circuit includes a first-stage output tube and an n-th-stage output tube connected in parallel, where n is a positive integer greater than 1; The gate width-to-length ratio of the i-th stage output tube is Ki=2 i-1 , i is a positive integer not greater than n, and W and L are both set constants.

14. The driving acceleration circuit according to claim 1, wherein: The bias circuit has at least one bias tube, and the output circuit has at least one output tube. The gate lengths of the bias tube and the output tube are both L, and the gate widths are different. L is a set constant.

15. An LED driving circuit, characterized in that: include: The driving acceleration circuit according to any one of claims 1 to 14; The output end of the driving acceleration circuit is connected to the LED lamp.

16. An electronic device, characterized in that: The LED driving circuit comprises the LED driving circuit as claimed in claim 15.

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