A System and Method for Detecting the Inter-Chip Synchronization Performance of a High-Speed and High-Precision Analog-to-Digital Converter

Abstract

A system and method for detecting the inter-chip synchronization performance of a high-speed and high-precision analog-to-digital converter. The core lies in that the FPGA module receives the acquisition control signal from the host computer, controls four ADCs to simultaneously acquire the synchronously input analog sine signal, uploads the waveform data to the host computer for FFT and phase calculation, records the SNR parameter value and the phase difference between it and the calibrated ADC and makes it correspond to the chip number. After the whole batch of chips is tested, cluster analysis is performed on the two-dimensional data point set to determine the final cluster centers K1 and K2 of the two-dimensional data point set. Then, according to the actual engineering requirements, the phase difference distance value D and the minimum SNR are determined, and the two-dimensional data points whose distance from the final cluster center K1 is less than D and whose SNR is higher than the minimum requirement are calculated and screened out. Through the one-to-one correspondence between the two-dimensional data points and the chip numbers, sorting is carried out from the whole batch, and finally two sub-batches are obtained. The chip synchronization performance and SNR index within each sub-batch can meet the specified actual engineering requirements, and thus the detection is completed.

Description

Technical Field

[0001] The present invention relates to a system and method for detecting the inter-chip synchronization performance of a high-speed and high-precision analog-to-digital converter, belonging to the technical field of analog-to-digital converters. Background Art

[0002] With the rapid development of integrated circuit technology and communication technology, it has greatly promoted the development and application of analog-to-digital converter technology. The pipelined structure is the mainstream design structure of high-speed and high-precision analog-to-digital converters, which has the characteristics of high linearity, low power, low offset, and fast transient response speed. It is widely used in communication systems with high requirements for frequency domain characteristics such as spurious-free dynamic range and total harmonic distortion, imaging systems with high requirements for time domain characteristics such as noise and bandwidth, and data acquisition systems with high requirements for both time domain and frequency domain characteristics.

[0003] In application fields such as image detection, phased array radar, and electronic countermeasures that require multi-channel synchronous data acquisition, it is a very mature design idea to build a system using a single-chip multi-channel high-speed and high-precision analog-to-digital converter. However, with the gradual increase in the number of channels and the integration level of the application system, this design idea can no longer meet the requirements. The scheme of using multiple high-speed and high-precision analog-to-digital converters for synchronous acquisition to build a large array and high-integration system is the most widely used technology at present, but the application of synchronous acquisition of multiple high-speed and high-precision analog-to-digital converters will inevitably pose challenges to the design of inter-chip channel consistency.

[0004] By detecting and screening the inter-chip synchronization performance of high-speed and high-precision analog-to-digital converters, the complexity and uncertainty of board-level design can be reduced in the initial stage of system design. At the same time, mastering the phase difference data between multiple chips can further accurately perform phase compensation in the software programming stage of system design. Therefore, many users of high-speed and high-precision analog-to-digital converters have put forward higher requirements for the detection and screening of converters. Summary of the Invention

[0005] The technical problem to be solved by the present invention is: to overcome the deficiencies of the prior art and provide a system and method for detecting the inter-chip synchronization performance of a high-speed and high-precision analog-to-digital converter, which can complete the detection, screening, and sorting of the synchronization performance of high-speed and high-precision analog-to-digital converter chips of the same batch according to the specified engineering actual demand conditions.

[0006] The technical solution of the present invention is:

[0007] A system for detecting the inter-chip synchronization performance of a high-speed and high-precision analog-to-digital converter includes an FPGA module, a calibration ADC chip, a to-be-tested ADC chip, a clock management module, a power management module, a DC power supply, an analog signal source, a clock source, and a host computer;

[0008] The DC power supply is used to provide a 12V DC voltage to the power management module, which then converts the 12V voltage into the operating voltages required by other modules;

[0009] The analog signal source is used to provide analog input signals for calibrating the ADC chip and the ADC under test;

[0010] The clock source is used to provide an input clock to the clock management module;

[0011] The clock management module is used to receive the input clock and generate 4 channels of synchronous clocks to be provided to the calibration ADC chip and the ADC chip under test;

[0012] The FPGA module is used to receive the acquisition control signal sent by the host computer, complete the synchronous acquisition of the waveform data of the calibration ADC chip and the ADC chip under test, and upload it to the host computer through the UART interface;

[0013] The host computer is used to perform FFT and phase calculations on the waveform data, record the signal-to-noise ratio parameter value SNR and the phase difference TΔ between it and the calibration ADC chip, and make them correspond one by one with the chip numbers. At the same time, the host computer is also used to perform clustering analysis on the two-dimensional data point set composed of SNR and TΔ after the entire batch of chips is tested, and complete the screening and detection.

[0014] Further, it also includes a splitter. The input signal generated by the analog signal source is divided into N channels by the splitter and respectively input into a calibration ADC chip and N - 1 ADC chips under test, where N is a positive integer.

[0015] Further, the calibration ADC chip and the ADC chips under test are high-speed and high-precision pipelined ADC chips of the same batch.

[0016] Further, the calibration ADC chip is randomly selected from the chips of the same batch and is used to calibrate the phase difference between all the ADC chips under test in this batch and this calibration ADC chip, so as to form a phase difference data set.

[0017] Further, the host computer determines the final clustering center of the two-dimensional data point set through clustering analysis, and then combines the specified engineering actual requirement conditions to output the chip numbers to be sorted.

[0018] Further, the clustering analysis specifically includes:

[0019] (1) Select the calibration ADC chip randomly selected from the chips of the same batch as the initial clustering center K1';

[0020] (2) By calculating the distances between all data objects and K1', take the data object with the maximum distance from the clustering center as the initial clustering center K2';

[0021] (3) Calculate the distances from all data objects to K1' and K2' respectively, and classify the data objects into the clusters where the closer clustering centers are located, finally forming two large clusters;

[0022] (4) Recalculate the newly formed clusters to determine new clustering centers;

[0023] (5) Repeat the processes of steps (3) and (4) until the clustering centers are no longer updated, and determine the final clustering centers K1 and K2.

[0024] Furthermore, the present invention also proposes a method for detecting the inter-chip synchronization performance of an analog-to-digital converter, including the following steps:

[0025] Step 1: Randomly select one chip from the chips of the same batch as the calibration ADC chip, install the calibration ADC chip and the ADC chip to be tested on the test positions of the test board, and power on the system;

[0026] Step 2: The host computer sends a collection control signal. After receiving the control signal, the FPGA module completes the synchronous acquisition of the waveform data of the calibration ADC chip and the ADC chip to be tested, and uploads it to the host computer;

[0027] Step 3: The host computer performs FFT and phase calculation on the received waveform data, records the signal-to-noise ratio parameter values SNR of each converter and the phase difference TΔ between it and the calibration ADC, and makes them correspond one by one with the chip numbers;

[0028] Step 4: Replace all the ADC chips to be tested, and repeat steps 2 and 3 until all the chips in this batch are tested, forming a two-dimensional data point set composed of the SNR and TΔ of all the chips;

[0029] Step 5: Operate the host computer to perform clustering analysis on the two-dimensional data point set, specifically including:

[0030] (1) Use the calibration ADC chip randomly selected from the chips of the same batch as the initial clustering center K1';

[0031] (2) By calculating the distances from all data objects to K1', take the data object with the largest distance from the clustering center as the initial clustering center K2';

[0032] (3) Calculate the distances from all data objects to K1' and K2' respectively, and classify the data objects into the clusters where the closer clustering centers are located, finally forming two large clusters;

[0033] (4) Recalculate the newly formed clusters to determine new clustering centers;

[0034] (5) Repeat the processes of steps (3) and (4) until the clustering centers no longer update, and determine the final clustering centers K1 and K2.

[0035] Step 6: Input the phase difference distance value D and the minimum SNR required for the actual engineering requirements specified to the host computer, calculate and screen out the two-dimensional data points that meet the requirements, and output the chip numbers to be sorted according to the corresponding relationship of the numbers.

[0036] The beneficial effects brought by the present invention compared with the prior art are as follows:

[0037] (1) In the traditional production and testing process, the converter chip mainly focuses on the full-process testing of a single chip, and rarely pays attention to the inter-chip synchronization performance index. The present invention fills the gap in the detection direction of the inter-chip synchronization performance of high-speed and high-precision analog-to-digital converters.

[0038] (2) Different engineering applications have different synchronization performance and dynamic performance requirements. The present invention only needs to input the specified engineering indicators to the host computer to complete the output of the numbers of the circuits to be sorted, which has strong applicability and convenient operation, is suitable for the specific condition screening work of a large number of ADC chips, and greatly improves the production efficiency.

[0039] (3) The host computer outputs the chip numbers and the inter-chip phase difference to the chip user terminal. The chip user can use this data to further accurately perform phase compensation when applying the chip, which greatly shortens the development cycle of the user project. Description of the Drawings

[0040] Figure 1 is the block diagram of the inter-chip synchronization performance detection system of the high-speed and high-precision analog-to-digital converter of the present invention.

[0041] Figure 2 is the schematic diagram of the host computer operation panel of the system.

[0042] Figure 3 is the flow chart of the synchronization performance and dynamic performance test work of the system.

[0043] Figure 4 is the schematic diagram of the host computer clustering analysis process of the system. Detailed Embodiment

[0044] The following further elaborates on the present invention in detail in conjunction with the embodiments and the drawings.

[0045] The present invention provides a system for detecting the inter-chip synchronization performance of a high-speed and high-precision analog-to-digital converter. The power supply module, clock management module, DC power supply, clock source, and analog signal source are used to provide the basis for the normal operation of the system. The core lies in that the FPGA module receives the acquisition control signal sent by the host computer, starts to control four ADCs to simultaneously acquire the synchronized input analog sine signal, and after the acquisition is completed, uploads the waveform data to the host computer through the UART port. The host computer performs FFT and phase calculation on the waveform data, records the signal-to-noise ratio parameter values (SNR) of each converter and the phase difference (TΔ) between it and the calibrated ADC, and makes them correspond one by one with the chip numbers. After the entire batch of chips is tested, clustering analysis is performed on the two-dimensional data point set composed of SNR and TΔ; after the analysis of the data set is completed, the final clustering centers K1 and K2 of the two-dimensional data point set can be determined, and then according to the actual engineering requirements, the phase difference distance value D (such as 20 ps) and the minimum SNR are determined, and the two-dimensional data points whose distance from the final clustering center K1 is less than D and whose SNR is higher than the minimum value requirement are calculated and screened out, and then sorted from the entire batch through the one-to-one correspondence between the two-dimensional data points and the chip numbers. Finally, two sub-batches are obtained, and the synchronization performance and SNR indexes of the chips in each sub-batch can meet the specified actual engineering requirements. Thus, the system completes the detection work.

[0046] Specifically, as Figure 1 shown, a system for detecting the inter-chip synchronization performance of a high-speed and high-precision analog-to-digital converter proposed by the present invention includes an FPGA module, a calibrated ADC chip, a to-be-tested ADC chip, a clock management module, a power management module, a DC power supply, an analog signal source, a clock source, and a host computer.

[0047] The DC power supply is used to provide a 12V DC voltage to the power management module, and the power management module then converts the 12V voltage into the working voltages required by other modules;

[0048] The analog signal source is used to provide analog input signals for the calibrated ADC chip and the to-be-tested ADC;

[0049] The clock source is used to provide an input clock for the clock management module;

[0050] The clock management module is used to receive the input clock and generate 4 channels of synchronous clocks to be provided to the calibrated ADC chip and the to-be-tested ADC chip;

[0051] The FPGA module is used to receive the acquisition control signal sent by the host computer, complete the synchronous acquisition of the waveform data of the calibrated ADC chip and the to-be-tested ADC chip, and upload it to the host computer through the UART interface;

[0052] The host computer is used to perform FFT and phase calculation on waveform data, record the signal-to-noise ratio parameter value SNR and the phase difference TΔ between it and the calibrated ADC chip, and make them correspond one by one with the chip numbers. At the same time, the host computer is also used to perform clustering analysis on the two-dimensional data point set composed of SNR and TΔ after all the chips in the whole batch are tested, and complete the screening and detection.

[0053] Preferably, the present invention further includes a splitter. The input signal generated by the analog signal source is divided into N paths by the splitter and respectively input into a calibrated ADC chip and N-1 ADC chips to be tested, where N is a positive integer.

[0054] The calibrated ADC chip and the ADC chips to be tested are high-speed and high-precision pipelined ADC chips of the same batch. The calibrated ADC chip is randomly selected from the chips of the same batch and is used to calibrate the phase difference between all the ADC chips to be tested in this batch and this calibrated ADC chip, so as to form a phase difference data set.

[0055] The host computer determines the final clustering center of the two-dimensional data point set by completing the clustering analysis, and then outputs the chip numbers to be sorted in combination with the specified engineering actual requirement conditions.

[0056] The present invention also proposes a method for detecting the inter-chip synchronization performance of an analog-to-digital converter, including the following steps:

[0057] Step 1: Randomly select a chip from the chips of the same batch as the calibrated ADC chip, install the calibrated ADC chip and the ADC chips to be tested on the test stations of the test board, and power on the system;

[0058] Step 2: The host computer sends a collection control signal. After the FPGA module receives the control signal, it completes the synchronous collection of the waveform data of the calibrated ADC chip and the ADC chips to be tested, and uploads it to the host computer;

[0059] Step 3: The host computer performs FFT and phase calculation on the received waveform data, records the signal-to-noise ratio parameter value SNR of each converter and the phase difference TΔ between it and the calibrated ADC, and makes them correspond one by one with the chip numbers;

[0060] Step 4: Replace all the ADC chips to be tested, and repeat Step 2 and Step 3 until all the chips in this batch are tested, forming a two-dimensional data point set composed of SNR and TΔ of all the chips;

[0061] Step 5: Operate the host computer to perform clustering analysis on the two-dimensional data point set, specifically including:

[0062] (1) Use the calibrated ADC chip randomly selected from the chips of the same batch as the initial clustering center K1';

[0063] (2) By calculating the distances between all data objects and K1', the data object with the largest distance from the clustering center is taken as the initial clustering center K2'.

[0064] (3) Then, calculate the distances from all data objects to K1' and K2' respectively, and assign the data objects to the clusters where the closer clustering center is located, finally forming two large clusters.

[0065] (4) Recalculate the new clustering centers for the newly formed clusters.

[0066] (5) Repeat the processes of steps (3) and (4) until the clustering centers are no longer updated, and determine the final clustering centers K1 and K2.

[0067] Step 6: Input the phase difference distance value D and the minimum SNR required by the specified engineering practice to the host computer, calculate and filter out the two-dimensional data points that meet the requirements, and output the chip numbers to be sorted according to the corresponding relationship of the numbers.

[0068] Example:

[0069] As Figure 1 shown, a high-speed and high-precision inter-chip synchronization performance detection system for analog-to-digital converters provided in this embodiment includes an FPGA module, a calibration ADC and an ADC under test, a clock management module, a power management module, a DC power supply, an analog signal source, a clock source, and a host computer.

[0070] The DC power supply and the power module are responsible for providing the system working voltage. The analog signal source is used to provide four-way synchronous analog input signals through a 1:4 splitter. The clock source and the clock module are used to provide 4-way synchronous clocks. The FPGA module completes the synchronous acquisition and upload of the waveform data of the ADC. The host computer is responsible for system control and calculation analysis. Place the calibration ADC and the ADC under test on the test board. After the system is powered on, the FPGA module initializes and configures the control registers of the clock module and the ADC, and then detects whether the ADC data clock DCO is working properly and feeds back to the host computer software. After receiving the normal working feedback signal, the host computer sends an acquisition control signal to the FPGA module. After receiving the control signal, the FPGA acquires data and uploads it. After the data upload is completed, the host computer performs FFT and phase difference calculation on the data, records the test results, and completes a single test. Each time, 3 ADCs under test are replaced for testing. After testing all the chips in the same batch, a test data set is formed. Then, through the built-in algorithm of the host computer, cluster analysis is performed on the data set, and combined with the actual engineering requirements, the filtered data is output. The testing personnel complete the sorting and screening detection work of the two sub-batches of chips according to the chip numbers corresponding to the filtered data.

[0071] Figure 2Schematic diagram of the host computer software of the system shown. The lighting of the host computer port indicator indicates that normal communication has been established with the test board. When the feedback light of the ADC data clock DCO is lit after receiving, it means that data acquisition can start; click the acquisition calculation button to start acquiring and uploading waveform data, and the calculation results are displayed on the host computer panel for facilitating real-time observation of the system working status; after all chips are tested, click the clustering analysis button to analyze the data set; input the actual engineering index requirements, complete data screening and display on the panel, and the final results can be exported to a document through the result export button, which is convenient for completing the sorting work or providing to chip users.

[0072] Figure 3 is the flowchart of the synchronous performance and dynamic performance test work, Figure 4 (a)-(f) are schematic diagrams of the host computer clustering analysis process. Combining Figure 3 、 Figure 4 can more intuitively understand the entire working process of a high-speed and high-precision analog-to-digital converter inter-chip synchronization performance detection system provided by the present invention, including the following steps:

[0073] After the system is powered on, perform initialization configuration;

[0074] The FPGA detects whether the ADC data clock DCO is normal. If it is not normal, return to the initialization configuration process. If it is normal, feedback the normal signal to the host computer and wait for the acquisition control instruction;

[0075] After receiving the normal signal of the data clock DCO, the host computer sends a start acquisition control instruction to the FPGA, and the FPGA receives the control instruction to start acquiring waveform data and uploading;

[0076] After the host computer receives the data, calculate the signal-to-noise ratio SNR and phase difference TΔ index data of the waveform data, and record the data to complete a single test;

[0077] After the entire batch of chips is tested, the host computer performs clustering analysis on the data set, Figure 4 (a)-(f) illustrate the clustering analysis process of the data set; combined with the input actual engineering index requirements, complete the screening and detection work of two sub-batch circuits.

[0078] The content not described in detail in the specification of the present invention belongs to the well-known technology of those skilled in the art.

Claims

1. A high-speed and high-precision inter-chip synchronization performance detection system for analog-to-digital converters, characterized in that: It includes an FPGA module, a calibration ADC chip, an ADC chip under test, a clock management module, a power management module, a DC power supply, an analog signal source, a clock source, and a host computer; The DC power supply is used to provide a 12V DC voltage to the power management module, and the power management module then converts the 12V voltage into the working voltages required by other modules; The analog signal source is used to provide analog input signals for the calibration ADC chip and the ADC under test; The clock source is used to provide an input clock to the clock management module; The clock management module is used to receive the input clock and generate 4 channels of synchronous clocks to be provided to 1 calibration ADC chip and 3 ADC chips under test; The FPGA module is used to receive the acquisition control signal sent by the host computer, complete the synchronous acquisition of the waveform data of the calibration ADC chip and the ADC chips under test, and upload it to the host computer through the UART interface; The host computer is used to perform FFT and phase calculations on the waveform data, record the signal-to-noise ratio parameter value SNR and the phase difference TΔ between it and the calibration ADC chip, and make them correspond one by one with the chip numbers. At the same time, the host computer is also used to perform clustering analysis on the two-dimensional data point set composed of SNR and TΔ after the whole batch of chips are tested, and complete the screening and detection; The host computer determines the final clustering centers of the two-dimensional data point set through clustering analysis, and then combines the specified engineering actual requirement conditions to output the chip numbers to be sorted; The clustering analysis specifically includes: (1) Randomly select a calibration ADC chip from the chips in the same batch as the initial clustering center K1'; (2) By calculating the distances between all data objects and K1', take the data object with the largest distance from the clustering center as the initial clustering center K2'; (3) Then calculate the distances from all data objects to K1' and K2' respectively, and classify the data objects into the clusters where the closer clustering center is located, finally forming two large clusters; (4) Recalculate the new clustering centers for the newly formed clusters; (5) Repeat the processes of step (3) and step (4) until the clustering centers are no longer updated, and determine the final clustering centers K1 and K2.

2. The inter-chip synchronization performance detection system for a high-speed and high-precision analog-to-digital converter according to claim 1, characterized in that: It also includes a splitter. The input signal generated by the analog signal source is divided into N channels by the splitter and respectively input into one calibration ADC chip and N - 1 ADC chips under test, where N is a positive integer.

3. A high-speed and high-precision inter-chip synchronization performance detection system for analog-to-digital converters according to claim 1, characterized in that: The calibration ADC chip and the ADC chips under test are high-speed and high-precision pipelined ADC chips of the same batch.

4. A high-speed and high-precision inter-chip synchronization performance detection system for analog-to-digital converters according to claim 3, characterized in that: The calibration ADC chip is randomly selected from the chips in the same batch and is used to calibrate the phase difference between all the ADC chips under test in this batch and this calibration ADC chip, and is used to form a phase difference data set.

5. A method for detecting the inter-chip synchronization performance of an analog-to-digital converter implemented based on the inter-chip synchronization performance detection system of the high-speed and high-precision analog-to-digital converter described in claim 1, characterized in that It includes: Randomly select a chip from the chips in the same batch as the calibration ADC chip, install the calibration ADC chip and the ADC chips under test on the test positions of the test board, and power on the system; The host computer sends an acquisition control signal. After the FPGA module receives the control signal, it completes the synchronous acquisition of the waveform data of the calibration ADC chip and the ADC chips under test, and uploads it to the host computer; The host computer performs FFT and phase calculation on the received waveform data, records the SNR parameter values of each converter and the phase difference TΔ between it and the calibrated ADC, and makes them correspond one by one with the chip numbers; Replace all the ADC chips to be tested, and repeat steps two and three until all the chips in this batch are tested, forming a two-dimensional data point set composed of SNR and TΔ of all the chips; Operate the host computer to perform cluster analysis on the two-dimensional data point set; Input the specified phase difference distance value D and the minimum SNR of the actual engineering requirements into the host computer, calculate and screen out the two-dimensional data points that meet the requirements, and output the chip numbers to be sorted according to the corresponding relationship of the numbers; The said performing cluster analysis specifically includes: (1) Select the calibrated ADC chip randomly selected from the chips in the same batch as the initial cluster center K1'; (2) By calculating the distances between all data objects and K1', take the data object with the largest distance from the cluster center as the initial cluster center K2'; (3) Then calculate the distances from all data objects to K1' and K2' respectively, and assign the data objects to the clusters where the closer cluster centers are located, finally forming two large clusters; (4) Recalculate and determine the new cluster centers for the newly formed clusters; (5) Repeat the processes of steps (3) and (4) until the cluster centers are no longer updated, and determine the final cluster centers K1 and K2; The host computer determines the final cluster centers of the two-dimensional data point set through cluster analysis, and then combines the specified actual engineering requirement conditions to output the chip numbers to be sorted.

6. The method for detecting the inter-chip synchronization performance of the analog-to-digital converter according to claim 5, wherein: The calibrated ADC chip and the ADC chips to be tested are high-speed and high-precision pipelined ADC chips of the same batch. The calibrated ADC chip is randomly selected from the chips in the same batch and is used to calibrate the phase difference between all the ADCs to be tested in this batch and form a phase difference data set.

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