A linearly adjustable dead time generation circuit

Abstract

The present invention provides a linearly adjustable dead time generation circuit, comprising: a first falling edge detector, a second falling edge detector, an OR gate, a linear delay module, a first AND gate and a second AND gate; a first input signal is connected to the input end of the first falling edge detector, the first input end of the first AND gate and the first input end of the second AND gate, and a second input signal is connected to the input end of the second falling edge detector, the second input end of the first AND gate and the second input end of the second AND gate; the output ends of the first falling edge detector and the second falling edge detector are respectively connected to the input end of the OR gate, the output end of the OR gate is connected to the input end of the linear delay module, and the output end of the linear delay module is respectively connected to the third input end of the first AND gate and the third input end of the second AND gate. The present invention can achieve precise linear adjustment of the delay, and has a wide delay adjustment range. The relationship between the dead time and the power supply voltage is extremely small, and it has very high consistency between chips.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and particularly to a linearly adjustable dead time generation circuit. Background Art

[0002] In a driving circuit, in order to prevent a large current phenomenon caused by "bridge arm direct connection" of the upper and lower two switching transistors, generally a dead time is inserted into the driving signals of the bridge arm to prevent the two driving signals from overlapping.

[0003] Existing dead time generation technologies have many deficiencies. For example, traditional methods use RC and logic gates to set the dead time, and the delay has a huge deviation affected by the power supply voltage process, as Figure 1 shown. Figure 1 It includes two completely complementary signal paths, an upper one and a lower one. RC fixed delay circuits are inserted on each path. The input signal IN is AND-operated with the signal output after being delayed by the first RC series circuit (composed of R1 and C1) of this input signal to obtain the output signal PWMA; the inverted signal of the input signal IN is AND-operated with the signal output after being delayed by the second RC series circuit (composed of R2 and C2) of the inverted signal of this input signal to obtain another output signal PWMB. After the input signal passes through two RC series circuits and logic AND gates, a dead time is thus generated between the output signals PWMA and PWMB. However, the delay generated by the RC series circuit varies violently with the power supply voltage and temperature; and there will be a deviation introduced between the first RC series circuit and the second RC series circuit, which will introduce pulse width distortion; secondly, the switching threshold of the AND gate depends severely on the process variation, making the deviation of the dead time between chips very large; finally, the RC parameters and the dead time are not in a linear relationship, and it is difficult to perform linear adjustment of the dead time in a wide range.

[0004] Generally speaking, the RC dead time generation circuit has a simple structure, but the dead time deviation is large, the adjustment is non-linear, and there are relatively large defects. An overly long delay will waste power consumption, and an overly short delay is prone to introducing risks. Therefore, an overly long or short adjusted dead time will affect the efficiency and stability of the entire circuit system. Other dead time generation methods have a narrow adjustment range or complex adjustment methods, and it is difficult to perform linear precision and wide-range adjustment. Summary of the Invention

[0005] In view of this, the embodiments of the present application provide a linearly adjustable dead time generation circuit. This dead time generation circuit can simply achieve precise linear adjustment of the delay by adjusting an external circuit, and has a wide delay adjustment range, a very small relationship between the dead time and the power supply voltage, and very high consistency between chips.

[0006] The embodiments of the present application provide the following technical solutions: A linearly adjustable dead-time generation circuit, comprising: a first falling-edge detector, a second falling-edge detector, an OR gate, a linear delay module, a first AND gate, and a second AND gate;

[0007] A first input signal is connected to the input end of the first falling-edge detector, the first input end of the first AND gate, and the first input end of the second AND gate. A second input signal is connected to the input end of the second falling-edge detector, the second input end of the first AND gate, and the second input end of the second AND gate. The output ends of the first falling-edge detector and the second falling-edge detector are respectively connected to the input end of the OR gate. The output end of the OR gate is connected to the input end of the linear delay module. The output end of the linear delay module is respectively connected to the third input end of the first AND gate and the third input end of the second AND gate;

[0008] The linear delay module includes an operational amplifier, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a current mirror circuit, a cascode current mirror, a first resistor, an external resistor, a capacitor, and a comparator. The non-inverting input end of the operational amplifier is connected to a reference voltage. The inverting input end is connected to the source of the first NMOS transistor and the upper end of the first resistor. The output end of the operational amplifier is connected to the gates of the first NMOS transistor and the second NMOS transistor. The source of the second NMOS transistor is connected to the upper end of the external resistor and the input end of the comparator. The drains of the first NMOS transistor and the second NMOS transistor are connected to the current mirror circuit. The drain of the second NMOS transistor is connected to the cascode current mirror. The gate of the third NMOS transistor is connected to the output end of the OR gate. The drain is connected to the current mirror circuit, the cascode current mirror, the upper plate of the capacitor, and the input end of the comparator. The lower plate of the capacitor, the source of the third NMOS transistor, the lower end of the first resistor, and the lower end of the external resistor are all connected to the reference ground.

[0009] Further, the current mirror circuit includes a first PMOS transistor, a second PMOS transistor, and a third PMOS transistor. The drain, gate of the first PMOS transistor, the gates of the second PMOS transistor and the third PMOS transistor are all connected to the drain of the first NMOS transistor. The sources of the first PMOS transistor, the second PMOS transistor, and the third PMOS transistor are connected to the power supply. The drain of the second PMOS transistor is connected to the drain of the second NMOS transistor and the cascode current mirror. The drain of the third PMOS transistor is connected to the drain of the third NMOS transistor and the upper plate of the capacitor.

[0010] Further, the cascode current mirror includes a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, and a seventh NMOS transistor. The drain and gate of the fourth NMOS transistor and the gate of the fifth NMOS transistor are connected to the drains of the second NMOS transistor and the second PMOS transistor. The source of the fourth NMOS transistor is connected to the drains and gates of the sixth NMOS transistor and the seventh NMOS transistor. The sources of the sixth NMOS transistor and the seventh NMOS transistor are connected to the reference ground. The drain of the seventh NMOS transistor is connected to the source of the fifth NMOS transistor. The drain of the fifth NMOS transistor is connected to the drain of the third NMOS transistor, the drain of the third PMOS transistor, the upper plate of the capacitor, and the input terminal of the comparator. The output terminal of the comparator is respectively connected to the first AND gate and the second AND gate.

[0011] Further, the capacitor uses a gate capacitor with zero temperature coefficient.

[0012] Further, it further includes a first debounce circuit and a second debounce circuit for eliminating short-time falling pulses. The first debounce circuit is connected between the first input signal and the input terminal of the first falling-edge detector. The second debounce circuit is connected between the second input signal and the input terminal of the second falling-edge detector.

[0013] Further, it further includes a signal buffer circuit. The signal buffer circuit includes a first inverter, a second inverter, a third inverter, and a fourth inverter.

[0014] The input terminal of the first inverter is connected to the output terminal of the first debounce circuit. The output terminal of the first inverter is connected to the input terminal of the second inverter and the first input terminal of the second AND gate. The output terminal of the second inverter is connected to the first input terminal of the first AND gate.

[0015] The input terminal of the third inverter is connected to the output terminal of the second debounce circuit. The output terminal of the third inverter is connected to the input terminal of the fourth inverter and the second input terminal of the first AND gate. The output terminal of the fourth inverter is connected to the second input terminal of the second AND gate.

[0016] Compared with the prior art, the beneficial effects that can be achieved by at least one of the above technical solutions adopted in the embodiments of this specification at least include:

[0017] (1) The dead time of the present invention hardly changes with the power supply voltage (the voltage coefficient is very small).

[0018] (2) The dead time of the present invention changes less with temperature (has a good temperature coefficient).

[0019] (3) The dead time of the present invention can be accurately linearly adjusted (up to less than 1‰).

[0020] (4) The dead time adjustment can be simply achieved by changing the external resistor, and the adjustable range of the dead time is wide (from 5 ns to 5 μs).

[0021] The above beneficial effects make the present invention convenient to apply in the system and highly reliable. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0023] Figure 1 is a traditional RC dead time generation circuit;

[0024] Figure 2 is a schematic structural diagram of the dead time generation circuit according to an embodiment of the present invention;

[0025] Figure 3 is a schematic structural diagram of the linear delay module according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0026] The embodiments of the present application will be described in detail below with reference to the drawings.

[0027] It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments can be combined with each other. The present invention will be described in detail below with reference to the drawings and embodiments. The technical solutions of the present invention will be clearly and completely described. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments. All other embodiments obtained by those of ordinary skill in the art without creative efforts based on the embodiments of the present invention belong to the scope of protection of the present invention.

[0028] As Figure 2 shown, an embodiment of the present invention provides a linearly adjustable dead time generation circuit, including: a first deburring circuit 1 and a second deburring circuit 2, a first falling edge detector 3, a second falling edge detector 4, a first inverter 5, a second inverter 6, a third inverter 7 and a fourth inverter 8, an OR gate 9, a linear delay module 10, a first AND gate 11 and a second AND gate 12;

[0029] The first input signal INA is connected to the first deburring circuit 1 to eliminate short-duration falling pulses; the output end of the first deburring circuit 1 is connected to the input end of the first falling-edge detector 3 and the input end of the first inverter 5; the second input signal INB is connected to the second deburring circuit 2 to eliminate short-duration falling pulses; the output end of the second deburring circuit 2 is connected to the input end of the second falling-edge detector 4 and the input end of the third inverter 7; the output ends of the first falling-edge detector 3 and the second falling-edge detector 4 are respectively connected to the input end of the OR gate 9, and the output end of the OR gate 9 is connected to the input end of the linear delay module 10; the output end of the first inverter 5 is connected to the input end of the second inverter 6 and the first input end of the second AND gate 12; the output end of the second inverter 6 is connected to the first input end of the first AND gate 11; the output end of the third inverter 7 is connected to the input end of the fourth inverter 8 and the second input end of the first AND gate 11; the output end of the fourth inverter 8 is connected to the second input end of the second AND gate 12; the output end of the linear delay module 10 is respectively connected to the third input end of the first AND gate 11 and the third input end of the second AND gate 12.

[0030] As Figure 3 shown, the linear delay module 10 includes an operational amplifier 13, a first NMOS transistor M1, a second NMOS transistor M2, a third NMOS transistor M10, a current mirror circuit, a cascode current mirror, a first resistor R1, an external resistor R2, and a capacitor C 0 , and a comparator 14; the non-inverting input end of the operational amplifier 13 is connected to a reference voltage, the inverting input end is connected to the source of the first NMOS transistor M1 and the upper end of the first resistor R1, the output end of the operational amplifier 13 is connected to the gates of the first NMOS transistor M1 and the second NMOS transistor M2, the source of the second NMOS transistor M2 is connected to the upper end of the external resistor R2 and the input end of the comparator 14, the drains of the first NMOS transistor M1 and the second NMOS transistor M2 are connected to the current mirror circuit, the drain of the second NMOS transistor M2 is connected to the cascode current mirror, the gate of the third NMOS transistor M10 is connected to the output end of the OR gate 9, and the drain is connected to the current mirror circuit, the cascode current mirror, the upper plate of the capacitor C 0 and the input end of the comparator 14, the lower plate of the capacitor C 0 , the source of the third NMOS transistor M10, the lower end of the first resistor R1, and the lower end of the external resistor R2 are all connected to the reference ground.

[0031] The current mirror circuit includes a first PMOS transistor M3, a second PMOS transistor M4, and a third PMOS transistor M5. The drain and gate of the first PMOS transistor M3, the gates of the second PMOS transistor M4 and the third PMOS transistor M5 are all connected to the drain of the first NMOS transistor M1. The sources of the first PMOS transistor M3, the second PMOS transistor M4, and the third PMOS transistor M5 are connected to the power supply. The drain of the second PMOS transistor M4 is connected to the drain of the second NMOS transistor M2 and the cascode current mirror. The drain of the third PMOS transistor M5 is connected to the drain of the third NMOS transistor M10 and the upper plate of the capacitor C 0 of the capacitor C.

[0032] Further, the cascode current mirror includes a fourth NMOS transistor M6, a fifth NMOS transistor M7, a sixth NMOS transistor M8, and a seventh NMOS transistor M9. The drain and gate of the fourth NMOS transistor M6 and the gate of the fifth NMOS transistor M7 are connected to the drains of the second NMOS transistor M2 and the second PMOS transistor M4. The source of the fourth NMOS transistor M6 is connected to the drains and gates of the sixth NMOS transistor M8 and the gate of the seventh NMOS transistor M9. The sources of the sixth NMOS transistor M8 and the seventh NMOS transistor M9 are connected to the reference ground. The drain of the seventh NMOS transistor M9 is connected to the source of the fifth NMOS transistor M7. The drain of the fifth NMOS transistor M7 is connected to the drains of the third NMOS transistor M10, the drain of the third PMOS transistor M5, the upper plate of the capacitor C 0 of the capacitor C and the input terminal of the comparator 14. The output terminal of the comparator 14, i.e., the delayed output, is respectively connected to the first AND gate 11 and the second AND gate 12.

[0033] In the embodiment of the present invention, the closed-loop operational amplifier and the cascode current mirror are used to accurately control the branch current, so that the dead time is only related to the external resistor and the charging capacitor, thereby achieving the effect of accurately controlling the delay time. On the other hand, the charging current of the capacitor is linearly related to the off-chip resistor. As long as the value of the off-chip resistor is changed, a wide-range linear adjustment of the delay time can be achieved.

[0034] The specific principle of the linear delay module of the present invention is as follows:

[0035] As Figure 3 shown, the present invention obtains an accurate linear delay through an operational amplifier and accurate current copying. Assuming that the reference voltage of the operational amplifier is Vref, the current flowing through the first resistor R1 due to the action of the operational amplifier is:

[0036]

[0037] PMOS transistors M3, M4, and M5 form a current mirror, so the current flowing through M4 and M5 is also I1.

[0038] If the resistance value of the externally connected resistor R2 is less than that of the first resistor R1 at this time, then all the current flowing through PMOS transistor M4 flows through NMOS transistor M2 and the externally connected resistor R2, and no current flows through NMOS transistors M6, M7, M8, and M9. At this time, the potential of the externally connected resistor R2 is I1R2. When the falling edges of the input signals INA and INB do not come, the reset signal remains at a low level all the time. At this time, NMOS transistor M10 is turned off, and the capacitor C 0 is charged to a high potential, and the output of comparator 14 is high. Until a falling edge appears in the INA or INB signal, the reset signal will appear a pulse signal, which will pull the potential of the upper plate of the capacitor C 0 to 0. At this time, the output of comparator 14 becomes 0. At this time, the current I1 flowing through PMOS transistor M5 will charge the capacitor C 0 until the output of comparator 14 becomes high again. The charging time for this period is

[0039]

[0040] This charging time of the capacitor is the dead time. It can be seen from the above formula that when the externally connected resistor R2 is less than the first resistor R1, the dead time only depends on the resistance value of the externally connected resistor R2 and the capacitance value of the capacitor C 0 and the capacitance value.

[0041] In another case, when the resistance value of the externally connected resistor R2 is greater than that of the first resistor R1, NMOS transistor M2 will enter the subthreshold region, and current will flow through NMOS transistors M6, M7, M8, and M9. NMOS transistors M6, M7, M8, and M9 form a cascode current mirror, ensuring that the current flowing through NMOS transistor M8 is the same as the current flowing through NMOS transistor M9. Assume that the potential of the non-grounded end of the externally connected resistor R2 is VDT at this time. Then the current flowing through the externally connected resistor R2 at this time is:

[0042]

[0043] When the pulse of the reset signal comes, the charging current for the capacitor C 0 at this time is equal to the current flowing through the externally connected resistor R2. So the charging time at this time is

[0044]

[0045] It can be seen that no matter what the resistance value of the externally connected resistor R2 is, the dead time can obtain the same expression, and this time only depends on the resistance value of the externally connected resistor R2 and the capacitor C0 is related to the capacitance value, making the dead time independent of the power supply voltage. For the capacitor, a gate capacitor with zero temperature coefficient can be selected, and since the resistor R2 is an external resistor, the dead time can be made independent of temperature. On the other hand, as long as the resistance value of the external resistor R2 is changed, the dead time can be linearly adjusted conveniently.

[0046] In actual large-scale applications, due to random errors in the chip manufacturing process, the actual sizes of various devices in the chip will have a certain degree of random deviation, causing changes in chip performance. For the dead time, this change will be manifested as a large offset in the dead time. For a general dead time generation circuit, the delay time is closely related to these MOSFETs, current biasing, and their parasitic RC, etc., so its random error is large, resulting in a large deviation in the delay time. However, the final dead time of the present invention is only related to the resistor and the capacitor. The resistance value of the external off-chip resistor is generally quite accurate, and the area of the capacitor can be made relatively large, and its own deviation is very small. Therefore, the dead time of the present invention has very high consistency between chips.

[0047] During the production and manufacturing process of integrated circuits, the chip will be affected by the process corner, and its performance will have some deviations. When reflected in the dead zone, it is the deviation of the dead time. Different from the random errors mentioned above, this deviation is global, that is, all chips in the entire batch will shift in the same direction. This is a problem that cannot be solved in the chip field. To offset the influence of this shift, a trimming method is usually adopted to adjust certain parts of the circuit. Because the dead time proposed by the present invention is only related to the external resistor R2 and the capacitor C 0 is related. Moreover, the external off-chip resistor R2 can be adjusted conveniently. Since the dead time is linearly related to the off-chip resistor, the dead time can be well controlled, preventing the dead time from being too long or too short; in addition, the capacitor C 0 can also be trimmed to some extent. Therefore, the dead time described in the present invention can be simply adjusted, and the dead time can be well controlled within a wide range.

[0048] In summary, the present invention proposes a precise linear dead time generation circuit, whose dead time is independent of the power supply voltage, almost independent of temperature, has small deviation between chips, the dead time is linearly related to the resistance value of the external resistor, the dead time adjustment is simple, and the adjustment range is wide.

[0049] The above is only the specific implementation manner of this application, but the protection scope of this application is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed in this application should be covered by the protection scope of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.

Claims

1. A linearly adjustable dead time generation circuit, characterized in that, comprising: a first falling edge detector, a second falling edge detector, an OR gate, a linear delay module, a first AND gate, a second AND gate, and a signal buffer circuit; the signal buffer circuit includes a first inverter, a second inverter, a third inverter, and a fourth inverter; A first input signal is connected to the input terminal of the first inverter, and the output terminal of the first inverter is respectively connected to the input terminal of the second inverter and the first input terminal of the second AND gate. The output terminal of the second inverter is connected to the first input terminal of the first AND gate; a second input signal is connected to the input terminal of the third inverter, and the output terminal of the third inverter is respectively connected to the input terminal of the fourth inverter and the second input terminal of the first AND gate. The output terminal of the fourth inverter is connected to the second input terminal of the second AND gate; The first input signal is further connected to the input terminal of the first falling edge detector, the second input signal is further connected to the input terminal of the second falling edge detector. The output terminals of the first falling edge detector and the second falling edge detector are respectively connected to the input terminals of the OR gate. The output terminal of the OR gate is connected to the input terminal of the linear delay module. The output terminal of the linear delay module is respectively connected to the third input terminal of the first AND gate and the third input terminal of the second AND gate; The linear delay module includes an operational amplifier, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a current mirror circuit, a cascode current mirror, a first resistor, an external resistor, a capacitor, and a comparator; the non-inverting input terminal of the operational amplifier is connected to a reference voltage, and the inverting input terminal is connected to the source of the first NMOS transistor and the upper end of the first resistor. The output terminal of the operational amplifier is connected to the gates of the first NMOS transistor and the second NMOS transistor. The source of the second NMOS transistor is connected to the upper end of the external resistor and the input terminal of the comparator. The drains of the first NMOS transistor and the second NMOS transistor are connected to the current mirror circuit. The drain of the second NMOS transistor is connected to the cascode current mirror. The gate of the third NMOS transistor is connected to the output terminal of the OR gate, and the drain is connected to the current mirror circuit, the cascode current mirror, the upper plate of the capacitor, and the input terminal of the comparator. The lower plate of the capacitor, the source of the third NMOS transistor, the lower end of the first resistor, and the lower end of the external resistor are all connected to the reference ground.

2. The linearly adjustable dead time generation circuit according to claim 1, characterized in that, The current mirror circuit includes a first PMOS transistor, a second PMOS transistor, and a third PMOS transistor. The drain and gate of the first PMOS transistor, the gates of the second PMOS transistor and the third PMOS transistor are all connected to the drain of the first NMOS transistor. The sources of the first PMOS transistor, the second PMOS transistor, and the third PMOS transistor are connected to the power supply. The drain of the second PMOS transistor is connected to the drain of the second NMOS transistor and the cascode current mirror. The drain of the third PMOS transistor is connected to the drain of the third NMOS transistor and the upper plate of the capacitor.

3. The linearly adjustable dead time generation circuit according to claim 2, characterized in that, the cascode current mirror includes a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, and a seventh NMOS transistor. The drain and gate of the fourth NMOS transistor and the gate of the fifth NMOS transistor are connected to the drains of the second NMOS transistor and the second PMOS transistor. The source of the fourth NMOS transistor is connected to the drain, gate of the sixth NMOS transistor, and the gate of the seventh NMOS transistor. The sources of the sixth NMOS transistor and the seventh NMOS transistor are connected to the reference ground. The drain of the seventh NMOS transistor is connected to the source of the fifth NMOS transistor. The drain of the fifth NMOS transistor is connected to the drain of the third NMOS transistor, the drain of the third PMOS transistor, the upper plate of the capacitor, and the input terminal of the comparator. The output terminal of the comparator is respectively connected to the first AND gate and the second AND gate.

4. The linearly adjustable dead time generation circuit according to claim 1, characterized in that, the capacitor uses a gate capacitor with zero temperature coefficient.

5. The linearly adjustable dead time generation circuit according to claim 1, characterized in that, further includes a first debouncing circuit and a second debouncing circuit for eliminating short-time falling pulses; the first debouncing circuit is connected between the first input signal and the input terminal of the first falling edge detector, and the second debouncing circuit is connected between the second input signal and the input terminal of the second falling edge detector; wherein, the first inverter is connected to the first input signal through the first debouncing circuit, and the third inverter is connected to the second input signal through the second debouncing circuit.

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