Clock frequency synchronization circuit and method

Abstract

The application relates to a clock frequency synchronization circuit and method, and relates to the field of wireless communication.The clock frequency synchronization circuit comprises a first frequency divider for frequency dividing an input first clock signal to obtain a third clock signal; a second frequency divider for frequency dividing an input second clock signal to obtain a fourth clock signal; a phase discriminator for comparing the third clock signal and the fourth clock signal to obtain a phase difference signal; a charge pump for converting the phase difference signal into a first voltage signal; a voltage-controlled oscillator for generating a first frequency signal output by using the first voltage signal; a frequency synthesizer for converting the first frequency signal into a fifth clock signal output; and feeding back the fifth clock signal to the first frequency divider or the second frequency divider as an input signal.The application has the effect of realizing high-precision clock frequency synchronization by using simple devices.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of wireless communication, in particular to a clock frequency synchronization circuit and a clock frequency synchronization method. BACKGROUND

[0002] For wireless communication, various different services need to be provided, such as voice, data and image and their integrated aspects, the existence of such a case makes the role of clock frequency synchronization in the system more and more important; stable clock signal is the basis for the work of each module on the communication link, if there is no synchronous clock frequency, digital signal will inevitably occur in the transmission process error and packet loss phenomenon, resulting in the decline of the whole communication quality, therefore, in wireless communication, clock frequency synchronization is essential.

[0003] For the related technologies in the above, the inventors find that at least the following problems exist in the related technologies: the clock frequency is difficult to synchronize; the clock frequency synchronization in the prior art adopts devices with high cost, which is not convenient for promotion, and the precision is low, which is not convenient for use in actual engineering. SUMMARY

[0004] In order to solve the above technical problems, the present application provides a clock frequency synchronization circuit and a clock frequency synchronization method.

[0005] The clock frequency synchronization circuit provided by the present application adopts the following technical scheme:

[0006] The clock frequency synchronization circuit comprises:

[0007] A first frequency divider is configured to divide and process an input first clock signal to obtain a third clock signal;

[0008] A second frequency divider is configured to divide and process an input second clock signal to obtain a fourth clock signal;

[0009] A phase detector is configured to compare the third clock signal and the fourth clock signal to obtain a phase difference signal;

[0010] A charge pump is configured to convert the phase difference signal into a first voltage signal;

[0011] A voltage-controlled oscillator is configured to generate a first frequency signal output by using the first voltage signal;

[0012] A frequency synthesizer is configured to convert the first frequency signal into a fifth clock signal output; and feed back the fifth clock signal to the first frequency divider or the second frequency divider as an input signal, so as to realize frequency synchronization between the first clock signal or the second clock signal and the fifth clock signal.

[0013] Preferably, further comprising:

[0014] a digital-to-analog conversion module for generating an analog voltage signal consistent with the first voltage signal and sending to a comparator;

[0015] a comparator for comparing whether the first voltage signal and the analog voltage signal are consistent; in the case of consistency, sending the first voltage signal to a voltage-controlled oscillator; in the case of inconsistency, sending the difference between the first voltage signal and the analog voltage signal to a control module;

[0016] a control module for controlling the frequency division ratio of the first frequency divider and the second frequency divider according to the output of the comparator and the clock frequency of the first clock signal and the second clock signal; and controlling the input digital signal of the digital-to-analog conversion module.

[0017] Preferably, further comprising:

[0018] a loop filter arranged between the comparator and the voltage-controlled oscillator; the loop filter is used to filter out high-frequency components and noise in the first voltage signal.

[0019] Preferably, further comprising: a clock driver arranged at the output of the frequency synthesizer; the clock driver is used to drive the fifth clock signal output by the frequency synthesizer and feed back the fifth clock signal to the first frequency divider or the second frequency divider.

[0020] Preferably, the clock frequency of the first clock signal and the second clock signal is different.

[0021] Preferably, the phase detector is a digital phase detector.

[0022] The second aspect also provides a clock frequency synchronization method, comprising:

[0023] dividing the input first clock signal to obtain a third clock signal;

[0024] dividing the input second clock signal to obtain a fourth clock signal;

[0025] comparing the third clock signal and the fourth clock signal to obtain a phase difference signal;

[0026] converting the phase difference signal into a first voltage signal;

[0027] generating a first frequency signal output using the first voltage signal;

[0028] converting the first frequency signal into a fifth clock signal output; and feeding back the fifth clock signal as the first clock signal or the second clock signal to realize the frequency synchronization of the first clock signal or the second clock signal with the fifth clock signal.

[0029] Preferably, further comprising:

[0030] generating an analog voltage signal consistent with the first voltage signal for a comparator;

[0031] comparing whether the first voltage signal and the analog voltage signal are consistent; in the case of consistency, sending the first voltage signal to a voltage-controlled oscillator; in the case of inconsistency, sending the difference between the first voltage signal and the analog voltage signal to a control module;

[0032] the control module controls the frequency division ratio of the first frequency divider and the second frequency divider according to the output of the comparator, and the clock frequency of the first clock signal and the second clock signal; and controls the input digital signal of the digital-to-analog conversion module.

[0033] Preferably, further comprising:

[0034] a loop filter arranged between the comparator and the voltage-controlled oscillator, for filtering out high-frequency components and noise in the first voltage signal.

[0035] Preferably, a clock driver is arranged at the output end of the frequency synthesizer, for driving the fifth clock signal output by the frequency synthesizer, and feeding back the fifth clock signal to the first frequency divider or the second frequency divider.

[0036] In summary, the present application includes at least one of the following beneficial technical effects:

[0037] 1. Using simple devices, high-precision clock frequency synchronization is achieved;

[0038] 2. Using a simple method, high-precision clock frequency synchronization is achieved. BRIEF DESCRIPTION OF DRAWINGS

[0039] Figure 1 is a logic block diagram of the first embodiment of the clock frequency synchronization circuit of the present application;

[0040] Figure 2 is a logic block diagram of the second embodiment of the clock frequency synchronization circuit of the present application;

[0041] Figure 3 is a logic block diagram of the third embodiment of the clock frequency synchronization circuit of the present application;

[0042] Figure 4 is a logic block diagram of the fourth embodiment of the clock frequency synchronization circuit of the present application;

[0043] Figure 5 is a step diagram of the clock frequency synchronization method of the present application.

[0044] REFERENCE SIGNS

[0045] 1. First frequency divider; 2. Second frequency divider;

[0046] 3. Phase detector; 4. Charge pump;

[0047] 5. Voltage-controlled oscillator; 6. Frequency synthesizer;

[0048] 7. Comparator; 8. Digital-to-analog converter module;

[0049] 9. Control module; 10. Loop filter;

[0050] 11. Clock driver. Detailed Implementation

[0051] To make the purpose, technical solution, and advantages of this application clearer, the following description is provided in conjunction with the appendix. Figures 1-5 The present application will be further described in detail below with reference to embodiments. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the application.

[0052] This application provides a clock frequency synchronization circuit, which adopts the following technical solution:

[0053] like Figure 1 As shown, a clock frequency synchronization circuit includes:

[0054] The first frequency divider 1 is used to divide the input first clock signal to obtain the third clock signal;

[0055] The second frequency divider 2 is used to divide the input second clock signal to obtain the fourth clock signal. The function of the frequency divider is to proportionally divide the original frequency, usually resulting in a new frequency smaller than the original frequency. For example, if the original frequency is 1024MHz and the division ratio is 1024, then the new frequency is 1024MHz divided by 1024, resulting in a new frequency of 1MHz. Here, two frequency dividers are set up to simultaneously divide the two input original frequencies, namely, the first frequency divider 1 and the second frequency divider 2, which divide the first clock signal and the second clock signal respectively.

[0056] Phase detector 3 is used to compare the third and fourth clock signals to obtain the phase difference signal. The purpose of phase detector 3 is to compare the differences between two different clock signals to obtain the phase difference between the third and fourth clock signals. Phase detector 3 is generally divided into analog phase detectors and digital phase detectors. An analog phase detector is essentially a multiplier, while a digital phase detector operates using pulse edge triggering.

[0057] Charge pump 4, for converting the phase difference signal into a first voltage signal; Charge pump is a kind of, for energy storage element, for generating larger output voltage than input. Here, that is, the phase difference signal is generated by charge pump 4 to generate a first voltage signal.

[0058] Voltage controlled oscillator 5, for generating a first frequency signal output using the first voltage signal; Voltage controlled oscillator 5 (VCO) is a conventional device for converting voltage to frequency. If the voltage signal is variable, the output frequency is also variable.

[0059] Frequency synthesizer 6, for converting the first frequency signal into a fifth clock signal output; and feeding back the fifth clock signal to the first frequency divider 1 or the second frequency divider 2 as an input signal, realizing the frequency synchronization of the first clock signal or the second clock signal with the fifth clock signal. So far, we have realized the clock frequency synchronization. With simple devices, we have realized the frequency synchronization of the first clock signal or the second clock signal with the final output fifth clock signal.

[0060] As shown in Figure 2 Preferably, it also includes:

[0061] Digital to analog conversion module 8, for generating an analog voltage signal consistent with the first voltage signal and sending it to comparator 7; Digital to analog conversion module 8, i.e. A / D, is used to convert digital signal to analog signal. Here, the source of digital signal is the digital signal sent by control module 9 to digital to analog conversion module 8; The digital signal includes two parts, one part is control signal, which is used to control the working mode of digital to analog conversion module 8; The other part is digital signal, which is converted to analog signal by digital to analog conversion module 8. And the analog voltage signal is equal to the first voltage signal. However, due to engineering practice problems, the analog voltage signal may not be equal to the first voltage signal, so the comparator 7 described below is needed for comparison.

[0062] Comparator 7, for comparing whether the first voltage signal and the analog voltage signal are consistent; In the case of consistency, the first voltage signal is sent to voltage controlled oscillator 5; In the case of inconsistency, the difference between the first voltage signal and the analog voltage signal is sent to control module 9; Comparator 7 realizes comparison and feedback. In the case of consistency between the first voltage signal and the analog voltage signal, the first voltage signal is directly outputted, which is used to control voltage controlled oscillator 5, so as to obtain clock frequency signal. If consistent, the first voltage signal is not outputted, but the difference between the first voltage signal and the analog voltage signal is fed back to control module 9, which controls the digital signal outputted to digital to analog conversion module 8 by control module 9, so as to realize that the analog voltage signal outputted by digital to analog conversion module 8 is finally equal to the first voltage signal.

[0063] The control module 9 is used to control the frequency division ratio of the first frequency divider 1 and the second frequency divider 2 according to the output of the comparator 7 and the clock frequency of the first clock signal and the second clock signal, and control the input digital signal of the digital-to-analog conversion module 8. The control module 9 is a single-chip microcomputer (MCU) in practice, which can output digital signals and be used to control the working mode of the comparator 7, the first frequency divider 1, the second frequency divider 2 and the digital-to-analog conversion module 8.

[0064] As shown in Figure 3 , preferably, further comprising:

[0065] A loop filter 10 is arranged between the comparator 7 and the voltage-controlled oscillator 5. The loop filter 10 is used to filter out high-frequency components and noise in the first voltage signal. The loop filter 10 filters out high-frequency components and noise in the first voltage signal, so that the output signal of the voltage-controlled oscillator 5 is cleaner and multiple frequency signals do not control the voltage-controlled oscillator 5 to generate multiple frequencies. The loop filter 5 can be composed of resistance and capacitance, which is simple in structure and low in cost.

[0066] As shown in Figure 4 , preferably, further comprising: a clock driver 11 arranged at the output end of the frequency synthesizer 6; the clock driver 11 is used to drive the fifth clock signal output by the frequency synthesizer 6 and feed back the fifth clock signal to the first frequency divider 1 or the second frequency divider 2. The clock driver 11 here not only drives the clock, but also feeds back the frequency output by the voltage-controlled oscillator 5 to the first frequency divider 1 or the second frequency divider 2.

[0067] Preferably, the clock frequency of the first clock signal and the second clock signal is different. Due to the existence of the first frequency divider 1 and the second frequency divider 2, the signals of different clock frequencies are changed into the third clock signal and the fourth clock signal of the same frequency before being input into the phase detector 3.

[0068] Preferably, the phase detector 3 is a digital phase detector.

[0069] The following is a practical case to describe the change of the clock signal in the circuit from a logical point of view. The design goal of the case is to realize a 32.768MHz single frequency signal and a 100MHz input signal, to synchronize the clock frequency between the two, and to filter out the corresponding spurs when outputting.

[0070] The voltage-controlled oscillator 5 outputs a frequency of 32.768 MHz to the first frequency divider 1, which is divided (÷2048) to obtain a frequency fn; the reference frequency 100 MHz is input to the second frequency divider 2, which is divided (÷6250) to obtain a frequency fr; the frequencies fn and fr formed after the division are compared in the phase detector;

[0071] When fn=fr, the phase detector 3 outputs a very narrow pulse, which is stably transmitted to the voltage-controlled oscillator 5 after the loop filter circuit 10, so that the frequency is kept unchanged;

[0072] When fn>fr, the phase detector 3 outputs a negative pulse, so that the voltage at the control end of the voltage-controlled oscillator 5 decreases, and the output frequency of the voltage-controlled oscillator 5 decreases;

[0073] When fn<fr, the phase detector 3 outputs a positive pulse, so that the voltage at the control end of the voltage-controlled oscillator 5 increases, and the output frequency of the voltage-controlled oscillator 5 increases. When the loop is locked, the output frequency of the voltage-controlled oscillator 5 is locked;

[0074] The frequency division formula of the first frequency divider 1 and the second frequency divider 2 can be written as: Fvco / N=Frefin / R, wherein Fvco is the output frequency of the voltage-controlled oscillator 5, Frefin is the reference frequency, R is the frequency division ratio of the 14-bit programmable reference frequency divider, the frequency division ratio is 1-16383; that is, the frequency division can be from 1 to 16383. N is the frequency division ratio of the 13-bit programmable frequency divider, the frequency division ratio is 1-8191; that is, the frequency division can be from 1 to 8191.

[0075] In this example, the reference input frequency is 100 MHz, and the locked output signal is required to be 32.768 MHz, so R=6250 and N=2048 are set;

[0076] In a second aspect, as Figure 5 shown, a clock frequency synchronization method is also provided, comprising:

[0077] S101: performing frequency division processing on an input first clock signal to obtain a third clock signal;

[0078] S102: performing frequency division processing on an input second clock signal to obtain a fourth clock signal;

[0079] S103: comparing the third clock signal and the fourth clock signal in a phase to obtain a phase difference signal;

[0080] S104: converting the phase difference signal into a first voltage signal;

[0081] S105: generating an output of a first frequency signal by using the first voltage signal;

[0082] S106: converting the first frequency signal into a fifth clock signal output; and feeding back the fifth clock signal as the first clock signal or the second clock signal, so as to realize frequency synchronization between the first clock signal or the second clock signal and the fifth clock signal.

[0083] Preferably, the application further comprises:

[0084] generating an analog voltage signal consistent with the first voltage signal, for the comparator 7;

[0085] comparing whether the first voltage signal and the analog voltage signal are consistent; in the case of consistency, sending the first voltage signal to the voltage-controlled oscillator 5; in the case of inconsistency, sending the difference between the first voltage signal and the analog voltage signal to the control module 9;

[0086] the control module 9 controls the frequency division ratio of the first frequency divider 1 and the second frequency divider 2 according to the output of the comparator 7, and the clock frequency of the first clock signal and the second clock signal; and controls the input digital signal of the digital-to-analog conversion module 8.

[0087] Preferably, the application further comprises:

[0088] a loop filter 10 arranged between the comparator 7 and the voltage-controlled oscillator 5, for filtering out high-frequency components and noise in the first voltage signal.

[0089] Preferably, a clock driver 11 is arranged at the output end of the frequency synthesizer 6, for driving the fifth clock signal output by the frequency synthesizer 6, and feeding back the fifth clock signal to the first frequency divider 1 or the second frequency divider 2.

[0090] The above are preferred embodiments of the application, and are not intended to limit the protection scope of the application. Any feature disclosed in the specification (including the abstract and the drawings) can be replaced by other equivalent or similar features, unless specifically stated otherwise. That is, each feature is only an example of a series of equivalent or similar features, unless specifically stated otherwise.

Claims

1. A clock frequency synchronization circuit, characterized by, The application relates to a frequency synchronization method and device. The application comprises: a first frequency divider (1) for dividing an input first clock signal to obtain a third clock signal; a second frequency divider (2) for dividing an input second clock signal to obtain a fourth clock signal; a phase comparator (3) for comparing the third clock signal and the fourth clock signal to obtain a phase difference signal; a charge pump (4) for converting the phase difference signal into a first voltage signal; a voltage-controlled oscillator (5) for generating a first frequency signal output by using the first voltage signal; a frequency synthesizer (6) for converting the first frequency signal into a fifth clock signal output; and feeding back the fifth clock signal to the first frequency divider (1) or the second frequency divider (2) as an input signal, so that the first clock signal or the second clock signal is frequency-synchronized with the fifth clock signal; a digital-to-analog conversion module (8) for generating an analog voltage signal consistent with the first voltage signal and sending the analog voltage signal to a comparator (7); the comparator (7) is used for comparing whether the first voltage signal and the analog voltage signal are consistent; in the case of consistency, the first voltage signal is sent to the voltage-controlled oscillator (5); and in the case of inconsistency, the difference between the first voltage signal and the analog voltage signal is sent to a control module (9); the control module (9) is used for controlling the frequency division ratio of the first frequency divider (1) and the second frequency divider (2) according to the output of the comparator (7) and the clock frequencies of the first clock signal and the second clock signal; and the control module (9) is also used for controlling the input digital signal of the digital-to-analog conversion module (8); 2. The circuit of claim 1, wherein a loop filter (10) arranged between the comparator (7) and the voltage-controlled oscillator (5); the loop filter (10) is used for filtering high-frequency components and noises in the first voltage signal. Further comprising:

3. The circuit of claim 1, wherein, a clock driver (11) arranged at the output end of the frequency synthesizer (6); the clock driver (11) is used for driving the fifth clock signal output by the frequency synthesizer (6) and feeding back the fifth clock signal to the first frequency divider (1) or the second frequency divider (2).

4. The circuit of claim 1, wherein, The clock frequencies of the first clock signal and the second clock signal are different.

5. A method of clock frequency synchronization, characterized by, The phase comparator (3) is a digital phase comparator. The application relates to a frequency synchronization method and device. The application comprises: dividing an input first clock signal to obtain a third clock signal; dividing an input second clock signal to obtain a fourth clock signal; comparing the third clock signal and the fourth clock signal to obtain a phase difference signal; converting the phase difference signal into a first voltage signal; generating a first frequency signal output by using the first voltage signal; converting the first frequency signal into a fifth clock signal output; feeding back the fifth clock signal as the first clock signal or the second clock signal, so that the first clock signal or the second clock signal is frequency-synchronized with the fifth clock signal; generating an analog voltage signal consistent with the first voltage signal for a comparator (7); comparing whether the first voltage signal and the analog voltage signal are consistent; in the case of consistency, sending the first voltage signal to the voltage-controlled oscillator (5); in the case of inconsistency, sending the difference between the first voltage signal and the analog voltage signal to the control module (9); The control module (9) controls the frequency division ratio of the first frequency divider (1) and the second frequency divider (2) according to the output of the comparator (7) and the clock frequency of the first clock signal and the second clock signal; also controls the input digital signal of the digital-to-analog conversion module (8).

6. The method of claim 5, wherein, Further comprising: A loop filter (10) arranged between the comparator (7) and the voltage-controlled oscillator (5) is arranged to filter out high-frequency components and noise in the first voltage signal.

7. The method of claim 5, wherein, A clock driver (11) is arranged at the output end of the frequency synthesizer (6) to drive the fifth clock signal output by the frequency synthesizer (6) and feed back the fifth clock signal to the first frequency divider (1) or the second frequency divider (2).

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