Bus decoder

Abstract

A bus decoder is provided. According to an aspect, a solution for providing access to a slave unit is provided. An address is received (400) from a master unit attempting to access the slave unit. The received address is mapped (402) to a slave address. Default access rights are associated (404) with the master-slave connection. Additional access rights associated with the master unit and the slave address are determined (406). If the additional access rights allow the master unit to access the slave unit, the master-slave connection is enabled (408), otherwise the connection is denied.

Description

Technical Field

[0001] Various example implementations involve bus decoders. Background Technology

[0002] In computational design, one of the primary goals is to achieve reliable and fast device operation. Modern computational designs involve complex circuits comprising a large number of different components. A typical architecture used in circuit design is the bus design, in which buses are used to connect components to each other. For example, a given number of master or management units can be connected to a given number of slave or subordinate units via one or more buses. A slave unit, for example, could be a memory.

[0003] Security is increasingly being considered in equipment design. Ensuring that data and data units are accessed only by those authorized to do so has become increasingly important. Summary of the Invention

[0004] According to one aspect, a bus decoder is provided that is operatively connectable to a set of master units and a set of slave units. The bus decoder includes means for causing the decoder to: receive an address from a master unit attempting to access a slave unit; map the received address to a slave address; associate default access permissions with a master-slave connection; determine additional access permissions associated with the master unit and the slave address; and enable the master-slave connection if the additional access permissions allow the master unit to access the slave unit, otherwise reject the connection.

[0005] According to another aspect, a method for providing access to a slave unit is provided, the method comprising: receiving an address from a master unit attempting to access the slave unit; mapping the received address to a slave address; associating a default access permission with a master-slave connection; determining additional access permissions associated with the master unit and the slave address; and enabling the master-slave connection if the additional access permissions allow the master unit to access the slave unit, otherwise rejecting the connection.

[0006] One of the advantages offered by these aspects is that the proposed bus decoder neither steals time from the main bus path nor from the secondary bus path. Since the lookup is parallel rather than serial, it adds very low overhead to the bus decoding time.

[0007] The technical solution of this invention defines the implementation methods. The technical solution of this invention specifies the scope of protection sought by various implementation methods.

[0008] The embodiments and features described in this specification that are not within the scope of the independent claims (if any) should be interpreted as examples useful for understanding various embodiments of the invention. Attached Figure Description

[0009] In the following description, exemplary embodiments will be described in more detail with reference to the accompanying drawings, in which:

[0010] Figure 1 An example of components used in a bus interconnect circuit is shown;

[0011] Figure 2 An example of a bus transaction is shown;

[0012] Figure 3 An implementation in which the bus decoder is configured to perform security filtering is shown;

[0013] Figure 4 This is a flowchart illustrating the implementation method;

[0014] Figure 5 An implementation of the main decoder is shown; and

[0015] Figure 6 An implementation of the security decoder is shown. Detailed Implementation

[0016] Integrated circuits, or chips, are designed in various ways for numerous purposes. A System-on-a-Chip (SoC) is an integrated circuit that utilizes many different components to design a desired system on a circuit. For example, computers or other types of electronic systems can be designed on a chip. Figure 1 An example of components in a bus interconnect circuit is shown. The figure shows three master units 100A, 100B, and 100C, which are connected to a group of slave units 102A, 102B, 102C, and 102D via a bus matrix 104.

[0017] The master unit can be, for example, a processor (Central Processing Unit, CPU, Digital Signal Processor, DSP), a Direct Memory Access (DMA) module (a module designed for data transfer between memories or between peripheral devices or memories), a peripheral device with built-in DMA, or a bridge connecting one bus to another. A bridge can be a slave unit on one bus and a master unit on another bus.

[0018] The slave unit can be, for example, memory (non-volatile memory, random access memory RAM, external memory), peripheral devices (configuration and data registers), or a bridge that connects one bus to another.

[0019] The list above is merely a non-limiting example of possible master and slave units. Because the implementation does not depend on the type of master or slave unit, the implementation is not limited to the examples above. The implementation can be applied to any integrated circuit including a bus and a bus decoder. The implementation can be particularly applied to integrated circuits in which the master unit can have different privileges.

[0020] Typically, bus 104 includes a bus decoder that maps the addresses received from master units 100A, 100B, and 100C to slave units 102A, 102B, 102C, and 102D.

[0021] Figure 2 An example of a bus transaction between the master and slave units in the system is shown.

[0022] This example shows two buses, bus 0 200 and bus 1 202. Each bus has its own bus decoder 204, 206.

[0023] Main units 100A, 100B, and 100C are connected to the first bus 200, and main units 208A and 208B are connected to the second bus 202. Slave units 102A, 102B, and 102C are connected to the first bus 200, and slave units 210A and 210B are connected to the second bus 202.

[0024] In this example, each bus also includes default slave units 212A and 212B, which are configured to act as error processors in the event of a transaction in which no actual slave unit can be connected to the system.

[0025] In one implementation, the system also includes a global slave unit 214A, which is used when a transaction does not match any local slave unit on the bus. The global slave unit may include a bridge 214B to another bus of the system—in this example, to a second bus 202. The device may also act as a master unit 214C to bus 202.

[0026] exist Figure 2 The following are three example transactions. Master unit 100C attempts to access slave unit 102B. Bus decoder 204 maps the address received from master unit 100C to slave unit 102B address and enables connection 216.

[0027] The master unit 100B attempts to access a slave address. The bus decoder 204 determines that the address does not match any slave unit on the bus, and the master unit 100B connects 218 to the default slave unit 212A, which generates a bus error.

[0028] The master unit 100A attempts to access the slave unit 210A. The bus decoder 204 determines that the transaction does not match any local slave unit, and the bus decoder connects the transaction 220 to the desired slave unit 210A via the global slave unit 214A, bridge 214B, and master unit 214C.

[0029] In some cases, security filtering is required, i.e., restricting the master unit's access to the slave unit. In the prior art, such solutions are based on a separate module on the master unit side that steals time from the master unit's bus access path. Alternatively, security filtering is performed by an address filter on the slave unit side, which steals time from the slave unit's decoding cycle. In both cases above, the security filtering is independent of the bus decoder.

[0030] Figure 3 An implementation in which the bus decoder 204 is configured to perform security filtering is shown.

[0031] The figure illustrates three master units or master units 100A, 100B, and 100C, which are connected via bus matrix 104 to a group of slave units 102A, 102B, 102C, and 102D, and a global slave unit 214A. The figure also illustrates a bus decoder 204. The bus decoder includes a group of master decoders 300A, 300B, and 300C. In this embodiment, the number of master decoders corresponds to the number of master units connected to the bus decoder. The bus decoder also includes tables or databases, which may be represented as a region table 304 and a cover table 306.

[0032] Figure 4 The flowchart illustrates the implementation of an embodiment. It shows the operation of a bus decoder 204 operatively connected to one or more master units or a set of slave units.

[0033] In step 400, the bus decoder is configured to receive the address from the master unit attempting to access the slave unit.

[0034] In step 402, the bus decoder is configured to map the received address to the slave address.

[0035] In step 404, the bus decoder is configured to associate default access permissions with master-slave connections. In this implementation, a default access permission is assigned to each slave unit connected to the bus matrix. This default access permission applies to all addresses within the same slave unit and to all master units accessing the slave unit. Each slave unit can have different default access permissions. Default permissions may have been set independently for read, write, execution, and security procedures.

[0036] In step 406, the bus decoder is configured to determine additional access permissions associated with the master and slave addresses. These additional access permissions depend on the master unit attempting to access the slave unit. In implementations, additional access permissions can be set for each master unit or a group of master units can share additional access permissions.

[0037] In this implementation, one or more master units include a unique identity. In this implementation, whenever a master unit attempts to access a slave unit, the access request can include the master unit's identity. In systems utilizing the Advanced Extensible Interface (AXI), the identity can be represented using unique OwnerID sideband information, for example, as the AxUSER signal.

[0038] For example, a system may include a group of system master units with the same access privileges, each system master unit having a unique identifier. They can be located anywhere in the system, not necessarily within local interconnects. Various interconnects can be connected to each other via a set of bridges, and transactions can be routed to parts of the system located in a different location than the system master units. In an implementation, when an address and the unique identifier of a system master unit are received, the bus decoder can be configured to determine additional access permissions in part based on the unique identifier.

[0039] In step 408, if the additional access permissions allow the master unit to access the slave unit, the bus decoder is configured to enable master-slave connection; otherwise, the connection is rejected.

[0040] In this implementation, region table 304 includes a set of slave unit entries, each containing a slave unit number, a starting address, and an address mask for the slave region. The region table also includes default access permissions. In this implementation, the region table is shared among all master decoders, allowing slave unit entries to be shared among master units. In this implementation, each master unit is configured to view only a specific subset of the complete region table. Therefore, the connection between region entries and master decoders can be viewed as a sparse padding matrix defined by the static configuration of each device, which may have been defined at design time. The mapping between addresses from master units and slave addresses, and the default permissions for slave addresses are also included.

[0041] In this implementation, overlay table 306 defines overlay access permissions for any physical address range, which can be mapped to a subset of the address range. Each master decoder can connect to a subset of overlay entries—also mapped as a sparse padding matrix.

[0042] In an implementation, the coverage table 306 includes entries from an address range and includes entries that include: the start and end addresses of the entries, an indication of which default access permissions are covered, additional access permissions of the covered default permissions, an indication of the main unit to which the additional access permissions are involved, and an indication of remapping.

[0043] In an implementation, the bus decoder can be configured to: determine the identity of the master unit requesting access to the slave unit, and use the identity and overlay table to determine access permissions.

[0044] In implementations, one or both of the region table and the overlay table may include a mixture of hardwired parameterized constants and programmable register entries.

[0045] As mentioned, in the implementation, if the bus decoder detects that the address from the master unit does not match any local slave unit of the bus connected to the bus decoder, the bus decoder is configured to forward the connection to a global slave unit 214A of another bus.

[0046] Figure 5 An embodiment of the master decoder 300A (and 300B, 300C) is shown. The master decoder 300A includes a first secure decoder 500 that takes a read address 502 from the master unit as input. The first secure decoder 500 takes the address 504 of the slave unit to be read as output. The master decoder also includes a second secure decoder 506 that takes a write address 508 from the master unit as input. The second secure decoder 506 takes the address 510 of the slave unit to be written as output.

[0047] Therefore, in this implementation, the main decoder includes separate decoders 500 and 506 for reading and writing the stream. These two operations can be performed simultaneously.

[0048] The proposed bus decoder for performing security filtering steals time from neither the master bus path nor the slave bus path. Because the lookup is parallel rather than serial, it adds very low overhead to bus decoding time. It provides security filtering at a very low cost because the same information can be used to limit slave and privileged regions.

[0049] Because additional access permissions can be associated with a master unit, complex security models are possible. Different master units can be granted different permissions regarding the same slave zone. Multiple transaction owners are supported in the system.

[0050] Figure 6Implementations of security decoders 500 and 506 are shown. Inputs to the security decoders include region table 304 and overlay table 306, address (read or write) AxADDR 600 from the master unit, and the master unit's identity AxUSER 602.

[0051] Address 600 from the master unit is provided to the region decoder 604, and address 600 and the identity 602 of the master unit are provided to the overlay decoder 606.

[0052] In this implementation, the region decoder is configured to receive address 600, map the received address to the slave address, and associate default access permissions with the master-slave connection. Information 608 can be provided to the overlay unit 610.

[0053] In one implementation, the overlay decoder 606 is configured to determine additional access permissions associated with the master and slave addresses. Information 612 may be provided to the overlay unit 610.

[0054] In the implementation, if the additional access permissions allow the master unit to access the slave unit, the overlay unit 610 enables the master-slave connection; otherwise, the connection is rejected.

[0055] In implementations, in systems utilizing the Advanced Extensible Interface (AXI), there may be additional checks in the privilege check unit 614 based on the AxPROT signal 616, which may provide additional access protection, such as privileged / non-privileged access or instruction / data access.

[0056] The output of the bus decoder is at address 618.

[0057] In one implementation, the bus decoder is configured to apply configurable delays to slave accesses. The bus decoder may include a delay table 620, which can be used to introduce programmable delays to slave accesses for debugging purposes. In another implementation, delay information 622 may be provided to a real-time choke for stress testing of the system with slow slave units. In some systems, some slave units may have different latency times. The delay table may include a given delay value for the slave address, simulating the maximum latency for the slave unit. The real-time choke (not shown) may delay a given transaction by a given number of cycles indicated in the delay table. Therefore, the worst-case latency of the slave unit can be simulated.

[0058] In other implementations, the overlay decoder can overlay the slave unit decoded by the region decoder, thus providing different slave addresses, thereby remapping the master unit to different slave units or different memory addresses of the slave units.

[0059] The proposed bus decoder supports remapping one address range to another.

[0060] In other implementations, the overlay decoder can apply an offset of 624 to the slave address. Therefore, an offset can be introduced to route master cells to different slave cells or different memory addresses of slave cells. The offset can be a programmable offset that provides remapping functionality. The offset can also be used to route access to different buses via global slave cells.

[0061] In this implementation, the region table and decoder can use hardwired entries, while the overlay table and decoder can use programmable entries. However, this can be a configurable option.

[0062] In implementations, the master unit connected to the bus decoder may only have access to a configurable subset of addresses in the region table and overlay table. Therefore, the master unit can use a mix of region / overlay entries shared with other master units and unique region / overlay entries not seen by other master units. The connection between the region / overlay and the master unit can be viewed as a sparse padding matrix configured at design time.

[0063] In an implementation, if different sub-ranges of an address space have different default access permissions, the address range can be broken down into multiple region entries / overlay entries.

[0064] The proposed device can be implemented as a circuit system operatively connected to or connectable to one or more master units, slave units, and buses.

[0065] As used herein, the term "circuit system" refers to one or more of the following: a circuit implementation that is only hardware, such as an implementation only in analog and / or digital circuit systems; a combination of hardware circuitry and software and / or firmware; and circuitry that requires software or firmware to operate even if the software or firmware is not physically present, such as a microprocessor or a portion thereof. This limitation of "circuit system" applies to the use of the term in this application. As another example, as used herein, the term "circuit system" will also cover an implementation of only a processor (or multiple processors) or a portion thereof, such as a core of a multi-core processor, and the accompanying software and / or firmware. For example, and if applicable, the term "circuit system" will also cover specific elements, baseband integrated circuits, application-specific integrated circuits (ASICs), and / or field-programmable grid array (FPGA) circuitry used in devices according to embodiments of the present invention.

[0066] The embodiments described herein are applicable not only to the various systems for accessing memory circuits defined above, but also to other systems. The protocols used, system specifications, and their elements are evolving rapidly. Such evolution may necessitate additional changes to the described embodiments. Therefore, all words and expressions should be interpreted broadly, and they are intended to be illustrative rather than limiting. It will be apparent to those skilled in the art that the inventive concept can be implemented in various ways as technology advances. Embodiments are not limited to the examples described above, but may vary within the scope of the claims.

Claims

1. A bus decoder, operatively connectable to a set of master units and a set of slave units, the bus decoder including means for causing the decoder to perform the following operations: From attempting to access the address received by the main cell of the cell; Map the received address to the slave address; Associating default access permissions with master-slave connections, wherein each master unit is able to access a specific subset of the default access permissions, the default access permissions depending on which slave unit the master server attempts to access; Determine additional access permissions associated with the master unit and the slave address, wherein each master unit is able to access a specific subset of the additional access permissions, which are obtained from an overlay table and depend on which master unit attempts to access the slave unit; and If the additional access permissions allow the master unit to access the slave unit, then the master-slave connection is enabled; otherwise, the connection is rejected.

2. The bus decoder according to claim 1, wherein, The device is configured to: An offset is applied to the slave address, which remaps the connection to a different slave unit or slave region than indicated by the address received from the master unit.

3. The bus decoder according to claim 1 or 2, wherein, The device is configured to apply a configurable delay to access for debugging purposes.

4. The bus decoder according to claim 1 or 2, wherein, The device is configured to enable the decoder to further maintain a region table including the following: The mapping between the address from the master unit and the slave address; as well as The default permissions for the address.

5. The bus decoder according to claim 1 or 2, wherein, The apparatus is configured to enable the decoder to further maintain an overlay table, the overlay table comprising entries from an address range and entries including: The start and end addresses of the entries; Indicator of which default access permissions are overridden; Additional access permissions to the default permissions that are overridden; The additional access permissions pertain to the instruction of the main unit; as well as Instructions for remapping.

6. The bus decoder according to claim 4, wherein, The region table and the overlay table are shared among multiple master units.

7. The bus decoder according to claim 4, wherein, The region table and the coverage table are different for different subsets of the main unit.

8. The bus decoder according to claim 1 or 2, wherein, The device is configured to: determine that the address from the master unit does not match any local slave unit, and forward the connection to another bus.

9. The bus decoder according to claim 1 or 2, wherein, The device is configured to: when receiving an address from a system master unit within a group of system master units with the same access privileges, receive a unique identifier of the system master unit and determine additional access permissions in part based on the unique identifier.

10. A method for providing access to a slave unit, the method comprising: From attempting to access the address received by the main cell of the cell; Map the received address to the slave address; Associating default access permissions with master-slave connections, wherein each master unit is able to access a specific subset of the default access permissions, the default access permissions depending on which slave unit the master server attempts to access; Determine additional access permissions associated with the master unit and the slave address, wherein each master unit is able to access a specific subset of the additional access permissions, which are obtained from an overlay table and depend on which master unit attempts to access the slave unit; and If the additional access permissions allow the master unit to access the slave unit, then the master-slave connection is enabled; otherwise, the connection is rejected.

11. The method of claim 10, further comprising: An offset is applied to the slave address, which remaps the connection to a different slave unit or slave region than indicated by the address received from the master unit.

12. The method according to claim 10 or 11, further comprising: Apply configurable delays to access for debugging purposes.

13. The method according to any one of claims 10 to 11 further comprises: If the address from the master unit does not match any local slave unit, the connection is forwarded to another bus.

14. The method according to any one of claims 10 to 11, further comprising: Receive the address from the system master unit within a group of system master units that have the same access privileges, and receive the unique identifier of the system master unit; as well as Additional access permissions are determined in part based on the unique identifier.

15. The method according to any one of claims 10 to 11, further comprising: Maintain a region table, which includes the following: The mapping between the address from the master unit and the slave address; as well as The default permissions for the address.

16. The method according to any one of claims 10 to 11, further comprising: Maintain a covering table, which includes entries from an address range and includes the following: The start and end addresses of the entries; Indicator of which default access permissions are overridden; Additional access permissions to the default permissions that are overridden; The additional access permissions pertain to the instruction of the main unit; as well as Instructions for remapping.

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