Silicon wafer in-situ doping method and battery preparation method

Abstract

The present invention discloses a silicon wafer in-situ doping method and a battery preparation method, belonging to the technical field of solar cells. The method comprises the following steps: the first stage: introducing disilane into a chamber loaded with a silicon wafer, and depositing a hydrogenated amorphous silicon layer on the back of the silicon wafer; the second stage: introducing disilane and borane or phosphine into the chamber, and depositing a boron-doped amorphous silicon layer or a phosphorus-doped amorphous silicon layer on the back of the hydrogenated amorphous silicon layer; the chamber temperature is controlled at 450°C to 500°C in the first stage and the second stage. In the present invention, the LPCVD process uses disilane instead of monosilane as a growth source, reduces the negative impact of in-situ doping, has a lower growth temperature of 450°C-500°C, ensures the quality of the film, and has a faster growth rate, lower power consumption, reduces production costs, has good film uniformity, good adjustability of doping concentration, and improves battery conversion efficiency.

Description

Technical Field

[0001] The invention belongs to the technical field of solar cells, and in particular relates to a silicon wafer in-situ doping method and a battery preparation method. Background Art

[0002] LPCVD deposition of polysilicon thin films is a common technology used in passivated contact cells. For this application, polysilicon must be heavily doped to reduce the resistivity of its film. Currently, this is mostly achieved through technologies such as ion implantation or thermal diffusion. Ion implantation does not produce particularly low resistivity, but the required equipment is expensive; thermal diffusion requires additional high-temperature steps to change the distribution of dopants. Therefore, researchers have turned their attention to in-situ doping technology.

[0003] The in-situ doping process currently has process problems of slow growth rate and poor uniformity. In the process of growing amorphous silicon from undoped to doped amorphous silicon, the growth rate drops sharply from 100 angstroms / min to 20 angstroms / min, resulting in low growth efficiency and considerable degradation of the thickness uniformity of the entire film. Summary of the invention

[0004] Purpose of the invention: In order to solve the above problems, the present invention provides a silicon wafer in-situ doping method and a battery preparation method.

[0005] Technical solution: A silicon wafer in-situ doping method, comprising the following steps:

[0006] The first stage: disilane is introduced into the chamber loaded with the silicon wafer to deposit a hydrogenated amorphous silicon layer on the back of the silicon wafer;

[0007] The second stage: disilane and borane or phosphine are introduced into the chamber to deposit a boron-doped amorphous silicon layer or a phosphorus-doped amorphous silicon layer on the back of the hydrogenated amorphous silicon layer;

[0008] The chamber temperature was controlled at 450°C to 500°C in the first and second stages;

[0009] In the first stage, disilane is heated to produce a gas phase reaction and decomposes to obtain products, which are deposited on the back of the silicon wafer to form a hydrogenated amorphous silicon layer;

[0010] In the second stage, disilane is heated to react in the gas phase to decompose to obtain products, which compete with borane or phosphine on the back surface of the hydrogenated amorphous silicon layer to promote the deposition of a boron-doped amorphous silicon layer or a phosphorus-doped amorphous silicon layer.

[0011] In a further embodiment, the method of introducing disilane in the first stage is: disilane is introduced into the front and rear tubes in the tube; the amount of disilane in the two paths is 600-700 sccm and 500-600 sccm respectively, and the source growth is continued for 1-5 minutes each time, wherein sccm is the unit of volume flow rate.

[0012] In a further embodiment, the method of introducing disilane and borane in the second stage is as follows: a mixture of disilane and borane in a predetermined ratio is introduced into the front and rear paths of the tube; the amounts of disilane and borane in the two paths are respectively: 700-800 sccm for disilane and 85-95 sccm for borane, and 650-750 sccm for disilane and 75-85 sccm for borane; each time the source is continuously passed for growth for 10-20 minutes to obtain a boron-doped amorphous silicon layer of 30-60 nm.

[0013] In a further embodiment, the method of introducing disilane and phosphine in the second stage is as follows: a mixture of disilane and phosphine in a predetermined ratio is introduced into the front and rear paths of the tube; the amounts of disilane and phosphine in the two paths are respectively: 700-800 sccm for disilane and 85-95 sccm for phosphine, and 650-750 sccm for disilane and 75-85 sccm for phosphine. Each time the source is continuously passed for growth for 10-20 minutes, and a phosphorus-doped amorphous silicon layer of 30-60 nm is grown.

[0014] A battery preparation method, using a silicon wafer in-situ doping method as described above to produce an HBC battery, comprises the following steps:

[0015] Step 1: Use the silicon wafer as the substrate material, clean and texture it; the silicon wafer can be an N-type silicon wafer;

[0016] Step 2: depositing an intrinsic hydrogenated amorphous silicon layer on the front side of the silicon wafer;

[0017] Step 3: growing a passivation layer on the intrinsic hydrogenated amorphous silicon layer on the front side of the silicon wafer; the passivation layer plays a role in passivation and anti-reflection;

[0018] Step 4: growing an intrinsic hydrogenated amorphous silicon layer and a boron-doped amorphous silicon layer on the back of the silicon wafer; using LPCVD to grow; the temperature in the chamber is controlled at 450°C-500°C; growing a boron-doped amorphous silicon layer, the growth sources of which are disilane and borane, and the ratio of disilane:borane is adjusted according to the actual process requirements to control the doping concentration;

[0019] Step 5: Prepare a mask on the back of the silicon wafer; polish and prepare using PECVD deposition method;

[0020] Step 6: Use laser equipment to define the slotted area according to the graphic design, and remove the mask and amorphous silicon layer in the slotted area in the laser slotting mode to expose the silicon wafer;

[0021] Step 7: Use any alkaline or acidic solution to clean the grooved area and etch away the amorphous silicon layer surrounding the silicon wafer;

[0022] Step 8: growing an intrinsic hydrogenated amorphous silicon layer and a phosphorus-doped amorphous silicon layer on the back of the silicon wafer; growing a hydrogenated amorphous silicon layer on the back surface of the crystalline silicon substrate by the LPCVD method, and depositing a doped amorphous silicon film layer on the hydrogenated amorphous silicon layer; controlling the chamber temperature at 450°C-500°C; growing a doped amorphous silicon layer, the growth sources of which are disilane and phosphine, and the ratio of disilane:phosphine is adjusted according to the actual process requirements to control the doping concentration;

[0023] Step 9: Use any alkaline or acidic solution to clean and etch away the amorphous silicon layer surrounding the silicon wafer;

[0024] Step 10: Grow a highly transparent conductive film on the back of the silicon wafer, use laser grooving to isolate the P / N regions, and perform slurry printing metallization in the P region / N region in turn.

[0025] In a further embodiment, in step 1, the surface of the silicon wafer is provided with a pyramid structure by cleaning and texturing, and the reflectivity is controlled within 11%.

[0026] In a further embodiment, the step 2 is prepared by LPCVD, the growth source introduced is disilane, and the deposition temperature is 450°C to 500°C.

[0027] In a further embodiment, in step three, a passivation layer is grown on the front surface of the silicon wafer by PECVD, and the passivation layer is any one or a combination of silicon nitride, silicon oxynitride or silicon oxide.

[0028] In a further embodiment, the thickness of the mask in step five is controlled to be 20-50 nm.

[0029] Researchers have found that in the existing battery growth process, the intrinsic amorphous silicon growth rate is slow, and the in-situ doping takes longer, which greatly reduces the battery production capacity; and the film uniformity is poor. After research, the reasons for the slow growth rate of intrinsic amorphous silicon are as follows: the growth sources of hydrogenated amorphous silicon layer, boron-doped amorphous silicon layer and phosphorus-doped amorphous silicon layer are monosilane, monosilane and phosphine, monosilane and borane, etc. Taking the growth of phosphorus-doped amorphous silicon layer as an example, in the LPCVD process, the isolated electrons of the phosphine molecule show strong polarity, which makes its adsorption on the silicon wafer surface much higher than that of monosilane, curbing the adsorption of monosilane on the silicon wafer surface, and then hindering the growth of amorphous silicon film. Monosilane (SiH4) generates SiH2 (silylene) in the gas phase reaction; the isolated electron pair of SiH2 also shows strong polarity, and SiH2 competes with phosphine in adsorption on the silicon wafer surface, making it difficult for phosphorus-doped amorphous silicon to grow, so the overall growth rate, film quality and uniformity will be greatly reduced. The same is true for the growth of boron-doped amorphous silicon. In addition, the deposition temperature during growth is very high (>560°C), and too high a temperature leads to slightly poor film density and uniformity.

[0030] In order to solve the above problems, disilane is used as a growth source in the present invention, because disilane has special chemical properties different from monosilane (easy to decompose), and the silicon content in disilane molecules is much higher than that of monosilane. In the gas phase reaction, disilane is evenly decomposed into more abundant silylene (SiH2), and its film forming temperature is much lower than that of monosilane in the LPCVD manufacturing process. Among them, an important element for transforming the non-uniformity is the low deposition temperature used for the growth of amorphous silicon film. When the temperature is lower than 500°C, the uniformity of the amorphous silicon film is improved. The decomposition process of disilane is as follows: Si2H6=SiH4+SiH2; SiH4=SiH2+H2. In the gas phase reaction, disilane is evenly decomposed into more abundant silylene (SiH2), and is in an advantageous position in the competition with phosphine, thereby allowing the reaction growth of phosphorus-doped amorphous silicon to proceed and improving the in-situ doping rate.

[0031] Beneficial effects: The present invention uses disilane instead of monosilane as a growth source in the LPCVD process, reduces the negative impact of in-situ doping, has a lower growth temperature, and reduces the growth temperature to within the range of 450°C to 500°C, thereby ensuring the quality of the film. At the same time, it has a faster growth rate, lower power consumption, reduced production costs, good film uniformity, good adjustability of doping concentration, and improved battery conversion efficiency.

[0032] Compared with the existing HBC battery production process technology, in steps 2, 4 and 8 of the present invention, when growing the intrinsic hydrogenated amorphous silicon layer, the boron-doped amorphous silicon layer and the phosphorus-doped amorphous silicon layer, disilane, disilane and borane, and a mixed gas of disilane and phosphine are used as growth sources respectively, and the production is completed by low-temperature LPCVD. This method has a fast growth rate and good film uniformity, effectively reduces production costs, and improves battery conversion efficiency. DETAILED DESCRIPTION

[0033] Example 1

[0034] A silicon wafer in-situ doping method is used to grow an intrinsic hydrogenated amorphous silicon layer and a boron-doped amorphous silicon layer on the back of the silicon wafer, comprising the following steps: placing the silicon wafer in a LPCVD equipment chamber, stabilizing the chamber temperature at 450°C, maintaining the pressure at 200 mtorr, introducing 650 sccm and 550 sccm of disilane as a growth source into the front and rear paths of the tube, and continuing the source growth for 3 minutes each time to produce a hydrogenated amorphous silicon layer;

[0035] The chamber temperature was kept stable at 450°C, the pressure was kept stable at 400mtorr, and the growth source disilane:borane was introduced into the front and rear paths of the tube at 750sccm:90sccm and 700sccm:80sccm. The source growth was continued for 15 minutes each time, and a boron-doped amorphous silicon layer of about 40nm was grown.

[0036] A silicon wafer in-situ doping method is used to grow an intrinsic hydrogenated amorphous silicon layer and a phosphorus-doped amorphous silicon layer on the back of the silicon wafer, comprising the following steps: placing the silicon wafer into an LPCVD device, stabilizing the temperature at 475°C, maintaining the pressure at 200 mtorr, introducing 650 sccm and 550 sccm of disilane as a growth source into the front and rear paths of the tube, and continuing the source growth for 3 minutes each time to produce a hydrogenated amorphous silicon layer;

[0037] The temperature was kept stable at 475°C, the pressure was kept stable at 400mtorr, and the growth sources of disilane:phosphine were introduced into the front and rear of the tube at 750sccm:90sccm and 700sccm:80sccm. The growth was continued for 16 minutes each time, and a phosphorus-doped amorphous silicon layer of about 45nm was grown with a uniformity of 1.48%.

[0038] Example 2

[0039] A silicon wafer in-situ doping method is used to grow an intrinsic hydrogenated amorphous silicon layer and a boron-doped amorphous silicon layer on the back of the silicon wafer, comprising the following steps: placing the silicon wafer in a LPCVD equipment chamber, stabilizing the chamber temperature at 500°C, maintaining the pressure at 200 mtorr, introducing 600 sccm and 500 sccm of disilane, a growth source, into the front and rear paths of the tube, and continuing the source growth for 1 minute each time to produce a hydrogenated amorphous silicon layer;

[0040] The chamber temperature was kept stable at 500°C, the pressure was kept stable at 400 mtorr, and the growth source disilane:borane was introduced into the front and rear paths of the tube at 700 sccm:85 sccm and 650 sccm:75 sccm. The source growth was continued for 10 minutes each time, and a boron-doped amorphous silicon layer of about 35 nm was grown.

[0041] A silicon wafer in-situ doping method is used to grow an intrinsic hydrogenated amorphous silicon layer and a phosphorus-doped amorphous silicon layer on the back of the silicon wafer, comprising the following steps: placing the silicon wafer into an LPCVD device, stabilizing the temperature at 500°C, maintaining the pressure at 200 mtorr, introducing 700 sccm and 600 sccm of disilane as a growth source into the front and rear paths of the tube, and continuing the source growth for 5 minutes each time to produce a hydrogenated amorphous silicon layer;

[0042] The temperature was kept stable at 500°C, the pressure was kept stable at 400mtorr, and the growth sources disilane and phosphine were introduced into the front and rear paths of the tube at 700sccm:85sccm and 650sccm:75sccm, respectively. The growth was continued for 10 minutes each time, and the phosphorus-doped amorphous silicon layer of about 40nm was grown, with a uniformity of 1.42%.

[0043] Example 3

[0044] A battery preparation method (hereinafter referred to as the method) for producing an HBC battery comprises the following steps:

[0045] (1) Cleaning the silicon wafer and making a velvet surface, using a solution of a mixture of hydrogen peroxide, deionized water, additives and sodium hydroxide, wherein the mass concentration of the alkali-made sodium hydroxide is 2.5%, the temperature is controlled at 82° C., and a pyramid velvet surface with a reflectivity of 10% is made;

[0046] (2) The cleaned and textured silicon wafer is placed in the LPCVD equipment, the temperature is stabilized at 500°C, the pressure is maintained at 200 mtorr, and the growth source disilane is introduced into the front and rear paths of the tube at 650 sccm and 550 sccm respectively. Each time the source is continuously passed through for 3 minutes to form a hydrogenated amorphous silicon layer.

[0047] (3) A silicon nitride passivation layer is grown on the surface of the silicon wafer by PECVD, and the film thickness is controlled at 78 nm.

[0048] (4) Place the coated silicon wafer into the LPCVD equipment, stabilize the temperature at 500°C, maintain the pressure at 200 mtorr, and introduce the growth source disilane into the front and rear paths of the tube at 650 sccm and 550 sccm, and continue the source growth for 3 minutes each time to produce a hydrogenated amorphous silicon layer;

[0049] The temperature was kept stable at 500°C, the pressure was kept stable at 400mtorr, and the growth sources of disilane:borane were introduced into the front and rear paths of the tube at 750sccm:90sccm and 700sccm:80sccm. The growth was continued for 15 minutes each time, and a boron-doped amorphous silicon layer of about 40nm was grown.

[0050] (5) Prepare a mask on the back side by depositing silicon nitride using PECVD, with the thickness controlled at 40 nm.

[0051] (6) Using laser equipment, according to the graphic design, the mask and amorphous silicon layer are removed in a laser grooving pattern to expose the N-type silicon.

[0052] (7) Use an acidic solution to clean the grooved area and etch away the amorphous silicon layer surrounding the silicon wafer.

[0053] (8) The cleaned silicon wafer is placed in the LPCVD equipment, the temperature is stabilized at 500°C, the pressure is maintained at 200 mtorr, and the growth source disilane is introduced into the front and rear paths of the tube at 650 sccm and 550 sccm respectively. Each time the source is continuously passed through for 3 minutes to form a hydrogenated amorphous silicon layer.

[0054] The temperature was kept stable at 500°C, the pressure was kept stable at 400mtorr, and the growth sources disilane:phosphine were introduced into the front and rear of the tube at 750sccm:90sccm and 700sccm:80sccm. The growth was continued for 16min each time, and a phosphorus-doped amorphous silicon layer of about 45nm was grown with a uniformity of 1.48%.

[0055] (9) Use an acidic solution to clean and etch away the amorphous silicon layer surrounding the silicon wafer.

[0056] (10) A highly transparent conductive film is grown on the back of the silicon wafer, and laser grooving is used to isolate the P / N regions. Then, slurry printing and metallization are performed in the P region and the N region in turn.

[0057] Example 4

[0058] A battery preparation method (hereinafter referred to as the method) for producing an HBC battery comprises the following steps:

[0059] (1) Cleaning the silicon wafer and making a velvet surface, using a solution of a mixture of hydrogen peroxide, deionized water, additives and sodium hydroxide, wherein the mass concentration of the alkali-made sodium hydroxide is 2.5%, the temperature is controlled at 82° C., and a pyramid velvet surface with a reflectivity of 11% is made;

[0060] (2) The cleaned and textured silicon wafer is placed in the LPCVD equipment, the temperature is stabilized at 450°C, the pressure is maintained at a stable level of 200 mtorr, and the growth source disilane is introduced into the front and rear paths of the tube at 650 sccm and 550 sccm, respectively. Each time the source is continuously passed through for 3 minutes to form a hydrogenated amorphous silicon layer.

[0061] (3) A composite passivation layer of silicon oxynitride and silicon oxide is grown on the surface of the silicon wafer by PECVD, and the film thickness is controlled at 75 nm.

[0062] (4) Place the coated silicon wafer into the LPCVD equipment, stabilize the temperature at 500°C, maintain the pressure at 200 mtorr, and introduce the growth source disilane into the front and rear paths of the tube at 700 sccm and 600 sccm, and continue the source growth for 5 minutes each time to produce a hydrogenated amorphous silicon layer;

[0063] The temperature was kept stable at 500°C, the pressure was kept stable at 400mtorr, and the growth sources disilane:borane were introduced into the front and rear paths of the tube at 800sccm:95sccm and 750sccm:85sccm. The growth was continued for 20min each time, and the grown boron-doped amorphous silicon layer was obtained to be 45nm.

[0064] (5) Prepare a mask on the back side by depositing silicon nitride using PECVD, with the thickness controlled at 50 nm.

[0065] (6) Using laser equipment, the groove area is designed according to the graphic design, and the mask and amorphous silicon layer in the groove area are removed in a laser groove mode to expose the N-type silicon.

[0066] (7) Use an alkaline solution to clean the grooved area and etch away the amorphous silicon layer surrounding the silicon wafer.

[0067] (8) The cleaned silicon wafer is placed in the LPCVD equipment, the temperature is stabilized at 500°C, the pressure is maintained at 200 mtorr, and the growth source disilane is introduced into the front and rear paths of the tube at 650 sccm and 550 sccm respectively. Each time the source is continuously passed through for 3 minutes to form a hydrogenated amorphous silicon layer.

[0068] The temperature was kept stable at 500°C, the pressure was kept stable at 400mtorr, and the growth sources disilane:phosphine were introduced into the front and rear of the tube at 800sccm:95sccm and 750sccm:85sccm. The growth was continued for 20min each time, and the grown phosphorus-doped amorphous silicon layer was 50nm with a uniformity of 1.51%.

[0069] (9) Use alkaline solution to clean and etch away the amorphous silicon layer surrounding the silicon wafer.

[0070] (10) A highly transparent conductive film is grown on the back of the silicon wafer, and laser grooving is used to isolate the P / N regions. Then, slurry printing and metallization are performed in the P region and the N region in turn.

[0071] Comparative Example

[0072] (1) Cleaning the silicon wafer and making a velvet surface, using a solution of a mixture of hydrogen peroxide, deionized water, additives and sodium hydroxide, wherein the mass concentration of the alkali-made sodium hydroxide is 2.5%, the temperature is controlled at 82° C., and a pyramid velvet surface with a reflectivity of 10% is made;

[0073] (2) The cleaned and textured silicon wafer is placed in the LPCVD equipment, the temperature is stabilized at 570°C, the pressure is maintained at 200 mtorr, and the growth source SiH4 is introduced into the front and rear of the tube at 650 sccm and 550 sccm respectively. Each time the source is continuously passed through for 3 minutes to form a hydrogenated amorphous silicon layer.

[0074] (3) A silicon nitride passivation layer is grown on the surface of the silicon wafer by PECVD, and the film thickness is controlled at 78 nm.

[0075] (4) Place the coated silicon wafer into the LPCVD equipment, stabilize the temperature at 570°C, maintain the pressure at 200 mtorr, and introduce the growth source SiH4 into the front and rear paths of the tube at 650 sccm and 550 sccm, and continue the source growth for 4 minutes each time to produce a hydrogenated amorphous silicon layer;

[0076] The temperature was kept stable at 570°C, the pressure was kept stable at 400mtorr, and the growth source SiH4:borane was introduced into the front and rear paths of the tube at 750sccm:90sccm and 700sccm:80sccm. The growth was continued for 26min each time, and a boron-doped amorphous silicon layer of about 40nm was grown.

[0077] (5) Prepare a mask on the back side by depositing silicon nitride using PECVD, with the thickness controlled at 40 nm.

[0078] (6) Using laser equipment, according to the graphic design, the mask and amorphous silicon layer are removed in a laser grooving pattern to expose the N-type silicon.

[0079] (7) Use an acidic solution to clean the grooved area and etch away the amorphous silicon layer surrounding the silicon wafer.

[0080] (8) The cleaned silicon wafer is placed in the LPCVD equipment, the temperature is stabilized at 570°C, the pressure is maintained at a stable level of 200 mtorr, and the growth source SiH4 is introduced into the front and rear paths of the tube at 650 sccm and 550 sccm, respectively. Each time the source is continuously passed through for 4 minutes to form a hydrogenated amorphous silicon layer.

[0081] The temperature was kept stable at 570°C, the pressure was kept stable at 400mtorr, and the growth source SiH4:phosphine was introduced into the front and rear of the tube at 750sccm:90sccm and 700sccm:80sccm. The growth was continued for 28min each time, and a phosphorus-doped amorphous silicon layer of about 46nm was grown with a uniformity of 3.68%.

[0082] (9) Use an acidic solution to clean and etch away the amorphous silicon layer surrounding the silicon wafer.

[0083] (10) A highly transparent conductive film is grown on the back of the silicon wafer, and laser grooving is used to isolate the P / N regions. Then, slurry printing and metallization are performed in the P region and the N region in turn.

[0084] The measurement data results in Examples 3, 4 and Comparative Examples are shown in the following table, wherein the measurement methods are known methods in the industry and are not described in detail.

[0085]

[0086] Table 1 Comparison of phosphorus-doped amorphous silicon film thickness test data:

[0087]

[0088]

[0089] Table 2 Comparison of Boron-doped Amorphous Silicon Film Thickness Test Data

[0090] ITEM Eta(%) Voc(V) Isc(A) Rs(mΩ) Rsh(Ω) FF Example 3 24.80 0.726 13.962 1.223 2697 81.62 Example 4 24.92 0.725 13.965 1.228 2685 81.59 Comparative Example 24.65 0.723 13.949 1.237 2384 81.54

[0091] Table 3 Electrical data comparison

[0092] Among them, Eta represents the conversion efficiency of the battery, Voc represents the open circuit voltage, Isc represents the short circuit current, Rs represents the series resistance, Rsh represents the parallel resistance, and FF represents the fill factor.

[0093] From the comparison of the data in Table 1 and Table 2, when disilane is used as the growth source, the deposition temperature is 450°C to 500°C, which has lower power consumption than the prior art, and the uniformity of the growth of the doped amorphous silicon layer is significantly better than the existing monosilane growth process, and the film thickness is more uniform. From the comparison in Table 3, the battery structure brought about by the better uniformity of the growth thickness and the controllable doping concentration of the embodiment of the present invention has good electrical performance.

Claims

1. A silicon wafer in-situ doping method, characterized in that: The following steps are involved: The first stage: disilane is introduced into the chamber loaded with the silicon wafer to deposit a hydrogenated amorphous silicon layer on the back of the silicon wafer; The second stage: disilane and borane or phosphine are introduced into the chamber to deposit a boron-doped amorphous silicon layer or a phosphorus-doped amorphous silicon layer on the back of the hydrogenated amorphous silicon layer; In the first stage and the second stage, the chamber temperature is controlled at 475°C to 500°C; in the first stage, disilane is heated to undergo a gas phase reaction and decompose to obtain a product, which is deposited on the back of the silicon wafer to form a hydrogenated amorphous silicon layer; in the second stage, disilane is heated to undergo a gas phase reaction and decompose to obtain a product, which competes with borane or phosphine on the back surface of the hydrogenated amorphous silicon layer to promote the deposition of a boron-doped amorphous silicon layer or a phosphorus-doped amorphous silicon layer; The disilane in the first stage is introduced as follows: disilane is introduced into the front and rear paths of the tube; the amount of disilane in the two paths is 600-700 sccm and 500-600 sccm respectively, and the source growth is continued for 1-5 minutes each time, wherein sccm is a unit of volume flow rate; The disilane and borane in the second stage are introduced as follows: a mixture of disilane and borane in a predetermined ratio is introduced into the front and rear paths of the tube; the amounts of disilane and borane in the two paths are respectively: 700-800 sccm for disilane and 85-95 sccm for borane, and 650-750 sccm for disilane and 75-85 sccm for borane; each source is continuously introduced for 10-20 minutes to obtain a boron-doped amorphous silicon layer of 30-60 nm; The method of introducing disilane and phosphine in the second stage is as follows: a mixture of disilane and phosphine in a predetermined ratio is introduced into the front and rear paths of the tube; the amounts of disilane and phosphine in the two paths are respectively: 700-800 sccm for disilane and 85-95 sccm for phosphine, and 650-750 sccm for disilane and 75-85 sccm for phosphine. Each time the source is continuously introduced for growth for 10-20 minutes, and a phosphorus-doped amorphous silicon layer of 30-60 nm is obtained.

2. A battery preparation method, characterized in that: The method for in-situ doping of silicon wafers as claimed in claim 1 is used to produce HBC cells, comprising the following steps: Step 1: Use the silicon wafer as the substrate material and clean and texturize it; Step 2: depositing an intrinsic hydrogenated amorphous silicon layer on the front side of the silicon wafer; Step 3: growing a passivation layer on the intrinsic hydrogenated amorphous silicon layer on the front side of the silicon wafer; Step 4: growing an intrinsic hydrogenated amorphous silicon layer and a boron-doped amorphous silicon layer on the back of the silicon wafer; Step 5: Prepare a mask on the back of the silicon wafer; Step 6: Use laser equipment to define the slotted area according to the graphic design, and remove the mask and amorphous silicon layer in the slotted area in the laser slotting mode to expose the silicon wafer; Step 7: Use any alkaline or acidic solution to clean the grooved area and etch away the amorphous silicon layer surrounding the silicon wafer; Step 8: growing an intrinsic hydrogenated amorphous silicon layer and a phosphorus-doped amorphous silicon layer on the back of the silicon wafer; Step 9: Use any alkaline or acidic solution to clean and etch away the amorphous silicon layer surrounding the silicon wafer; Step 10: Grow a highly transparent conductive film on the back of the silicon wafer, use laser grooving to isolate the P / N regions, and perform slurry printing metallization in the P region / N region in turn; In the step 1, the surface of the silicon wafer is provided with a pyramid-shaped structure by cleaning and texturing, and the reflectivity is controlled within 11%; In the step 2, the LPCVD method is adopted, the growth source introduced is disilane, and the deposition temperature is 475°C~500°C.

3. A battery preparation method according to claim 2, characterized in that: In the step three, a passivation layer is grown on the front surface of the silicon wafer by PECVD, and the passivation layer is any one or a combination of silicon nitride, silicon oxynitride or silicon oxide.

4. A battery preparation method according to claim 2, characterized in that: In the step 5, the mask thickness is controlled at 20-50 nm.

Images