Semiconductor element and method for manufacturing the same

Abstract

A semiconductor device includes a substrate, a plurality of active regions disposed in the substrate and arranged in an array along a first direction. A plurality of isolation structures are disposed in the substrate and between the active regions. The isolation structures each include an upper portion and a lower portion. A sidewall of the upper portion includes a first slope, and a sidewall of the lower portion includes a second slope. The first slope is different from the second slope. A semiconductor layer is disposed between the upper portion and the active region. A contact plug is disposed on the active region and in direct contact with the semiconductor layer. The semiconductor device improves the filling quality of the isolation structure and reduces the contact resistance of the contact plug.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor device and a method of manufacturing the same, and more particularly to a dynamic random access memory (DRAM) and a method of manufacturing the same. BACKGROUND

[0002] A dynamic random access memory (DRAM) is a volatile memory device including an array area composed of a plurality of memory cells and a peripheral area composed of a control circuit. Each memory cell includes a transistor electrically connected to a capacitor, and the storage or release of electric charges in the capacitor is controlled by the transistor to achieve the purpose of storing data. The control circuit can be positioned to each memory cell to control the access of data thereof through a word line (WL) and a bit line (BL) which are electrically connected to each memory cell and cross the array area.

[0003] In order to achieve higher integration density, the structure of a DRAM has been developed toward three-dimension, such as using a buried word line gate and a stacked capacitor architecture. As the arrangement of memory cells is more and more compact, how to ensure the electrical isolation between memory cells to reduce the leakage and signal crosstalk phenomenon is an important research project in the field. SUMMARY

[0004] The present application aims to provide a semiconductor device and a method of manufacturing the same, which uses two-stage etching to manufacture isolation trenches between active regions, so that the sidewalls of the isolation trenches have two-stage slopes, and the dielectric material can be filled more easily to obtain a better quality isolation structure, and the electrical isolation between memory cells is improved.

[0005] One embodiment of the present application provides a semiconductor device, including a substrate, a plurality of active regions disposed in the substrate and arranged in an array along a first direction. A plurality of isolation structures are disposed in the substrate and between the plurality of active regions, wherein each of the isolation structures includes an upper half and a lower half, wherein the sidewall of the upper half includes a first slope, and the sidewall of the lower half includes a second slope, and the first slope is different from the second slope. A semiconductor layer is between the upper half and the active region.

[0006] Another embodiment of the present application provides a method for manufacturing a semiconductor device. The method includes the following steps. First, a substrate is provided. Then, a first etching process is performed to form a plurality of first trenches in the substrate and define a plurality of active regions. The sidewalls of the first trenches include a first slope. The active regions respectively extend along a first direction and are arranged in an array. Next, a semiconductor layer is formed along the bottom surface and sidewalls of each of the first trenches. Then, a second etching process is performed to etch down from between the semiconductor layers on the sidewalls of the first trenches to form a second trench directly below each of the first trenches. The sidewalls of the second trenches include a second slope, which is different from the first slope. Subsequently, a dielectric layer is formed to fill each of the first trenches and each of the second trenches. BRIEF DESCRIPTION OF DRAWINGS

[0007] The accompanying drawings are included to provide a further understanding of the present application and are incorporated in and constitute a part of this specification. The drawings illustrate the principles of the application and, although not to be limited thereto, serve to explain the principles of the application. It is emphasized that all drawings are schematic representations to facilitate understanding of the application, and relative dimensions and proportions of parts in the drawings have been set to facilitate an understanding of the application. Identical or nearly identical components are represented by the same reference numerals in different figures.

[0008] Figures 1 to 8 A schematic diagram of the steps of a method for manufacturing a semiconductor device according to an embodiment of the present application.

[0009] Figure 9 A schematic diagram of a cross-section of a semiconductor device according to another embodiment of the present application.

[0010] Figure 10 A schematic diagram of a cross-section of a semiconductor device according to yet another embodiment of the present application.

[0011] In the drawings, the following reference numerals are used:

[0012] 100 substrate

[0013] 102 pad layer

[0014] 104 hard mask layer

[0015] 106 isolation trench

[0016] 108 active region

[0017] 120 semiconductor layer

[0018] 122 dielectric layer

[0019] 130 isolation structure

[0020] 132 air gap

[0021] 140 insulating layer

[0022] 142 Interlayer Dielectric Layer

[0023] 162 Passivation layer

[0024] 202 character line groove

[0025] 204 Dielectric Layer

[0026] 206 conductive layer

[0027] 208 Insulating Cover

[0028] 106a First Trench

[0029] 106b Second Trench

[0030] 108a Middle section

[0031] 108b end

[0032] 130a Upper half

[0033] 130b lower half

[0034] BL bitline

[0035] D1 Depth

[0036] D2 Depth

[0037] D3 Depth

[0038] D4 Depth

[0039] DR1 First Direction

[0040] DR2 Second Direction

[0041] DR3 Third Direction

[0042] E1 First Etching Process

[0043] E2 Second Etching Process

[0044] II Tangent

[0045] II-II' Tangent

[0046] SNC contact plug

[0047] SNP contact pads

[0048] S1 sidewall

[0049] S2 sidewall

[0050] T0 thickness

[0051] T1 thickness

[0052] T2 thickness

[0053] T3 thickness

[0054] T4 thickness

[0055] W1 width

[0056] W2 width

[0057] W3 width

[0058] W4 width

[0059] WL word line DETAILED DESCRIPTION

[0060] In order to enable persons having ordinary skill in the art to make or use the application, the preferred embodiments of the application will be discussed below with reference to the accompanying drawings, in which:

[0061] Figures 1 to 8 A flow chart of a method for manufacturing a semiconductor device according to an embodiment of the application. Figure 2 and Figure 7 is a plan view. Figure 1 、 Figures 3 to 6 and Figure 8 The right side is a cross-sectional view along the cutting line I-I' in the plan view, and the left side is a cross-sectional view along the cutting line II-II' in the plan view. It should be noted that the first direction DR1, the second direction DR2 and the third direction DR3 indicated in the plan view are all along the surface of the substrate 100, in which the second direction DR2 and the third direction DR3 are perpendicular to each other, and the first direction DR1 is different from the second direction DR2 and the third direction DR3. The cutting line I-I' extends along the second direction DR2 to cut through the active region 108, and the cutting line II-II' extends along the first direction DR1 to cut through the active region 108.

[0062] First, please refer to Figure 1 A substrate 100, such as a silicon substrate, a silicon epitaxial substrate, a silicon germanium substrate, a silicon carbide substrate, or a silicon-on-insulator substrate, but not limited thereto, is provided first. The substrate 100 can include a doping to have a specific conductivity type, such as a P-type. The surface of the substrate 100 can be provided with a liner layer 102, such as a silicon oxide layer.

[0063] Please refer to Figure 2 and Figure 3Next, a hard mask layer 104 (e.g., a silicon nitride layer) is formed on the pad layer 102. Then, a patterning process is performed on the hard mask layer 104 to transfer the expected active region pattern into the hard mask layer 104. Using the hard mask layer 104 as a mask, a first etching process E1 is performed on the substrate 100 to further transfer the active region pattern into the substrate 100, forming multiple active regions 108 and first trenches 106a separating each active region 108. After the first etching process E1, a cleaning process can be performed on the substrate 100 to remove byproducts generated during etching, such as polymers.

[0064] The first etching process E1 can be a reactive ion etching (RIE) process, and the reactive gases used may include oxygen-containing gases, fluorine-containing gases (e.g., CF4, SF6, CH2F2, CHF3 and / or C2F6), chlorine-containing gases (e.g., Cl2, CHCl3, CCl4 and / or BCl3), bromine-containing gases (e.g., HBr and / or CHBr3), iodine-containing gases, other suitable gases, and / or combinations thereof. The gases used in the first etching process E1 may also include passivating gases, such as argon (Ar). According to an embodiment of the present invention, the etching endpoint of the first etching process E1 is determined by a time mode, which adjusts the process time of the first etching process E1 based on the expected depth of the first trench 106a.

[0065] like Figure 2 As shown, the active region 108 is elongated, with its long axis extending along the first direction DR1, and arranged in an array parallel to each other. Figure 3 As shown in the left-hand diagram, the first trench 106a between the sides of the active region 108 may include a width W1 and a depth D1. For example... Figure 3 As shown in the right-hand illustration, the first trench 106a between the ends of the active region 108 may include a width W2 and a depth D2. In some embodiments, the width W1 is smaller than the width W2, and the depth D1 is approximately equal to the depth D2. The cross-sectional profile of the first trench 106a can be adjusted by adjusting the process parameters of the first etching process E1, such as the gas ratio and power. In some embodiments, the sidewall S1 of the first trench 106a may be defined to have a first slope. If the slope is represented by the angle between the sidewall and the surface of the substrate 100, the first slope may be between 90 degrees and 80 degrees, but is not limited thereto. In a preferred embodiment, the sidewall S1 of the first trench 106a is almost perpendicular to the surface of the substrate 100 to enable more accurate control of the critical dimensions of the active region 108 and the first trench 106a.

[0066] Please refer to Figure 4A deposition process, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or epitaxial growth, is then performed to form a semiconductor layer 120 on the substrate 100 and conformally cover the hardmask layer 104 and the sidewalls S1 and the bottom of the first trench 106a. In some embodiments, the semiconductor layer 120 can be formed only on the sidewalls S1 and the bottom of the first trench 106a, without covering the hardmask layer 104. The semiconductor layer 120 can be any suitable semiconductor material, such as silicon, germanium, silicon germanium, silicon carbide, but is not limited thereto. In some embodiments, the semiconductor layer 120 can include a dopant to have a specific conductivity type, such as N-type. The slope of the sidewalls of the semiconductor layer 120 can be substantially equal to the first slope of the sidewalls S1 of the first trench 106a.

[0067] Referring to Figure 5 A second etching process E2 is then performed to remove the semiconductor layer 120 from the bottom of the first trench 106a and further etch the substrate 100 to form a second trench 106b directly below the first trench 106a. After the second etching process E2, the sidewalls of the first trench 106a are still covered by the semiconductor layer 120 and are not exposed. The opening of the second trench 106b is cut flush with the bottom end of the semiconductor layer 120, where the position of the bottom end of the semiconductor layer 120 is substantially determined by the depth (bottom) of the first trench 106a. In some embodiments, the bottom end of the semiconductor layer 120 is located at the same depth below the surface of the substrate 100, i.e., at the same plane. After the second etching process E2, a cleaning process can be performed on the substrate 100 to remove byproducts, such as polymers, generated during the etching.

[0068] The second etching process E2 can be a reactive ion etching (RIE) process, and the gases used may include oxygen-containing gases, fluorine-containing gases (e.g., CF4, SF6, CH2F2, CHF3 and / or C2F6), chlorine-containing gases (e.g., Cl2, CHCl3, CCl4 and / or BCl3), bromine-containing gases (e.g., HBr and / or CHBr3), iodine-containing gases, other suitable gases, and / or combinations thereof. The gases used in the second etching process E2 may also include passivating gases, such as argon (Ar). It is worth noting that, compared to the first etching process E1, the second etching process E2 generates more polymer byproducts that deposit on the sidewalls, resulting in more pronounced sidewall passivation. Therefore, the cross-sectional profile of the etched second trench 106b will differ from that of the first trench 106a, for example, having a more inclined, trapezoidal, or conical cross-sectional profile. The second etching process E2 can also be referred to as a high polymer etching process. In some embodiments, the sidewall S2 of the second trench 106b may be defined to have a second slope, and the second slope is different from the first slope of the sidewall S1 of the first trench 106a. If the slope is represented by the angle between the sidewall and the surface of the substrate 100, the second slope may be between approximately 90 degrees and 70 degrees, but is not limited thereto.

[0069] The etching endpoint of the second etching process, E2, can be determined by time mode or terminate naturally due to the accumulation of polymer byproducts, making further etching impossible. For example... Figure 5 As shown in the left-hand diagram, the second trench 106b between the sides of the active region 108 may include a width W3 (at the opening) and a depth D3. For example... Figure 5 As shown in the right-hand diagram, the second trench 106b between the ends of the active region 108 may include a width W4 and a depth D4. In some embodiments, the width W3 is smaller than the width W4, the depth D3 is smaller than the depth D4, and due to the presence of the semiconductor layer 120, the widths W3 and W4 are smaller than the widths W1 and W2 of the first trench 106a, respectively. The first trench 106a and the second trench 106b together constitute the isolation trench 106, and their ratio can be adjusted according to actual needs to simultaneously meet the structural support and electrical isolation of the active region 108, and the dielectric layer 122 (reference) Figure 6 The groove filling capability and contact plug SNC (reference) Figure 8 Contact area and resistance, word line WL (reference) Figure 8 The depth of the active region 108 and the specifications for insulation, parasitic electrons, and parasitic capacitance are required. In some embodiments, depth D3 is greater than depth D1, and depth D4 is greater than depth D2.

[0070] Please refer to Figure 6A deposition process such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition is then performed to form a dielectric layer 122 on the substrate 100. A planarization process such as a chemical mechanical polishing process is then performed to remove excess dielectric layer 122 outside the isolation trench 106, resulting in an isolation structure 130 filled in the isolation trench 106. In some embodiments, a liner 100 such as a silicon oxide layer can be formed prior to forming the dielectric layer 122 along the sidewalls and the bottom of the isolation trench 106. In some embodiments, a portion of the substrate 100 can be oxidized to form the dielectric layer 122 using an oxidation process such as thermal oxidation or local vapor phase oxidation. The liner layer 102 and the remaining hard mask layer 104 on the surface of the substrate 100 can be removed simultaneously during the chemical mechanical polishing process or can be removed by an etching process after the chemical mechanical polishing process.

[0071] The material of the isolation structure 130 (i.e., the material of the dielectric layer 122) can include silicon oxide, silicon nitride, and / or other suitable dielectric materials. The upper half 130a of the isolation structure 130 directly contacts the semiconductor layer 120 and is separated from the substrate 100 (active region 108) by the semiconductor layer 120 without direct contact. In some embodiments, the slope of the sidewall of the upper half 130a of the isolation structure 130 can be substantially equal to the first slope. The lower half 130b of the isolation structure 130 directly contacts the substrate 100, and the interface between the upper half 130a and the lower half 130b is flush with the bottom end of the semiconductor layer 120. In some embodiments, the lower half 130b of the isolation structure 130 has a trapezoidal or tapered cross-sectional profile, and the slope of the sidewall can be substantially equal to the second slope of the sidewall S2 of the second trench 106b. The thickness TO of the isolation structure 130 is equal to the sum of the thickness of the upper half 130a and the thickness of the lower half 130b. As shown in the left side legend, Figure 6 As shown in the left side legend, the upper half 130a between the side edges of the active region 108 has a thickness Tl, and the lower half 130b has a thickness T3, which are determined by a depth Dl and a depth D3, respectively. As shown in the right side legend, Figure 6 As shown in the right side legend, the upper half 130a between the end portions of the active region 108 has a thickness T2, and the lower half 130b has a thickness T4, which are determined by a depth D2 and a depth D4, respectively. In some embodiments, the thickness T3 is greater than the thickness Tl, and the thickness T4 is greater than the thickness T2. That is, the lower half 130b occupies a greater proportion of the overall thickness (depth) of the isolation structure 130 than the upper half 130a.

[0072] Please refer to Figure 7 and Figure 8Next, an insulating layer 140, such as a silicon oxide layer, can be formed on the substrate 100. Then, a series of semiconductor manufacturing processes are performed to form multiple word lines WL buried in the substrate 100, multiple bit lines BL disposed on the substrate 100, contact plugs SNC disposed between the bit lines BL, and contact pads SNP disposed on the contact plugs SNC. Figure 7 and Figure 8 As shown, word lines WL are formed within word line trenches 202, extending parallel to the second direction DR2 and cutting through the isolation structure 130 and the active regions 108, thus dividing each active region 108 into a middle portion 108a and two end portions 108b. Each word line WL includes a conductive layer 206 filling the lower half of the word line trench 202, an insulating capping layer 208 disposed on the conductive layer 206, and a dielectric layer 204 between the conductive layer 206 and the substrate 100. The conductive layer 206 may include a metallic material, such as tungsten, copper, aluminum, titanium, tantalum, work function metals, or compounds, alloys, and / or composite layers of the aforementioned metallic materials, but is not limited thereto. The insulating capping layer 208 and the dielectric layer 204 may each include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, high-k dielectric material, or a combination of the above materials, but are not limited thereto. In some embodiments, such as Figure 8 As shown, the top surface of the insulating cap 208 can be flush with the top surface of the isolation structure 130, the top of the semiconductor layer 120, and / or the surface of the substrate 100 (the surface in contact with the insulating layer 140), and the bottom surface of the insulating cap 208 (or the top surface of the conductive layer 206) is higher than the bottom of the semiconductor layer 120.

[0073] The bit line BL extends parallel to the third direction DR3 and is in direct contact with the middle portion 108a of the active region 108 and the semiconductor layers 120 on both sides of the middle portion 108a, while being separated from other portions by the insulating layer 140 and not in direct contact. The bit line BL may include a stacked structure, comprising, from bottom to top, a semiconductor layer 120, a metal layer, and a hard mask layer 104. The material of the semiconductor layer 120 may include polycrystalline silicon, amorphous silicon, or other suitable semiconductor materials. The material of the metal layer may include aluminum, tungsten, copper, titanium-aluminum alloy, or other suitable low-resistance metal materials. The hard mask layer 104 may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or a combination of the above materials, but is not limited thereto. In some embodiments, an interface layer (not shown) may be included between the semiconductor layer 120 and the metal layer, such as a single-layer or multi-layer structure layer composed of titanium, tungsten silicide, tungsten nitride, and / or other metal silicides or metal nitrides, but is not limited thereto. The bottom surface of the bit line BL can be recessed into the substrate 100, below the top surface of the isolation structure 130 and above the bottom end of the semiconductor layer 120.

[0074] The contact plug SNC penetrates the interlayer dielectric layer 142 filled between the bit lines BL, directly contacts the end portion 108b of the active region 108 and the semiconductor layer 120 on the sidewall of the end portion 108b, respectively, and is separated from the bit lines BL by the spacer disposed on the sidewall of the bit lines BL without direct contact. The contact plug SNC can include a conductive material, such as a semiconductor material or a metallic material, wherein the semiconductor material can include single crystal silicon, polycrystalline silicon, amorphous silicon, or other suitable semiconductor material, and the metallic material can include tungsten, copper, aluminum, titanium, tantalum, or a compound, an alloy, and / or a composite layer of the aforementioned metallic material, but is not limited thereto. The material of the interlayer dielectric layer 142 can include silicon oxide, but is not limited thereto. In some embodiments, the contact plug SNC is composed of both the semiconductor material and the metallic material. The bottom surface of the contact plug SNC can be sunken into the substrate 100, but is higher than the bottom surface of the bit line BL. Due to the different depths of the bit line BL and the bottom surface of the contact plug SNC sunken into the substrate 100, the top end of the semiconductor layer 120 in contact therewith is also located at different depths of the substrate 100, i.e., not in the same plane, and is lower than the top end of the semiconductor layer 120 not in contact with the bit line BL or the contact plug SNC.

[0075] The contact pad SNP is directly disposed on the contact plug SNC, with the lower half thereof between the bit lines BL and the upper half thereof higher than the bit lines BL and can partially overlap the top surface of the bit lines BL. The contact pad SNP can include a metallic material, such as tungsten, copper, aluminum, titanium, tantalum, or a compound, an alloy, and / or a composite layer of the aforementioned metallic material, but is not limited thereto. The gap between the upper half of the contact pad SNP can be filled with the passivation layer 162 to provide a flat surface for the subsequent fabrication of a capacitor structure (not shown) thereon. The material of the passivation layer 162 can include silicon nitride, but is not limited thereto.

[0076] The present application utilizes a two-stage etching, i.e., the first etching process E1 and the second etching process E2, to fabricate the isolation trench 106, so that the sidewall of the isolation trench 106 has a two-stage slope, wherein the upper sidewall is more vertical to be able to more accurately control the critical dimension of the active region 108, and the lower sidewall is more inclined to help the filling of the dielectric layer 122, so that the dielectric layer 122 can completely fill the entire isolation trench 106, or ensure that there is no air gap or seam caused by poor filling at least in the depth range of the word line WL, thereby improving the quality of the isolation structure 130.

[0077] Please refer to Figure 9 and Figure 10 , respectively, which show cross-sectional schematic views of semiconductor elements according to some other embodiments of the present application, both of which are similar to Figure 8The structures of the illustrated semiconductor elements are substantially the same, each including a substrate 100, an active region 108 (indicated as middle portion 108a and end portion 108b), an isolation structure 130, and a semiconductor layer 120 between the upper half 130a of the isolation structure 130 and the active region 108. The difference is that, as shown in Figure 9 As shown, when the second trench 108b is deeper, an air gap 132 can be formed at the bottom of the second trench 108b, and the position of the air gap 132 is lower than the word line WL, so it will not be exposed when etching the word line trench 202 to cause abnormal structure of the word line WL. As shown, Figure 10 As shown, more material of the end portion 108b of the active region 108 can be removed when manufacturing the contact hole of the contact plug SNC until the semiconductor layer 120 of the sidewall is exposed, so that the contact plug SNC is in direct contact with the semiconductor layer 120 on the other side of the end portion 108b, further reducing the contact resistance and obtaining better performance.

[0078] The above only describes the preferred embodiments of the present application and is not intended to limit the present application. Those skilled in the art can make various modifications and changes to the present application. Any modification, equivalent replacement, improvement, etc. within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A semiconductor element characterized by comprising: Comprising: a substrate; a plurality of active regions disposed in the substrate, respectively extending along a first direction and arranged in an array; a plurality of isolation structures disposed in the substrate and located between the plurality of active regions, wherein the isolation structures respectively comprise an upper half and a lower half located below the upper half, wherein the isolation structure sidewall of the upper half comprises a first slope and a first thickness, the isolation structure sidewall of the lower half comprises a second slope and a second thickness, the first slope is different from the second slope; and a semiconductor layer between the upper half and the active regions; the width of the upper half and the lower half at the interface between the semiconductor layer is equal; the depth of the isolation structure between the side edges of the active regions is less than the depth of the isolation structure between the ends of the active regions; a plurality of word lines disposed in the substrate; the word line comprises a conductive layer, the top surface of the conductive layer is higher than the bottom of the semiconductor layer, and the bottom of the conductive layer is higher than the bottom of the lower half.

2. The semiconductor device according to claim 1, wherein The material of the substrate comprises silicon, and the material of the semiconductor layer comprises silicon, germanium, or silicon germanium.

3. The semiconductor device according to claim 1, wherein The bottom end of the semiconductor layer is cut flush with the interface of the upper half and the lower half.

4. The semiconductor device according to claim 1, wherein The second thickness is greater than the first thickness.

5. The semiconductor device according to claim 1, wherein The top end of the semiconductor layer is not in the same plane.

6. The semiconductor device according to claim 1, wherein The lower half comprises an air gap.

7. The semiconductor device according to claim 1, wherein Further comprising: the plurality of word lines extend parallel along a second direction and cut through the plurality of isolation structures and the plurality of active regions, and each of the active regions is divided into a middle part and two end parts; a plurality of bit lines disposed on the substrate, extending parallel along a third direction, and directly contacting the middle part of each of the active regions and the semiconductor layer on both sides of the middle part, wherein the second direction and the third direction are perpendicular to each other, and different from the first direction; and a plurality of contact plugs located between the plurality of bit lines, respectively directly contacting one of the end parts.

8. The semiconductor device according to claim 7, wherein The contact plug directly contacts the semiconductor layer on one side of the end part.

9. The semiconductor device according to claim 7, wherein The bottom of the isolation structure between the end parts is lower than the bottom of the isolation structure on both sides of the middle part.

10. The semiconductor device according to claim 7, wherein The bottom end of the semiconductor layer is lower than the bottom surface of the contact plug.

11. The semiconductor device according to claim 7, wherein The word line further comprises: an insulating cap layer located on the conductive layer, wherein the top end of the semiconductor layer is cut flush with the top surface of the insulating cap layer, and the bottom end of the semiconductor layer is lower than the bottom surface of the insulating cap layer.

12. A method of manufacturing a semiconductor element, characterized by, Comprising: providing a substrate; performing a first etching process to form a plurality of first trenches in the substrate and define a plurality of active regions, respectively extending along a first direction and arranged in an array, wherein the sidewall of the first trench comprises a first slope; forming a semiconductor layer along the bottom surface and sidewall of each of the first trenches; performing a second etching process to etch down from between the semiconductor layers on the sidewall of the first trench to form a second trench directly below each of the first trenches, wherein the sidewall of the second trench comprises a second slope, and the first slope is different from the second slope; The first trench and the second trench have equal width at the junction between the semiconductor layers; the second trench has a greater depth between adjacent ends of the plurality of active regions than between adjacent sides of the plurality of active regions; and forming a dielectric layer filling each of the first trenches and each of the second trenches; forming a plurality of word lines in the substrate, the word lines comprising a conductive layer having a top surface higher than a bottom of the semiconductor layer and a bottom surface higher than a bottom of the second trench.

13. The method for manufacturing a semiconductor element according to claim 12, wherein The second etching process is a high polymer etching process.

14. The method for manufacturing a semiconductor element according to claim 12, wherein The substrate and the semiconductor layer comprise silicon, germanium, or silicon germanium, respectively.

15. The method for manufacturing a semiconductor element according to claim 12, wherein The second trench has an opening flush with a bottom end of the semiconductor layer.

16. The method for manufacturing a semiconductor element according to claim 12, wherein The second trench has a greater depth than the first trench.

17. The method for manufacturing a semiconductor element according to claim 12, wherein The second trench comprises a tapered profile.

18. The method for manufacturing a semiconductor element according to claim 12, wherein Further comprising: The plurality of word lines extend parallel along a second direction and cut through the dielectric layer and the plurality of active regions, dividing each of the active regions into a middle portion and two end portions; forming a plurality of bit lines on the substrate, extending parallel along a third direction and directly contacting the middle portion of each of the active regions and the semiconductor layer on both sides of the middle portion, wherein the second direction and the third direction are perpendicular to each other and different from the first direction; and forming a plurality of contact plugs between the plurality of bit lines, each directly contacting one of the end portions.

19. The method of manufacturing a semiconductor element according to claim 18, wherein The plurality of contact plugs directly contact the semiconductor layer on one side of the end portions, respectively.

20. A semiconductor device, characterized by comprising: Comprising: a substrate; a plurality of active regions disposed in the substrate, each extending along a first direction and arranged in an array; a plurality of isolation structures disposed in the substrate and between the plurality of active regions, wherein each of the isolation structures comprises an upper half and a lower half below the upper half, wherein a sidewall of the upper half of the isolation structure comprises a first slope and a first thickness, a sidewall of the lower half of the isolation structure comprises a second slope and a second thickness, and the first slope is different from the second slope; and a semiconductor layer between the upper half and the active regions, a bottom end of the semiconductor layer flush with the upper half and the lower half; a bottom of the isolation structure between the end portions of the active regions is lower than a bottom of the isolation structure on both sides of the middle portion of the active regions.

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