Semiconductor structure with power connection structure under transistor and method of manufacturing thereof

Abstract

A method of manufacturing a semiconductor structure with power connection structure under a transistor includes forming a stop layer structure in a semiconductor substrate, dividing the semiconductor substrate into a substrate first portion and a substrate second portion, forming a plurality of stop portions in the substrate first portion and adjacent to an active surface, disposing a transistor element on the active surface, a contact portion of the transistor element corresponding to the stop portions, removing the substrate second portion and the stop layer structure, forming a first patterned mask layer with a first patterned opening on a bottom surface of the substrate first portion, the first patterned opening corresponding to the stop portions, forming a through opening in the substrate first portion, the contact portion being exposed through the through opening, forming a protective layer covering sidewalls of the through opening, forming a conductive layer covering the contact portion, and forming the power connection structure in the through opening. The method has flexibility and can improve device performance.

Description

Technical Field

[0001] The present invention relates to a semiconductor technology, and in particular to a method for manufacturing a semiconductor structure with a power connection structure under a transistor and a semiconductor structure with a power connection structure under a transistor. Background Art

[0002] The semiconductor industry has experienced rapid growth due to improvements in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). With the increasing demand for miniaturization, higher speed, greater bandwidth, lower power consumption, and lower latency, chip layouts have become increasingly complex and difficult to implement in semiconductor die manufacturing. For example, one of the challenges is the decreasing routing area.

[0003] The current implementation of multi-gate transistors reduces device size and increases device packaging density, which poses challenges to the design of power and signal routing. Although existing source / drain contact structures are generally adequate for their intended purposes, they are not satisfactory in all aspects. Summary of the Invention

[0004] The present invention provides a method for manufacturing a semiconductor structure having a power connection structure under a transistor and a semiconductor structure having a power connection structure under a transistor. The design in which the power connection structure is directly formed under the transistor makes the overall process more flexible, thereby improving device performance and alleviating the problem of reduced wiring area.

[0005] The present invention provides a method for manufacturing a semiconductor structure having a power connection structure under a transistor, comprising: providing a semiconductor substrate having an active surface and a back surface relative to each other; forming a stop layer structure in the semiconductor substrate, dividing the semiconductor substrate into a first substrate portion and a second substrate portion, wherein the first substrate portion is located between the stop layer structure and the active surface, and the second substrate portion is located between the stop layer structure and the back surface; forming a patterned stop layer in the first substrate portion and adjacent to the active surface, the patterned stop layer comprising a plurality of stop portions; setting an active layer on the active surface, the active layer comprising a transistor element and an interconnect layer, the interconnect layer covering the transistor element, the transistor element comprising a contact portion, and the contact portion corresponding to the stop portion; performing a thinning process to remove the second substrate portion and the stop layer. A stop layer structure is provided so that the first part of the substrate is exposed on the bottom surface opposite to the active surface; a first patterned mask layer is formed on the bottom surface, the first patterned mask layer includes a first patterned opening, and the first patterned openings correspond to the stop portions respectively; a groove is formed in the first part of the substrate corresponding to the first patterned opening, the groove passes through the first part of the substrate, the groove includes opposite side walls and a through opening end, and the contact portion of the transistor element of the active layer is exposed through the through opening end; a protective layer is formed to cover the bottom surface of the first part of the substrate and the two side walls of the groove; a conductive layer is formed to cover the contact portion exposed through the groove; an electroplating seed layer is formed to cover the protective layer and the conductive layer; and a power connection structure is formed on the electroplating seed layer of the groove, wherein the power connection structure fills the groove.

[0006] The semiconductor structure provided by the present invention, which has a power connection structure under a transistor, includes a substrate, an active layer, a stopper, a protective layer, a conductive layer, an electroplated seed layer, and a power connection structure. The substrate has an active surface and a bottom surface, wherein a groove is formed on the bottom surface, extending through the active surface and including two opposing side walls and a through-opening end. The active layer is disposed on the active surface, the active layer including a transistor element and an interconnect layer, the interconnect layer covering the transistor element, the transistor element including a contact portion, the contact portion being exposed through the through-opening end. The stopper is respectively embedded in the two side walls of the groove and adjacent to the through-opening end. The protective layer is conformally disposed on the two side walls and the bottom surface. The conductive layer is disposed on the contact portion exposed through the through-opening end. The electroplated seed layer conformally covers portions of the protective layer and the conductive layer located on the two side walls. The power connection structure is filled in the groove.

[0007] In one embodiment of the present invention, the transistor element includes a source, a gate, and a drain. The gate is located between the source and the drain. The contact portion of the transistor element is disposed at at least one of the source and the drain.

[0008] In one embodiment of the present invention, the stop layer structure includes a first stop layer and a second stop layer stacked on each other. The material of the first stop layer is different from that of the second stop layer. The second stop layer is located between the first stop layer and the second active layer.

[0009] In one embodiment of the present invention, the method for forming the above-mentioned patterned stop layer and stop layer structure includes: performing a first ion implantation from the active surface of the semiconductor substrate to a first depth of the semiconductor substrate; performing a second ion implantation from the active surface of the semiconductor substrate to a second depth of the semiconductor substrate, and the second depth is less than the first depth; forming a patterned photoresist layer on the active surface, performing a third ion implantation to a third depth of the semiconductor substrate using the patterned photoresist layer as a mask, and the third depth is less than the second depth; and removing the patterned photoresist layer and performing a high-temperature treatment process, so that the area of ​​the first ion implantation forms a first stop layer, the area of ​​the second ion implantation forms a second stop layer, and the area of ​​the third ion implantation forms a patterned stop layer.

[0010] In one embodiment of the present invention, the material of the first stop layer is silicon nitride, the material of the second stop layer is silicon dioxide, and the material of the patterned stop layer is silicon nitride.

[0011] In one embodiment of the present invention, the thickness of the semiconductor substrate is between 700 microns and 800 microns, the distance between the stop layer structure and the active surface is between 30 nanometers and 200 nanometers, and the distance between the patterned stop layer and the active surface is between 5 nanometers and 20 nanometers.

[0012] In one embodiment of the present invention, the steps of the above-mentioned thinning process include: performing a backside polishing process, polishing from the back side of the semiconductor substrate to remove a portion of the second portion of the substrate; a first removal step to remove the remaining second portion of the substrate; a second removal step to remove the first stop layer; and a third removal step to remove the second stop layer, wherein the first removal step, the second removal step and the third removal step are selected from one of chemical mechanical polishing and wet etching.

[0013] In one embodiment of the present invention, the above-mentioned step of forming a groove in the first part of the substrate includes: using the first patterned mask layer as a mask, removing part of the first part of the substrate to form a plurality of grooves, wherein the stop portion serves as an etching stop layer; using the first patterned mask layer as a mask, removing a part of each stop portion exposed through the groove to form a through groove in each stop portion; using the first patterned mask layer as a mask, removing the part of the first part of the substrate exposed through the through groove to form a through opening end; and removing the first patterned mask layer.

[0014] In one embodiment of the present invention, a plasma etching process is used to remove a portion of the first portion of the substrate to form a groove, a pad removal process is used to remove a portion of each stop portion to form a through groove, and a dry etching process is used to remove the portion of the first portion of the substrate exposed through the through groove.

[0015] In one embodiment of the present invention, the step of forming the protective layer includes: conformally forming a dielectric film to cover the bottom surface of the first portion of the substrate, the sidewalls of the groove, and the contact portion exposed through the through-opening end; forming a second patterned mask layer to cover the dielectric film, the second patterned mask layer including a plurality of second patterned openings, the second patterned openings corresponding to portions of the dielectric film in contact with the contact portion; removing portions of the dielectric film exposed through the second patterned openings to expose the contact portion; and removing the second patterned mask layer.

[0016] In one embodiment of the present invention, the above-mentioned steps of forming a conductive layer include: conformally forming a metal film to cover the protective layer and the contact portion exposed by the groove; performing an annealing process on the metal film to make the metal film become a silicide layer; and removing a portion of the silicide layer located on the protective layer, leaving another portion of the silicide layer in contact with the contact portion as a conductive layer.

[0017] In one embodiment of the present invention, the above-mentioned step of forming the power connection structure includes: electroplating the electroplating layer to cover the electroplating seed layer, and the electroplating layer fills each groove; and removing part of the electroplating layer and part of the electroplating seed layer located outside the groove, wherein the part of the electroplating layer filled in the groove serves as the power connection structure.

[0018] The present invention forms a stop layer structure at a depth of the semiconductor substrate and gradually performs a subsequent thinning process, so that the semiconductor substrate can be polished or etched until only an extremely thin first portion of the substrate remains. The power connection structure is directly connected longitudinally to the source and / or drain of the transistor element, allowing the transistor element to be powered or grounded via the back side (bottom side) of the substrate, thereby improving the problem of reduced wiring area. The longitudinal length of the power connection structure can be adjusted according to the thickness of the retained first portion of the substrate, making the overall process more flexible and improving device performance.

[0019] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, which can be implemented in accordance with the contents of the specification, and to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the following specifically cites preferred embodiments and describes them in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figures 1A to 1R FIG2 is a cross-sectional view of a method for manufacturing a semiconductor structure having a power connection structure under a transistor according to an embodiment of the present invention.

[0021] Figure 2 Schematic diagram of an application of a semiconductor structure with a power connection structure under a transistor according to an embodiment of the present invention.

[0022] Figure 3This is another application diagram of a semiconductor structure with a power connection structure under a transistor according to an embodiment of the present invention.

[0023] Figure 4 This is another application diagram of a semiconductor structure with a power connection structure under a transistor according to an embodiment of the present invention. DETAILED DESCRIPTION

[0024] Figures 1A to 1R FIG. 1 is a cross-sectional view of a method for manufacturing a semiconductor structure having a power supply connection structure under a transistor according to an embodiment of the present invention. Figure 1A As shown, a semiconductor substrate 10 is provided. The semiconductor substrate 10 can be, for example, a silicon substrate, an epitaxial silicon substrate, a silicon germanium substrate, a silicon carbide substrate, or a silicon-on-insulation (SOI) substrate. In one embodiment, the thickness of the semiconductor substrate 10 is, for example, 700 to 800 microns (um), preferably 775 microns. The semiconductor substrate 10 has an active surface 101 and a back surface 102 opposite to each other.

[0025] like Figure 1D As shown, a stop layer structure 20 is formed within a semiconductor substrate 10. The stop layer structure 20 divides the semiconductor substrate 10 into a first substrate portion 103 and a second substrate portion 104. The portion of the semiconductor substrate 10 between the stop layer structure 20 and the active surface 101 is referred to as the first substrate portion 103, and the portion of the semiconductor substrate 10 between the stop layer structure 20 and the back surface 102 is referred to as the second substrate portion 104. Furthermore, a patterned stop layer 18 is formed within the first substrate portion 103 and closer to the active surface 101. The patterned stop layer 18 includes a plurality of stop portions 181. In one embodiment, the stop layer structure 20 includes a first stop layer 12 and a second stop layer 14 stacked together. The material of the first stop layer 12 is different from that of the second stop layer 14. The second stop layer 14 is interposed between the first stop layer 12 and the active surface 101. In one embodiment, the distance between the stop layer structure 20 and the active surface 101 is between 30 nanometers and 200 nanometers, and the distance between the patterned stop layer 18 and the active surface 101 is between 5 nanometers and 20 nanometers; and the thickness of the first stop layer 12 and the second stop layer 14 is, for example, approximately 300 nanometers, the thickness of the stop portion 181 is, for example, approximately 10 nanometers, and the width of the stop portion 181 is, for example, approximately 50 nanometers.

[0026] Please continue reading Figures 1A to 1DAs shown, in one embodiment, the method for forming the stop layer structure 20 and the patterned stop layer 18 includes first performing a first ion implantation 12a at a first depth D1 from the active surface 101 of the semiconductor substrate 10, as shown in FIG. Figure 1A As shown, a first ion implantation region 12' is formed; and a second ion implantation 14a is performed at a second depth D2 from the active surface 101 of the semiconductor substrate 10. Figure 1B As shown, a second ion implantation region 14' is formed, wherein the second depth D2 of the second ion implantation region 14' is smaller than the first depth D1 of the first ion implantation region 12'; then, as shown Figure 1C As shown, a patterned photoresist layer 16 is formed on the active surface 101, and a third ion implantation 18a is performed on the third depth D3 of the semiconductor substrate 10 using the patterned photoresist layer 16 as a mask to form a third ion implantation region 18'. The third depth D3 is less than the second depth D2, and the third ion implantation region 18' is very close to the active surface 101. The patterned photoresist layer 16 is then removed and a high temperature treatment process is performed, such as Figure 1D As shown, the first ion implantation region 12 ′ forms the first stop layer 12 , the second ion implantation region 14 ′ forms the second stop layer 14 , and the third ion implantation region 18 ′ forms the patterned stop layer 18 .

[0027] Among them, the first ion implantation 12a is, for example, nitrogen ion implantation, and the first stop layer 12 is, for example, a silicon nitride (Si3N4) layer; the second ion implantation 14a is, for example, oxygen ion implantation, and the second stop layer 14 is, for example, a silicon dioxide (SiO2) layer; the third ion implantation 18a is, for example, nitrogen ion implantation, and the material of the patterned stop layer 18 is silicon nitride.

[0028] Continuing the above description, an active layer 22 is provided on the active surface 101, such as Figure 1E As shown, the active layer 22 includes a transistor element 24 and an interconnect layer 26. The interconnect layer 26 covers the transistor element 24. The transistor element 24 includes a contact portion 241. In one embodiment, the transistor element 24 includes a source 242, a gate 243, and a drain 244. The gate 243 is located between the source 243 and the drain 244. The contact portion 241 of the transistor element 24 is disposed on at least one of the source 242 and the drain 244. Figure 1E In the embodiment shown, the transistor element 24 is horizontally arranged on the active surface 101. The source 242 and the drain 244 of the transistor element 24 are both in contact with the active surface 101. The portions of the source 242 and the drain 244 in contact with the active surface 101 serve as the contact portion 241 of the transistor element 24. Figure 1E As shown, each contact portion 241 corresponds to each stop portion 181 .

[0029] Then, a thinning process is performed to remove the second portion 104 of the substrate and the stop layer structure 20, so that the first portion 103 of the substrate is exposed at the bottom surface 105. Figure 1F As shown, the bottom surface 105 is located on the opposite side of the active surface 101. In one embodiment, the thinning process includes first performing a backside polishing process to polish the backside 102 of the semiconductor substrate 10 to remove a portion of the second substrate portion 104, leaving a very thin thickness of the second substrate portion 104; then performing a first removal step to remove the remaining second substrate portion 104; performing a second removal step to remove the first stop layer 12; and performing a third removal step to remove the second stop layer 14. The first removal step, the second removal step, and the third removal step are selected from one of chemical mechanical polishing (CMP) and wet etching.

[0030] Specifically, when the material of the first stop layer 12 is silicon nitride and the material of the second stop layer 14 is silicon oxide, the first removal step is a first chemical mechanical polishing process, wherein the selectivity of silicon and silicon nitride is, for example, 20, that is, Si / Si3N4 is 20; the second removal step is to remove the first stop layer 12 by a second chemical mechanical polishing process to reveal the second stop layer 14, wherein the selectivity of silicon nitride and silicon dioxide is, for example, 10, that is, Si3N4 / SiO2 is 10; the third removal step is to remove the second stop layer 14 by a third chemical mechanical polishing process to reveal the bottom surface 105 of the first portion 103 of the substrate, wherein the selectivity of silicon dioxide and silicon is, for example, 5, that is, SiO2 / Si is 5.

[0031] Then, if Figure 1G As shown, a first patterned mask layer 28 is formed on the bottom surface 105. The first patterned mask layer 28 includes a plurality of first patterned openings 281. The first patterned openings 281 correspond to the stop portions 181. In one embodiment, the first patterned mask layer 28 is, for example, a patterned photoresist layer. Subsequently, a plurality of grooves 30 (shown in the following figure) are formed on the first portion 103 of the substrate corresponding to the first patterned openings 281. Figure 1J ), each groove 30 includes two opposite side walls 301 and a through opening end 302, through which the contact portion 241 of the transistor element 24 is exposed, for example, the contact portion 241 of the source 242 and the drain 244 is exposed.

[0032] In one embodiment, the steps of forming the slot 30 are as follows: Figures 1H to 1J As shown, the first patterned mask layer 28 is used as a mask to remove part of the first portion 103 of the substrate to form a plurality of grooves 30a, as shown in FIG. Figure 1HAs shown, the stop portion 181 serves as an etching stop layer. In one embodiment, a plasma etching process is used to remove a portion of the first substrate portion 103 to form a groove 30a. Next, the first patterned mask layer 28 is used as a mask to remove a portion of the stop portion 181 exposed through the groove 30a. Figure 1I As shown, a through groove 30b is formed in the stop portion 181. In one embodiment, a liner removal process is used to remove a portion of the stop portion 181 to form the through groove 30b. Then, the first patterned mask layer 28 is used as a mask to remove the portion of the first substrate portion 103 exposed through each through groove 30b. Figure 1J As shown, to form the through opening 302, in one embodiment, a dry etching process is used to remove the portion of the first substrate portion 103 exposed by the through groove 30b. Thereafter, the first patterned mask layer 28 is removed. In one embodiment, the patterned mask layer 28 is removed by an ash process.

[0033] Afterwards, a protective layer 32 is formed (shown in the subsequent Figure 1M ) to cover the bottom surface 105 of the first portion 103 of the substrate and the two sidewalls 301 of each groove 30, wherein the protective layer 32 does not cover the contact portion 241, and the contact portion 241 is still exposed through the groove 30. In one embodiment, the steps of forming the protective layer 32 are as follows: Figure 1M First, a dielectric film 32' is formed conformally, as shown in FIG. Figure 1K As shown, the dielectric film 32' covers the bottom surface 105 of the first portion 103 of the substrate, the two side walls 301 of each slot 30 and the through opening end 302 (marked at Figure 1J ) exposed contact portion 241, in one embodiment, a dielectric film 32' is formed by a plasma assisted atomic layer deposition (PEALD) process. Figure 1L As shown, a second patterned mask layer 34 is formed to cover the dielectric film 32'. The second patterned mask layer 34 includes a plurality of second patterned openings 341. Each second patterned opening 341 corresponds to a portion of the dielectric film 32' that contacts the contact portion 241. Figure 1M As shown, the portion of the dielectric film 32 ′ exposed through the second patterned opening 341 is removed to expose the contact portion 241 . In one embodiment, the portion of the dielectric film 32 ′ is removed by a dry etching process. Thereafter, the second patterned mask layer 34 is further removed.

[0034] Then, a conductive layer 36 is formed to cover the contact portion 241 exposed by each groove 30. In one embodiment, the steps of forming the conductive layer 36 are as follows: Figure 1N and Figure 1O First, a metal film 38 is formed conformally, as shown in FIG. Figure 1NAs shown, the metal film 38 covers the protective layer 32 and passes through the opening end 302 (marked at Figure 1J ) The contact portion 241 is exposed. In one embodiment, the metal film 38 is formed by a metal sputtering deposition process. Suitable metal films 38 include titanium (Ti), tantalum (Ta), nickel (Ni), cobalt (Co), or tungsten (W). Next, the metal film 38 is subjected to an annealing process to induce silicide between the metal film 38 and the contact portion 241 to form a silicide layer. The material of the silicide layer is, for example, titanium silicide (TiSi), titanium silicon nitride (TiSiN), tantalum silicide (TaSi), tungsten silicide (WSi), cobalt silicide (CoSi), or nickel silicide (NiSi); Figure 1O As shown, a portion of the silicide layer on the protection layer 32 is removed, and another portion of the silicide layer in contact with the contact portion 241 is left as the conductive layer 36 .

[0035] Afterwards, if Figure 1P As shown, an electroplating seed layer 40 is formed to conformally cover the protective layer 32 and the conductive layer 36. In one embodiment, the electroplating seed layer 40 is formed by sputtering, for example. Figure 1Q As shown, the electroplating process forms an electroplating layer 42 to cover the electroplating seed layer 40 and fill the groove 30 (marked at Figure 1P ); thereafter, removing the portion of the electroplating layer 42 and the portion of the electroplating seed layer 40 located outside each slot 30, such as Figure 1R As shown, only the electroplating layer 42 and the electroplating seed layer 40 filling the groove 30 are left, and the electroplating layer 42 filling the groove 30 is used as a power connection structure 44. The power connection structure 44 corresponds to the source 242 and / or the drain 244 of the transistor element 24. In one embodiment, the height of the power connection structure 44 is approximately between 50 nanometers and 200 nanometers.

[0036] Continuing with the above description, if Figure 1R As shown, a semiconductor structure 100 with a power connection structure under a transistor according to an embodiment of the present invention includes a substrate (i.e., a first portion 103 of the substrate), an active layer 22, a stop portion 181', a protective layer 32, a conductive layer 36, an electroplating seed layer 40, and a power connection structure 44. The active layer 22 is disposed on the active surface 101. The active layer 22 includes a transistor element 24 and an interconnect layer 26. The interconnect layer 26 covers the transistor element 24. The transistor element 24 includes a source 242, a gate 243, and a drain 244. The gate 243 is located between the source 242 and the drain 244. A groove 30 (marked at Figure 1J ), the slot 30 has two side walls 301 and a through-opening end 302 (marked at Figure 1J), exposing the contact portion 241 of the source 242 and / or drain 244 of the transistor element 24 through the through-opening end 302. The stop portion 181' is embedded in the sidewalls 301 of the trench 30 and adjacent to the through-opening end 302. A protective layer 32 is disposed on the sidewalls 301 and bottom surface 105 of the trench 30; a conductive layer 36 is disposed on the contact portion 241 exposed through the through-opening end 302; an electroplating seed layer 40 conformally covers the protective layer 32 and conductive layer 36 on the sidewalls 301; and a power connection structure 44 fills each trench 30.

[0037] Figure 2 FIG. 1 is a schematic diagram of an application of a semiconductor structure having a power supply connection structure under a transistor according to an embodiment of the present invention. Figure 2 As shown, a redistribution layer 46 is provided on the active layer 22. For example, metal wiring, metal pillars (VIAs) and microbumps are formed on the redistribution layer. The gate 243 of the transistor element 24 is electrically connected to the redistribution layer 46 by, for example, a conductive contact 48. An interconnect layer 50 is further provided below the substrate (i.e., the first portion 103 of the substrate), and the power connection structure 44 protrudes from the groove 30 (marked at Figure 1J ) and penetrates the interconnect layer 50. In an embodiment not shown, another redistribution layer may be provided below the interconnect layer 50, and a solder ball, for example, may be provided on a side of the redistribution layer away from the interconnect layer 50 to electrically connect the power connection structure 44 and the solder ball using the redistribution layer.

[0038] Figure 3 FIG. 1 is another application diagram of a semiconductor structure having a power supply connection structure under a transistor according to an embodiment of the present invention. Figure 3As shown, the semiconductor structure with a power connection structure under the transistor is used in an inverter, wherein a P-type transistor (PMOS) 24P and an N-type transistor (NMOS) 24N are provided on the active layer 22, and a power connection structure 44P is contacted below the source 242P of the P-type transistor 24P to be coupled to the voltage source Vdd, and a power connection structure 44N is contacted below the source 242N of the N-type transistor 24N to be coupled to the ground terminal Vss. A redistribution layer 46 is further provided on the active layer 22, wherein conductive contacts 48' are respectively formed between the gate 243P of the P-type transistor 24P and the gate 243N of the N-type transistor 24N and the redistribution layer 46, and the conductive contacts 48' electrically connect the gates 243P / 243N and the redistribution layer 46, so as to electrically connect the gate 243P of the P-type transistor 24P and the gate 243N of the N-type transistor 24N to the redistribution layer 46. Input voltage terminal Vin; conductive contacts 48" are also formed between the drain 244P of the P-type transistor 24P and the drain 244N of the N-type transistor 24N and the redistribution layer 46, respectively. The conductive contacts 48" are electrically connected to the drain 244P / 244N and the redistribution layer 46, so as to electrically connect the drain 244P of the P-type transistor 24P and the drain 244N of the N-type transistor 24N to the input voltage terminal Vout through the redistribution layer 46.

[0039] Figure 4 FIG. 1 is another application diagram of a semiconductor structure having a power supply connection structure under a transistor according to an embodiment of the present invention. Figure 4 As shown, the semiconductor structure with a power connection structure under the transistor is used in an inverter, wherein a P-type vertical transfer field effect transistor 52P (P-type VTFET) and an N-type VTFET 52N are provided on the active surface 101. Figure 4 As shown, the source 521P of the P-type VTFET 52P and the source 521N of the N-type VTFET 52N contact the power connection structure 44P and the power connection structure 44N, respectively, wherein the power connection structure 44P contacting the source 521P of the P-type VTFET 52P is coupled to the voltage source Vdd, and the power connection structure 44N contacting the source 521N of the N-type VTFET 52N is coupled to the ground terminal Vss; the gate 522P of the P-type VTFET 52P and the gate 522N of the N-type VTFET 52N are electrically connected to the input voltage terminal Vin via the conductive contact 48', and the drain 523P of the P-type VTFET 52P and the drain 523N of the N-type VTFET 52N are electrically connected to the voltage terminal Vout via the conductive contact 48".

[0040] In a method for manufacturing a semiconductor structure having a power connection structure beneath a transistor according to an embodiment of the present invention, by forming a stop layer structure at a depth within the semiconductor substrate and subsequently performing a gradual thinning process, the semiconductor substrate can be polished or etched until only the first portion of the substrate remains, i.e., only an extremely thin substrate thickness of 30 to 200 nanometers remains. Furthermore, the power connection structure is directly and longitudinally bonded to the source and / or drain of the transistor element, allowing the transistor element to be powered or grounded via the backside (bottom) of the substrate, thereby alleviating the problem of reduced wiring area. Furthermore, the longitudinal length of the power connection structure can be adjusted based on the thickness of the remaining first portion of the substrate, making the overall process more flexible and improving device performance.

[0041] The above description is merely a preferred embodiment of the present invention and does not constitute any form of limitation to the present invention. Although the present invention has been disclosed as a preferred embodiment, it is not intended to limit the present invention. Any technician familiar with the present profession can make slight changes or modifications to equivalent embodiments of equivalent changes using the methods and technical contents disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. A method for manufacturing a semiconductor structure having a power supply connection structure under a transistor, characterized in that: Include: Providing a semiconductor substrate having an active surface and a back surface opposite to each other; forming a stop layer structure in the semiconductor substrate, dividing the semiconductor substrate into a first substrate portion and a second substrate portion, wherein the first substrate portion is located between the stop layer structure and the active surface, and the second substrate portion is located between the stop layer structure and the back surface; forming a patterned stop layer in the first portion of the substrate and adjacent to the active surface, wherein the patterned stop layer comprises a plurality of stop portions; An active layer is provided on the active surface, the active layer including at least one transistor element and an interconnect layer, the interconnect layer covers the at least one transistor element, the at least one transistor element includes at least one contact portion, the at least one contact portion corresponds to at least one of the stop portions; Performing a thinning process to remove the second portion of the substrate and the stop layer structure, so that the first portion of the substrate exposes a bottom surface located on the opposite side of the active surface; forming a first patterned mask layer on the bottom surface, wherein the first patterned mask layer comprises a plurality of first patterned openings, wherein the first patterned openings respectively correspond to the stop portions; Corresponding to the first patterned openings, a plurality of grooves are formed in the first portion of the substrate, the grooves penetrating the first portion of the substrate, each of the grooves including opposite sidewalls and a through-opening end, the at least one contact portion of the at least one transistor element of the active layer being exposed through the through-opening end; forming a protective layer to cover the bottom surface of the first portion of the substrate and the two side walls of each of the grooves; forming a conductive layer to cover the at least one contact portion exposed by each of the grooves; forming an electroplating seed layer to cover the protective layer and the conductive layer; and A plurality of power connection structures are formed and located on the electroplating seed layer in the grooves respectively, wherein the power connection structures fill up the grooves respectively.

2. The method for manufacturing a semiconductor structure having a power supply connection structure under a transistor according to claim 1, wherein: The at least one transistor element includes a source, a gate and a drain. The gate is located between the source and the drain. The at least one contact portion of the transistor element is disposed on at least one of the source and the drain.

3. The method for manufacturing a semiconductor structure having a power supply connection structure under a transistor according to claim 1, wherein: The stop layer structure includes a first stop layer and a second stop layer stacked on each other. The material of the first stop layer is different from that of the second stop layer. The second stop layer is located between the first stop layer and the active surface.

4. The method for manufacturing a semiconductor structure having a power supply connection structure under a transistor according to claim 3, wherein: The method for forming the patterned stop layer and the stop layer structure includes: Performing a first ion implantation from the active surface of the semiconductor substrate to a first depth of the semiconductor substrate; Performing a second ion implantation from the active surface of the semiconductor substrate to a second depth of the semiconductor substrate, wherein the second depth is smaller than the first depth; forming a patterned photoresist layer on the active surface, and performing a third ion implantation on a third depth of the semiconductor substrate using the patterned photoresist layer as a mask, wherein the third depth is smaller than the second depth; as well as The patterned photoresist layer is removed and a high temperature treatment process is performed to form the first stop layer in the first ion implantation area, the second stop layer in the second ion implantation area, and the patterned stop layer in the third ion implantation area.

5. The method for manufacturing a semiconductor structure having a power supply connection structure under a transistor according to claim 3, wherein: The material of the first stop layer is silicon nitride, the material of the second stop layer is silicon dioxide layer, and the material of the patterned stop layer is silicon nitride.

6. The method for manufacturing a semiconductor structure having a power supply connection structure under a transistor according to claim 3, wherein: The thickness of the semiconductor substrate is between 700 micrometers and 800 micrometers, the distance between the stop layer structure and the active surface is between 30 nanometers and 200 nanometers, and the distance between the patterned stop layer and the active surface is between 5 nanometers and 20 nanometers.

7. The method for manufacturing a semiconductor structure having a power supply connection structure under a transistor according to claim 3, wherein: The steps of performing the thinning process include: performing a backside polishing process to polish the backside of the semiconductor substrate to remove a portion of the second portion of the substrate; a first removing step of removing the remaining second portion of the substrate; a second removing step of removing the first stop layer; as well as A third removing step is performed to remove the second stop layer, wherein the first removing step, the second removing step and the third removing step are selected from one of chemical mechanical polishing and wet etching.

8. The method for manufacturing a semiconductor structure having a power supply connection structure under a transistor according to claim 1, wherein: The step of forming the grooves in the first portion of the substrate comprises: Using the first patterned mask layer as a mask, partially remove the first portion of the substrate to form a plurality of grooves, wherein the stop portions serve as an etching stop layer; Using the first patterned mask layer as a mask, removing a portion of each of the stop portions exposed through the grooves to form a through groove in each of the stop portions; Using the first patterned mask layer as a mask, removing a portion of the first portion of the substrate exposed through each through-groove to form the through-opening end; and The first patterned mask layer is removed.

9. The method for manufacturing a semiconductor structure having a power supply connection structure under a transistor according to claim 8, wherein: A plasma etching process is used to remove a portion of the first portion of the substrate to form the grooves, a liner removal process is used to remove a portion of each of the stop portions to form the through slots, and a dry etching process is used to remove a portion of the first portion of the substrate exposed through the through slots.

10. The method for manufacturing a semiconductor structure having a power connection structure under a transistor according to claim 1, wherein: The steps of forming the protective layer include: Conformally forming a dielectric film to cover the bottom surface of the first portion of the substrate, the two sidewalls of each of the grooves, and the at least one contact portion exposed through the through-opening end; forming a second patterned mask layer covering the dielectric film, wherein the second patterned mask layer comprises a plurality of second patterned openings, each of the second patterned openings corresponding to a portion of the dielectric film in contact with the at least one contact portion; removing the portion of the dielectric film exposed through the second patterned openings to expose the at least one contact portion; and The second patterned mask layer is removed.

11. The method for manufacturing a semiconductor structure having a power supply connection structure under a transistor according to claim 1, wherein: The steps of forming the conductive layer include: Conformally forming a metal film to cover the protection layer and the at least one contact portion exposed through each of the grooves; performing an annealing process on the metal film to convert the metal film into a silicide layer; as well as A portion of the silicide layer located on the protection layer is removed, and another portion of the silicide layer in contact with the at least one contact portion is left as the conductive layer.

12. The method for manufacturing a semiconductor structure having a power connection structure under a transistor according to claim 1, wherein: The steps of forming the power connection structure include: Electroplating an electroplating layer to cover the electroplating seed layer, and the electroplating layer at least fills each of the grooves; and A portion of the electroplating layer and a portion of the electroplating seed layer located outside each of the grooves are removed, wherein the portion of the electroplating layer filled in each of the grooves serves as the power connection structure.

13. A semiconductor structure having a power connection structure under a transistor, characterized in that: Include: A substrate having an active surface and a bottom surface, wherein the bottom surface is formed with at least one slot extending through the active surface, the at least one slot including two opposite side walls and a through opening; an active layer disposed on the active surface, the active layer including at least one transistor element and an interconnect layer, the interconnect layer covering the at least one transistor element, the at least one transistor element including at least one contact portion, the at least one contact portion being exposed through the through-opening end; A plurality of stop portions are respectively embedded in the two side walls of the at least one slot and adjacent to the through opening end; a protective layer conformally disposed on the two side walls and the bottom surface; At least one conductive layer is disposed on the at least one contact portion exposed through the through opening end; an electroplating seed layer conformally covering portions of the protection layer and the at least one conductive layer located on the two side walls; and At least one power connection structure is filled in the at least one slot.

14. The semiconductor structure with a power connection structure under the transistor according to claim 13, wherein: The distance between the stop portions and the active surface is between 5 nanometers and 20 nanometers, and the material of the stop portions is silicon nitride.

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