Semiconductor Capacitor Array Layout

Abstract

A semiconductor capacitor array layout includes a first conductive structure and a second conductive structure. The first conductive structure includes: a plurality of longitudinal first conductive bars located in a first integrated circuit layer; a plurality of transverse first conductive bars located in a second integrated circuit layer and coupled to the plurality of longitudinal first conductive bars via vias, and together with the plurality of longitudinal first conductive bars forming a plurality of well-shaped structures. The plurality of well-shaped structures include an outer well and an inner well, and the outer well and the inner well are not electrically connected. The second conductive structure includes: a plurality of second conductors located in the first integrated circuit layer and located in the plurality of well-shaped structures. The plurality of second conductors include an outer second conductor and an inner second conductor, respectively located in the outer well and the inner well. The outer second conductor and the inner second conductor are not electrically connected. The outer well and the outer second conductor together serve as a dummy capacitor unit.

Description

Technical Field

[0001] The present invention relates to the layout of a semiconductor capacitor array, and more particularly to the layout of a semiconductor capacitor array with a dummy capacitor structure. Background Art

[0002] Generally, a semiconductor integrated circuit is usually a multi-layer structure. A conventional semiconductor capacitor array is usually located in a single metal layer of the multi-layer structure. The semiconductor capacitor array usually includes multiple parallel rows of capacitor units, including an adjacent first row of capacitor units and a second row of capacitor units. To avoid the parasitic capacitance formed jointly by the upper electrodes (lower electrodes) of the first row of capacitor units and the lower electrodes (upper electrodes) of the second row of capacitor units, resulting in inaccurate capacitance values (where the upper electrodes (lower electrodes) of the first row of capacitor units are parallel to the traces, so their corresponding areas are relatively large), the spacing between the first row of capacitor units and the second row of capacitor units needs to be increased, but this will waste circuit area.

[0003] In addition, the design of the capacitor units of some semiconductor capacitor arrays is as Figure 1a shown, where the upper electrode 110 is a U-shaped structure (including a longitudinal structure and a transverse structure), and the lower electrode 120 is a strip-shaped structure. Compared with general mature processes, in some advanced processes (such as: FinFET process), the ratio (W / L) of the width "W" of the transverse part to the length "L" of the longitudinal part of the U-shaped structure will be larger to meet the specifications of the advanced process, as Figure 1b shown. Since a semiconductor capacitor array usually includes a large number of capacitor units, if the ratio (W / L) of the U-shaped structures of these capacitor units is enlarged, overall, the semiconductor capacitor array will consume a large amount of additional circuit area. Note that Figure 1a and Figure 1b are used to show the ratio change of the U-shaped structure, rather than the actual size of the U-shaped structure.

[0004] In addition, a semiconductor capacitor array usually includes multiple groups of capacitors, which can be used to implement a capacitive digital-to-analog converter (CDAC). When manufacturing an integrated circuit (especially through an advanced process), the matching of multiple groups of capacitors of the CDAC is related to the uniformity of the layout density of the multiple groups of capacitors and their surrounding components. Generally speaking, the better the uniformity of the layout density, the better the matching. Therefore, dummy capacitors are usually arranged around multiple groups of capacitors of the CDAC to ensure that the circuit density at the edge of the layout of the multiple groups of capacitors is the same as / approximate to the circuit density inside the layout of the multiple groups of capacitors. Summary of the Invention

[0005] One object of the present disclosure is to provide a semiconductor capacitor array layout with a dummy capacitor structure to avoid the problems of the prior art.

[0006] An embodiment of the semiconductor capacitor array layout of the present disclosure includes a first conductive structure and a second conductive structure. The first conductive structure includes M longitudinal first conductive bars and N transverse first conductive bars, where M is an integer greater than 2 and N is an integer greater than 1. The M longitudinal first conductive bars are located in a first integrated circuit layer; the N transverse first conductive bars are located in a second integrated circuit layer and together with the M longitudinal first conductive bars form [(M - 1)×(N - 1)] well-shaped structures. The [(M - 1)×(N - 1)] well-shaped structures include (N - 1) outer wells and {[(M - 2)×(N - 1)]} inner wells; the outer wells and the {[(M - 2)×(N - 1)]} inner wells are not electrically connected. The second conductive structure includes [(M - 1)×(N - 1)] second conductors. The [(M - 1)×(N - 1)] second conductors are located in the first integrated circuit layer and are respectively located in the [(M - 1)×(N - 1)] well-shaped structures. The [(M - 1)×(N - 1)] second conductors include (N - 1) outer second conductors and {[(M - 2)×(N - 1)]} inner second conductors; the (N - 1) outer second conductors are respectively located in the (N - 1) outer wells; the {[(M - 2)×(N - 1)]} inner second conductors are respectively located in the {[(M - 2)×(N - 1)]} inner wells; the (N - 1) outer second conductors and the {[(M - 2)×(N - 1)]} inner second conductors are not electrically connected. The (N - 1) outer wells and the (N - 1) outer second conductors together serve as at least a part of the dummy capacitor structure, which is located at the periphery of the semiconductor capacitor array layout.

[0007] Another embodiment of the semiconductor capacitor array layout of the present disclosure includes a first conductive structure and a second conductive structure. The first conductive structure includes M longitudinal first conductive bars and N transverse first conductive bars, where M is an integer greater than 1 and N is an integer greater than 1. The M longitudinal first conductive bars are located in a first integrated circuit layer; the N transverse first conductive bars are located in a second integrated circuit layer. Each of the N transverse first conductive bars includes an outer portion and an inner portion that are not electrically connected. The N transverse first conductive bars collectively include N outer portions and N inner portions. Among them, the N inner portions are coupled to the M longitudinal first conductive bars via a plurality of first vias. The N outer portions are located at the periphery of the semiconductor capacitor array layout and collectively serve as at least a part of the dummy capacitor structure. The second conductive structure includes (M - 1) longitudinal second conductive bars and (N - 1) transverse second conductive bars. The (M - 1) longitudinal second conductive bars are located in the first integrated circuit layer; the (N - 1) transverse second conductive bars are located in the second integrated circuit layer; the (N - 1) transverse second conductive bars are coupled to the (M - 1) longitudinal second conductive bars via a plurality of second vias. The M longitudinal first conductive bars and the (M - 1) longitudinal second conductive bars are alternately arranged in the first integrated circuit layer; the N transverse first conductive bars and the (N - 1) transverse second conductive bars are alternately arranged in the second integrated circuit layer.

[0008] Another embodiment of the semiconductor capacitor array layout of the present disclosure includes a main capacitor structure and a dummy capacitor structure. The main capacitor structure includes a first conductive structure and a second conductive structure. The first conductive structure includes a plurality of longitudinal first conductive bars and a plurality of transverse first conductive bars, and the plurality of longitudinal first conductive bars are coupled to the plurality of longitudinal first conductive bars via a plurality of first vias. The second conductive structure includes a plurality of longitudinal second conductive bars and a plurality of transverse second conductive bars, and the plurality of transverse second conductive bars are coupled to the plurality of longitudinal second conductive bars via a plurality of second vias. The plurality of longitudinal first conductive bars and the plurality of longitudinal second conductive bars are alternately arranged in a first integrated circuit layer, and the plurality of transverse first conductive bars and the plurality of transverse second conductive bars are alternately arranged in a second integrated circuit layer. The dummy capacitor structure is located at least on one outer side of the main capacitor structure and at the periphery of the semiconductor capacitor array layout, and includes a third conductive structure and a fourth conductive structure. The third conductive structure includes a plurality of longitudinal third conductive bars and a plurality of transverse third conductive bars. The fourth conductive structure includes a plurality of longitudinal fourth conductive bars and a plurality of transverse fourth conductive bars. The plurality of longitudinal third conductive bars and the plurality of longitudinal fourth conductive bars are alternately arranged in the first integrated circuit layer, and the plurality of transverse third conductive bars and the plurality of transverse fourth conductive bars are alternately arranged in the second integrated circuit layer.

[0009] The features, actual operations, and effects of the present invention will be described in detail with reference to the accompanying drawings in the preferred embodiments as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1a Showing the design of a capacitor unit of the prior art;

[0011] Figure 1b Showing Figure 1a a variation of the design of the capacitor unit to meet the specifications of advanced processes;

[0012] Figure 2a Showing an embodiment of the semiconductor capacitor array layout of the present invention;

[0013] Figure 2b Showing Figure 2a a variation of the semiconductor capacitor array layout;

[0014] Figure 2c Showing Figure 2a another variation of the semiconductor capacitor array layout;

[0015] Figure 3 Showing another embodiment of the semiconductor capacitor array layout of the present invention; and

[0016] Figure 4 Showing another embodiment of the semiconductor capacitor array layout of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0017] The semiconductor capacitor array layout with a dummy capacitor structure according to the present disclosure can not only reduce the parasitic capacitance problem of the prior art but also avoid the problems brought by the U-shaped structure of the prior art in advanced processes.

[0018] Figure 2a Showing an embodiment of the semiconductor capacitor array layout of the present disclosure. Figure 2a The semiconductor capacitor array layout 200 of includes a first conductive structure and a second conductive structure. The first conductive structure includes M longitudinal first conductive bars 210 (i.e., Figure 2a the slanted longitudinal long bars in ) and N discontinuous transverse first conductive bars 220 (i.e., Figure 2a the discontinuous gray transverse long bars in ), where M is an integer greater than 2 and N is an integer greater than 1. The M longitudinal first conductive bars 210 are located in a first integrated circuit layer; the N transverse first conductive bars 220 are located in a second integrated circuit layer; the N transverse first conductive bars 220 are connected via a plurality of first vias (e.g., Figure 2aThe light gray square coupled to the gray horizontal long strip in [Figure] couples to the M longitudinal first conductive strips 210 and together with the M longitudinal first conductive strips 210 forms [(M - 1)×(N - 1)] well-shaped structures. The [(M - 1)×(N - 1)] well-shaped structures include (N - 1) outer wells and {[(M - 2)×(N - 1)]} inner wells; the (N - 1) outer wells are within the combination of a first layout region 202 and its vertical projection region (e.g., the region directly above the first layout region 202), the {[(M - 2)×(N - 1)]} inner wells are within the combination of a second layout region 204 and its vertical projection region (e.g., the region directly above the second layout region 204), the two layout regions are adjacent, but the (N - 1) outer wells and the {[(M - 2)×(N - 1)]} inner wells are not electrically connected. It should be noted that the first integrated circuit layer and the second integrated circuit layer are a first metal layer and a second metal layer respectively, and there is no other metal layer between the first metal layer and the second metal layer; however, this is not a limitation of the implementation of the present invention. Additionally, it should be noted that the first vias used to couple the longitudinal first conductive strips 210 and the horizontal first conductive strips 220 in the first layout region 202 and its vertical projection region can be omitted; furthermore, as long as the purpose of electrical connection can be satisfied, the number of vias can be determined according to implementation requirements.

[0019] Please refer to Figure 2a . The second conductive structure includes [(M - 1)×(N - 1)] second conductors (i.e., Figure 2a the black longitudinal long strip, the longitudinal long strip with dots, and the longitudinal long strip with grids in [Figure]), and the shape of each second conductor (e.g., a single long / horizontal strip, a combination of multiple long / horizontal strips, a combination of at least one long strip and at least one horizontal strip, or a square) can be determined according to implementation requirements. The [(M - 1)×(N - 1)] second conductors are located in the first integrated circuit layer and are respectively located in the [(M - 1)×(N - 1)] well-shaped structures. The [(M - 1)×(N - 1)] second conductors include (N - 1) outer second conductors 232 (e.g., Figure 2a the black longitudinal long strip in [Figure]) and {[(M - 2)×(N - 1)]} inner second conductors 234, 236 (e.g., Figure 2aThe longitudinal strips with dots and grids). The (N - 1) outer second conductors 232 are located in the (N - 1) outer wells and also within the first layout region 202. The {[(M - 2)×(N - 1)]} inner second conductors 234, 236 are located in the {[(M - 2)×(N - 1)]} inner wells and also within the second layout region 204; each inner second conductor 234 / 236 and the inner well surrounding the inner second conductor 234 / 236 are electrically isolated (e.g., isolated by an oxide (not shown in the figure)), and together form a capacitor unit of the semiconductor capacitor array layout 200. The (N - 1) outer second conductors 232 are not electrically connected to the {[(M - 2)×(N - 1)]} inner second conductors 234, 236. The (N - 1) outer wells and the (N - 1) outer second conductors 232 together serve as at least a part of a dummy capacitor structure, which is located at the periphery of the semiconductor capacitor array layout 200 to increase the uniformity of the layout density of the semiconductor capacitor array layout 200.

[0020] It should be noted that the semiconductor capacitor array layout 200 may further include other outer wells and second conductors located therein as other parts of the dummy capacitor structure, and these other outer wells are also located at the periphery of the semiconductor capacitor array layout 200. For example, as Figure 2b shown, these other outer wells are located on the other three sides of the layout region 204 of Figure 2a to surround the {[(M - 2)×(N - 1)]} inner wells. Additionally, according to implementation requirements, the peripheral contour of the {[(M - 2)×(N - 1)]} inner wells can be rectangular or other polygons. Since those skilled in the art can derive the implementation and variations of the above technical features based on the present disclosure, repeated and redundant descriptions are omitted here. Furthermore, to ensure the reliability of electrical connections or other implementation requirements, at the boundary near the second layout region 204, the longitudinal first conductive strip 210 and the transverse first conductive strip 220 can protrude as Figure 2c shown.

[0021] Please refer to Figure 2a . The {[(M - 2)×(N - 1)]} inner wells are used for the transmission of a first voltage. The {[(M - 2)×(N - 1)]} inner second conductors are used for the transmission of a second voltage, and the second voltage is different from the first voltage. K of the {[(M - 2)×(N - 1)]} inner second conductors 234, 236 (e.g., Figure 2aThe longitudinal strip with dots in the middle belongs to a first capacitor group among the P capacitor groups; P is a positive integer, and K is a positive integer not greater than {[(M - 2)×(N - 1)]}; in short, all the capacitor units belonging to the same capacitor group can be regarded as a larger capacitor as a whole. Those with ordinary knowledge in the art can deduce from the present disclosure the situation where the P capacitor groups include more capacitor groups; for example, L of the second conductors 236 among the {[(M - 2)×(N - 1)]} inner second conductors 234 and 236 (such as: Figure 2a The longitudinal strip with a grid in the middle belongs to a second capacitor group among the P capacitor groups. At this time, [(M - 2)×(N - 1)] is an integer greater than 1, P is an integer greater than 1, K is a positive integer not greater than {[(M - 2)×(N - 1)] - 1}, and L is a positive integer not greater than {[(M - 2)×(N - 1)] - K}.

[0022] It should be noted that according to the implementation requirements, the semiconductor capacitor array layout 200 may further include a plurality of capacitor group power supply bars (not shown in the figure), which are located in the second integrated circuit layer, the first integrated circuit layer, or a third integrated circuit layer (such as a metal layer), and serve as the voltage transmission path for the {[(M - 2)×(N - 1)]} inner second conductors 234 and 236. For example, the plurality of capacitor group power supply bars include a first capacitor group power supply bar and a second capacitor group power supply bar. The first capacitor group power supply bar is coupled to the aforementioned K second conductors 234, and the second capacitor group power supply bar is coupled to the aforementioned L second conductors 236; since the means of coupling the power supply bar and the conductor are common techniques in the art, the details are omitted here. In addition, the (N - 1) outer second conductors 232 can be electrically coupled together, and / or the (N - 1) outer wells and the (N - 1) outer second conductors 232 can be electrically coupled together; however, this is not a limitation of the implementation of the present invention.

[0023] It should be noted that Figure 2a The conductive bars and conductors in the second layout area 204 of can all be longitudinal conductive bars to facilitate compliance with the process specifications; however, this is not a limitation of the implementation of the present invention. More specifically, when there are only longitudinal conductive bars and no transverse conductive bars in the second layout area 204, the manufacturing process of the capacitor units in the layout area 204 can meet the specifications of an advanced process (such as a fin field-effect transistor (FinFET) process) without wasting circuit area; for example, the FinFET process specifications require Figure 1b The aspect ratio (W / L) of the U-shaped structure of is greater than Figure 1a The aspect ratio of the U-shaped structure of, and the capacitor units in the layout area 204 do not adopt the U-shaped structure, so there is no need to waste circuit area to meet the process specifications.

[0024] Figure 3Shows another embodiment of the semiconductor capacitor array layout of the present disclosure. Figure 3 The semiconductor capacitor array layout 300 includes a first conductive structure and a second conductive structure. The first conductive structure includes M longitudinal first conductive bars 310 (i.e., Figure 3 the slanted longitudinal long bars in ) and N discontinuous transverse first conductive bars (i.e., Figure 3 the combination of N black transverse long bars 322 and N gray transverse long bars 324 in ). The M longitudinal first conductive bars 310 are located in a first integrated circuit layer (e.g., a metal layer); the N discontinuous transverse first conductive bars are located in a second integrated circuit layer (e.g., another metal layer). Each of the N discontinuous transverse first conductive bars includes an outer portion 322 (i.e., Figure 3 the black transverse long bar in ) that is electrically unconnected and an inner portion 324 (i.e., Figure 3 the gray transverse long bar in ). Thus, the N discontinuous transverse first conductive bars include N outer portions 322 and N inner portions 324. The N inner portions 324 are coupled to the M longitudinal first conductive bars 310 via a plurality of first vias (e.g., Figure 3 the light gray squares coupled to the gray transverse long bars in ). The N outer portions 322 are located at the periphery of the semiconductor capacitor array layout 300 and together serve as at least a part of a dummy capacitor structure to increase the uniformity of the layout density of the semiconductor capacitor array layout 300.

[0025] Please refer to Figure 3 . The second conductive structure includes (M - 1) longitudinal second conductive bars 330 (e.g., Figure 3 the dotted longitudinal long bars in ) and (N - 1) transverse second conductive bars 340 (e.g., Figure 3 the white transverse long bars in ). The (M - 1) longitudinal second conductive bars 330 are located in the first integrated circuit layer; the (N - 1) transverse second conductive bars 340 are located in the second integrated circuit layer. The (N - 1) transverse second conductive bars 340 are coupled via a plurality of second vias (e.g., Figure 3The black squares (coupled to the white horizontal strips) are coupled to the (M - 1) longitudinal second conductive strips 330. The M longitudinal first conductive strips 310 and the (M - 1) longitudinal second conductive strips 330 are alternately arranged in the first integrated circuit layer; thus, a longitudinal second (first) conductive strip is provided between two adjacent longitudinal first (second) conductive strips. The N inner portions 324 and the (N - 1) transverse second conductive strips 340 are alternately arranged in the second integrated circuit layer; thus, a transverse second conductive strip (inner portion) is provided between two adjacent inner portions (transverse second conductive strips). In this embodiment, the N inner portions 324 are used for the transmission of a first voltage, and the (N - 1) transverse second conductive strips 340 are used for the transmission of a second voltage, and the first voltage is different from the second voltage.

[0026] Figure 4 Another embodiment of the semiconductor capacitor array layout of the present disclosure is shown. Figure 4 The semiconductor capacitor array layout 400 includes a main capacitor structure 402 and a dummy capacitor structure 404. The main capacitor structure 402 includes a first conductive structure and a second conductive structure. The dummy capacitor structure 404 includes a third conductive structure and a fourth conductive structure.

[0027] Please refer to Figure 4 . The first conductive structure includes a plurality of longitudinal first conductive strips 412 (i.e., Figure 4 the longitudinal strips with slashes in Figure 4 ) and a plurality of transverse first conductive strips 414 (i.e., Figure 4 the gray horizontal strips in

[0028] Please refer to Figure 4 . The second conductive structure includes a plurality of longitudinal second conductive strips 422 (i.e., Figure 4 the longitudinal strips with grids in Figure 4 ) and a plurality of transverse second conductive strips 424 (i.e., Figure 4The black square (coupled to the white horizontal strip in []) is coupled to the plurality of longitudinal second conductive strips 422 and is used for the transmission of a second voltage, which is different from the first voltage. The plurality of longitudinal first conductive strips 412 and the plurality of longitudinal second conductive strips 422 are alternately arranged in the first integrated circuit layer. The plurality of horizontal first conductive strips 414 and the plurality of horizontal second conductive strips 424 are alternately arranged in the second integrated circuit layer.

[0029] Please refer to Figure 4 . The third conductive structure includes a plurality of longitudinal third conductive strips 432 (i.e., Figure 4 the slanted longitudinal strip in []) and a plurality of horizontal third conductive strips 434 (i.e., Figure 4 the gray horizontal strip in []). The plurality of horizontal third conductive strips 434 can be coupled to the plurality of longitudinal third conductive strips 432 via a plurality of third vias (e.g., Figure 4 the white square coupled to the gray horizontal strip in []) according to the implementation requirements; however, this is not necessary. The fourth conductive structure includes a plurality of longitudinal fourth conductive strips 442 (i.e., Figure 4 the dotted longitudinal strip in []) and a plurality of horizontal fourth conductive strips 444 (i.e., Figure 4 the light gray horizontal strip in []). The plurality of horizontal fourth conductive strips 444 can be coupled to the plurality of longitudinal fourth conductive strips 442 via a plurality of fourth vias (e.g., Figure 4 the white square coupled to the light gray horizontal strip in []) according to the implementation requirements; however, this is not necessary. The plurality of longitudinal third conductive strips 432 and the plurality of longitudinal fourth conductive strips 442 are alternately arranged in the first integrated circuit layer, and the plurality of horizontal third conductive strips 434 and the plurality of horizontal fourth conductive strips 444 are alternately arranged in the second integrated circuit layer.

[0030] Please refer to Figure 4。The main capacitor structure 402 is electrically unconnected to the dummy capacitor structure 404. The dummy capacitor structure 404 is located at the periphery of the semiconductor capacitor array layout 400 (e.g., one side / multiple sides / around the semiconductor capacitor array layout 400) to increase the uniformity of the layout density of the semiconductor capacitor array layout 400. Additionally, the plurality of longitudinal first conductive bars 412, the plurality of longitudinal second conductive bars 422, the plurality of transverse first conductive bars 414, and the plurality of transverse second conductive bars 424 together form an effective capacitor unit. The effective capacitor unit is the smallest capacitor unit of the semiconductor capacitor array layout 400; however, this is not a limitation of the implementation of the present invention. The plurality of longitudinal third conductive bars 432, the plurality of longitudinal fourth conductive bars 442, the plurality of transverse third conductive bars 434, and the plurality of transverse fourth conductive bars 444 together form a dummy capacitor unit. The dummy capacitor unit and the voltage applied thereto do not form a capacitor as a whole; however, this is not a limitation of the implementation of the present invention. The third conductive structure can be electrically coupled to the fourth conductive structure; however, this is not a limitation of the implementation of the present invention.

[0031] It should be noted that the main capacitor structure 402 may include other effective capacitor units, and the dummy capacitor structure 404 can also include other dummy capacitor units. To avoid Figure 4 the complexity of the drawings, these other effective capacitor units and dummy capacitor units are represented by ellipsis. Since those of ordinary skill in the art can derive the implementation of other effective capacitor units and dummy capacitor units based on the present disclosure, repeated and redundant descriptions are omitted herein. In Figure 4 the embodiment, the conductive bars for the first voltage transmission in all effective capacitor units are electrically coupled together; the conductive bars for the second voltage transmission in all effective capacitor units, if belonging to the same capacitor group, are electrically coupled together, and the capacitor units belonging to the same capacitor group can be regarded as a larger capacitor as a whole.

[0032] Please note that there are no special limitations on the length, width, and thickness of the strip-shaped conductors (e.g., conductive bars, power supply bars) described in this specification and their variations, which are determined according to the implementation requirements, so the shape is not necessarily the traditional strip shape. Also, please note that on the premise that implementation is possible, those of ordinary skill in the art can selectively implement some or all of the technical features in any of the foregoing embodiments, or selectively implement the combination of some or all of the technical features in the foregoing multiple embodiments, thereby increasing the flexibility during the implementation of the present invention.

[0033] In summary, the semiconductor capacitor array layout with a dummy capacitor structure of the present disclosure can not only reduce the parasitic capacitance problem of the prior art but also avoid the problems brought by the U-shaped structure of the prior art in advanced processes.

[0034] Although the embodiments of the present invention are described above, these embodiments are not intended to limit the present invention. Those with ordinary knowledge in the technical field can make changes to the technical features of the present invention based on the explicit or implicit content of the present invention. All such changes may fall within the scope of patent protection sought by the present invention. In other words, the scope of patent protection of the present invention shall be determined by the scope of the claims in this specification.

[0035]

Symbol Explanation

[0036] 110: Upper electrode plate

[0037] 120: Lower electrode plate

[0038] W: Transverse width

[0039] L: Longitudinal length

[0040] 200: Semiconductor capacitor array layout

[0041] 202: First layout area

[0042] 204: Second layout area

[0043] 210: Longitudinal first conductive strip

[0044] 220: Transverse first conductive strip

[0045] 232: Outer second conductor

[0046] 234, 236: Inner second conductors

[0047] 300: Semiconductor capacitor array layout

[0048] 310: First conductive strip

[0049] 322: Outer part of the transverse first conductive strip

[0050] 324: Inner part of the transverse first conductive strip

[0051] 330: Longitudinal second conductive strip

[0052] 340: Transverse second conductive strip

[0053] 400: Semiconductor capacitor array layout

[0054] 402: Main capacitor structure

[0055] 404: dummy capacitor structure

[0056] 412: Longitudinal first conductive strip

[0057] 414: Transverse first conductive strip

[0058] 422: Second longitudinal conductive bar

[0059] 424: Second transverse conductive bar

[0060] 432: Third longitudinal conductive bar

[0061] 434: Third transverse conductive bar

[0062] 442: Fourth longitudinal conductive bar

[0063] 444: Fourth transverse conductive bar.

Claims

1. A semiconductor capacitor array layout with a dummy capacitor structure, the semiconductor capacitor array layout comprising: A first conductive structure, comprising: M longitudinal first conductive bars, located in a first integrated circuit layer, where M is an integer greater than 2; N transverse first conductive bars, located in a second integrated circuit layer, and jointly forming [(M - 1)×(N - 1)] well structures with the M longitudinal first conductive bars. The [(M - 1)×(N - 1)] well structures include (N - 1) outer wells and {[(M - 2)×(N - 1)]} inner wells. The (N - 1) outer wells and the {[(M - 2)×(N - 1)]} inner wells are not electrically connected. Where N is an integer greater than 1; A second conductive structure, comprising: [(M - 1)×(N - 1)] second conductors, located in the first integrated circuit layer, and respectively located in the [(M - 1)×(N - 1)] well structures. The [(M - 1)×(N - 1)] second conductors include (N - 1) outer second conductors and {[(M - 2)×(N - 1)]} inner second conductors. The (N - 1) outer second conductors are located in the (N - 1) outer wells, and the {[(M - 2)×(N - 1)]} inner second conductors are located in the {[(M - 2)×(N - 1)]} inner wells. The (N - 1) outer second conductors and the {[(M - 2)×(N - 1)]} inner second conductors are not electrically connected. Where the (N - 1) outer wells and the (N - 1) outer second conductors jointly serve as at least a part of the dummy capacitor structure, and each of the {[(M - 2)×(N - 1)]} inner wells includes four sides formed by two of the M longitudinal first conductive bars and two of the N transverse first conductive bars, and thus surrounds one of the {[(M - 2)×(N - 1)]} inner second conductors.

2. The semiconductor capacitor array layout according to claim 1, wherein The {[(M - 2)×(N - 1)]} inner wells are used for the transmission of a first voltage, and the {[(M - 2)×(N - 1)]} inner second conductors are used for the transmission of a second voltage, which is different from the first voltage. K of the {[(M - 2)×(N - 1)]} inner second conductors belong to a first capacitor group of P capacitor groups. P is a positive integer, and K is a positive integer not greater than {[(M - 2)×(N - 1)]}.

3. The semiconductor capacitor array layout according to claim 2, wherein, L of the {[(M - 2)×(N - 1)]} inner second conductors belong to a second capacitor group of the P capacitor groups. [(M - 2)×(N - 1)] is an integer greater than 1, P is an integer greater than 1, K is a positive integer not greater than {[(M - 2)×(N - 1)] - 1}, and L is a positive integer not greater than {[(M - 2)×(N - 1)] - K}.

4. The semiconductor capacitor array layout according to claim 1, wherein, The (N - 1) outer second conductors are electrically coupled together.

5. The semiconductor capacitor array layout according to claim 1, wherein, The (N - 1) outer wells and the (N - 1) outer second conductors are electrically coupled together.

6. A semiconductor capacitor array layout with a dummy capacitor structure, the semiconductor capacitor array layout comprising: A first conductive structure including M longitudinal first conductive bars and N discontinuous transverse first conductive bars, the M longitudinal first conductive bars being located in a first integrated circuit layer, the N discontinuous transverse first conductive bars being located in a second integrated circuit layer, each of the N discontinuous transverse first conductive bars including a lateral portion and an inner portion that are electrically unconnected, the N discontinuous transverse first conductive bars collectively including N lateral portions and N inner portions, the N lateral portions being located at the periphery of the semiconductor capacitor array layout and collectively serving as at least a part of the dummy capacitor structure, M being an integer greater than 1, and N being an integer greater than 1; and A second conductive structure including (M - 1) longitudinal second conductive bars and (N - 1) transverse second conductive bars, the (M - 1) longitudinal second conductive bars being located in the first integrated circuit layer, the (N - 1) transverse second conductive bars being located in the second integrated circuit layer, wherein the M longitudinal first conductive bars and the (M - 1) longitudinal second conductive bars are alternately arranged in the first integrated circuit layer; the N inner portions and the (N - 1) transverse second conductive bars are alternately arranged in the second integrated circuit layer; the N inner portions are coupled to the M longitudinal first conductive bars via a plurality of first vias; and the (N - 1) transverse second conductive bars are coupled to the (M - 1) longitudinal second conductive bars via a plurality of second vias.

7. The semiconductor capacitor array layout according to claim 6, wherein The N inner portions and the M longitudinal first conductive bars are for the transmission of a first voltage, and the (N - 1) transverse second conductive bars and the (M - 1) longitudinal second conductive bars are for the transmission of a second voltage, the first voltage being different from the second voltage.

8. A semiconductor capacitor array layout including a main capacitor structure and a dummy capacitor structure, wherein: The main capacitor structure includes: A first conductive structure including a plurality of longitudinal first conductive bars and a plurality of transverse first conductive bars, the plurality of transverse first conductive bars being coupled to the plurality of longitudinal first conductive bars via a plurality of first vias; and A second conductive structure including a plurality of longitudinal second conductive bars and a plurality of transverse second conductive bars, wherein the plurality of longitudinal first conductive bars and the plurality of longitudinal second conductive bars are alternately arranged in a first integrated circuit layer, the plurality of transverse first conductive bars and the plurality of transverse second conductive bars are alternately arranged in a second integrated circuit layer, and the plurality of transverse second conductive bars are coupled to the plurality of longitudinal second conductive bars via a plurality of second vias; and The dummy capacitor structure is located at at least one outer side of the main capacitor structure and includes: A third conductive structure including a plurality of longitudinal third conductive bars and a plurality of transverse third conductive bars; and A fourth conductive structure including a plurality of longitudinal fourth conductive bars and a plurality of transverse fourth conductive bars, wherein the plurality of longitudinal third conductive bars and the plurality of longitudinal fourth conductive bars are alternately arranged in the first integrated circuit layer, and the plurality of transverse third conductive bars and the plurality of transverse fourth conductive bars are alternately arranged in the second integrated circuit layer; Wherein the main capacitor structure and the dummy capacitor structure are not electrically connected, the dummy capacitor structure is located at the periphery of the semiconductor capacitor array layout, and the plurality of longitudinal first conductive bars, the plurality of longitudinal second conductive bars, the plurality of transverse first conductive bars and the plurality of transverse second conductive bars commonly form a first capacitor unit, and the plurality of longitudinal third conductive bars, the plurality of longitudinal fourth conductive bars, the plurality of transverse third conductive bars and the plurality of transverse fourth conductive bars commonly form a first dummy capacitor unit, and wherein the first capacitor unit is a minimum capacitor unit of the semiconductor capacitor array layout, and the first dummy capacitor unit and the voltage applied thereto do not form a capacitor as a whole.

9. The semiconductor capacitor array layout according to claim 8, wherein, The plurality of longitudinal first conductive bars and the plurality of transverse first conductive bars are used for the transmission of a first voltage, the plurality of longitudinal second conductive bars and the plurality of transverse second conductive bars are used for the transmission of a second voltage, and the first voltage is different from the second voltage.

10. The semiconductor capacitor array layout according to claim 8, wherein, The third conductive structure is electrically coupled to the fourth conductive structure.

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