Semiconductor capacitor array layout capable of forming parasitic capacitance towards layout edges

Abstract

A semiconductor capacitor array layout capable of forming parasitic capacitance towards layout edges to reduce the capacitance difference between peripheral and inner capacitor cells. The semiconductor capacitor array layout includes a first conductive structure and a second conductive structure. The first conductive structure includes a plurality of longitudinal first conductive strips in a first integrated circuit layer and a plurality of transverse first conductive strips in a second integrated circuit layer forming a plurality of well structures with the longitudinal first conductive strips. The well structures include outer wells and inner wells electrically connected. The second conductive structure includes a plurality of second conductors in the first integrated circuit layer and in the well structures. The second conductors include outer conductors and inner conductors electrically disconnected and located in the outer wells and the inner wells, respectively. The inner conductors closest to the outer wells form parasitic capacitance with the outer wells.

Description

Technical Field

[0001] This invention relates to the layout of semiconductor capacitor arrays, and more particularly to a semiconductor capacitor array layout capable of forming parasitic capacitances toward the edges of the layout. Background Technology

[0002] Typical semiconductor integrated circuits are usually multilayer structures. A traditional semiconductor capacitor array is typically located in a single metal layer of this multilayer structure. This semiconductor capacitor array usually contains multiple parallel rows of capacitor cells, including an adjacent first row and a second row of capacitor cells. To avoid the parasitic capacitance formed by the traces of the upper (lower) plates of the first row of capacitor cells and the lower (upper) plates of the second row of capacitor cells, which would result in inaccurate capacitance values ​​(since the upper (lower) plates of the first row of capacitor cells are parallel to the traces, their corresponding areas are relatively large), the spacing between the first row and the second row of capacitor cells needs to be increased, but this wastes circuit area.

[0003] In addition, the design of capacitor units in some semiconductor capacitor arrays, such as Figure 1a As shown, the upper electrode 110 has a U-shaped structure (including longitudinal and transverse structures), and the lower electrode 120 has a strip-shaped structure. Compared to general mature processes, in some advanced processes (e.g., FinFET technology), the ratio (W / L) of the width "W" of the transverse portion of the U-shaped structure to the length "L" of the longitudinal portion is larger to conform to the specifications of the advanced process. Figure 1b As shown. Since a semiconductor capacitor array typically contains a large number of capacitor cells, if the ratio (W / L) of the U-shaped structure of these capacitor cells is increased, the semiconductor capacitor array will consume a large amount of circuit area overall. Please note that... Figures 1a to 1b It is used to show the proportional changes of the U-shaped structure, not the actual size of the U-shaped structure.

[0004] Furthermore, such as Figure 2 As shown, a typical semiconductor capacitor array layout 200 includes effective capacitor cells ( Figure 2 Capacitor units marked with "C" and imitation capacitor units ( Figure 2 (Capacitor cells marked "D"). The simulated capacitor cells surrounding layout 200 are short-circuited together to avoid generating unwanted capacitance values. Among the effective capacitor cells within layout 200, adjacent simulated capacitor cells will not form parasitic capacitances with the simulated capacitors, but will only form parasitic capacitances with other effective capacitor cells (such as...). Figure 2As shown by the dashed line, this results in a difference between the overall capacitance value of an effective capacitor cell adjacent to a simulated capacitor cell and the overall capacitance value of an effective capacitor cell not adjacent to a simulated capacitor cell. This difference can adversely affect certain applications (e.g., capacitive digital-to-analog converters (CDACs)) (e.g., deviations in capacitance ratios can lead to a decrease in the linearity of the CDAC). Summary of the Invention

[0005] One of the purposes of this disclosure is to provide a semiconductor capacitor array layout capable of forming parasitic capacitances toward the layout edges, thereby avoiding the problems of the prior art.

[0006] One embodiment of the semiconductor capacitor array layout disclosed herein includes a first conductive structure and a second conductive structure. The first conductive structure includes M vertical first conductive strips and N horizontal first conductive strips, where M is an integer greater than two and N is an integer greater than one. The M vertical first conductive strips are located on a first integrated circuit layer; the N horizontal first conductive strips are located on a second integrated circuit layer; the N horizontal first conductive strips are coupled to the M vertical first conductive strips via a plurality of first vias, and together with the M vertical first conductive strips, form [(M−1)×(N−1)] well-shaped structures. The [(M−1)×(N−1)] well-shaped structures include (N−1) outer wells and {[(M−2)×(N−1)]} inner wells, and the (N−1) outer wells and the {[(M−2)×(N−1)]} inner wells are electrically connected.

[0007] As described above, the second conductive structure includes [(M−1)×(N−1)] second conductors located in the first integrated circuit layer. These [(M−1)×(N−1)] second conductors are respectively located within the [(M−1)×(N−1)] well-shaped structures, and include (N−1) outer second conductors and {[(M−2)×(N−1)]} inner second conductors. The (N−1) outer second conductors are located within the (N−1) outer wells, and the {[(M−2)×(N−1)]} inner second conductors are located within the {[(M−2)×(N−1)]} inner wells. The (N−1) outer second conductors and the {[(M−2)×(N−1)]} inner second conductors are not electrically connected. The M longitudinal first conductive strips and the N transverse first conductive strips are used for the transmission of a first voltage; the {[(M−2)×(N−1)]} inner second conductors are used for the transmission of P types of voltages; the (N−1) outer second conductors are used for the transmission of a preset voltage or are not used for the transmission of any voltage; the first voltage is different from any of the P types of voltages and also different from the preset voltage; the preset voltage is different from any of the P types of voltages; the (N−1) outer wells and the (N−1) inner second conductors closest to the (N−1) outer wells among the {[(M−2)×(N−1)]} inner second conductors form a parasitic capacitance.

[0008] Another embodiment of the semiconductor capacitor array layout disclosed herein includes a primary structure and an outer capacitor structure. The primary capacitor structure includes a first conductive structure and a second conductive structure. The first conductive structure includes a plurality of vertical first conductive strips and a plurality of horizontal first conductive strips; the plurality of vertical first conductive strips are located on a first integrated circuit layer; the plurality of horizontal first conductive strips are located on a second integrated circuit layer and coupled to the plurality of vertical first conductive strips via a plurality of first vias. The second conductive structure includes a plurality of vertical second conductive strips and a plurality of horizontal second conductive strips; the plurality of vertical second conductive strips are located on the first integrated circuit layer; the plurality of horizontal second conductive strips are located on the second integrated circuit layer and coupled to the plurality of vertical second conductive strips via a plurality of second vias. The plurality of vertical first conductive strips and the plurality of vertical second conductive strips are alternately disposed on the first integrated circuit layer; the plurality of horizontal first conductive strips and the plurality of horizontal second conductive strips are alternately disposed on the second integrated circuit layer.

[0009] As described above, the outer capacitor structure includes a third conductive structure and a fourth conductive structure. The third conductive structure includes multiple vertical third conductive strips and multiple horizontal third conductive strips; the multiple vertical third conductive strips are located in the first integrated circuit layer; the multiple horizontal third conductive strips are located in the second integrated circuit layer and are coupled to the multiple vertical third conductive strips via multiple third vias. The fourth conductive structure includes multiple vertical fourth conductive strips and multiple horizontal fourth conductive strips; the multiple vertical fourth conductive strips are located in the first integrated circuit layer; the multiple horizontal fourth conductive strips are located in the second integrated circuit layer. The multiple vertical third conductive strips and the multiple vertical fourth conductive strips are alternately disposed in the first integrated circuit layer; the multiple horizontal third conductive strips and the multiple horizontal fourth conductive strips are alternately disposed in the second integrated circuit layer.

[0010] In the above embodiments, the first conductive structure is electrically connected to the third conductive structure and is used for the transmission of a first voltage; the second conductive structure is used for the transmission of a second voltage; the fourth conductive structure is used for the transmission of a preset voltage or is not used for the transmission of any voltage; the first voltage is different from the second voltage and also different from the preset voltage; the preset voltage is different from the second voltage; the second conductive structure and the third conductive structure form the parasitic capacitance.

[0011] The features, practical operation, and effects of the present invention are described in detail below with reference to the accompanying drawings, and preferred embodiments are described in detail. Attached Figure Description

[0012] Figure 1a This illustrates the design of a capacitor cell in the prior art;

[0013] Figure 1b Show Figure 1a The design of the capacitor unit was modified to conform to the specifications of advanced processes;

[0014] Figure 2 This illustrates a typical semiconductor capacitor array layout;

[0015] Figure 3a An embodiment of the semiconductor capacitor array layout of the present invention is shown;

[0016] Figure 3b Show Figure 3a A variation of the semiconductor capacitor array layout; and

[0017] Figure 4 Another embodiment of the semiconductor capacitor array layout of the present invention is shown. Detailed Implementation

[0018] The semiconductor capacitor array layout disclosed herein avoids the problem of wasted circuit area in the prior art, avoids the problems caused by the U-shaped structure of the prior art under advanced processes, and reduces the capacitance difference between the peripheral capacitor cells and the internal capacitor cells.

[0019] Figure 3a An embodiment of the semiconductor capacitor array layout of the present invention is shown. Figure 3a The semiconductor capacitor array layout 300 includes a first conductive structure and a second conductive structure. The first conductive structure includes M vertical first conductive strips 310 (i.e.: Figure 3a The black vertical strip in the middle) and N horizontal first conductive strips 320 (that is: Figure 3a (a medium gray horizontal bar), where M is an integer greater than two. Figure 3a In the example, M=7), where N is an integer greater than one. Figure 3a In the diagram, N=4). The M vertical first conductive strips 310 are located in a first integrated circuit layer, and the N horizontal first conductive strips 320 are located in a second integrated circuit layer. Both the first and second integrated circuit layers are metal layers, and there are no other metal layers between the two metal layers; however, this is not a limitation of the present invention. The N horizontal first conductive strips 320 are connected via a plurality of first vias (i.e.: Figure 3a The light gray square (coupled to the gray horizontal strip) is coupled to the M vertical first conductive strips 310, and together with the M vertical first conductive strips 310, forms [(M−1)×(N−1)] well-shaped structures. The [(M−1)×(N−1)] well-shaped structures include (N−1) outer wells and {[(M−2)×(N−1)]} inner wells, and the (N−1) outer wells and the {[(M−2)×(N−1)]} inner wells are electrically connected.

[0020] Please see Figure 3a The second conductive structure contains [(M−1)×(N−1)] second conductors (i.e.: Figure 3aThe shapes of each second conductor (e.g., single long / horizontal strip, combination of multiple long / horizontal strips, combination of at least one long strip and at least one horizontal strip, or box) can be determined according to implementation requirements. The [(M−1)×(N−1)] second conductors are located in the first integrated circuit layer and are respectively located in the [(M−1)×(N−1)] well-shaped structures. The [(M−1)×(N−1)] second conductors include (N−1) outer second conductors 332 and {[(M−2)×(N−1)]} inner second conductors 334 and 336. The (N−1) outer second conductors 332 are located in the (N−1) outer wells. The {[(M−2)×(N−1)]} inner second conductors 334, 336 are located in the {[(M−2)×(N−1)]} inner wells, and each inner second conductor is electrically isolated from the inner wells surrounding it (e.g., isolated by oxides (not shown in the figure).

[0021] Please see Figure 3a The M longitudinal first conductive strips 310 and the N transverse first conductive strips 320 are used for the transmission of a first voltage; the {[(M−2)×(N−1)]} inner second conductors 334 and 336 are used for the transmission of a second voltage; the (N−1) outer second conductors 332 are used for the transmission of a preset voltage or are not used for the transmission of any voltage; the voltages mentioned above depend on the implementation requirements. The first voltage is different from the second voltage and also different from the preset voltage. The preset voltage is different from the second voltage; therefore, the (N−1) outer second conductors 332 and the {[(M−2)×(N−1)]} inner second conductors 334 and 336 are not electrically connected. Of the {[(M-2)×(N-1)]} inner second conductors 334 and 336, the (N-1) inner second conductors 334 are closest to the (N-1) outer wells, and the (N-1) inner second conductors 334 and the (N-1) outer wells together form a parasitic capacitance, which makes the capacitance values ​​of all effective capacitor cells in the semiconductor capacitor array layout 300 more consistent.

[0022] It is worth noting that each inner well and its inner second conductor 334 / 336 together constitute a capacitor unit. Furthermore, the (N-1) outer wells and the (N-1) outer second conductors 332 can serve as at least part of a simulated capacitor structure; however, this is not a limitation of the invention. Moreover, the (N-1) outer second conductors can be electrically connected together using common techniques such as wiring and vias; however, this is not a limitation of the invention. Additionally, the shape of each of the (N-1) outer second conductors is substantially the same as the shape of each of the {[(M-2)×(N-1)]} inner second conductors; however, this is not a limitation of the invention.

[0023] Figure 3b Show Figure 3a A variation of an embodiment. For example... Figure 3b As shown, the semiconductor capacitor array layout 300 may further include other outer wells and a second conductor located therein (i.e.: Figure 3b The white longitudinal strip), to connect with the inner second conductor adjacent to the other outer well (i.e.: Figure 3b The vertical strips with dots in the middle form parasitic capacitance. Figure 3a In this configuration, the (N−1) outer wells are located on one side of the semiconductor capacitor array layout 300; Figure 3b In this context, these outer wells are located around the semiconductor capacitor array layout 300. It is worth noting that, depending on implementation requirements, Figure 3a / Figure 3b The surrounding contour of the inner well can be rectangular or other polygonal. Since those skilled in the art can derive other embodiments based on the above description, repetitive and redundant descriptions are omitted here.

[0024] Please see Figure 3a The K second conductors 334 in the {[(M−2)×(N−1)]} inner second conductors 334, 336 (e.g.: Figure 3a The vertical strip with dots in the middle) belongs to a first capacitor group of P capacitor groups; where P is a positive integer and K is a positive integer not greater than {[(M−2)×(N−1)]}; in short, all capacitor units belonging to the same capacitor group can be regarded as a large capacitor as a whole. Those skilled in the art can deduce from this disclosure that the P capacitor groups contain more capacitor groups; for example, L of the {[(M−2)×(N−1)]} inner second conductors 334, 336 (e.g.: Figure 3a The vertical strip with grid in the middle belongs to the second capacitor group of the P capacitor groups. At this time, [(M−2)×(N−1)] is an integer greater than one, P is an integer greater than one, K is a positive integer not greater than {[(M−2)×(N−1)]−1}, and L is a positive integer not greater than {[(M−2)×(N−1)]−K}.

[0025] It is worth noting that, depending on the implementation requirements, the semiconductor capacitor array layout 300 may further include multiple capacitor group power supply bars (not shown in the figure), which are located on the second integrated circuit layer, the first integrated circuit layer, or a third integrated circuit layer (e.g., a metal layer), and serve as voltage transmission paths for the {[(M−2)×(N−1)]} inner second conductors 334, 336. For example, the multiple capacitor group power supply bars include a first capacitor group power supply bar and a second capacitor group power supply bar, the first capacitor group power supply bar being coupled to the aforementioned K second conductors 334, and the second capacitor group power supply bar being coupled to the aforementioned L second conductors 336; since the means of coupling the power supply bars and conductors is a common technique in this art, its details are omitted here.

[0026] It is worth noting that, Figure 3a In the [(M−1)×(N−1)] well-shaped structures, the conductive strips and conductors located in the first integrated circuit layer can all be conductive strips in the same direction to facilitate compliance with process specifications; however, this is not a limitation of the present invention. More specifically, when the conductive strips and conductors constituting the capacitor unit are all conductive strips in the same direction and not... Figure 1b When constructing such a structure, the capacitor cells can be fabricated without wasting circuit area and in accordance with the specifications of an advanced process (e.g., FinFET process).

[0027] Figure 4 Another embodiment of the semiconductor capacitor array layout is disclosed. Figure 4 The semiconductor capacitor array layout 400 includes a main capacitor structure 402 and an outer capacitor structure 404. The main capacitor structure 402 includes a first conductive structure and a second conductive structure. The outer capacitor structure 404 includes a third conductive structure and a fourth conductive structure.

[0028] Please see Figure 4 The first conductive structure includes a plurality of longitudinal first conductive strips 412 (i.e.: Figure 4 The longitudinal strip with anti-diagonal lines in the middle) and multiple transverse first conductive strips 414 (that is: Figure 4 (Medium gray horizontal stripes). The plurality of vertical first conductive strips 412 are located on a first integrated circuit layer (e.g., a metal layer); the plurality of horizontal first conductive strips 414 are located on a second integrated circuit layer (e.g., another metal layer). The plurality of horizontal first conductive strips 414 are located via a plurality of first vias (e.g., vias). Figure 4 The white square (coupled to the gray horizontal strip) is coupled to the plurality of vertical first conductive strips 412 and is used for the transmission of a first voltage.

[0029] Please see Figure 4 The second conductive structure includes a plurality of longitudinal second conductive strips 422 (i.e.: Figure 4The longitudinal strip with a grid in the middle) and multiple transverse second conductive strips 424 (that is: Figure 4 (A white horizontal strip). The plurality of vertical second conductive strips 422 are located in the first integrated circuit layer; the plurality of horizontal second conductive strips 424 are located in the second integrated circuit layer. The plurality of horizontal second conductive strips 424 are located via a plurality of second vias (e.g.: Figure 4 The black square (coupled to the white horizontal strip) is coupled to the plurality of vertical second conductive strips 422 and is used for the transmission of a second voltage, which is different from the first voltage. The plurality of vertical first conductive strips 412 and the plurality of vertical second conductive strips 422 are alternately disposed on the first integrated circuit layer; the plurality of horizontal first conductive strips 414 and the plurality of horizontal second conductive strips 424 are alternately disposed on the second integrated circuit layer.

[0030] Please see Figure 4 The third conductive structure comprises multiple longitudinal third conductive strips 432 (i.e.: Figure 4 The longitudinal strip with diagonal lines in the middle) and multiple transverse third conductive strips 434 (that is: Figure 4 (Medium gray horizontal stripes). The plurality of vertical third conductive strips 432 are located in the first integrated circuit layer; the plurality of horizontal third conductive strips 434 are located in the second integrated circuit layer and are transmitted via a plurality of third vias (e.g.: Figure 4 The white square coupled to the gray horizontal stripe) is coupled to the plurality of vertical third conductive strips 432; the plurality of horizontal first conductive strips 414 and the plurality of horizontal third conductive strips 434 are respectively a first part and a second part of the plurality of horizontal conductive strips. The fourth conductive structure includes a plurality of vertical fourth conductive strips 442 (that is: Figure 4 The longitudinal strip with dots in the middle) and multiple transverse fourth conductive strips 444 (that is: Figure 4 (A white horizontal strip); the plurality of vertical fourth conductive strips 442 are located on the first integrated circuit layer; the plurality of horizontal fourth conductive strips 444 are located on the second integrated circuit layer. The plurality of horizontal fourth conductive strips 444 may be located via a plurality of fourth vias (e.g., depending on implementation requirements). Figure 4 The multiple vertical fourth conductive strips 442 are coupled to the white squares (coupled to the light gray horizontal strips); however, this is not necessary. The multiple vertical third conductive strips 432 and the multiple vertical fourth conductive strips 442 are alternately disposed on the first integrated circuit layer; the multiple horizontal third conductive strips 434 and the multiple horizontal fourth conductive strips 444 are alternately disposed on the second integrated circuit layer. It is worth noting that the number of the multiple vertical first conductive strips may be the same as or different from the number of the multiple vertical third conductive strips, and the number of the multiple vertical second conductive strips may be the same as or different from the number of the multiple vertical fourth conductive strips.

[0031] Please see Figure 4The first conductive structure is electrically connected to the third conductive structure and is used for the transmission of the first voltage; the second conductive structure is used for the transmission of the second voltage; the fourth conductive structure is used for the transmission of a preset voltage or is not used for the transmission of any voltage; the first voltage is different from the second voltage and also different from the preset voltage; the preset voltage is different from the second voltage. The first conductive structure and the second conductive structure of the main capacitor structure 402 together form an effective capacitor unit. The third conductive structure and the fourth conductive structure of the outer capacitor structure 404 together serve as an auxiliary capacitor unit. The second conductive structure of the main capacitor structure 402 and the third conductive structure of the outer capacitor structure 404 together form a parasitic capacitance.

[0032] It is worth noting that the main capacitor structure 402 may include other effective capacitor units, and the outer capacitor structure 404 may also include other auxiliary capacitor units. To avoid... Figure 4 The diagram is complex, and these other effective capacitor units and auxiliary capacitor units are represented by ellipsis. Since those skilled in the art can deduce other implementations of effective capacitor units and replica capacitor units based on this disclosure, redundant and repetitive descriptions are omitted here. Figure 4 In the embodiments, the conductive strips used for the first voltage transmission in all effective capacitor units are electrically coupled together; if the conductive strips used for the second voltage transmission in all effective capacitor units belong to the same capacitor group, these conductive strips are electrically coupled together, wherein the capacitor units belonging to the same capacitor group can be regarded as a large capacitor as a whole.

[0033] Please note that the length, width, and thickness of the strip conductors (e.g., conductive strips, power supply strips) described in this specification are not particularly limited and are determined according to implementation requirements; therefore, their shape is not necessarily a traditional strip shape. Also note that, where implementation is possible, those skilled in the art may selectively implement some or all of the technical features in any of the foregoing embodiments, or selectively implement a combination of some or all of the technical features in multiple foregoing embodiments, thereby increasing the flexibility in implementing this invention.

[0034] In summary, the semiconductor capacitor array layout disclosed herein avoids the problem of wasted circuit area in the prior art, avoids the problems caused by the U-shaped structure of the prior art under advanced processes, and reduces the capacitance difference between the peripheral capacitor cells and the internal capacitor cells.

[0035] While the embodiments of the present invention have been described above, these embodiments are not intended to limit the present invention. Those skilled in the art can make changes to the technical features of the present invention based on the explicit or implicit content of the present invention. All such changes may fall within the scope of patent protection sought by the present invention. In other words, the scope of patent protection of the present invention shall be determined by the scope of the claims in this specification.

[0036] [Symbol Explanation]

[0037] 110: Upper electrode plate

[0038] 120: Lower electrode plate

[0039] W: Horizontal width

[0040] L: Longitudinal length

[0041] 200: Semiconductor capacitor array layout

[0042] C: Effective capacitor unit

[0043] D: Imitation capacitor unit

[0044] 300: Semiconductor capacitor array layout

[0045] 310: Longitudinal first conductive strip

[0046] 320: First transverse conductive strip

[0047] 332: Second outer conductor

[0048] 334, 336: Inner second conductor

[0049] 400: Semiconductor capacitor array layout

[0050] 402: Main capacitor structure

[0051] 404: External capacitor structure

[0052] 412: Longitudinal first conductive strip

[0053] 414: First transverse conductive strip

[0054] 422: Second longitudinal conductive strip

[0055] 424: Second transverse conductive strip

[0056] 432: Vertical third conductive strip

[0057] 434: Third transverse conductive strip

[0058] 442: Fourth longitudinal conductive strip

[0059] 444: Fourth horizontal conductive strip.

Claims

1. A semiconductor capacitor array layout structure capable of forming parasitic capacitance toward one edge of the semiconductor capacitor array layout structure, the semiconductor capacitor array layout structure comprising: A first conductive structure, comprising: M vertical first conductive strips are located in a first integrated circuit layer, where M is an integer greater than two; N horizontal first conductive strips are located on a second integrated circuit layer. The N horizontal first conductive strips are coupled to the M vertical first conductive strips through multiple first vias, and together with the M vertical first conductive strips, they form [(M−1)×(N−1)] well-shaped structures. The [(M−1)×(N−1)] well-shaped structures include (N−1) outer wells and {[(M−2)×(N−1)]} inner wells. The (N−1) outer wells and the {[(M−2)×(N−1)]} inner wells are electrically connected, where N is an integer greater than one. A second conductive structure, comprising: [(M−1)×(N−1)] second conductors are located in the first integrated circuit layer and are respectively located in the [(M−1)×(N−1)] well-shaped structures. The [(M−1)×(N−1)] second conductors include (N−1) outer second conductors and {[(M−2)×(N−1)]} inner second conductors. The (N−1) outer second conductors are located in the (N−1) outer wells, and the {[(M−2)×(N−1)]} inner second conductors are located in the {[(M−2)×(N−1)]} inner wells. The (N−1) outer second conductors and the {[(M−2)×(N−1)]} inner second conductors are not electrically connected. The M longitudinal first conductive strips and the N transverse first conductive strips are used for the transmission of a first voltage. The {[(M−2)×(N−1)]} inner second conductors are used for the transmission of a second voltage. The (N−1) outer second conductors are used for the transmission of a preset voltage or are not used for the transmission of any voltage. The first voltage is different from the second voltage and also different from the preset voltage. The preset voltage is different from the second voltage. Among the {[(M−2)×(N−1)]} inner second conductors, the (N−1) inner second conductors are closest to the (N−1) outer wells. The (N−1) inner second conductors and the (N−1) outer wells together form the parasitic capacitance. The shape of each of the (N−1) outer second conductors is substantially the same as the shape of each of the {[(M−2)×(N−1)]} inner second conductors.

2. The semiconductor capacitor array layout structure as claimed in claim 1, wherein each of the [(M−1)×(N−1)] second conductors comprises one or more conductive strips.

3. The semiconductor capacitor array layout structure as described in claim 1, wherein K of the {[(M−2)×(N−1)]} inner second conductors belong to a first capacitor group of P capacitor groups, L of the {[(M−2)×(N−1)]} inner second conductors belong to a second capacitor group of P capacitor groups, M is an integer greater than three, P is an integer greater than one, K is a positive integer not greater than {[(M−2)×(N−1)]−1}, and L is a positive integer not greater than {[(M−2)×(N−1)]−K}.

4. The semiconductor capacitor array layout structure as claimed in claim 1, wherein the (N−1) outer second conductors are electrically coupled together.

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