Thin film transistor and manufacturing method thereof, array substrate, display panel and device

Abstract

The present disclosure provides a thin film transistor and a manufacturing method thereof, an array substrate, a display panel and a device, and relates to the field of display technology. The thin film transistor comprises: a gate and an active layer, located on one side of a substrate; a gate insulating layer, located between the gate and the active layer; and a source electrode and a drain electrode separated from each other, both in contact with the active layer, wherein a first ratio of the thickness of the gate insulating layer to the thickness of the active layer ranges from 3 to 4.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a thin film transistor and a manufacturing method thereof, an array substrate, a display panel and a device. Background Art

[0002] With the development of display technology, the resolution of display panels is getting higher and higher, and the number of pixels per unit area is increasing.

[0003] With the increasing popularization of 5G, large-size ultra-high-definition display panels will be widely used in medical fields, display fields, live event broadcasting and other fields. Summary of the invention

[0004] According to one aspect of an embodiment of the present disclosure, a thin film transistor is provided, comprising: a gate and an active layer, located on one side of a substrate; a gate insulating layer, located between the gate and the active layer; and a source and a drain, spaced apart, both in contact with the active layer, wherein a first ratio of the thickness of the gate insulating layer to the thickness of the active layer ranges from 3 to 4.

[0005] In some embodiments, the active layer includes: a heavily doped first semiconductor layer, including a first portion and a second portion separated from each other, the first portion contacting the source and the second portion contacting the drain; and a second semiconductor layer located between the first semiconductor layer and the gate insulating layer and contacting the gate insulating layer.

[0006] In some embodiments, a second ratio of the thickness of the gate insulating layer to the thickness of the first semiconductor layer ranges from 15 to 24.

[0007] In some embodiments, the second ratio ranges from 18 to 22.

[0008] In some embodiments, a first portion of the first semiconductor layer contacts a third portion of the second semiconductor layer, a second portion of the first semiconductor layer contacts a fourth portion of the second semiconductor layer, a portion of the second semiconductor layer between the third portion and the fourth portion is a channel, and a width-to-length ratio of the channel ranges from 0.52 to 0.6.

[0009] In some embodiments, the width-to-length ratio of the channel is in a range of 0.54 to 0.58.

[0010] In some embodiments, the source electrode contacts the fifth portion of the second semiconductor layer, the drain electrode contacts the sixth portion of the second semiconductor layer, the thickness of the source electrode and the drain electrode is the first thickness, the thickness of the fifth portion and the sixth portion is the second thickness, and the third ratio of the first thickness to the second thickness ranges from 5.2 to 7.

[0011] In some embodiments, the third ratio ranges from 5.8 to 6.5.

[0012] In some embodiments, the thin film transistor also includes: an insulating protection layer covering the source and the drain, the insulating protection layer including: a first surface, in contact with a first side surface of the source close to the drain; a second surface, in contact with a second side surface of the drain close to the source; and a third surface, in contact with a side of the second semiconductor layer away from the gate insulating layer, and adjacent to the first surface and the second surface, the angle between the third surface and the first surface is a first angle, the angle between the third surface and the second surface is a second angle, and at least one of the first angle and the second angle is greater than 90 degrees and less than or equal to 110 degrees.

[0013] In some embodiments, the conductivity type of the first semiconductor layer is n-type, and the second semiconductor layer is an intrinsic semiconductor layer.

[0014] In some embodiments, materials of the first semiconductor layer and the second semiconductor layer include amorphous silicon.

[0015] In some embodiments, a material of the second semiconductor layer includes hydrogenated amorphous silicon.

[0016] In some embodiments, the gate insulating layer has a thickness ranging from 4500 angstroms to 5000 angstroms; and the active layer has a thickness ranging from 1000 angstroms to 1500 angstroms.

[0017] In some embodiments, the first ratio ranges from 3.4 to 3.8.

[0018] In some embodiments, the gate is located between the base substrate and the gate insulating layer.

[0019] According to another aspect of an embodiment of the present disclosure, an array substrate is provided, comprising: a plurality of pixel driving circuits, each pixel driving circuit comprising a plurality of thin film transistors, at least one of the plurality of thin film transistors comprising the thin film transistor described in any one of the above embodiments.

[0020] According to another aspect of the embodiments of the present disclosure, there is provided a display panel, comprising: the array substrate described in any one of the above embodiments.

[0021] According to another aspect of the embodiments of the present disclosure, there is provided a display device, comprising: the display panel described in any one of the above embodiments.

[0022] According to another aspect of the embodiments of the present disclosure, a method for manufacturing a thin film transistor is provided, comprising: forming a gate, an active layer and a gate insulating layer on one side of a substrate, wherein the gate insulating layer is located between the gate and the active layer; and forming a spaced-apart source and a drain, wherein the source and the drain are both in contact with the active layer, wherein a first ratio of the thickness of the gate insulating layer to the thickness of the active layer ranges from 3 to 4.

[0023] In some embodiments, the active layer includes: a heavily doped first semiconductor layer, including a first portion and a second portion separated from each other, the first portion contacting the source and the second portion contacting the drain; and a second semiconductor layer located between the first semiconductor layer and the gate insulating layer and contacting the gate insulating layer.

[0024] Other features, aspects and advantages of the present disclosure will become apparent from the following detailed description of exemplary embodiments of the present disclosure with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The accompanying drawings constitute a part of this specification, and illustrate exemplary embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0026] The present disclosure may be more clearly understood from the following detailed description with reference to the accompanying drawings, in which:

[0027] Figure 1 is a schematic diagram showing the structure of a thin film transistor according to an embodiment of the present disclosure;

[0028] Figure 2 is a schematic diagram showing the change of the on-state current of the thin film transistor along with the first ratio T1 / T2;

[0029] Figure 3 is a schematic diagram showing the change of the on-state current of the thin film transistor along with the second ratio T1 / T3;

[0030] Figure 4 is a schematic structural diagram showing a thin film transistor according to another embodiment of the present disclosure;

[0031] Figure 5 is a schematic top view showing a channel according to an embodiment of the present disclosure;

[0032] Fig. 6A is an IV curve showing a thin film transistor in a dark state;

[0033] Figure 6B is an IV curve showing a thin film transistor in a bright state;

[0034] Figure 7is a schematic structural diagram showing a thin film transistor according to another embodiment of the present disclosure;

[0035] Figure 8 FIG. 4 is a schematic flow chart showing a method for manufacturing a thin film transistor according to an embodiment of the present disclosure.

[0036] It should be understood that the size of each part shown in the accompanying drawings is not necessarily drawn according to the actual proportional relationship. In addition, the same or similar reference numerals represent the same or similar components. DETAILED DESCRIPTION

[0037] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. The description of the exemplary embodiments is merely illustrative and is in no way intended to limit the present disclosure and its application or use. The present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. These embodiments are provided to make the present disclosure thorough and complete and to fully express the scope of the present disclosure to those skilled in the art. It should be noted that unless otherwise specifically stated, the relative arrangement of the components and steps, the composition of the materials, the numerical expressions and the numerical values ​​set forth in these embodiments should be interpreted as being merely exemplary and not as limiting.

[0038] The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different parts. The words "include" or "comprises" and similar words mean that the elements before the word include the elements listed after the word, and do not exclude the possibility of including other elements. "Up", "down" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0039] In the present disclosure, when a specific component is described as being located between a first component and a second component, there may or may not be an intermediate component between the specific component and the first component or the second component. When a specific component is described as being connected to other components, the specific component may be directly connected to the other components without an intermediate component, or may not be directly connected to the other components but have an intermediate component.

[0040] All terms (including technical terms or scientific terms) used in the present disclosure have the same meanings as those understood by ordinary technicians in the field to which the present disclosure belongs, unless otherwise specifically defined. It should also be understood that terms defined in general dictionaries should be interpreted as having meanings consistent with their meanings in the context of the relevant technology, and should not be interpreted in an idealized or extremely formal sense, unless explicitly defined herein.

[0041] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered as part of the specification.

[0042] As the resolution of display panels increases, the picture quality of display panels also needs to be improved. However, in high-resolution display panels, such as 8K display panels, display defects are increasing.

[0043] Through analysis, the inventors realize that the performance of the thin film transistors in the array substrate of the display panel affects the display effect of the display panel. Through research, the inventors propose the following technical solution for optimizing the performance of the thin film transistors. This will be described below in conjunction with different embodiments.

[0044] The inventors analyzed the relationship between the thickness of the gate insulating layer and the active layer in the thin film transistor and found that the ratio of the thicknesses of the two layers has an influence on the on-state current of the thin film transistor.

[0045] Figure 1 FIG. 4 is a schematic diagram showing the structure of a thin film transistor according to an embodiment of the present disclosure.

[0046] like Figure 1 As shown, the thin film transistor includes a gate electrode 11 , an active layer 12 , a gate insulating layer 13 , a source electrode 14 and a drain electrode 15 .

[0047] The gate 11 and the active layer 12 are both located on one side of the base substrate 10. For example, the base substrate 10 may be a glass substrate, etc. As some implementations, see Figure 1 The active layer 12 may include a plurality of semiconductor layers, for example, a first semiconductor layer 121 and a second semiconductor layer 122. As another implementation, the active layer 12 may include only one semiconductor layer.

[0048] The gate insulating layer 13 is located between the gate 11 and the active layer 12. Figure 1 The gate 11 is located between the base substrate 10 and the gate insulating layer 13 .

[0049] The source electrode 14 and the drain electrode 15 are spaced apart from each other and both contact the active layer 12. It should be understood that the source electrode 14 and the drain electrode 15 contact different portions of the active layer 12, respectively.

[0050] Here, a first ratio T1 / T2 of the thickness T1 of the gate insulating layer 13 to the thickness T2 of the active layer 12 ranges from 3 to 4. For example, the first ratio T1 / T2 may be 3.2, 3.5, 3.6, 3.8, or the like.

[0051] It should be understood that the thickness T2 of the active layer 12 refers to the thickness of the active layer 12 as a whole. For example, in the case where the active layer 12 includes a plurality of semiconductor layers, some parts of the active layer have a smaller thickness and some parts have a larger thickness. As a whole, the smaller thickness and the larger thickness are both represented as T2, and both satisfy the range of T1 / T2 being 3 to 4.

[0052] In the above embodiment, the range of T1 / T2 is 3 to 4, and such a range helps to increase the on-state current of the thin-film transistor and can ensure the insulation breakdown voltage capability of the gate insulating layer 13.

[0053] In some embodiments, the thickness T1 of the gate insulating layer 13 ranges from 4500 angstroms to 5000 angstroms, and the thickness T2 of the active layer 12 ranges from 1000 angstroms to 1500 angstroms. For example, T1 is 4700 angstroms, 4800 angstroms, 4900 angstroms, etc. For example, T2 is 1200 angstroms, 1300 angstroms, 1400 angstroms, etc.

[0054] In some embodiments, the range of the first ratio T1 / T2 is 3.4 to 3.8. For example, 3.5, 3.6, 3.7, etc. In this way, the on-state current of the thin-film transistor and the insulation breakdown voltage capability of the gate insulating layer 13 can be better balanced.

[0055] When the gate-source voltage Vgs > threshold voltage Vth and the drain-source voltage Vds < Vgs - Vth, the thin-film transistor operates in the non-saturation region, and the current of the thin-film transistor in the non-saturation region can be expressed by the following formula:

[0056]

[0057] μ is the electron mobility, C ox is the capacitance per unit area of the metal-insulator-semiconductor (MIS) structure in the thin-film transistor, and W / L represents the ratio of the channel width to the channel length of the thin-film transistor.

[0058] Assuming that Vgs, Vth, and Vds remain unchanged, and setting the parts related to these three variables as a constant 1 as a whole, the above formula can be transformed into:

[0059]

[0060] μ is proportional to the thickness T2 of the active layer 12, C ox is inversely proportional to the thickness T1 of the gate insulating layer 13. When W / L is a fixed value, the above formula can be transformed into:

[0061] I ds =(T2 / T1)·μ·C ox ·W / L

[0062] Through analysis, it can be seen that the change of T1 / T2 will lead to the change of the on-state current of the thin film transistor.

[0063] Figure 2 is a schematic diagram showing how the on-state current of the thin film transistor changes with the first ratio T1 / T2 .

[0064] like Figure 2 As shown, the on-state current I on As the first ratio T1 / T2 increases, it increases first and then decreases. Experimental verification shows that when the first ratio T1 / T2 is in the range of 3 to 4, the on-state current of the thin film transistor can be increased and the insulation withstand voltage capability of the gate insulating layer 13 can be guaranteed.

[0065] In some embodiments, the active layer 12 of the thin film transistor includes a plurality of semiconductor layers. Figure 1 The active layer 12 includes a first semiconductor layer 121 and a second semiconductor layer 122. The first semiconductor layer 121 is a heavily doped semiconductor layer. For example, the conductivity type of the first semiconductor layer 121 is n-type. As some implementations, the second semiconductor layer 122 is an intrinsic semiconductor layer.

[0066] The first semiconductor layer 121 includes a first portion P1 and a second portion P2 separated from each other, wherein the first portion P1 contacts the source electrode 14 and the second portion P2 contacts the drain electrode 15. In other words, the portion of the first semiconductor layer 121 contacting the source electrode 14 is the first portion P1, and the portion contacting the drain electrode 15 is the second portion P2.

[0067] The second semiconductor layer 122 is located between the first semiconductor layer 121 and the gate insulating layer 13, and contacts the gate insulating layer 13. In some embodiments, the second semiconductor layer 122 contacts the first semiconductor layer 121, that is, there is no other additional layer therebetween.

[0068] In some embodiments, the materials of the first semiconductor layer 121 and the second semiconductor layer 122 include amorphous silicon. For example, the material of the first semiconductor layer 121 includes n-type heavily doped amorphous silicon (a-Si), and the material of the second semiconductor layer 122 includes hydrogenated amorphous silicon (a-Si-H).

[0069] The inventors noticed that when the active layer 12 includes the first semiconductor layer 121 and the second semiconductor layer 122, since the leakage current of the thin film transistor is mainly the hole current formed by the channel thermal ion emission, a PN junction is formed between the hole accumulation layer on the channel and the first semiconductor layer. The existence of this PN junction makes the current flow only from the hole accumulation layer to the outside and not from the outside to the inside, which can effectively reduce the output efficiency of the holes. Therefore, the inventors realized that by adjusting the thickness T3 of the first semiconductor layer 121, the on-state current of the thin film transistor can be further adjusted.

[0070] In some embodiments, the second ratio T1 / T3 of the thickness T1 of the gate insulating layer 13 to the thickness T3 of the first semiconductor layer 121 ranges from 15 to 24. In this way, the on-state current of the thin film transistor can be further increased. For example, the second ratio T1 / T3 is 17, 18, 20, 22, etc.

[0071] Figure 3 is a schematic diagram showing how the on-state current of the thin film transistor changes with the second ratio T1 / T3 .

[0072] It is verified through experiments that when the ratio of the thickness T2 of the active layer to the thickness T3 of the first semiconductor layer is in the range of 5 to 6, the on-state current of the thin film transistor is relatively large.

[0073] like Figure 3 As shown, the on-state current I on As the second ratio T1 / T3 increases, it shows a trend of first increasing and then decreasing. When the second ratio T1 / T3 is in the range of 15 to 24, the on-state current of the thin film transistor can be further increased.

[0074] In some embodiments, the second ratio T1 / T3 is in a range of 18 to 22, for example, the second ratio T1 / T3 is 19, 20, 21, etc. In this way, the on-state current of the thin film transistor can be further increased.

[0075] The inventors also noticed that by adjusting the width-to-length ratio of the thin film transistor channel, the off-state current of the thin film transistor can be adjusted. In order to further improve the performance of the thin film transistor, the embodiment of the present disclosure also proposes the following technical solution to reduce the off-state current of the thin film transistor.

[0076] Figure 4 FIG. 4 is a schematic diagram showing the structure of a thin film transistor according to another embodiment of the present disclosure.

[0077] like Figure 4 As shown, the first portion P1 of the first semiconductor layer 121 contacts the third portion P3 of the second semiconductor layer 122, the second portion P2 of the first semiconductor layer 121 contacts the fourth portion P4 of the second semiconductor layer 122, and the portion of the second semiconductor layer 122 between the third portion P3 and the fourth portion P4 is the channel CL. Here, the width-to-length ratio W / L of the channel CL ranges from 0.52 to 0.6.

[0078] In the above embodiment, the width-to-length ratio W / L of the channel CL ranges from 0.52 to 0.6, which helps to reduce the off-state current of the thin film transistor, thereby helping to improve the pixel voltage holding rate of the pixel driving circuit including the thin film transistor.

[0079] In some embodiments, the width-to-length ratio W / L of the channel CL ranges from 0.54 to 0.58, for example, 0.56, 0.57, etc. In this way, the off-state current of the thin film transistor can be further reduced.

[0080] Figure 5 is a schematic top view of a channel according to an embodiment of the present disclosure.

[0081] like Figure 5 As shown, from the top view of the channel CL, the length of the channel CL can be understood as the length of the channel CL in the first direction from the source 14 to the drain 15, and the width of the channel CL can be understood as the length of the channel CL in the second direction perpendicular to the first direction.

[0082] It should be noted that Figure 5 The channel CL, source 14 and drain 15 are schematic and are not intended to limit the scope of the present disclosure. Those skilled in the art should understand that the width and length of the channel can be determined accordingly according to the positions of the gate, source and drain of the thin film transistor, thereby determining the channel width-to-length ratio.

[0083] When the first ratio T1 / T2 of the thickness T1 of the gate insulating layer 13 and the thickness T2 of the active layer 12 remains unchanged, the inventors obtain the changes of the on-state current Ion and the off-state current Ioff of the thin film transistor by studying the changes of the width-to-length ratio of the channel.

[0084] Fig. 6A FIG. 1 is an IV curve of a thin film transistor in a dark state according to an example of the present disclosure. Figure 6B 1 is an IV curve of a thin film transistor in a bright state according to an example of the present disclosure. It should be understood that the dark state (DARK) and the bright state (PHOTO) here refer to the dark state and the bright state of the display panel when the thin film transistor is applied to the display panel.

[0085] exist Fig. 6A and Figure 6B In the figure, the width-to-length ratio W / L of the channel corresponding to curve 1 is 0.56, and the width-to-length ratio W / L of the channel corresponding to curve 2 is 0.72.

[0086] Table 1 shows a plurality of parameters of the thin film transistor when the width-to-length ratio W / L of the channel is different in the dark state and the light state.

[0087] Table 1

[0088]

[0089] In Table 1, Ion_15 represents the on-state current of the thin film transistor when the gate-source voltage is 15 V, Ioff_-8 and Ioff_-20 represent the off-state current of the thin film transistor when the gate-source voltage is 8 V and 20 V, respectively. Vth1 represents the threshold voltage of the thin film transistor, and Mob represents the electron mobility of the thin film transistor.

[0090] from Fig. 6A , Figure 6B It can be seen from Table 1 that a large width-to-length ratio W / L of the channel has limited effect on the improvement of the on-state current Ion, but will significantly increase the off-state current Ioff. It has been verified that when the width-to-length ratio W / L is in the range of 0.52 to 0.6, the off-state current Ioff of the thin film transistor can be reduced well.

[0091] The inventors also noticed that the metal elements in the source and drain may diffuse, resulting in increased off-state current of the thin film transistor and short circuit failure, thereby reducing the performance of the thin film transistor, for example, causing a display panel including the thin film transistor to have poor display such as afterimages, crosstalk, and grown black spots (GDS).

[0092] Through research, it is found that by adjusting the thickness relationship between the source electrode 14 / drain electrode 15 and the second semiconductor layer 122, the diffusion of metal elements in the source electrode 14 and the drain electrode 15 can be effectively blocked to further improve the performance of the thin film transistor. Based on this, the embodiment of the present disclosure also proposes the following technical solution.

[0093] See also Figure 4 , the source electrode 14 contacts the fifth portion P5 of the second semiconductor layer 122, and the drain electrode 15 contacts the sixth portion P6 of the second semiconductor layer 122. It should be understood that the source electrode 14 contacts a portion of the second semiconductor layer 122 in addition to the first semiconductor layer 121; the drain electrode 15 contacts another portion of the second semiconductor layer 122 in addition to the first semiconductor layer 121.

[0094] Here, the thickness of the source 14 and the drain 15 is the first thickness, the thickness of the fifth portion P5 and the sixth portion P6 is the second thickness, and the third ratio of the first thickness to the second thickness ranges from 5.2 to 7. For example, the third ratio is 5.5, 6, 6.5, 6.8, etc. In this way, the diffusion of metal elements (such as copper elements) in the source 14 and the drain 15 can be effectively blocked.

[0095] In some embodiments, the third ratio ranges from 5.8 to 6.5, for example, 6.2, 6.3, etc. In this way, the diffusion of metal elements in the source 14 and the drain 15 can be more effectively blocked.

[0096] Figure 7 FIG. 4 is a schematic diagram showing the structure of a thin film transistor according to another embodiment of the present disclosure.

[0097] like Figure 7 As shown, the thin film transistor further includes an insulating protection layer 16 covering the source electrode 14 and the drain electrode 15. For example, the material of the insulating protection layer 16 may include silicon nitride or the like.

[0098] The insulating protection layer 16 includes a first surface S1, a second surface S2 and a third surface S3. It should be understood that the first surface S1, the second surface S2 and the third surface S3 are part of the bottom surface of the insulating protection layer 16. The insulating protection layer 16 also includes other surfaces, such as the top surface, and other parts of the bottom surface.

[0099] The first surface S1 contacts a first side surface SE1 of the source 14 close to the drain 15 , and the second surface S2 contacts a second side surface SE2 of the drain 15 close to the source 14 .

[0100] The third surface S3 contacts a surface of the second semiconductor layer 122 away from the gate insulating layer 13 (i.e., the top surface of the channel), and is adjacent to the first surface S1 and the second surface S2. Here, the angle between the third surface S3 and the first surface S1 is a first angle θ1, and the angle between the third surface S3 and the second surface S2 is a second angle θ2.

[0101] The inventors have found that the magnitudes of the first angle θ1 and the second angle θ2 have an effect on the diffusion of metal elements in the source 14 and the drain 15. In order to more effectively block the diffusion of metal elements, at least one of the first angle θ1 and the second angle θ2 is greater than 90 degrees and less than or equal to 110 degrees. In some embodiments, at least one of the first angle θ1 and the second angle θ2 may be 95 degrees, 100 degrees, 105 degrees, etc.

[0102] In the above embodiment, at least one of the first angle θ1 and the second angle θ2 is greater than 90 degrees and less than or equal to 110 degrees, so as to effectively prevent the metal element of at least one of the source 14 and the drain 15 from diffusing toward the gate 11 .

[0103] It is understandable that the technical solutions of the above different embodiments can be combined with each other. In some embodiments, a thin film transistor can be combined with the technical solutions of the above different embodiments, so as to further improve the performance of the thin film transistor.

[0104] Figure 8 FIG. 4 is a schematic flow chart showing a method for manufacturing a thin film transistor according to an embodiment of the present disclosure.

[0105] In step 802, a gate, an active layer and a gate insulating layer are formed on one side of a substrate, wherein the gate insulating layer is located between the gate and the active layer.

[0106] For example, a gate may be first formed on one side of the substrate, and then a gate insulating layer covering the gate may be formed, and then an active layer may be formed on a side of the gate insulating layer away from the gate.

[0107] For example, the material of the gate insulating layer may include silicon oxide.

[0108] In step 804, a source electrode and a drain electrode are formed to be spaced apart. Here, both the source electrode and the drain electrode are in contact with the active layer.

[0109] For example, a metal layer (eg, a copper layer) may be formed first, and then the metal layer may be patterned to form spaced-apart source and drain electrodes.

[0110] Here, a first ratio of the thickness of the gate insulating layer to the thickness of the active layer ranges from 3 to 4.

[0111] The thin film transistor formed in the above embodiment helps to increase the on-state current of the thin film transistor.

[0112] In some embodiments, the structure of the active layer may be the structure described above, which will not be described in detail here.

[0113] In some embodiments, the formed thin film transistor may be a thin film transistor of any one of the embodiments described above.

[0114] The embodiment of the present disclosure further provides an array substrate, including: a plurality of pixel driving circuits, each pixel driving circuit including a plurality of thin film transistors, at least one of the plurality of thin film transistors including a thin film transistor of any of the above embodiments. It should be understood that the array substrate may also include a base substrate, and the plurality of pixel driving circuits are located on one side of the base substrate.

[0115] For example, the source electrode 14 of the thin film transistor may be connected to the data line, for example, integrally provided with the data line, and the drain electrode 15 may be connected to the pixel electrode.

[0116] Since the on-state current of the thin film transistor increases, it helps to improve the driving effect of the pixel driving circuit in the array substrate, thereby helping to improve the display effect.

[0117] In some embodiments, each thin film transistor in each pixel driving circuit may be a thin film transistor of any of the above embodiments, which can further improve the driving effect of the pixel driving circuit in the array substrate, thereby helping to further improve the display effect.

[0118] The embodiment of the present disclosure further provides a display panel, comprising: the array substrate of any one of the above embodiments. In some embodiments, the display panel may be a liquid crystal display panel. For example, the display panel further comprises a color film substrate.

[0119] The present disclosure also provides a display device, which may include a display panel of any of the above embodiments. In one embodiment, the display device may be, for example, a mobile terminal, a television (e.g., an 8K resolution television), a monitor, a laptop, a digital photo frame, a navigator, an electronic paper, or any other product or component with a display function.

[0120] So far, various embodiments of the present disclosure have been described in detail. In order to avoid obscuring the concept of the present disclosure, some details known in the art are not described. Based on the above description, those skilled in the art can fully understand how to implement the technical solution disclosed here.

[0121] Although some specific embodiments of the present disclosure have been described in detail by way of examples, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present disclosure. It should be understood by those skilled in the art that the above embodiments may be modified or some technical features may be replaced by equivalents without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. A thin film transistor, comprising: The gate and active layer are located on one side of the substrate; A gate insulating layer, located between the gate and the active layer; A source electrode and a drain electrode spaced apart from each other, both in contact with the active layer; and an insulating protective layer covering the source electrode and the drain electrode; Wherein, a first ratio of the thickness of the gate insulating layer to the thickness of the active layer is in a range of 3 to 4; Wherein, the active layer comprises: a heavily doped first semiconductor layer, comprising a first portion and a second portion spaced apart from each other, the first portion being in contact with the source electrode, and the second portion being in contact with the drain electrode; and a second semiconductor layer, located between the first semiconductor layer and the gate insulating layer, Wherein, a second ratio of the thickness of the gate insulating layer to the thickness of the first semiconductor layer ranges from 15 to 24.

2. The thin film transistor according to claim 1, wherein: The second ratio ranges from 18 to 22.

3. The thin film transistor according to any one of claims 1 to 2, wherein: The first portion of the first semiconductor layer contacts the third portion of the second semiconductor layer, the second portion of the first semiconductor layer contacts the fourth portion of the second semiconductor layer, and the portion of the second semiconductor layer between the third portion and the fourth portion is a channel, and a width-to-length ratio of the channel ranges from 0.52 to 0.

6.

4. The thin film transistor according to claim 3, wherein: The width-to-length ratio of the channel is in the range of 0.54 to 0.

58.

5. The thin film transistor according to any one of claims 1 to 2, wherein: The source electrode contacts the fifth portion of the second semiconductor layer, the drain electrode contacts the sixth portion of the second semiconductor layer, the thickness of the source electrode and the drain electrode is a first thickness, the thickness of the fifth portion and the sixth portion is a second thickness, and a third ratio of the first thickness to the second thickness ranges from 5.2 to 7.

6. The thin film transistor according to claim 5, wherein: The third ratio ranges from 5.8 to 6.

5.

7. The thin film transistor according to any one of claims 1 to 2, wherein: The material of the insulating protective layer includes silicon nitride, and the insulating protective layer includes: A first surface, in contact with a first side surface of the source electrode close to the drain electrode; A second surface, in contact with a second side surface of the drain electrode close to the source electrode; and The third surface is in contact with a surface of the second semiconductor layer away from the gate insulating layer, and is adjacent to the first surface and the second surface. The angle between the third surface and the first surface is a first angle, and the angle between the third surface and the second surface is a second angle. At least one of the first angle and the second angle is greater than 90 degrees and less than or equal to 110 degrees.

8. The thin film transistor according to any one of claims 1 to 2, wherein: The conductivity type of the first semiconductor layer is n-type, and the second semiconductor layer is an intrinsic semiconductor layer.

9. The thin film transistor according to any one of claims 1 to 2, wherein: The materials of the first semiconductor layer and the second semiconductor layer include amorphous silicon, the conductivity type of the first semiconductor layer is n-type, and the second semiconductor layer is in contact with the gate insulating layer.

10. The thin film transistor according to claim 9, wherein: The material of the second semiconductor layer includes hydrogenated amorphous silicon.

11. The thin film transistor according to any one of claims 1 to 2, wherein: The gate insulating layer has a thickness ranging from 4500 angstroms to 5000 angstroms; The thickness of the active layer ranges from 1000 angstroms to 1500 angstroms.

12. The thin film transistor according to claim 1, wherein: The first ratio ranges from 3.4 to 3.

8.

13. The thin film transistor according to claim 1, wherein: The gate is located between the base substrate and the gate insulating layer.

14. An array substrate, comprising: A plurality of pixel driving circuits, each pixel driving circuit comprising a plurality of thin film transistors, at least one of the plurality of thin film transistors comprising the thin film transistor according to any one of claims 1-13.

15. A display panel, comprising: The array substrate as claimed in claim 14.

16. A display device, comprising: The display panel according to claim 15.

17. A method for manufacturing a thin film transistor, comprising: Forming a gate, an active layer and a gate insulating layer on one side of the substrate, wherein the gate insulating layer is located between the gate and the active layer; and forming a spaced-apart source and a drain, each of the source and the drain being in contact with the active layer, Wherein, a first ratio of the thickness of the gate insulating layer to the thickness of the active layer is in a range of 3 to 4; Wherein, the active layer comprises: a heavily doped first semiconductor layer, comprising a first portion and a second portion spaced apart from each other, the first portion being in contact with the source electrode, and the second portion being in contact with the drain electrode; and a second semiconductor layer, located between the first semiconductor layer and the gate insulating layer, Wherein, a second ratio of the thickness of the gate insulating layer to the thickness of the first semiconductor layer ranges from 15 to 24.

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