Floating gate type split-gate flash memory device and method of manufacturing the same

Abstract

The application provides a floating gate type split-gate flash memory device and a preparation method thereof, wherein the device comprises a substrate, a floating gate oxide layer, a step type floating gate polysilicon layer, an ONO dielectric layer, a source side wall, a first side wall, a source polysilicon layer, a protective layer, a second side wall, a select gate oxide silicon layer, a select gate polysilicon layer and a third side wall. The application forms a package for the floating gate polysilicon layer in the left, right and upper directions of the floating gate polysilicon layer by using the source side wall, increases the overlapping area of the source side wall and the floating gate polysilicon layer, and can improve the coupling coefficient of SL-FG while reducing the size of the micro flash memory device. Further, the application makes the inner and outer sides of the floating gate polysilicon layer into step shapes with different thicknesses, thickens the thickness of the inner side of the floating gate polysilicon layer, simultaneously thins the thickness of the outer side of the floating gate polysilicon layer, makes the effective overlapping area of the select gate to the floating gate basically unchanged, simultaneously forms a package for the upper corner of the outer side of the floating gate by the select gate, and improves the erasing efficiency of the device.

Description

Technical Field

[0001] This application relates to the field of semiconductor flash memory device manufacturing technology, specifically to a floating gate type split-gate flash memory device and its preparation method. Background Technology

[0002] In existing floating-gate type split-gate flash memory devices, the overlap size (L) between the heavily doped source line (SL) region and the floating gate (FG) is... op The coupling coefficient of the SL-FG is relatively large, and increasing the overlap area between the heavily doped source region and the floating gate can result in a larger coupling coefficient. However, a large overlap area between the heavily doped source region and the floating gate is not conducive to the miniaturization of flash memory cells, therefore, the L-FG needs to be reduced. op However, L op The reduction in size will decrease the coupling coefficient of the SL-FG, thereby reducing the programming speed of the device. Summary of the Invention

[0003] This application provides a floating-gate type split-gate flash memory device and its fabrication method, which can solve at least one of the problems of large overlap area between the source-end heavily doped region and the floating gate, and slow programming operation speed of the floating-gate type split-gate flash memory device.

[0004] On one hand, embodiments of this application provide a floating-gate type split-gate flash memory device, including:

[0005] A substrate in which a well region and a shallow trench isolation structure are formed; a floating gate oxide layer and a stepped floating gate polysilicon layer are formed sequentially from bottom to top on the substrate; a lightly doped drain region and a drain electrode located outside the floating gate polysilicon layer and a source electrode located inside the floating gate polysilicon layer are formed in the well region;

[0006] A first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer are stacked, with the first silicon oxide layer covering the stepped floating gate polysilicon layer; wherein, the first silicon oxide layer, the silicon nitride layer, and the second silicon oxide layer constitute an ONO dielectric layer; the second silicon oxide layer in the ONO dielectric layer is L-shaped.

[0007] A source-end sidewall is located on the second silicon oxide layer; wherein, deep trenches are formed in the source-end sidewall, the ONO dielectric layer, the stepped floating gate polysilicon layer, and the floating gate oxide layer;

[0008] The first sidewall covers the top and bottom sidewalls of the deep trench;

[0009] A source-end polysilicon layer, the source-end polysilicon layer covering the source electrode and filling a portion of the depth of the deep trench;

[0010] a protection layer covering the source end polysilicon layer and filling the deep trench of the remaining depth;

[0011] a second side wall covering the outer side surface of the ONO dielectric layer and the outer side surface of the floating gate polysilicon layer;

[0012] a select gate oxide silicon layer, a select gate polysilicon layer and a third side wall, the select gate oxide silicon layer is located at the side of the second side wall; the select gate polysilicon layer is located at the side of the select gate oxide silicon layer and wraps the outer side upper corner of the floating gate polysilicon layer; the third side wall is located at the side of the select gate polysilicon layer.

[0013] Optionally, in the floating gate type split gate flash memory device, the step type floating gate polysilicon layer comprises: a lower step and an upper step located on the lower step, wherein the thickness of the upper step is the thickness of the lower step is

[0014] Optionally, in the floating gate type split gate flash memory device, the second side wall covers the outer side surface of the floating gate polysilicon layer in the length direction; the ONO dielectric layer covers the two opposite side surfaces of the floating gate polysilicon layer in the width direction.

[0015] Optionally, in the floating gate type split gate flash memory device, the middle side wall of the deep trench not covered by the first side wall exposes the upper surface of the source end side wall, and the upper surface of the source end side wall is in direct contact with the source end polysilicon layer.

[0016] In another aspect, the embodiments of the present application also provide a preparation method of a floating gate type split gate flash memory device, comprising:

[0017] providing a substrate, a well region is formed in the substrate, and a floating gate oxide layer, a floating gate polysilicon layer and a blocking layer are sequentially formed on the substrate from bottom to top, wherein the floating gate oxide layer, the floating gate polysilicon layer, the blocking layer and the substrate have a first trench formed therein;

[0018] forming an isolation layer, the isolation layer fills the first trench;

[0019] removing the blocking layer, and etching back part of the thickness of the isolation layer so that the upper surface of the isolation layer is not higher than the lower surface of the floating gate polysilicon layer, wherein the remaining thickness of the isolation layer in the first trench is a shallow trench isolation structure;

[0020] sequentially forming a first silicon oxide layer, a silicon nitride layer, a sacrifice layer and an etching stop layer on the floating gate polysilicon layer, wherein the first silicon oxide layer covers the upper surface and the two opposite side surfaces of the floating gate polysilicon layer;

[0021] etching the etching stop layer and the sacrificial layer to form a second trench;

[0022] forming a second silicon oxide layer covering sidewalls, a bottom wall of the second trench and the etching stop layer; wherein the first silicon oxide layer, the silicon nitride layer and the second silicon oxide layer constitute an ONO dielectric layer;

[0023] forming a source-side spacer in the second trench, the source-side spacer covering part of the sidewalls and part of the bottom wall of the second trench;

[0024] self-aligned etching the second silicon oxide layer, the silicon nitride layer, the first silicon oxide layer and the floating gate polysilicon layer to form a third trench;

[0025] performing an ion implantation process on the bottom wall of the third trench to form a source in the well region;

[0026] forming a first spacer covering top and bottom end sidewalls of the third trench;

[0027] etching the floating gate oxide layer in the third trench to form a fourth trench;

[0028] forming a source-side polysilicon layer to lead out the source, the source-side polysilicon layer filling the fourth trench and covering the etching stop layer;

[0029] polishing the source-side polysilicon layer on the surface of the etching stop layer and etching back the source-side polysilicon layer in the fourth trench by a certain thickness;

[0030] forming a protection layer covering the source-side polysilicon layer and filling the fourth trench;

[0031] removing the etching stop layer;

[0032] etching the sacrificial layer, the silicon nitride layer, the first silicon oxide layer and part of the thickness of the floating gate polysilicon layer on the side of the fourth trench to obtain a step-type floating gate polysilicon layer;

[0033] forming a second spacer covering the outer surface of the ONO dielectric layer and the outer surface of the floating gate polysilicon layer;

[0034] removing the remaining thickness of the floating gate polysilicon layer on the side of the second spacer to the surface of the floating gate oxide layer;

[0035] forming a select gate oxide layer on the second sidewall, a select gate polysilicon layer on the side of the select gate oxide layer and wrapping the outer upper corner of the floating gate polysilicon layer, a lightly doped drain region in the well region, a drain and a third sidewall on the side of the select gate polysilicon layer.

[0036] Optionally, in the method for manufacturing the floating gate split-gate flash memory device, the step of etching the sacrificial layer, the silicon nitride layer, the first silicon oxide layer and a part of the floating gate polysilicon layer on the side of the fourth trench to obtain a stepped floating gate polysilicon layer comprises:

[0037] self-aligned etching the sacrificial layer, the silicon nitride layer and the first silicon oxide layer on the side of the fourth trench;

[0038] etching the floating gate polysilicon layer to a certain thickness to obtain the stepped floating gate polysilicon layer; wherein the stepped floating gate polysilicon layer comprises a lower step and an upper step on the lower step, and the thickness of the upper step is the thickness of the lower step is

[0039] Optionally, in the method for manufacturing the floating gate split-gate flash memory device, the second sidewall covers the outer surface of the floating gate polysilicon layer in the length direction; and the ONO dielectric layer covers the opposite two side surfaces of the floating gate polysilicon layer in the width direction.

[0040] Optionally, in the method for manufacturing the floating gate split-gate flash memory device, the first sidewall does not cover the middle sidewall of the third trench to expose the upper surface of the source end sidewall, so that the upper surface of the source end sidewall directly contacts the source end polysilicon layer.

[0041] The technical scheme of the present application has at least the following advantages:

[0042] The present application reduces the overlapping size (L op ) of the source and the floating gate polysilicon layer, and uses the source end sidewall to wrap the floating gate polysilicon layer in the left, right and upper directions, thereby increasing the overlapping area of the source end sidewall and the floating gate polysilicon layer, and improving the coupling coefficient of the SL-FG while reducing the size of the flash memory device. Furthermore, the present application forms a stepped floating gate polysilicon layer, which has different thicknesses on the inner and outer sides, thereby thickening the thickness of the inner floating gate polysilicon layer and simultaneously thinning the thickness of the outer floating gate polysilicon layer, i.e., the inner side of the floating gate polysilicon layer is thicker than the outer side. This can ensure that the effective overlapping area of the select gate and the floating gate remains basically unchanged, and at the same time, the select gate wraps the upper corner of the floating gate, thereby effectively improving the erasing efficiency of the device. BRIEF DESCRIPTION OF DRAWINGS

[0043] In order to more clearly illustrate the technical solutions in the specific embodiments or prior art of the present application, the accompanying drawings required to be used in the description of the specific embodiments or prior art will be briefly introduced. Obviously, the accompanying drawings in the following description are some embodiments of the present application, and all other embodiments obtained by those of ordinary skill in the art without creative work based on these drawings are within the scope of the present application.

[0044] Figures 1-20 is a schematic diagram of a semiconductor structure in each process step of preparing a floating gate type split-gate flash memory device according to an embodiment of the present application;

[0045] In the drawings, the reference signs are explained as follows:

[0046] 100-substrate, 101-P-type well region, 102-floating gate oxide layer, 103-floating gate polysilicon layer, 104-ONO dielectric layer, 104-1-first silicon oxide layer, 104-2-silicon nitride layer, 104-3-second silicon oxide layer, 105-source side wall, 106-first side wall, 107-source polysilicon layer, 108-source electrode, 109-protective layer, 110-second side wall, 111-selective gate oxide layer, 112-selective gate polysilicon layer, 113-third side wall, 113-1-third side wall sub-layer, 113-2-third side wall sub-layer, 114-lightly doped drain region, 115-drain electrode, 116-1-isolation layer, 116-isolation layer (shallow trench isolation structure);

[0047] 501-barrier layer, 502-sacrificial layer, 503-etching stop layer. DETAILED DESCRIPTION

[0048] The technical solutions in the present application will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work are within the scope of the present application.

[0049] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and therefore cannot be understood as indicating or implying that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", "third" are only for the purpose of description, and cannot be understood as indicating or implying relative importance.

[0050] In the description of the present application, it is necessary to point out that, unless otherwise explicitly specified and limited, the terms "mounting", "connection", "linking" should be understood in a broad sense, for example, can be fixed connection, can also be detachable connection, or integrally connected; can be mechanical connection, can also be electrical connection; can be directly connected, can also be indirectly connected through intermediate medium, can also be the internal communication of two elements, can be wireless connection, can also be wired connection. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0051] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as there is no conflict between them.

[0052] The embodiment of the present application provides a preparation method of a floating gate type split gate flash memory device. Specifically, please refer to Figures 1-20 , Figures 1-20 is a semiconductor structure schematic diagram in each process step of preparing the floating gate type split gate flash memory device of the embodiment of the present application. The preparation method of the floating gate type split gate flash memory device comprises:

[0053] First, as shown in Figure 1 and Figure 2 , Figure 1 is a cross-sectional view of the semiconductor structure after forming the first trench in the channel length direction, Figure 2 is a cross-sectional view of the semiconductor structure after forming the first trench in the channel width direction, a substrate 100 is provided, an ion implantation process is performed on the substrate 100 to form a P-type well region 101 in the substrate 100, and a floating gate oxide layer 102, a floating gate polysilicon layer 103 and a barrier layer 501 are sequentially formed from bottom to top on the substrate 100, wherein the floating gate oxide layer 102, the floating gate polysilicon layer 103, the barrier layer 501 and the substrate 100 are formed with a first trench 116-1. Further, the barrier layer 501 can be a silicon nitride material.

[0054] Then, as shown in Figure 3 and Figure 4 , Figure 3 is a cross-sectional view of the semiconductor structure after forming the shallow trench isolation structure in the channel length direction, Figure 4 is a cross-sectional view of the semiconductor structure after forming the shallow trench isolation structure in the channel width direction, an isolation layer 116 is formed, and the isolation layer 116 fills the first trench 116-1. Preferably, the isolation layer 116 includes but is not limited to a silicon oxide material.

[0055] Further, continuing to refer to Figure 3 and Figure 4The barrier layer 501 is removed, and a portion of the thickness of the isolation layer 116 is etched back so that the upper surface of the isolation layer 116 is not higher than the lower surface of the floating gate polysilicon layer 103. The remaining thickness of the isolation layer 116 in the first trench 116-1 is a shallow trench isolation structure. In this embodiment, the upper surface of the isolation layer 116 after the etch-back process can be flush with the upper surface of the floating gate oxide layer 102.

[0056] Next, as Figure 5 and Figure 6 As shown, Figure 5 It is a cross-sectional view of the semiconductor structure after the formation of the source-end sidewalls along the length of the channel. Figure 6 This is a cross-sectional view of the semiconductor structure after the source sidewalls are formed in the channel width direction. A first silicon oxide layer 104-1, a silicon nitride layer 104-2, a sacrificial layer 502, and an etch stop layer 503 are sequentially formed on the floating gate polysilicon layer 103. The first silicon oxide layer 104-1 covers the upper surface and the two opposite side surfaces of the floating gate polysilicon layer 103. Preferably, the sacrificial layer 502 includes, but is not limited to, the silicon oxide layer, and the etch stop layer 503 includes, but is not limited to, the silicon nitride layer.

[0057] Furthermore, the etch stop layer 503 and the sacrificial layer 502 are etched to form a second trench / deep trench. Specifically, the etch stop layer 503 and the sacrificial layer 502 can be opened using photolithography, dry etching, or other methods.

[0058] Next, a second silicon oxide layer 104-3 is formed, which covers the sidewalls, bottom wall and etch stop layer 503 of the second trench; wherein the first silicon oxide layer 104-1, the silicon nitride layer 104-2 and the second silicon oxide layer 104-3 constitute an ONO dielectric layer 104.

[0059] In this embodiment, as Figure 6 As shown, the ONO dielectric layer 104 completely covers the two opposite side surfaces of the floating gate polysilicon layer 103 in the width direction, as well as the upper surface of the floating gate polysilicon layer 103.

[0060] Furthermore, a source-end sidewall 105 is formed in the second trench, the source-end sidewall 105 covering part of the sidewall and part of the bottom wall of the second trench. In this embodiment, the source-end sidewall 105 is made of polycrystalline silicon. Specifically, the second trench is first filled with polycrystalline silicon material, and then the source-end sidewall 105 is formed using anisotropic etching. Figure 6 As shown, the source sidewall 105 can enclose the floating gate polysilicon layer 103 in three directions: left, right, and top. Next, as...Figure 7 and Figure 8 as shown, Figure 7 is a cross-sectional view of the semiconductor structure after forming the source in the channel length direction, Figure 8 is a cross-sectional view of the semiconductor structure after forming the source in the channel width direction, on the basis of the second trench, the second silicon oxide layer 104-3, the silicon nitride layer 104-2, the first silicon oxide layer 104-1 (the ONO dielectric layer 104) and the floating gate polysilicon layer 103 are etched self-alignedly to form a third trench / deep trench.

[0061] Further, an ion implantation process is performed on the bottom wall of the third trench to form a heavily doped region in the well region 101, i.e. to form a source 108.

[0062] Next, as shown in Figure 9 and Figure 10 as shown, Figure 9 is a cross-sectional view of the semiconductor structure after forming the source polysilicon layer in the channel length direction, Figure 10 is a cross-sectional view of the semiconductor structure after forming the source polysilicon layer in the channel width direction, a first side wall 106 is formed, which covers the top and bottom side walls of the third trench. Specifically, the first side wall 106 can be a silicon oxide layer; in this embodiment, a layer of silicon oxide is first deposited on the side walls and bottom wall of the third trench, and then anisotropic etching is performed on the silicon oxide layer to obtain the first side wall 106. As can be seen from Figure 9 , the first side wall 106 does not cover the middle side wall of the third trench to expose the upper surface of the source side wall 105.

[0063] Further, the floating gate oxide layer 102 is anisotropically etched in the third trench to form a fourth trench / deep trench, at which time the source 108 is exposed.

[0064] Next, a source polysilicon layer 107 is formed, which fills the fourth trench and covers the etching stop layer 503. Specifically, the source polysilicon layer 107 serves to lead out the source 108 in the substrate 100.

[0065] In this embodiment, the first side wall 106 does not cover the middle side wall of the third trench to expose the upper surface of the source side wall, so that the upper surface of the source side wall 105 is in direct contact with the source polysilicon layer 107.

[0066] Further, as shown in Figure 11 and Figure 12 as shown, Figure 11 is a cross-sectional view of the semiconductor structure after forming the protection layer in the channel length direction,Figure 12 is a cross-sectional view of the semiconductor structure after forming the protection layer in the channel width direction, the source-end polysilicon layer 107 on the surface of the etching stop layer 503 is polished and the source-end polysilicon layer 107 in the fourth trench is etched by a certain thickness.

[0067] Then, a protection layer 109 is formed, which covers the source-end polysilicon layer 107 and fills the fourth trench. Specifically, the protection layer 109 can be a silicon oxide layer, which can be formed by a thermal oxidation process or a CVD vapor deposition process in this embodiment.

[0068] Further, the etching stop layer 503 is removed by a wet etching process.

[0069] Then, as shown in FIG. 11A and FIG. 11B, Figure 13 and Figure 14 , Figure 13 is a cross-sectional view of the semiconductor structure after forming the step-type floating gate polysilicon layer in the channel length direction, Figure 14 is a cross-sectional view of the semiconductor structure after forming the step-type floating gate polysilicon layer in the channel width direction, the sacrifice layer 502, the silicon nitride layer 104-2, the first silicon oxide layer 104-1 and part of the floating gate polysilicon layer 103 on the side of the fourth trench are etched to obtain the step-type floating gate polysilicon layer 103.

[0070] Specifically, the step of etching the sacrifice layer, the silicon nitride layer, the first silicon oxide layer and part of the floating gate polysilicon layer on the side of the fourth trench to obtain the step-type floating gate polysilicon layer can include:

[0071] Step one: self-aligned etching the sacrifice layer 502, the silicon nitride layer 104-2 and the first silicon oxide layer 104-1 on the side of the fourth trench;

[0072] Step two: etching the floating gate polysilicon layer 103 by a certain thickness to obtain the step-type floating gate polysilicon layer 103; wherein the step-type floating gate polysilicon layer 103 includes a lower step and an upper step on the lower step, and the thickness of the upper step can be the thickness of the lower step can be

[0073] The source-end spacer 105 is used to wrap the floating gate polysilicon layer 103 in the left, right and upper directions of the floating gate polysilicon layer 103, while reducing the overlapping size (L op ) between the source 108 and the floating gate polysilicon layer 103, which can reduce the size of the micro flash memory device and meet the requirement of higher integration of flash memory devices while improving the coupling coefficient of the SL-FG.

[0074] Further, as shown in Figure 15 and Figure 16 , Figure 15 is a cross-sectional view of the semiconductor structure after removing the floating gate polysilicon layer 103 from the side of the second side wall 110 in the channel length direction, Figure 16 is a cross-sectional view of the semiconductor structure after removing the floating gate polysilicon layer 103 from the side of the second side wall 110 in the channel width direction, the second side wall 110 covers the outer side surface of the ONO dielectric layer 104, and the second side wall 110 covers the outer side surface of the upper step and the upper surface of the lower step of the floating gate polysilicon layer 103.

[0075] In this embodiment, the second side wall 110 covers most of the outer side surface of the floating gate polysilicon layer 103 in the length direction.

[0076] Then, the remaining thickness of the floating gate polysilicon layer 103 from the side of the second side wall 110 is removed to the surface of the floating gate oxide layer 102 by using an anisotropic etching process.

[0077] Finally, as shown in Figures 17-20 and Figure 17 , Figure 18 is a cross-sectional view of the semiconductor structure after forming the select gate oxide silicon layer in the channel length direction, Figure 19 is a cross-sectional view of the semiconductor structure after forming the third side wall in the channel length direction, Figure 20 is a cross-sectional view of the semiconductor structure after forming the third side wall in the channel width direction, the select gate oxide silicon layer 111, the select gate polysilicon layer 112, the lightly doped drain region 114, the drain 115, and the third side wall 113 are formed; specifically, the select gate oxide silicon layer 111 is located on the side of the second side wall 110; the select gate polysilicon layer 112 is located on the side of the select gate oxide silicon layer 111 and wraps the outer side upper corner of the step-type floating gate polysilicon layer 103; the lightly doped drain region 114 (Halo injection) and the drain 115 are located in the well region 101; the third side wall 113 is located on the side of the select gate polysilicon layer 112.

[0078] The third side wall 113 can include a third side wall sub-layer 113-1 and a third side wall sub-layer 113-2. In this embodiment, the material of the third side wall sub-layer 113-1 can be silicon oxide, and the material of the third side wall sub-layer 113-2 can be silicon nitride.

[0079] Based on the same inventive concept, the embodiments of the present application also provide a floating gate type split gate flash memory device, as shown in Figure 19 andFigure 20 As shown, the floating gate type split-gate flash memory device comprises:

[0080] a substrate 100, wherein a (P-type) well region 101 and a shallow trench isolation structure 116 are formed in the substrate 100; a floating gate oxide layer 102 and a step-type floating gate polysilicon layer 103 are sequentially formed on the substrate 100 from bottom to top; a lightly doped drain region 114 and a drain 115 located outside the floating gate polysilicon layer 103 and a source 108 located inside the floating gate polysilicon layer 103 are formed in the well region 101;

[0081] a first silicon oxide layer 104-1, a silicon nitride layer 104-2 and a second silicon oxide layer 104-3 stacked together, wherein the first silicon oxide layer 104-1 covers the step-type floating gate polysilicon layer 103; the first silicon oxide layer 104-1, the silicon nitride layer 104-2 and the second silicon oxide layer 104-3 constitute an ONO dielectric layer 104; the second silicon oxide layer 104-3 in the ONO dielectric layer 104 is in L shape;

[0082] a source-side spacer 105 located on the second silicon oxide layer 104-3; wherein a deep trench is formed in the source-side spacer 105, the ONO dielectric layer 104, the step-type floating gate polysilicon layer 103 and the floating gate oxide layer 102;

[0083] a first side wall 106 covering the top and bottom sidewalls of the deep trench;

[0084] a source-side polysilicon layer 107 covering the source 108 and filling the deep trench partially;

[0085] a protective layer 109 covering the source-side polysilicon layer 107 and filling the deep trench to the remaining depth;

[0086] a second side wall 110 covering the outer surface of the ONO dielectric layer 104 and the outer surface of the floating gate polysilicon layer 103;

[0087] a select gate silicon oxide layer 111, a select gate polysilicon layer 112 and a third side wall 113, wherein the select gate silicon oxide layer 111 is located on the side of the second side wall 110; the select gate polysilicon layer 112 is located on the side of the select gate silicon oxide layer 111 and wraps the outer corner of the floating gate polysilicon layer 103; the third side wall 113 is located on the side of the select gate polysilicon layer 112.

[0088] Preferably, the stepped floating gate polysilicon layer 103 comprises a lower step and an upper step on the lower step, wherein the thickness of the upper step can be The thickness of the lower step can be

[0089] Further, from Figure 19 It can be seen that the second side wall 110 covers the outer side surface of the floating gate polysilicon layer 103 in the length direction; from Figure 20 It can be seen that the ONO dielectric layer 104 covers the two opposite side surfaces of the floating gate polysilicon layer 103 in the width direction.

[0090] The middle side wall of the deep trench not covered by the first side wall 106 exposes the upper surface of the source side wall 105, which is in direct contact with the source polysilicon layer 107.

[0091] In summary, the present application provides a floating gate type split gate flash memory device and a preparation method thereof, wherein the device comprises a substrate 100 in which a well region 101 and a shallow trench isolation structure 116 are formed; a floating gate oxide layer 102, a stepped floating gate polysilicon layer 103; an ONO dielectric layer 104; a source side wall 105; a first side wall 106; a source polysilicon layer 107; a protective layer 109; a second side wall 110; a select gate oxide silicon layer 111, a select gate polysilicon layer 112 and a third side wall 113. The present application reduces the overlapping size (L op ) of the source 108 and the floating gate polysilicon layer 103, and uses the source side wall 105 to wrap the stepped floating gate polysilicon layer 103 in the left, right and upper three directions, thereby increasing the overlapping area of the source side wall 105 and the floating gate polysilicon layer 103, improving the coupling coefficient of the SL-FG while reducing the size of the flash memory device; further, the present application forms a stepped floating gate polysilicon layer 103, which has different thicknesses on the inside and outside, thickens the thickness of the inner floating gate polysilicon layer 103 and thins the thickness of the outer floating gate polysilicon layer 103, i.e. the floating gate polysilicon layer 103 is thick on the inside and thin on the outside, which can ensure that the effective overlapping area of the select gate and the floating gate remains unchanged, and at the same time, the outer upper corner of the select gate to the floating gate is wrapped, thereby effectively improving the erasing efficiency of the flash memory device.

[0092] Obviously, the above embodiments are only examples for clearly illustrating the present application, and are not intended to limit the present application. Based on the above description, other different forms of changes or modifications can be made by those skilled in the art. Here, all the embodiments are not required to be exhausted, and the obvious changes or modifications derived therefrom are still within the protection scope of the present application.

Claims

1. A method for fabricating a floating-gate type split-gate flash memory device, characterized in that, The application relates to a method for manufacturing a floating gate memory cell. The method comprises the following steps: providing a substrate, wherein a well region is formed in the substrate, and a floating gate oxide layer, a floating gate polysilicon layer and a barrier layer are sequentially formed on the substrate from bottom to top, wherein the floating gate oxide layer, the floating gate polysilicon layer, the barrier layer and the substrate are provided with a first groove; forming an isolation layer, wherein the isolation layer fills the first groove; removing the barrier layer and etching back a part of the thickness of the isolation layer so that the upper surface of the isolation layer is not higher than the lower surface of the floating gate polysilicon layer, wherein the remaining thickness of the isolation layer in the first groove is a shallow trench isolation structure; sequentially forming a first silicon oxide layer, a silicon nitride layer, a sacrifice layer and an etching stop layer on the floating gate polysilicon layer, wherein the first silicon oxide layer covers the upper surface and the opposite two side surfaces of the floating gate polysilicon layer; etching the etching stop layer and the sacrifice layer to form a second groove; forming a second silicon oxide layer, wherein the second silicon oxide layer covers the side wall, the bottom wall of the second groove and the etching stop layer; wherein the first silicon oxide layer, the silicon nitride layer and the second silicon oxide layer constitute an ONO dielectric layer; forming a source side wall in the second groove, wherein the source side wall covers a part of the side wall and a part of the bottom wall of the second groove, and the source side wall wraps the floating gate polysilicon layer in the left, right and upper three directions of the floating gate polysilicon layer; self-aligned etching the second silicon oxide layer, the silicon nitride layer, the first silicon oxide layer and the floating gate polysilicon layer to form a third groove; performing an ion implantation process on the bottom wall of the third groove to form a source electrode in the well region; forming a first side wall, wherein the first side wall covers the top end side wall and the bottom end side wall of the third groove; etching the floating gate oxide layer in the third groove to form a fourth groove; forming a source end polysilicon layer to lead out the source electrode, wherein the source end polysilicon layer fills the fourth groove and covers the etching stop layer; grinding the source end polysilicon layer on the surface of the etching stop layer and etching back the source end polysilicon layer in the fourth groove by a certain thickness; forming a protection layer, wherein the protection layer covers the source end polysilicon layer and fills the fourth groove; removing the etching stop layer; etching the sacrifice layer, the silicon nitride layer, the first silicon oxide layer and a part of the thickness of the floating gate polysilicon layer on the side of the fourth groove to obtain a stepped floating gate polysilicon layer, wherein the floating gate polysilicon layer has a stepped appearance with an inner side being thick and an outer side being thin, wherein the side close to the source end polysilicon layer is the inner side of the floating gate polysilicon layer, and the side far away from the source end polysilicon layer is the outer side of the floating gate polysilicon layer; forming a second side wall, wherein the second side wall covers the outer surface of the ONO dielectric layer and the outer surface of the floating gate polysilicon layer; removing the remaining thickness of the floating gate polysilicon layer on the side of the second side wall to the surface of the floating gate oxide layer; forming a select gate oxide layer on the second side wall, a select gate polysilicon layer on the side of the select gate oxide layer and wrapping the outer side upper corner of the floating gate polysilicon layer, a lightly doped drain region in the well region, a drain electrode and a third side wall on the side of the select gate polysilicon layer.

2. The method of claim 1, wherein the method further comprises: The step of etching the sacrificial layer, the silicon nitride layer, the first silicon oxide layer and a partial thickness of the floating gate polysilicon layer on the fourth trench side to obtain a step-type floating gate polysilicon layer comprises: self-aligned etching the sacrificial layer, the silicon nitride layer, the first silicon oxide layer on the fourth trench side; etching the floating gate polysilicon layer to a certain thickness to obtain the stepped floating gate polysilicon layer; wherein the stepped floating gate polysilicon layer comprises a lower step and an upper step on the lower step, wherein the thickness of the upper step is the thickness of the lower step is 3. The method for fabricating a floating-gate type split-gate flash memory device according to claim 1, characterized in that, The second side wall covers the outer side surface of the floating gate polysilicon layer in the length direction; and the ONO dielectric layer covers the two opposite side surfaces of the floating gate polysilicon layer in the width direction.

4. The method for fabricating a floating-gate type split-gate flash memory device according to claim 1, characterized in that, The first side wall does not cover the middle side wall of the third trench to expose the upper surface of the source end side wall, so that the upper surface of the source end side wall is in direct contact with the source end polysilicon layer.

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