Level shifting circuits and methods

Abstract

This disclosure relates to level shifting circuits and methods. One circuit includes a bias circuit and a level shifter. The bias circuit includes a first input terminal and a second input terminal configured to receive a first power supply voltage and a second power supply voltage, and the bias circuit is configured to generate a bias voltage having the greater of a first voltage level of the first power supply voltage or a second voltage level of the second power supply voltage. The level shifter includes a first PMOS transistor configured to receive the first power supply voltage and a second PMOS transistor configured to receive the second power supply voltage, and each of the first and second PMOS transistors includes a body terminal configured to receive the bias voltage.

Description

Technical Field

[0001] This disclosure relates to level shifting circuits and methods. Background Technology

[0002] Integrated circuits (ICs) sometimes comprise multiple sections corresponding to independently controlled power domains. In some cases, a first power domain has a first power supply voltage level, and a second power domain has a second power supply voltage level different from the first power supply voltage level. Level shifters are often used to propagate signals between such sections, shifting logic levels between the first and second power supply voltage levels.

[0003] In order to shift logic levels, a level shifter typically includes both an n-type metal-oxide-semiconductor (NMOS) transistor and a p-type metal-oxide-semiconductor (PMOS) transistor that operate in both a first power domain and a second power domain. Summary of the Invention

[0004] According to one aspect of this disclosure, a level shifting circuit is provided, comprising: a bias circuit including: a first input terminal configured to receive a first power supply voltage; and a second input terminal configured to receive a second power supply voltage, wherein the bias circuit is configured to generate a bias voltage having a greater of a first voltage level of the first power supply voltage or a second voltage level of the second power supply voltage; and a level shifter including: a first PMOS transistor configured to receive the first power supply voltage; and a second PMOS transistor configured to receive the second power supply voltage, wherein each of the first PMOS transistor and the second PMOS transistor includes a body terminal configured to receive the bias voltage.

[0005] According to another aspect of this disclosure, an integrated circuit (IC) is provided, comprising: an n-well; a first power node configured to have a first power supply voltage; a second power node configured to have a second power supply voltage; a bias circuit comprising: a first PMOS transistor located in the n-well and including a first source / drain S / D terminal coupled to the first power supply node; and a second PMOS transistor located in the n-well and including a second S / D terminal coupled to the second power supply node, wherein the bias circuit is configured to bias the n-well using a bias voltage having a bias voltage level based on the greater of a first voltage level of the first power supply voltage or a second voltage level of the second power supply voltage; and a level shifter comprising: a third PMOS transistor located in the n-well and including a third S / D terminal coupled to the first power supply node; and a fourth PMOS transistor located in the n-well and including a fourth S / D terminal coupled to the second power supply node.

[0006] According to another aspect of this disclosure, a method of operating a level shifting circuit is provided, the method comprising: receiving a first power supply voltage and a second power supply voltage at a bias circuit; generating a bias voltage using the bias circuit based on the greater of a first voltage level of the first power supply voltage or a second voltage level of the second power supply voltage; receiving the first power supply voltage at a first source / drain S / D terminal of a first PMOS transistor of a level shifter; receiving the second power supply voltage at a second S / D terminal of a second PMOS transistor of the level shifter; and using the bias voltage to bias an n-well comprising the first PMOS transistor and the second PMOS transistor. Attached Figure Description

[0007] Various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily enlarged or reduced.

[0008] Figure 1A and Figure 1B This is a diagram of a level shifting circuit according to some embodiments.

[0009] Figure 2 This is a diagram of a level shifter according to some embodiments.

[0010] Figure 3A This is a schematic diagram of a bias circuit according to some embodiments.

[0011] Figure 3B These are illustrations of IC layout diagrams and level shifting circuits based on some embodiments.

[0012] Figure 4A This is a schematic diagram of a bias circuit according to some embodiments.

[0013] Figure 4B These are illustrations of IC layout diagrams and level shifting circuits based on some embodiments.

[0014] Figure 5 This is a diagram illustrating a method of operating a level shifting circuit according to some embodiments.

[0015] Figure 6 This is an illustration of a method for generating an IC layout diagram according to some embodiments.

[0016] Figure 7 This is a diagram illustrating a method for manufacturing a level shifting circuit according to some embodiments.

[0017] Figure 8 It is a block diagram of a system generated based on IC layout diagrams of some embodiments.

[0018] Figure 9 This is a block diagram of an IC manufacturing system according to some embodiments and the associated IC manufacturing process. Detailed Implementation

[0019] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components, values, operations, materials, arrangements, etc., are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. Other components, values, operations, materials, arrangements, etc., are contemplated. For example, in the following description, forming a first feature above or on a second feature can include embodiments where the first and second features are formed in direct contact, and can also include embodiments where an additional feature can be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0020] In addition, spatially related terms (e.g., "below," "below," "lower than," "above," "upper") may be used herein to facilitate the description of the relationship of one element or feature shown in the figure relative to another element(s) or feature(s). These spatially related terms are intended to cover different orientations of the device in use or operation other than those shown in the figure. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein may be interpreted accordingly.

[0021] The level shifting circuit includes a bias circuit and a level shifter comprising a first PMOS transistor and a second PMOS transistor. The first and second PMOS transistors are located in a common n-well and configured to operate in respective first and second power domains. The bias circuit is configured to bias the common n-well based on the greater of a first voltage level in the first power domain or a second voltage level in the second power domain. Compared to a level shifter comprising PMOS transistors configured to operate in separate power domains and located in separately biased n-wells, by including a bias circuit configured to bias the common n-well, the level shifting circuit avoids latch-up risk while having reduced space requirements.

[0022] Figure 1A and Figure 1B This is a diagram of a level shifting circuit 100 according to some embodiments. Figure 1A This is a schematic diagram of the level shifting circuit 100, and Figure 1B It is a plan view of a level shifting circuit 100 including the X direction and the Y direction perpendicular to the X direction.

[0023] A level shifting circuit 100 (also referred to in some embodiments as circuit 100 or IC 100) is an IC configured to operate in a first power domain and a second power domain (unlabeled). The first power domain includes a first power distribution structure comprising a power node NVDD1 configured to have a power supply voltage VDD1 and a reference node NVSS configured to have a reference voltage VSS. The second power domain includes a second power distribution structure comprising the reference node NVSS and a power node NVDD2 configured to have a power supply voltage VDD2 separate from the power supply voltage VDD1.

[0024] Each of the first and second power domains is capable of operating in either a power-on or power-off mode. In power-on mode, the power supply voltage VDD1 at power node NVDD1 has a first power supply voltage level of the first power domain, and the power supply voltage VDD2 at power node NVDD2 has a second power supply voltage level of the second power domain. In power-off mode, each of the power supply voltages VDD1 at power node NVDD1 and VDD2 at power node NVDD2 has a reference voltage level (e.g., ground voltage level) of a reference voltage VSS at reference node NVSS. A voltage (e.g., power supply voltage VDD1) is considered to have a given voltage level by having a voltage level at or near a given voltage level (e.g., the first power supply voltage level).

[0025] In various embodiments, the first power supply voltage level is less than, equal to, or greater than the second power supply voltage level.

[0026] like Figure 1A As shown, the level shifting circuit 100 includes a bias circuit 110 coupled to the level shifter 120. The bias circuit 110 includes an input terminal 111 coupled to power node NVDD1, an input terminal 113 coupled to power node NVDD2, an input terminal 115 coupled to reference node NVSS, and an output terminal 112 coupled to the n-well NW. In some embodiments, the bias circuit 110 does not include the input terminal 115 coupled to the reference node NVSS.

[0027] like Figure 1B As shown, the level shifting circuit 100 is located in a substrate region 100S including an n-well NW. The substrate region (e.g., substrate region 100S) is some or all of a semiconductor wafer (e.g., a silicon (Si) wafer or an epitaxial Si layer) suitable for forming one or more IC devices. In some embodiments, the substrate region includes a p-type semiconductor (e.g., Si) having one or more acceptor dopants (e.g., boron (B) or aluminum (Al)). The n-well (e.g., n-well NW) is a portion of the semiconductor wafer located within the substrate region and including an n-type semiconductor (e.g., Si) having one or more donor dopants (e.g., phosphorus (P) or arsenic (As)).

[0028] The level shifter 120 includes an input terminal 121 (which is coupled to an n-well NW), an input terminal 123, an output terminal 122, and the level shifter 120 is coupled to each of the power supply nodes NVDD1 and NVDD2 and the reference node NVSS.

[0029] Two or more circuit elements are considered to be coupled based on one or more direct electrical connections and / or one or more indirect electrical connections between the two or more circuit elements (the one or more indirect electrical connections including one or more logic devices, such as inverters or logic gates). In some embodiments, the electrical communication between the two or more coupled circuit elements can be modified by one or more logic devices (e.g., inverted or conditionalized).

[0030] The bias circuit 110 is thus configured to receive a power supply voltage VDD1 at input terminal 111, a power supply voltage VDD2 at input terminal 113, and a reference voltage VSS (if present) at input terminal 115.

[0031] The bias circuit 110 includes two or more transistors. Figure 1A and Figure 1B (not shown in the image) (For example, see the reference below) Figure 3A and Figure 3B The PMOS transistors P4 and P5 are discussed, or refer to the following: Figure 4A and Figure 4B The electronic circuit of the PMOS transistors P6-P8 and NMOS transistor N4 is discussed and configured to generate a bias voltage VNW at the output terminal 112 (and thus at the n-well NW) based on the greater of the voltage level of the power supply voltage VDD1 or the voltage level of the power supply voltage VDD2.

[0032] In some embodiments, the bias circuit 110 is configured to generate a bias voltage VNW having a bias voltage level equal to the greater of a voltage level equal to a supply voltage VDD1 or a voltage level equal to a voltage level equal to a supply voltage VDD2. In some embodiments, the bias circuit 110 is configured to generate a bias voltage VNW having a fraction equal to the greater of a voltage level equal to a voltage level equal to a supply voltage VDD1 or a voltage level equal to ...

[0033] In various embodiments, the bias circuit 110 includes the following references Figure 3A and Figure 3B The bias circuit 300 discussed, or see the reference below. Figure 4A and Figure 4B The bias circuit 400 is discussed.

[0034] The level shifter 120 is configured as described above to receive power supply voltages VDD1 and VDD2, a reference voltage VSS, a bias voltage VNW at input terminal 121, and an input signal IN at input terminal 123, and to generate an output signal OUT at output terminal 122 in response to the input signal IN.

[0035] The input signal IN is an electronic signal configured to vary between a logic high state corresponding to the voltage level of the power supply voltage VDD1 and a logic low state corresponding to the reference voltage level of the reference voltage VSS.

[0036] Level shifter 120 includes at least one PMOS transistor ( Figure 1A and Figure 1B (not shown in the image) (For example, the following about Figure 2 The electronic circuit of the PMOS transistor P1 discussed includes a source / drain (S / D) terminal configured to receive a power supply voltage VDD1, a gate configured to receive an input signal IN, and a body terminal coupled to an n-well NW (thereby configured to receive a bias voltage VNW).

[0037] A body terminal is a transistor feature that corresponds to the substrate region or n-well in which the transistor is located. An S / D terminal is one of two features of a given transistor (which includes portions of the substrate region or n-well with the opposite doping type to the substrate region or n-well), for example, the p-type S / D terminal of a PMOS transistor located in an n-well.

[0038] Level shifter 120 includes two or more additional PMOS transistors ( Figure 1A and Figure 1B (not shown in the image) (For example, the following about Figure 2 The PMOS transistors P2 and P3 discussed each include an S / D terminal configured to receive a power supply voltage VDD2 and a body terminal coupled to an n-well NW (and thus configured to receive a bias voltage VNW).

[0039] In some embodiments, the level shifter 120 further includes one or more NMOS transistors ( Figure 1A and Figure 1B (not shown in the image), for example, the following about Figure 2 The NMOS transistors N1-N3 are discussed.

[0040] A level shifter 120, comprising at least one PMOS transistor, two or more additional PMOS transistors, and one or more NMOS transistors (if present), is configured to generate an output signal OUT in response to an input signal IN, the output signal OUT varying between a logic high state corresponding to a supply voltage VDD2 and a logic low state corresponding to a reference voltage VSS. In some embodiments, the output terminal 122 includes two signal paths, and the level shifter 120 is configured to generate the output signal OUT as a differential signal comprising complementary components on the signal paths, each component varying between a logic high state corresponding to a supply voltage VDD2 and a logic low state corresponding to a reference voltage VSS.

[0041] In some embodiments, the level shifter 120 includes the following about Figure 2 The level shifter 200 is under discussion.

[0042] like Figure 1BAs shown, the level shifting circuit 100 includes a portion located inside the n-well NW and a portion located outside the n-well NW. The PMOS transistor of each of the bias circuit 110 and the level shifter 120 is located inside the n-well NW, and other elements of the bias circuit 110 and / or the level shifter 120 (e.g., one or more NMOS transistors) are located outside the n-well. In some embodiments, the level shifting circuit 100 includes one or more circuit elements (not shown) in addition to those elements included in the bias circuit 110 and the level shifter 120 located inside and / or outside the n-well NW.

[0043] With the configuration discussed above, the PMOS transistor of the level shift circuit 100 includes a diode junction based on a p-type S / D terminal and an n-type body terminal corresponding to the n-well NW. The level shift circuit 100 includes a bias circuit 110 configured to bias the n-well NW by continuously generating a bias voltage VNW having one or more bias voltage levels sufficiently large to avoid forward biasing the diode junction of the PMOS transistor of the level shifter 120.

[0044] In operation, when both the first and second power domains are in power-on mode, the bias circuit 110 generates a bias voltage VNW with a bias voltage level based on the greater of a power supply voltage VDD1 having a first power supply voltage level or a power supply voltage VDD2 having a second power supply voltage level. When the first power domain is in power-on mode and the second power domain is in power-off mode, the bias circuit 110 generates a bias voltage VNW with a bias voltage level equal to all or part of the first power supply voltage level. When the first power domain is in power-off mode and the second power domain is in power-on mode, the bias circuit 110 generates a bias voltage VNW with a bias voltage level equal to all or part of the second power supply voltage level.

[0045] When each of the first and second power domains operates in power-down mode, the bias circuit 110 generates a bias voltage VNW with a bias voltage level equal to the reference voltage level, based on the fact that each power supply voltage VDD1 and VDD2 has a reference voltage level. Because the S / D terminal of each PMOS transistor in the level shifter 120 also has a reference voltage level based on the fact that each power supply voltage VDD1 and VDD2 has a reference voltage level, forward biasing of the junction diodes of the PMOS transistors is avoided.

[0046] In some embodiments, an n-well NW is one of a plurality of n-wells NWs, the PMOS transistor of the level shift circuit 100 is located inside the plurality of n-wells NWs, and the bias circuit 110 is configured to bias each of the plurality of n-wells NWs by generating a bias voltage VNW as described above, such that the diode junction of the PMOS transistor of the level shifter 120 is avoided from being forward biased.

[0047] In various embodiments, each of the single n-well NW and the plurality of n-well NWs configured to be biased by the bias voltage VNW generated by the bias circuit 110 is referred to as the common n-well of the level shift circuit 100.

[0048] In other methods where the level shifter includes PMOS transistors configured to operate in separate power domains and located in separately biased n-wells, the separately biased n-wells are spaced apart with minimal distance to reduce latch-up risk based on the bias voltage level of the separate power domain. In embodiments where the common n-well comprises a single n-well NW, n-well spacing is avoided. In embodiments where the common n-well comprises multiple n-well NWs, the n-well spacing can be reduced compared to the n-well spacing in other such methods because each n-well in the multiple n-well NWs is biased by the same bias voltage VNW.

[0049] By configuring as described above to avoid forward biasing the PMOS diode junction of the level shifter 120, the level shifter 100, which includes bias circuit 110, avoids latch-up risk and has reduced space requirements compared to a method where the level shifter includes a PMOS transistor configured to operate in a separate power domain and located in a separately biased n-well.

[0050] Figure 2 This is a schematic diagram of a level shifter 200 according to some embodiments. The level shifter 200 can be used as described above regarding... Figure 1A and Figure 1B The level shifter 120 is discussed.

[0051] Level shifter 200 includes power supply nodes NVDD1 and NVDD2, a reference node NVSS, input terminals 121 and 123, and output terminal 122, represented as signal paths 122A and 122B, as described above. Figure 1A and Figure 1B The level shifter 200 is thus configured to receive the power supply voltage VDD1 at power node NVDD1, the power supply voltage VDD2 at power node NVDD2, the reference voltage VSS at reference node NVSS, the bias voltage VNW at input terminal 121, and the signal IN at input terminal 123, each as described above regarding... Figure 1A and Figure 1B Discussed.

[0052] The level shifter 200 also includes PMOS transistors P1-P3, NMOS transistors N1-N3, and node ND1. PMOS transistor P1, node ND1, and NMOS transistor N1 are coupled in series between power node NVDD1 and reference node NVSS, and the gates of PMOS transistor P1 and NMOS transistor N1 are coupled to each other and to input terminal 123. PMOS transistor P1 and NMOS transistor N1 are thus arranged as an inverter configured to invert the signal IN received at input terminal 123 during operation and output the inverted signal IN at node ND1.

[0053] PMOS transistor P2, signal path 122A, and NMOS transistor N2 are coupled in series between power node NVDD2 and reference node NVSS. The gate of PMOS transistor P2 is coupled to signal path 122B, and the gate of NMOS transistor N2 is coupled to node ND1. PMOS transistor P3, signal path 122B, and NMOS transistor N3 are coupled in series between power node NVDD2 and reference node NVSS. The gate of PMOS transistor P3 is coupled to signal path 122A, and the gate of NMOS transistor N3 is coupled to input terminal 123.

[0054] PMOS transistors P2 and P3 and NMOS transistors N2 and N3 are thus configured to receive the input signal IN at input terminal 123 and the inverted input signal IN at node ND1 during operation, and to generate the output signal OUT as complementary components OUTA on signal path 122A and OUTB on signal path 122B, as described above. Figure 1A and Figure 1B Discussed.

[0055] The body terminal of each PMOS transistor P1-P3 is coupled to input terminal 121 and is thus configured to receive bias voltage VNW. In various embodiments, the body terminals of PMOS transistors P1-P3 are coupled to the same input terminal 121 (which is coupled to a single n-well NW) and are thus configured to receive bias voltage VNW, or the body terminals of PMOS transistors P1-P3 are coupled to multiple input terminals 121 (which are coupled to multiple n-well NW) and are thus configured to receive bias voltage VNW.

[0056] The body terminal of each NMOS transistor N1-N3 is coupled to the reference node NVSS and is thus configured to receive the reference voltage VSS.

[0057] With the configuration discussed above, level shifter 200 possesses the characteristics discussed above regarding level shifter 120, enabling circuit 100 including level shifter 200 to achieve the characteristics discussed above regarding level shifter 120. Figure 1A and Figure 1B Benefits of the discussion.

[0058] Figure 3A and Figure 4A These are schematic diagrams of corresponding bias circuits 300 and 400 according to some embodiments. Each bias circuit 300 and 400 can be used as described above regarding... Figure 1A and Figure 1B The bias circuit 110 is discussed.

[0059] Figure 3B It is based on IC layout diagram 100A of some embodiments and the above regarding Figure 1A and Figure 1B The corresponding embodiments of the level shifting circuit 100 discussed above (which include the above-mentioned...) Figure 2 The diagram shows the level shifter 200 and the bias circuit 300 discussed. Figure 4B This is an illustration of IC layout diagram 100B according to some embodiments and a corresponding embodiment of level shifting circuit 100 (which includes level shifter 200 and bias circuit 400). Figure 3B and Figure 4B The plan view depicts the level shifting circuit 100 and the corresponding IC layout diagrams 100A and 100B, each including an n-well NW located in the substrate region 100S and the X and Y directions, as described above. Figure 1B Discussed.

[0060] Each IC layout 100A and 100B is executed by following the reference. Figure 6 The discussion covers non-limiting examples of IC layout diagrams generated from some or all of the methods 600, and each corresponding embodiment of the level shifting circuit 100 is based on IC layout diagram 100A or 100B by performing the following... Figure 7 Non-limiting examples of IC structures manufactured using some or all of the methods discussed in 700.

[0061] Figure 3B and Figure 4B The illustrations have been simplified for illustrative purposes. Figure 3B and Figure 4B Views depicting IC layout diagram 100A or 100B and level shifting circuit 100 are provided, including and excluding various features to facilitate the discussion below. In various embodiments, besides... Figure 3B and Figure 4BIn addition to the depicted components, one or more of the IC layout diagram 100A or 100B or the level shift circuit 100 also include one or more components corresponding to the following: metal interconnects, contacts, vias, gate structures, S / D structures, or other transistor components, wells, isolation structures, etc.

[0062] The bias circuit 300 includes power nodes NVDD1 and NVDD2 and an output terminal 112, and is thereby configured to receive the power supply voltage VDD1 on power node NVDD1 and the power supply voltage VDD2 on power node NVDD2, respectively as described above. Figure 1A and Figure 1B Discussed.

[0063] The bias circuit 300 also includes PMOS transistors P4 and P5. PMOS transistor P4 is coupled between power node NVDD1 and output terminal 112, with its gate coupled to power node NVDD2 and its body coupled to output terminal 112. PMOS transistor P5 is coupled between power node NVDD2 and output terminal 112, with its gate coupled to power node NVDD1 and its body coupled to output terminal 112.

[0064] PMOS transistors P4 and P5 are thus arranged as cross-coupled PMOS transistors, wherein each of the first S / D terminal of PMOS transistor P4 and the gate of PMOS transistor P5 is configured to receive power supply voltage VDD1, and each of the first S / D terminal of PMOS transistor P5 and the gate of PMOS transistor P4 is configured to receive power supply voltage VDD2.

[0065] The second S / D terminals of PMOS transistors P4 and P5 are coupled to each other and to output terminal 112. In some embodiments, the second S / D terminals of PMOS transistors P4 and P5 are the same S / D terminal shared by PMOS transistors P4 and P5. In some embodiments, output terminal 112 corresponds to the n-well NW where PMOS transistors P4 and P5 are located.

[0066] In some embodiments, when both the first and second power domains are operating in a power-on mode, the first power supply voltage level of power supply voltage VDD1 is greater than the second power supply voltage level of power supply voltage VDD2 by an amount greater than the threshold voltage of PMOS transistor P4. When the first power domain is operating in a power-on mode and the second power domain is operating in a power-off mode, the first power supply voltage level of power supply voltage VDD1 is greater than the reference voltage level of power supply voltage VDD2 by an amount greater than the threshold voltage of PMOS transistor P4. In such an embodiment, when the first power domain is operating in a power-on mode, the bias circuit 300 is thereby configured to turn on PMOS transistor P4 and turn off PMOS transistor P5, regardless of whether the second power domain is in a power-on or power-off mode.

[0067] In some embodiments, when both the first and second power domains are operating in a power-on mode, the second power supply voltage level of power supply voltage VDD2 is greater than the first power supply voltage level of power supply voltage VDD1 by an amount greater than the threshold voltage of PMOS transistor P5. When the second power domain is operating in a power-on mode and the first power domain is operating in a power-off mode, the second power supply voltage level of power supply voltage VDD2 is greater than the reference voltage level of power supply voltage VDD1 by an amount greater than the threshold voltage of PMOS transistor P5. In such an embodiment, when the second power domain is operating in a power-on mode, the bias circuit 300 is thereby configured to turn on PMOS transistor P5 and turn off PMOS transistor P4, regardless of whether the first power domain is in a power-on or power-off mode.

[0068] Because the S / D terminal of PMOS transistor P4 is coupled to output terminal 112, the combination of PMOS transistor P4 being turned on and PMOS transistor P5 being turned off couples output terminal 112 to power node NVDD1, thereby generating a bias voltage VNW at output terminal 112 with a first power supply voltage level of power supply voltage VDD1. Because the S / D terminal of PMOS transistor P5 is coupled to output terminal 112, the combination of PMOS transistor P5 being turned on and PMOS transistor P4 being turned off couples output terminal 112 to power node NVDD2, thereby generating a bias voltage VNW at output terminal 112 with a second power supply voltage level of power supply voltage VDD2.

[0069] In each of the above embodiments, the bias circuit 300 is thus configured such that when the first power domain operates in a power-off mode, the bias circuit 300 generates a bias voltage VNW at the output terminal 112 with a voltage level of the power supply voltage VDD2, and when the second power domain operates in a power-off mode, the bias circuit 300 generates a bias voltage VNW at the output terminal 112 with a voltage level of the power supply voltage VDD1. When both the first and second power domains operate in a power-off mode, the bias circuit 300 is thus configured to generate a bias voltage VNW at the output terminal 112 with a reference voltage level for each power supply voltage VDD1 and VDD2.

[0070] exist Figure 3B In the illustrated embodiment, each of the PMOS transistors P1-P3 of the level shifter 200 and the PMOS transistors P4 and P5 of the bias circuit 300 is located in an n-well NW, and each of the NMOS transistors N1-N3 of the level shifter 200 is located outside the n-well NW in the substrate region 100S.

[0071] n-well (e.g., n-well NW) refers both to the region in an IC layout (e.g., IC layout 100A) and to the region of a semiconductor wafer located on the substrate (as mentioned above). Figure 1B The portion within the discussion is at least partially defined by the IC layout area included in the manufacturing process.

[0072] A transistor (e.g., PMOS transistors P1-P5 or NMOS transistors N1-N3) refers both to multiple regions in an IC layout diagram and to an IC device that is at least partially defined by multiple IC layout regions included in the manufacturing process. Figure 3B In the illustrated embodiment, the transistor includes an active region AR, one or more gate regions GR, and one or more conductive regions CR, which is a representative subset labeled with respect to the NMOS transistor N1.

[0073] An active region (e.g., an active region AR) refers both to a region in an IC layout and to a resulting structure at least partially defined by a region included in the manufacturing process. This structure is one or more continuum volumes of one or more semiconductor materials having n-type or p-type doping. In various embodiments, the active region structure includes one or more of the following: Si, silicon germanium (SiGe), silicon carbide (SiC), B, P, As, Al, gallium (Ga), or another suitable material. In some embodiments, the active region structure comprises a single monolayer or multiple monolayers of a given material.

[0074] In various embodiments, the active region structure includes one or more portions of one or more planar transistors, FinFETs, or gate-all-around (GAA) transistors, and / or includes one or more S / D structures (not shown). In some embodiments, the active region structure is electrically isolated from other elements in the semiconductor substrate region by one or more isolation structures (not shown) (e.g., one or more shallow trench isolation (STI) structures).

[0075] A gate region (e.g., gate region GR) refers both to a region in an IC layout and to a resulting structure at least partially defined by a region included in the manufacturing process. A gate region structure is a bulk above a semiconductor substrate and an active region, and includes one or more conductive materials substantially surrounded by one or more dielectric layers (not shown), which include one or more dielectric materials configured to electrically isolate this one or more conductive materials from above, below, and / or adjacent structures (e.g., active region AR).

[0076] The conductive material includes one or more of the following: polycrystalline silicon, Al, copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), or one or more other metals, and / or one or more other suitable materials. The dielectric material includes one or more of the following: silicon dioxide (SiO2), silicon nitride (Si3N4), and / or high-k dielectric materials, for example, dielectric materials with a k value greater than 3.8 or 7.0, such as alumina (Al2O3), hafnium oxide (HfO2), tantalum pentoxide (Ta2O5), or titanium oxide (TiO2), or other suitable materials.

[0077] In some cases, the location where the gate region intersects with the active region in the IC layout corresponds to a transistor in the IC structure. This transistor includes some or all of the corresponding gate structure, some or all of the corresponding active region partially surrounded and / or adjacent to the corresponding gate structure, and an S / D structure within and / or above the corresponding active region and adjacent to the corresponding gate structure. In other cases, the gate region intersects with the active region at a location that does not correspond to a transistor, and in some embodiments, the corresponding gate structure or a portion thereof is referred to as a dummy gate structure.

[0078] A conductive region (e.g., a conductive region CR) refers both to a region in an IC layout and to a resulting structure at least partially defined by a region included in the manufacturing process. A conductive region structure (also referred to in some embodiments as a conductive segment, conductive line, or via) is one or more portions of one or more corresponding layers comprising one or more conductive materials suitable for providing low-resistance electrical connections between IC structural elements, i.e., resistance levels below a predetermined threshold corresponding to one or more permissible levels of resistance-based impact on circuit performance. In some embodiments, a conductive region refers to multiple conductive regions in an IC layout and corresponding multiple resulting structures (e.g., conductive segments and vias).

[0079] In some embodiments, one or more conductive regions correspond to nodes, for example, as mentioned above. Figure 1A-Figure 2 The reference node NVSS or power node NVDD1 or NVDD2 discussed below, or the following regarding... Figure 4A and Figure 4B The power nodes discussed are one or more of the NVDDA or NVDDB. In some embodiments, one or more conductive regions correspond to the power distribution structure (e.g., as mentioned above). Figure 1A and Figure 1B The discussion concerns one or more parts of the power distribution structure of the power domain.

[0080] exist Figure 3B In the illustrated embodiment, IC layout 100A includes an n-well NW, an active region AR, a gate region GR, and a conductive region CR, which are thus arranged to at least partially define PMOS transistors P1-P3 and NMOS transistors N1-N3 configured according to level shifter 200, and PMOS transistors P4 and P5 configured according to bias circuit 300 (corresponding to the embodiment of level shifter circuit 100 described above). In some embodiments, layout 100A includes an n-well NW, an active region AR, a gate region GR, and a conductive region CR, which (e.g., by including the regions arranged as described above) Figure 1B The multiple n-wells (NW) of the common n-well discussed are arranged such that PMOS transistors P1-P3 and NMOS transistors N1-N3 are configured according to level shifter 200, and PMOS transistors P4 and P5 are configured according to bias circuit 300 (corresponding to the embodiment of level shifter circuit 100 described above).

[0081] With the above configuration, the bias circuit 300 can generate a bias voltage VNW having the voltage level discussed above regarding the bias circuit 110, enabling the circuit 100 including the bias circuit 300 to achieve the above-mentioned... Figure 1A and Figure 1B Benefits of the discussion.

[0082] The bias circuit 400 includes a reference node NVSS and an output terminal 112, and is thereby configured to receive a reference voltage VSS on the reference node NVSS, as described above. Figure 1A and Figure 1B The bias circuit 400 also includes a power node NVDDA configured to have a supply voltage VDDA and a power node NVDDB configured to have a supply voltage VDDB.

[0083] In some embodiments, the power nodes NVDDA and NVDDB correspond to the above regarding Figure 1A and Figure 1B The corresponding power nodes NVDD1 and NVDD2 are discussed such that the bias circuit 400 is configured to receive the power voltage VDDA at power node NVDDA corresponding to the power supply voltage VDD1, and the power voltage VDDB at power node NVDDB corresponding to the power supply voltage VDD2. In some embodiments, power nodes NVDDA and NVDDB correspond to corresponding power nodes NVDD2 and NVDD1, such that the bias circuit 400 is configured to receive the power voltage VDDA at power node NVDDA corresponding to the power supply voltage VDD2, and the power voltage VDDB at power node NVDDB corresponding to the power supply voltage VDD1.

[0084] When both the first and second power domains are operating in power-on mode, the voltage level of the power supply voltage VDDB is greater than the voltage level of the power supply voltage VDDA.

[0085] The bias circuit 400 also includes PMOS transistors P6-P8, an NMOS transistor N4, and node ND2. PMOS transistor P6, node ND2, and NMOS transistor N4 are coupled in series between the power supply node NVDDA and the reference node NVSS, and the gates of PMOS transistor P6 and NMOS transistor N4 are coupled to each other and to the power supply node NVDDB. PMOS transistor P6, node ND2, and NMOS transistor N4 are thus arranged as an inverter configured to receive the power supply voltage VDDB. The body terminal of PMOS transistor P6 is coupled to the output terminal 112, and the body terminal of NMOS transistor N4 is coupled to the reference node NVSS.

[0086] PMOS transistor P7 is coupled between power node NVDDB and output terminal 112. The gate of transistor P7 is coupled to node ND2, and the body terminal of transistor P7 is coupled to output terminal 112. PMOS transistor P8 is coupled between power node NVDDA and output terminal 112. The gate of transistor P8 is coupled to power node NVDDB, and the body terminal of transistor P8 is coupled to output terminal 112.

[0087] The S / D terminals of PMOS transistors P7 and P8 are coupled to each other and to output terminal 112. In some embodiments, the S / D terminals of PMOS transistors P7 and P8 are the same S / D terminal shared by PMOS transistors P7 and P8. In some embodiments, output terminal 112 corresponds to the n-well NW where PMOS transistors P7 and P8 are located.

[0088] When the power domain corresponding to the supply voltage VDDB (the VDDB domain) operates in power-on mode, the voltage level of the supply voltage VDDB is greater than the reference voltage level of the reference voltage VSS by a greater margin than the threshold voltage of NMOS transistor N4. This causes NMOS transistor N4 to be turned on, regardless of the power-on or power-off mode of the power domain corresponding to the supply voltage VDDA (the VDDA domain). Because the voltage level of the supply voltage VDDB is greater than the voltage level of the supply voltage VDDA (regardless of the power-on or power-off mode of the VDDA domain), the operation of the VDDB domain in power-on mode causes each PMOS transistor P6 and P8 to be turned off, regardless of the power-on or power-off mode of the VDDA domain.

[0089] The NMOS transistor N4 being turned on and the PMOS transistor P6 being turned off couples node ND2 to the reference node NVSS and decouples node ND2 from the power supply node NVDDA, so that the voltage VND2 on node ND2 has the reference voltage level. The power supply voltage VDDB is greater than the reference voltage level by a factor greater than the threshold voltage of PMOS transistor P7, causing PMOS transistor P7 to be turned on. When the power supply voltage VDDB domain is operating in power-on mode, PMOS transistor P7 is thus turned on and PMOS transistor P8 is thus turned off, regardless of whether the power supply voltage VDDA domain is in power-on or power-off mode.

[0090] Because the S / D terminal of PMOS transistor P7 is coupled to output terminal 112, the combination of PMOS transistor P7 being turned on and PMOS transistor P8 being turned off couples output terminal 112 to power node NVDDB, and bias circuit 400 is thus configured to generate a bias voltage VNW at output terminal 112 with a voltage level of power supply voltage VDDB, regardless of the power-on or power-off mode of the power supply voltage VDDA domain.

[0091] When the power supply voltage VDDA domain operates in power-on mode and the power supply voltage VDDB domain operates in power-off mode, the power supply voltage VDDB has a reference voltage level that turns off NMOS transistor N4. The voltage level of the power supply voltage VDDA is greater than the reference voltage level of the power supply voltage VDDB by a greater margin than the threshold voltages of PMOS transistors P6 and P8, causing each PMOS transistor P6 and P8 to be turned on.

[0092] The NMOS transistor N4 is turned off and the PMOS transistor P6 is turned on, coupling node ND2 to the power node NVDDA and decoupling node ND2 from the reference node NVSS, so that the voltage VND2 on node ND2 has the voltage level of the power supply voltage VDDA. The voltage level of the power supply voltage VDDA is greater than the reference voltage level of the power supply voltage VDDB, causing the PMOS transistor P7 to be turned off. When the power supply voltage VDDA domain operates in power-on mode and the power supply voltage VDDB domain operates in power-off mode, the PMOS transistor P8 is turned on and the PMOS transistor P7 is turned off.

[0093] Because the S / D terminal of PMOS transistor P8 is coupled to output terminal 112, the combination of PMOS transistor P8 being turned on and PMOS transistor P7 being turned off couples output terminal 112 to power node NVDDA, and bias circuit 400 is thus configured to generate a bias voltage VNW with the voltage level of power supply voltage VDDA on output terminal 112 when the power supply voltage VDDA domain operates in power-on mode and the power supply voltage VDDB domain operates in power-off mode.

[0094] When each of the power supply voltage domains VDDA and VDDB is operating in power-off mode, the bias circuit 400 is thus configured to generate a bias voltage VNW with a reference voltage level at the output terminal 112.

[0095] exist Figure 4B In the illustrated embodiment, each of the PMOS transistors P1-P3 of the level shifter 200 and the PMOS transistors P6-P8 of the bias circuit 400 is located in the n-well NW, and each of the NMOS transistors N1-N3 of the level shifter 200 and the NMOS transistor N4 of the bias circuit 400 is located outside the n-well NW in the substrate region 100S.

[0096] exist Figure 4BIn the illustrated embodiment, IC layout 100B includes an n-well NW, an active region AR, a gate region GR, and a conductive region CR, which are thus arranged to at least partially define PMOS transistors P1-P3 and NMOS transistors N1-N3 configured according to level shifter 200, and PMOS transistors P6-P8 and NMOS transistor N4 configured according to bias circuit 400 (corresponding to the embodiment of level shifter circuit 100 described above). In some embodiments, layout 100B includes an n-well NW, an active region AR, a gate region GR, and a conductive region CR, which (e.g., by including the regions arranged as described above) Figure 1B The multiple n-wells (NW) of the common n-well discussed are arranged such that PMOS transistors P1-P3 and NMOS transistors N1-N3 are configured according to level shifter 200, and PMOS transistors P6-P8 and NMOS transistor N4 are configured according to bias circuit 400 (corresponding to the embodiment of level shifter circuit 100 described above).

[0097] With the above configuration, the bias circuit 400 can generate a bias voltage VNW having the voltage level discussed above regarding the bias circuit 110, enabling the circuit 100 including the bias circuit 400 to achieve the above-mentioned... Figure 1A and Figure 1B Benefits of the discussion.

[0098] Compared to bias circuit 300, bias circuit 400 includes additional features, and thus is further capable of generating a bias voltage VNW having the voltage level discussed above with respect to bias circuit 110 in the following embodiments: in the embodiments, the voltage level of power supply voltage VDDB (corresponding to one of power supply voltages VDD1 or VDD2) is greater than the voltage level of power supply voltage VDDA (corresponding to the other of power supply voltages VDD1 or VDD2) by a magnitude less than the threshold voltage of the corresponding PMOS transistor (e.g., PMOS transistor P4 or P5).

[0099] Figure 5 This is a flowchart of a method 500 for operating a level shifting circuit according to one or more embodiments. Method 500 can be used with a level shifting circuit (e.g., as described above regarding...). Figure 1A and Figure 1B The circuit 100 discussed is used together.

[0100] exist Figure 5 The order of operations of method 500 described herein is for illustrative purposes only; the operations of method 500 can be performed in conjunction with... Figure 5 The different sequences of execution described herein. In some embodiments, also Figure 5 The operations described in the text are performed before, between, during, and / or after the operations, except for... Figure 5Other operations besides those described in the text.

[0101] In some embodiments, some or all of the operations of method 500 are subsets of methods for operating circuits including level shifting circuits (e.g., input / output circuits, or power or sleep mode control circuits).

[0102] At operation 510, a first power supply voltage and a second power supply voltage are received at the bias circuit. Receiving the first power supply voltage includes receiving a first power supply voltage having a first power supply voltage level equal to the first power supply voltage level of the first power supply domain or a reference voltage level. In some embodiments, receiving a first power supply voltage having a first voltage level equal to the first power supply voltage level includes operating the first power supply domain in a power-on mode; and receiving a first power supply voltage having a first voltage level equal to the reference voltage level includes operating the first power supply domain in a power-off mode.

[0103] Receiving a second power supply voltage includes receiving a second power supply voltage having a second power supply voltage level equal to that of a second power supply domain or a reference voltage level. In some embodiments, receiving a second power supply voltage having a second voltage level equal to that of a second power supply voltage level includes operating the second power supply domain in a power-on mode; and receiving a second power supply voltage having a second voltage level equal to that of a reference voltage level includes operating the second power supply domain in a power-off mode.

[0104] Receiving a first power supply voltage and a second power supply voltage having a first voltage level equal to a first power supply voltage level and / or a second voltage level equal to a second power supply voltage level includes: the first power supply voltage level being different from the second power supply voltage level.

[0105] In some embodiments, receiving a first power supply voltage and a second power supply voltage at the bias circuit includes: as stated above regarding Figure 1A and Figure 1B The bias circuit 110 discussed above or related to Figure 3A and Figure 3B The bias circuit 300 discussed receives power supply voltages VDD1 and VDD2 at one of its locations. In some embodiments, receiving the first and second power supply voltages at the bias circuit includes: as discussed above... Figure 4A and Figure 4B The bias circuit discussed receives power supply voltages VDDA and VDDB at point 400.

[0106] In some embodiments, receiving the first power supply voltage and the second power supply voltage at the bias circuit includes: receiving the first power supply voltage and the second power supply voltage at the S / D terminal of the PMOS transistor of the bias circuit. In some embodiments, receiving the first power supply voltage and the second power supply voltage at the bias circuit includes: as mentioned above... Figure 3A and Figure 3B The bias circuit 300 discussed receives power supply voltages VDD1 and VDD2 at the S / D terminals of PMOS transistors P4 and P5, or as mentioned above. Figure 4A and Figure 4B The bias circuit 400 discussed receives power supply voltages VDDA and VDDB at the S / D terminals of PMOS transistors P6-P8.

[0107] At operation 520, a bias circuit is used to generate a bias voltage based on the greater of a first voltage level of a first supply voltage or a second voltage level of a second supply voltage. In various embodiments, generating the bias voltage includes generating a bias voltage having a bias voltage level equal to the greater of the first voltage level or the second voltage level, or having a bias voltage level equal to a portion of the greater of the first voltage level or the second voltage level.

[0108] In some embodiments, generating a bias voltage includes: operating each of a first power domain and a second power domain in a power-on mode; and generating a bias voltage having a first voltage level based on a first voltage level being greater than a second voltage level, or generating a bias voltage having a second voltage level based on a second voltage level being greater than a first voltage level.

[0109] In some embodiments, generating a bias voltage includes: operating a first power domain in a power-on mode and operating a second power domain in a power-off mode; and generating a bias voltage having a first voltage level based on a first voltage level being greater than a reference voltage level.

[0110] In some embodiments, generating a bias voltage includes: operating a first power domain in a power-down mode and operating a second power domain in a power-on mode; and generating a bias voltage having a second voltage level based on the second voltage level being greater than a reference voltage level.

[0111] In some embodiments, generating a bias voltage includes: operating each of a first power domain and a second power domain in a power-down mode; and generating a bias voltage having a reference voltage level based on the fact that each of the first power supply voltage and the second power supply voltage has a reference voltage level.

[0112] In some embodiments, using a bias circuit to generate a bias voltage includes: using the above-mentioned... Figure 1A and Figure 1B The bias circuit 110 discussed above, regarding... Figure 3A and Figure 3B The bias circuit 300 discussed above, or the bias circuit mentioned above... Figure 4A and Figure 4B One of the bias circuits 400 discussed is used to generate the bias voltage VNW.

[0113] In some embodiments, using a bias circuit to generate a bias voltage includes using two PMOS transistors in a bias circuit, the two PMOS transistors being located in a common n-well and including an S / D terminal coupled to each other. In some embodiments, using a PMOS transistor located in a common n-well and including an S / D terminal coupled to each other includes using an S / D terminal shared by the two PMOS transistors. In some embodiments, using two PMOS transistors located in a common n-well includes using two PMOS transistors located in one or more n-wells NW, as described above regarding... Figures 1A-4B Discussed.

[0114] In some embodiments, using two PMOS transistors, each including an S / D terminal coupled to the other, to generate a bias voltage includes: generating a bias voltage having a first voltage level by turning on one of the two PMOS transistors, and generating a bias voltage having a second voltage level by turning on the other of the two PMOS transistors.

[0115] In some embodiments, using two PMOS transistors, including S / D terminals coupled to each other, to generate a bias voltage includes: using the above-mentioned... Figure 3A and Figure 3B The bias circuit 300 discussed uses PMOS transistors P4 and P5, or the above regarding... Figure 4A and Figure 4B The bias circuit 400 discussed uses PMOS transistors P7 and P8.

[0116] At operation 530, a first power supply voltage is received at the first S / D terminal of the first PMOS transistor of the level shifter. Receiving the first power supply voltage at the first S / D terminal of the first PMOS transistor of the level shifter includes: the first PMOS transistor is located in a common n-well, for example, an n-well NW or multiple n-wells NW, as described above. Figures 1A-4B Discussed.

[0117] In some embodiments, receiving a first power supply voltage at the first S / D terminal of the first PMOS transistor of the level shifter includes: receiving a power supply voltage VDD1 at the level shifter 120, as described above. Figure 1A and Figure 1B Discussed. In some embodiments, receiving a first power supply voltage at the first S / D terminal of the first PMOS transistor of the level shifter includes: receiving a power supply voltage VDD1 at the S / D terminal of the PMOS transistor P1 of the level shifter 200, as described above regarding... Figure 2 Discussed.

[0118] In some embodiments, receiving a first power supply voltage at the first S / D terminal of the first PMOS transistor includes receiving the first power supply voltage at an inverter including the first PMOS transistor. In some embodiments, receiving the first power supply voltage at the inverter includes receiving a power supply voltage VDD1 at the S / D terminal of a PMOS transistor P1 that is series coupled to an NMOS transistor N1, as described above. Figure 2 Discussed.

[0119] At operation 540, a second power supply voltage is received at the second S / D terminal of the second PMOS transistor of the level shifter. Receiving the second power supply voltage at the second S / D terminal of the second PMOS transistor of the level shifter includes: the second PMOS transistor is located in a common n-well, for example, an n-well NW or multiple n-wells NW, as described above. Figures 1A-4B Discussed.

[0120] In some embodiments, receiving the second power supply voltage at the second S / D terminal of the second PMOS transistor of the level shifter includes: receiving a power supply voltage VDD2 at the level shifter 120, as described above. Figure 1A and Figure 1B Discussed. In some embodiments, receiving the second power supply voltage at the second S / D terminal of the second PMOS transistor of the level shifter includes: receiving a power supply voltage VDD2 at the S / D terminal of the PMOS transistor P2 or P3 of the level shifter 200, as described above regarding... Figure 2 Discussed.

[0121] In some embodiments, receiving the second power supply voltage at the second S / D terminal of the second PMOS transistor includes receiving the second power supply voltage at a cross-coupled transistor pair including the second PMOS transistor. In some embodiments, receiving the second power supply voltage at the cross-coupled transistor pair includes receiving a power supply voltage VDD2 at the S / D terminal of one of the cross-coupled PMOS transistors P2 or P3, as described above. Figure 2 Discussed.

[0122] At operation 550, a bias voltage is used to bias the common n-well containing the first PMOS transistor and the second PMOS transistor. In some embodiments, biasing the common n-well using a bias voltage includes biasing the n-well NW using a bias voltage VNW, as described above regarding... Figures 1A-4B Discussed.

[0123] In some embodiments, using a bias voltage to bias a common n-well includes: operating each of a first power domain and a second power domain in a power-on mode; and using a bias voltage having a first voltage level based on a first voltage level being greater than a second voltage level, or using a bias voltage having a second voltage level based on a second voltage level being greater than a first voltage level.

[0124] In some embodiments, operating each of the first and second power domains in a power-on mode includes: receiving an input signal at an input terminal of a level shifter; and generating an output signal at an output terminal of the level shifter in response to the input signal. In some embodiments, receiving the input signal includes: receiving an input signal IN, as described above regarding... Figure 1A-Figure 2 The discussion continues. In some embodiments, generating an output signal includes generating an output signal OUT, as discussed above. Figure 1A-Figure 2 The discussion, or the generation of complementary components OUTA and OUTB, as mentioned above... Figure 2 Discussed.

[0125] In some embodiments, using a bias voltage to bias a common n-well includes: operating a first power domain in a power-on mode and operating a second power domain in a power-off mode; and using a bias voltage having a first voltage level based on the first voltage level being greater than a reference voltage level.

[0126] In some embodiments, using a bias voltage to bias a common n-well includes: operating a first power domain in a power-down mode and operating a second power domain in a power-on mode; and using a bias voltage having a second voltage level based on the second voltage level being greater than a reference voltage level.

[0127] In some embodiments, biasing a common n-well using a bias voltage includes: operating each of a first power domain and a second power domain in a power-down mode; and using a bias voltage having a reference voltage level based on the fact that each of the first power voltage and the second power voltage has a reference voltage level.

[0128] In some embodiments, using a bias voltage to bias the common n-well includes: reverse biasing the diode junction of the first PMOS transistor and the second PMOS transistor. In some embodiments, reverse biasing the diode junction of the first PMOS transistor and the second PMOS transistor includes: reverse biasing the diode junction of the PMOS transistors P1-P3 of the level shifter 200, as described above. Figure 2 Discussed.

[0129] By performing some or all of the operations of method 500, a bias voltage is generated by the bias circuit and used to bias the common n-well (in which the PMOS transistor of the level shifter operates), thereby obtaining the benefits discussed above regarding the level shift circuit 100.

[0130] Figure 6 This is a flowchart of a method 600 for generating an IC layout diagram according to some embodiments. In some embodiments, generating the IC layout diagram includes: generating an IC layout diagram, such as IC layout diagram 100A or 100B corresponding to a level shifting circuit 100 manufactured based on the generated IC layout diagram, as described above regarding... Figures 1A-4B Discussed.

[0131] In some embodiments, some or all of method 600 is executed by a computer processor. In some embodiments, some or all of method 600 is executed by the processor 802 of the IC layout generation system 800, as described below. Figure 8 Discussed.

[0132] Some or all of the operations of method 600 can be performed in the design room (for example, see below for reference). Figure 9 The design process is carried out as part of the design process discussed in Design Room 920.

[0133] In some embodiments, the operation of method 600 is as follows: Figure 6 The described sequence of execution. In some embodiments, the operations of method 600 are performed concurrently, and / or in conjunction with... Figure 6 The described order of execution differs. In some embodiments, one or more operations are performed before, between, during, and / or after one or more operations of method 600.

[0134] At operation 610, in some embodiments, a first PMOS transistor to a fourth PMOS transistor are defined in the n-well region. Defining the first PMOS transistor to the fourth PMOS transistor includes at least partially defining each of the first PMOS transistor to the fourth PMOS transistor by arranging a plurality of IC layout regions in the IC layout. In some embodiments, arranging the plurality of IC layout regions includes arranging an active region AR in the n-well NW and intersecting the active region AR with the gate region GR, each as described above regarding... Figure 3B and Figure 4B Discussed.

[0135] In some embodiments, defining the first PMOS transistor to the fourth PMOS transistor in the n-well region includes: defining the first PMOS transistor to the fourth PMOS transistor in the n-well region NW, as described above. Figures 1A-5 Discussed. In some embodiments, defining the first PMOS transistor to the fourth PMOS transistor in an n-well NW includes defining the first PMOS transistor to the fourth PMOS transistor in a common n-well comprising a plurality of n-wells NW.

[0136] In some embodiments, defining the first PMOS transistor to the fourth PMOS transistor includes defining the first PMOS transistor and the second PMOS transistor as described above with respect to the bias circuit 300 and Figure 3A and Figure 3B The PMOS transistors P4 and P5 are discussed. In some embodiments, defining the first PMOS transistor to the fourth PMOS transistor includes defining the first PMOS transistor and the second PMOS transistor as described above with respect to the bias circuit 400 and Figure 4A and Figure 4B The PMOS transistors P6-P8 are discussed.

[0137] In some embodiments, defining the third PMOS transistor and the fourth PMOS transistor among the first to fourth PMOS transistors includes: defining the above regarding Figures 2-4B The PMOS transistors P1-P3 are discussed.

[0138] In some embodiments, defining the first to fourth PMOS transistors in the n-well region includes defining one or more NMOS transistors outside the n-well region, for example, as mentioned above. Figures 2-4B The NMOS transistors N1-N3 discussed and / or the above regarding Figure 4A and Figure 4B The NMOS transistor N4 is discussed.

[0139] At operation 620, multiple conductive regions are arranged, thereby configuring a bias circuit to include a first PMOS transistor and a second PMOS transistor, and configuring a level shifter to include a third PMOS transistor and a fourth PMOS transistor. In some embodiments, configuring the bias circuit to include the first PMOS transistor and the second PMOS transistor includes configuring the bias circuit 110 as described above. Figure 1A and Figure 1B The discussion continues. In some embodiments, configuring the bias circuit to include a first PMOS transistor and a second PMOS transistor includes: configuring the bias circuit 300 to include PMOS transistors P4 and P5, as discussed above. Figure 3A and Figure 3B The discussion continues. In some embodiments, configuring the bias circuit to include a first PMOS transistor and a second PMOS transistor includes: configuring the bias circuit 400 to include PMOS transistors P6-P8, as discussed above. Figure 4A and Figure 4B Discussed.

[0140] In some embodiments, configuring the level shifter to include a third PMOS transistor and a fourth PMOS transistor includes: configuring the level shifter 120 as described above. Figure 1A and Figure 1B The discussion continues. In some embodiments, configuring the level shifter to include a third PMOS transistor and a fourth PMOS transistor includes: configuring the level shifter 200 to include PMOS transistors P1-P3, as discussed above. Figures 2-4B Discussed.

[0141] Arranging multiple conductive regions includes: defining a conductive structure at least partially by arranging multiple conductive regions in an IC layout diagram. In some embodiments, arranging multiple conductive regions includes: arranging conductive regions CR, as described above regarding... Figure 3B and Figure 4B Discussed.

[0142] At operation 630, a plurality of conductive elements are arranged such that a first power domain includes electrical connections to each of a first PMOS transistor and a third PMOS transistor, and a second power domain includes electrical connections to each of a second PMOS transistor and a fourth PMOS transistor. Arranging the plurality of conductive elements includes arranging conductive regions corresponding to each of the first and second power domains, thereby at least partially defining electrical connections to the S / D structure of each of the first to fourth PMOS transistors.

[0143] In some embodiments, arranging multiple conductive elements includes: configuring the power distribution structure of a first power domain to include power node NVDD1, and configuring the power distribution structure of a second power domain to include power node NVDD2, each as described above. Figures 1A-4B The discussion continues. In some embodiments, arranging multiple conductive elements includes configuring the power distribution structure of the first power domain and the second power domain to include power nodes NVDDA and NVDDB, as discussed above. Figure 4A and Figure 4B Discussed.

[0144] In some embodiments, arranging multiple conductive elements includes configuring one or more power distribution structures to include a reference node NVSS, as described above. Figures 1A-4B Discussed.

[0145] At operation 640, in some embodiments, an IC layout pattern including n wells is generated. In some embodiments, generating the IC layout pattern includes generating IC layout pattern 100A or 100B, as described above regarding... Figure 3B and Figure 4B Discussed.

[0146] At operation 650, in some embodiments, the IC layout diagram is stored in a storage device. The generation of the IC layout diagram is performed by a processor (e.g., as described below regarding...). Figure 8The IC layout generation system 800 discussed is executed by processor 802.

[0147] In various embodiments, storing the IC layout diagram in a storage device includes storing the IC layout diagram in a non-volatile computer-readable storage medium or a layout library (e.g., a database), and / or includes storing the IC layout diagram on a network. In various embodiments, storing the IC layout diagram in a storage device includes storing the IC layout diagram in a layout library 807 of the IC layout diagram generation system 800 and / or on a network 814, as described below. Figure 8 Discussed.

[0148] In some embodiments, the memory IC layout diagram includes: memory IC layout diagram 100A or 100B, as described above. Figure 3B and Figure 4B Discussed.

[0149] At operation 660, in some embodiments, at least one of one or more semiconductor masks, or at least one component of a layer of a semiconductor IC, is fabricated based on an IC layout diagram. The following concerns IC manufacturing system 900 and... Figure 9 The invention discusses at least one component in the fabrication of one or more semiconductor masks or layers of a semiconductor IC.

[0150] In some embodiments, the fabrication of one or more semiconductor masks, or at least one component of a layer of a semiconductor IC, is based on IC layout diagram 100A or 100B, as described above. Figure 3B and Figure 4B Discussed.

[0151] At operation 670, in some embodiments, one or more manufacturing operations are performed based on an IC layout diagram. In some embodiments, performing one or more manufacturing operations includes performing one or more photolithographic exposures based on the IC layout diagram. The following is about... Figure 9 The execution of one or more manufacturing operations (e.g., one or more photolithography exposures) based on IC layout diagrams is discussed.

[0152] In some embodiments, one or more manufacturing operations are performed based on IC layout diagram 100A or 100B, as described above. Figure 3B and Figure 4B Discussed.

[0153] By performing some or all of the operations of method 600, an IC layout diagram (e.g., IC layout diagram 100A or 100B) is generated, which is capable of at least partially defining a level shifting circuit (configured according to the above discussion regarding level shifting circuit 100) including bias circuitry and level shifter, and thereby possessing the capabilities and benefits discussed above regarding level shifting circuit 100.

[0154] Figure 7 This is a flowchart of a method 700 for manufacturing an IC structure according to some embodiments.

[0155] Method 700 is operable for forming IC structures, for example, as mentioned above. Figures 1A-5 The level shifting circuit 100 is discussed. In some embodiments, one or more operations of method 700 are based on the above regarding... Figure 3B and Figure 4B The IC layout diagram 100A or 100B discussed is implemented in accordance with one or both.

[0156] In some embodiments, method 700 may be used by an IC manufacturing system as part of an IC manufacturing process, for example, as described below. Figure 9 The IC manufacturing system 900 is under discussion.

[0157] exist Figure 7 The order of operations of method 700 described herein is for illustrative purposes only; the operations of method 700 can be performed simultaneously and / or in conjunction with... Figure 7 The different sequences of execution described herein. In some embodiments, also Figure 7 The operations described in the text are performed before, between, during, and / or after the operations, except for... Figure 7 Other operations besides those described in the text.

[0158] In some embodiments, one or more operations of method 700 are performed using various manufacturing tools, such as one or more of the following: wafer stepper, photoresist coater, ion implanter, processing chamber (e.g., CVD chamber or LPCVD furnace), CMP system, plasma etching system, wafer cleaning system, or other manufacturing equipment capable of performing one or more suitable manufacturing processes discussed below.

[0159] At operation 710, in some embodiments, an n-well is formed in a semiconductor substrate. Forming an n-well includes performing one or more suitable fabrication processes, such as photolithography and / or ion implantation processes.

[0160] In some embodiments, forming an n-well includes: forming a common n-well comprising one or more n-wells NW, as described above regarding... Figures 1A-4B Discussed. In some embodiments, forming an n-well includes: forming an n-well NW based on the n-well NW of IC layout diagram 100A or 100B, as discussed above. Figure 3B and Figure 4B Discussed.

[0161] At operation 720, a first PMOS transistor to a fourth PMOS transistor is formed in an n-well. Forming the first PMOS transistor to the fourth PMOS transistor includes performing multiple suitable fabrication processes, such as photolithography, etching, deposition, and / or ion implantation processes.

[0162] In some embodiments, forming the first PMOS transistor and the second PMOS transistor among the first to fourth PMOS transistors includes: forming the bias circuit 300 and... Figure 3A and Figure 3B The PMOS transistors P4 and P5 are discussed. In some embodiments, forming the first PMOS transistor and the second PMOS transistor among the first to fourth PMOS transistors includes: forming the bias circuit 400 as described above. Figure 4A and Figure 4B The PMOS transistors P6-P8 are discussed.

[0163] In some embodiments, forming the third and fourth PMOS transistors among the first to fourth PMOS transistors includes: forming the above-mentioned... Figures 2-4B The PMOS transistors P1-P3 are discussed.

[0164] In some embodiments, forming the first to fourth PMOS transistors in the n-well region includes: forming one or more NMOS transistors outside the n-well, for example, as mentioned above. Figures 2-4B The NMOS transistors N1-N3 discussed, and / or the above regarding Figure 4A and Figure 4B The NMOS transistor N4 is discussed.

[0165] In some embodiments, forming the first to fourth back-side via structures includes: forming a semiconductor wafer including an IC structure (e.g., the one mentioned above). Figures 1A-5 The substrate 100S under discussion was subjected to a thinning operation.

[0166] At operation 730, a bias circuit including a first PMOS transistor and a second PMOS transistor, and a level shifter including a third PMOS transistor and a fourth PMOS transistor are constructed. Constructing the bias circuit and the level shifter includes configuring a plurality of conductive segments supported and electrically isolated by one or more insulating layers. In some embodiments, configuring the plurality of conductive segments includes performing one or more manufacturing processes suitable for creating conductive structures arranged according to circuit configuration requirements, such as one or more deposition, patterning, etching, planarization, and / or cleaning processes.

[0167] In some embodiments, forming one or more insulating layers includes: depositing one or more insulating materials, such as dielectric materials, as described above. Figure 1B , Figure 3B and Figure 4B Discussed. In some embodiments, forming a conductive segment includes performing one or more deposition processes to deposit one or more conductive materials, as described above. Figure 1B , Figure 3B and Figure 4B Discussed.

[0168] In some embodiments, forming a conductive segment includes: forming a conductive segment based on a conductive region CR, as described above. Figure 3B and Figure 4B Discussed.

[0169] In some embodiments, forming a bias circuit including a first PMOS transistor and a second PMOS transistor includes: forming a bias circuit 110, as described above. Figure 1A and Figure 1B The discussion continues. In some embodiments, forming a bias circuit including a first PMOS transistor and a second PMOS transistor includes: forming a bias circuit 300 including PMOS transistors P4 and P5, as described above. Figure 3A and Figure 3B The discussion continues. In some embodiments, forming a bias circuit including a first PMOS transistor and a second PMOS transistor includes: forming a bias circuit 400 including PMOS transistors P6-P8, as described above regarding... Figure 4A and Figure 4B Discussed.

[0170] In some embodiments, forming a level shifter including a third PMOS transistor and a fourth PMOS transistor includes: forming a level shifter 120, as described above regarding... Figure 1A and Figure 1B The discussion continues. In some embodiments, forming a level shifter including a third PMOS transistor and a fourth PMOS transistor includes: forming a level shifter 200 including PMOS transistors P1-P3, as discussed above. Figures 2-4B Discussed.

[0171] At operation 740, a first power distribution structure is constructed including electrical connections to each of the first and third PMOS transistors, and a second power distribution structure is constructed including electrical connections to each of the second and fourth PMOS transistors. Constructing the first and second power distribution structures includes configuring multiple conductive segments supported and electrically isolated by one or more insulating layers, as discussed above with respect to operation 730.

[0172] Constructing the first power distribution structure and the second power distribution structure includes: configuring multiple conductive segments such that each of the power distribution structures in the first power domain and the second power domain is electrically connected to the S / D structure of the first PMOS transistor to the fourth PMOS transistor.

[0173] In some embodiments, configuring multiple conductive elements includes: configuring the power distribution structure of a first power domain to include power node NVDD1, and configuring the power distribution structure of a second power domain to include power node NVDD2, each as described above. Figures 1A-4B The discussion continues. In some embodiments, configuring multiple conductive segments includes: configuring the power distribution structure of the first power domain and the second power domain to include power nodes NVDDA and NVDDB, as discussed above. Figure 4A and Figure 4B Discussed.

[0174] In some embodiments, configuring multiple conductive segments includes: configuring one or more power distribution structures to include a reference node NVSS, as described above. Figures 1A-4B Discussed.

[0175] The operation of method 700 can be used to form an IC structure, such as a level shifting circuit 100, which includes a bias circuit and a level shifter (configured according to the above discussion of level shifting circuit 100), and thereby has the capabilities and benefits discussed above of level shifting circuit 100.

[0176] Figure 8 This is a block diagram of an IC layout generation system 800 according to some embodiments. According to one or more embodiments, the methods for designing IC layouts described herein can be implemented, for example, using the IC layout generation system 800 according to some embodiments.

[0177] In some embodiments, the IC layout generation system 800 is a general-purpose computing device including a hardware processor 802 and a non-transitory computer-readable storage medium 804. Among other things, the storage medium 804 is encoded with (i.e., stores) computer program code 806 (i.e., a set of executable instructions). The hardware processor 802 executes the instructions 806 (at least partially) representing an implementation method (e.g., regarding...). Figure 6 The method for generating IC layout diagrams described in 600 (hereinafter referred to as the referred process and / or method) is part or all of the EDA tools.

[0178] Processor 802 is electrically coupled to computer-readable storage medium 804 via bus 808. Processor 802 is also electrically coupled to I / O interface 810 via bus 808. Network interface 812 is also electrically coupled to processor 802 via bus 808. Network interface 812 is connected to network 814, enabling processor 802 and computer-readable storage medium 804 to be connected to external components via network 814. Processor 802 is configured to execute computer program code 806 encoded in computer-readable storage medium 804, such that IC layout generation system 800 can be used to perform some or all of the aforementioned processes and / or methods. In one or more embodiments, processor 802 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0179] In one or more embodiments, the computer-readable storage medium 804 is an electrical, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or apparatus or device). For example, the computer-readable storage medium 804 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), rigid disk, and / or optical disk. In one or more embodiments using optical disk, the computer-readable storage medium 804 includes optical disc read-only memory (CD-ROM), CD-R / W, and / or digital video optical disc (DVD).

[0180] In one or more embodiments, storage medium 804 stores computer program code 806 configured to cause IC layout generation system 800 (where such execution (at least partially) represents an EDA tool) to perform part or all of the mentioned processes and / or methods. In one or more embodiments, storage medium 804 also stores information that facilitates the execution of part or all of the mentioned processes and / or methods. In one or more embodiments, storage medium 804 stores layout library 807, including IC layouts of the type disclosed herein, as described above. Figure 3B and Figure 4B The IC layout diagrams 100A and 100B are discussed.

[0181] IC layout generation system 800 includes an I / O interface 810. The I / O interface 810 is coupled to external circuitry. In one or more embodiments, the I / O interface 810 includes a keyboard, keypad, mouse, trackball, touchpad, touchscreen, and / or cursor arrow keys for conveying information and commands to processor 802.

[0182] The IC layout generation system 800 also includes a network interface 812 coupled to the processor 802. The network interface 812 allows the system 800 to communicate with a network 814 to which one or more other computer systems are connected. The network interface 812 includes a wireless network interface, such as Bluetooth, Wi-Fi, WiMAX, GPRS, or WCDMA; or a wired network interface, such as Ethernet, USB, or IEEE-1364. In one or more embodiments, some or all of the aforementioned processes and / or methods are implemented in two or more IC layout generation systems 800.

[0183] The IC layout generation system 800 is configured to receive information via I / O interface 810. The information received via I / O interface 810 includes instructions, data, design rules, libraries of standard cells, and / or one or more other parameters for processing by processor 802. The information is transmitted to processor 802 via bus 808. The IC layout generation system 800 is also configured to receive UI-related information via I / O interface 810. This information is stored as a user interface (UI) 842 on computer-readable medium 804.

[0184] In some embodiments, some or all of the mentioned processes and / or methods are implemented as a standalone software application executed by a processor. In some embodiments, some or all of the mentioned processes and / or methods are implemented as a software application part of an additional software application. In some embodiments, some or all of the mentioned processes and / or methods are implemented as a plug-in to a software application. In some embodiments, at least one of the mentioned processes and / or methods is implemented as a software application part of an EDA tool. In some embodiments, some or all of the mentioned processes and / or methods are implemented as a software application used by an IC layout generation system 800. In some embodiments, software applications such as those available from CADENCE DESIGN SYSTEMS are used. Tools such as those used in the layout generation tool or other suitable layout generation tools can be used to generate layouts that include standard cells.

[0185] In some embodiments, the process is implemented as the function of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage devices or memory units, such as one or more of optical discs such as DVDs, magnetic disks such as hard disks, and semiconductor memories such as ROM, RAM, memory cards, etc.

[0186] Figure 9This is a block diagram of an IC manufacturing system 900 and an associated IC manufacturing process according to some embodiments. In some embodiments, the manufacturing system 900 is used to manufacture at least one of (A) one or more semiconductor masks or (B) at least one component of a layer of a semiconductor integrated circuit, based on an IC layout diagram.

[0187] exist Figure 9 In this IC manufacturing system 900, entities such as design room 920, mask room 930, and IC manufacturer / fab 950 interact with each other in the design, development, and manufacturing cycle and / or services related to the manufacture of IC devices 960. The entities in system 900 are connected via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of the design room 920, mask room 930, and IC fab 950 are owned by a single large company. In some embodiments, two or more of the design room 920, mask room 930, and IC fab 950 coexist in a shared facility and use shared resources.

[0188] The design studio (or design team) 920 generates the IC design layout 922. The IC design layout 922 includes various geometric patterns, such as those shown above. Figure 3B and Figure 4B The IC layout diagrams 100A or 100B are discussed. The geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that constitute the various components of the IC device 960 to be manufactured. These layers combine to form various IC functions. For example, a portion of the IC design layout diagram 922 includes various IC features to be formed in a semiconductor substrate (e.g., a silicon wafer) and various material layers disposed on the semiconductor substrate, such as active regions, gate electrodes, source and drain electrodes, metal lines or vias for interlayer interconnects, and openings for pads. The design room 920 implements appropriate design processes to form the IC design layout diagram 922. These design processes include logic design, physical design, or layout and routing, or one or more of these. The IC design layout diagram 922 is presented in one or more data files containing geometric pattern information. For example, the IC design layout diagram 922 may be expressed in GDSII or DFII file format.

[0189] Mask chamber 930 includes data preparation 932 and mask fabrication 944. Mask chamber 930 uses an IC design layout 922 to fabricate one or more masks 945 for fabricating various layers of an IC device 960 according to the IC design layout 922. Mask chamber 930 performs mask data preparation 932, in which the IC design layout 922 is converted into a representative data file (“RDF”). Mask data preparation 932 provides the RDF for use in mask fabrication 944. Mask fabrication 944 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (reticle) 945 or a semiconductor wafer 953. The IC design layout 922 is processed by mask data preparation 932 to conform to the specific characteristics of the mask writer and / or the requirements of the IC fab 950. Figure 9 In this embodiment, mask data preparation 932 and mask manufacturing 944 are shown as separate elements. In some embodiments, mask data preparation 932 and mask manufacturing 944 may be collectively referred to as mask data preparation.

[0190] In some embodiments, mask data preparation 932 includes optical proximity correction (OPC), which uses lithographic enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, other processing effects, etc. OPC adjusts the IC design layout diagram 922. In some embodiments, mask data preparation 932 includes other resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution auxiliary features, phase-shift masks, other suitable techniques, or combinations thereof. In some embodiments, inverse lithography (ILT) is also used, which treats OPC as an inverse imaging problem.

[0191] In some embodiments, mask data preparation 932 includes a mask rule checker (MRC) that uses a set of mask creation rules to check the IC design layout 922, which has already been processed in the OPC, including certain geometric and / or connectivity constraints to ensure sufficient margin to account for variability in semiconductor manufacturing processes, etc. In some embodiments, the MRC modifies the IC design layout 922 to compensate for constraints during mask fabrication 944, and may undo a portion of the modifications performed by the OPC to satisfy the mask creation rules.

[0192] In some embodiments, mask data preparation 932 includes a lithography process check (LPC), which is simulated by an IC fab 950 to fabricate an IC device 960. The LPC simulates this process based on an IC design layout 922 to create a simulated fabricated device, such as IC device 960. Process parameters in the LPC simulation may include parameters associated with various processes in the IC manufacturing cycle, parameters associated with the tools used to manufacture the IC, and / or other aspects of the manufacturing process. The LPC considers various factors, such as projection contrast, depth of focus (“DOF”), mask error enhancement factor (“MEEF”), other suitable factors, etc., or combinations thereof. In some embodiments, after the simulated fabricated device has been created via LPC, if the simulated device is not close enough in shape to meet design rules, OPC and / or MRC are repeated to further refine the IC design layout 922.

[0193] It should be understood that, for clarity, the above description of mask data preparation 932 has been simplified. In some embodiments, data preparation 932 includes additional features such as logic operations (LOPs) to modify the IC design layout 922 according to manufacturing rules. Furthermore, the processes applied to the IC design layout 922 during data preparation 932 can be performed in various different sequences.

[0194] Following mask data preparation 932 and during mask fabrication 944, a mask 945 or mask set 945 is fabricated based on a modified IC design layout 922. In some embodiments, mask fabrication 944 includes performing one or more photolithographic exposures based on the IC design layout 922. In some embodiments, a mechanism using an electron beam (e-beam) or multiple electron beams is used to form a pattern on the mask (photomask or mask stencil) 945 based on the modified IC design layout 922. The mask 945 can be formed using various techniques. In some embodiments, a binary technique is used to form the mask 945. In some embodiments, the mask pattern includes opaque regions and transparent regions. Radiation beams (e.g., ultraviolet (UV) or EVU beams) used to expose an image-sensitive material layer (e.g., photoresist) already coated on the wafer are blocked by the opaque regions and transmitted through the transparent regions. In one example, a binary mask version of the mask 945 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in the opaque regions of the binary mask. In another example, a phase-shifting technique is used to form mask 945. In the phase-shifting mask (PSM) version of mask 945, various features in the pattern formed on the phase-shifting mask are configured to have appropriate phase difference to enhance resolution and imaging quality. In various examples, the phase-shifting mask can be attenuated PSM or adjusted PSM. The mask(s) generated by mask fabrication 944 are used in various processes. For example, such masks(s) are used in ion implantation processes to form various doped regions in semiconductor wafer 953, in etching processes to form various etched regions in semiconductor wafer 953, and / or in other suitable processes.

[0195] IC Fab 950 is an IC manufacturing company that includes one or more manufacturing facilities for manufacturing various different IC products. In some embodiments, IC Fab 950 is a semiconductor foundry. For example, there may be one manufacturing plant for front-end manufacturing (front-end process (FEOL) manufacturing) of multiple IC products, a second manufacturing plant for back-end manufacturing (back-end process (BEOL) manufacturing) of IC product interconnects and packaging, and a third manufacturing plant for additional services such as foundry operations.

[0196] IC fab 950 includes a wafer fabrication tool 952 configured to perform various fabrication operations on a semiconductor wafer 953 to fabricate an IC device 960 according to one or more masks (e.g., mask 945). In various embodiments, the fabrication tool 952 includes one or more of the following: a wafer stepper, an ion implanter, a photoresist coater, a processing chamber (e.g., a CVD chamber or LPCVD furnace), a CMP system, a plasma etching system, a wafer cleaning system, or other fabrication equipment capable of performing one or more of the fabrication processes discussed herein.

[0197] IC fab 950 uses one or more masks 945 manufactured by mask chamber 930 to fabricate IC device 960. Therefore, IC fab 950 uses IC design layout 922 at least indirectly to fabricate IC device 960. In some embodiments, IC fab 950 uses one or more masks 945 to fabricate semiconductor wafer 953 to form IC device 960. In some embodiments, IC fabrication includes performing one or more photolithographic exposures at least indirectly based on IC design layout 922. Semiconductor wafer 953 includes a silicon substrate or other suitable substrate on which material layers are formed. Semiconductor wafer 953 also includes one or more of various doped regions, dielectric features, multilayer interconnects, etc. (formed in subsequent fabrication steps).

[0198] Regarding IC manufacturing systems (e.g., Figure 9 Details of the system (900) and the associated IC manufacturing process can be found in the following documents: for example, U.S. Patent No. 9,256,709, granted February 9, 2016; U.S. Pre-Grant Publication No. 20150278429, published October 1, 2015; U.S. Pre-Grant Publication No. 20140040838, published February 6, 2014; and U.S. Patent No. 7,260,442, granted August 21, 2007, which are incorporated herein by reference in their entirety.

[0199] In some embodiments, a circuit includes: a bias circuit including: a first input terminal configured to receive a first power supply voltage; and a second input terminal configured to receive a second power supply voltage, wherein the bias circuit is configured to generate a bias voltage having a greater of a first voltage level of the first power supply voltage or a second voltage level of the second power supply voltage; and a level shifter including: a first PMOS transistor configured to receive the first power supply voltage; and a second PMOS transistor configured to receive the second power supply voltage, wherein each of the first and second PMOS transistors includes a body terminal configured to receive the bias voltage. In some embodiments, the bias circuit includes: a third PMOS transistor configured to receive the first power supply voltage; and a fourth PMOS transistor configured to receive the second power supply voltage, wherein each of the third and fourth PMOS transistors includes a body terminal configured to receive the bias voltage. In some embodiments, the third PMOS transistor includes a gate configured to receive a second power supply voltage, a first S / D terminal configured to receive a first power supply voltage, and a second S / D terminal; the fourth PMOS transistor includes a gate configured to receive a first power supply voltage, a third S / D terminal configured to receive a second power supply voltage, and a fourth S / D terminal; and the second S / D terminal and the fourth S / D terminal are coupled together and configured to generate a bias voltage. In some embodiments, the bias circuit includes an inverter configured to receive either a first power supply voltage or a second power supply voltage. The inverter includes a fifth PMOS transistor with a body terminal configured to receive a bias voltage. A third PMOS transistor includes a gate configured to receive either the first or second power supply voltage, a first S / D terminal configured to receive the other of the first or second power supply voltage, and a second S / D terminal. A fourth PMOS transistor includes a gate coupled to a node of the inverter, a third S / D terminal configured to receive either the first or second power supply voltage, and a fourth S / D terminal. The second and fourth S / D terminals are coupled together and configured to generate a bias voltage.

[0200] In some embodiments, the level shifter includes a third PMOS transistor configured to receive a second power supply voltage, the third PMOS transistor including a body terminal configured to receive a bias voltage.

[0201] In some embodiments, the level shifter includes: a first NMOS transistor coupled in series with a first PMOS transistor; a second NMOS transistor coupled in series with the second PMOS transistor; and a third NMOS transistor coupled in series with the third PMOS transistor, wherein the first NMOS transistor and the first PMOS transistor are arranged as an inverter configured to receive an input signal, the second NMOS transistor is configured to receive a signal output from the inverter, and the third NMOS transistor is configured to receive the input signal. In some embodiments, the body terminals of the first PMOS transistor and the second PMOS transistor are coupled to the same n-well.

[0202] In some embodiments, an IC includes: an n-well; a first power node configured to have a first power supply voltage; a second power node configured to have a second power supply voltage; a bias circuit including: a first PMOS transistor located in the n-well and including a first S / D terminal coupled to the first power node; and a second PMOS transistor located in the n-well and including a second S / D terminal coupled to the second power node, wherein the bias circuit is configured to bias the n-well with a bias voltage level having a bias voltage level based on the greater of a first voltage level of the first power supply voltage or a second voltage level of the second power supply voltage; and a level shifter including: a third PMOS transistor located in the n-well and including a third S / D terminal coupled to the first power node; and a fourth PMOS transistor located in the n-well and including a fourth S / D terminal coupled to the second power node. In some embodiments, the bias circuit is configured to bias the n-well with a bias voltage level having a bias voltage level equal to the greater of the first voltage level or the second voltage level. In some embodiments, a first PMOS transistor includes a fifth S / D terminal, a second PMOS transistor includes a sixth S / D terminal, and the fifth and sixth S / D terminals are coupled together and configured to generate a bias voltage. In some embodiments, the first PMOS transistor includes a gate coupled to a second power node, and the second PMOS transistor includes a gate coupled to a first power node. In some embodiments, the bias circuit includes: a fifth PMOS transistor located in an n-well and including a seventh S / D terminal coupled to a first power node, a gate coupled to a second power node, and an eighth S / D terminal coupled to an inner node; and an NMOS transistor including a ninth S / D terminal coupled to an inner node, a gate coupled to a second power node, and a tenth S / D terminal coupled to a reference node configured to have a reference voltage, wherein the first PMOS transistor includes a gate coupled to the second power node, and the second PMOS transistor includes a gate coupled to an inner node. In some embodiments, the bias circuit includes: a fifth PMOS transistor located in an n-well and including a gate coupled to a first power node, a seventh S / D terminal coupled to a second power node, and an eighth S / D terminal coupled to an internal node; and an NMOS transistor including a ninth S / D terminal coupled to an internal node, a gate coupled to the first power node, and a tenth S / D terminal coupled to a reference node configured to have a reference voltage, wherein the first PMOS transistor includes a gate coupled to an internal node, and the second PMOS transistor includes a gate coupled to a second power node.In some embodiments, the level shifter includes: a fifth PMOS transistor located in an n-well and including a fifth S / D terminal coupled to a second power node; a first NMOS transistor coupled between a third PMOS transistor and a reference node configured to have a reference voltage; a second NMOS transistor coupled between a fourth PMOS transistor and the reference node; and a third NMOS transistor coupled between the fifth PMOS transistor and the reference node, wherein each of the first to third NMOS transistors includes a body terminal coupled to the reference node.

[0203] In some embodiments, a method of operating a level shifting circuit includes: receiving a first power supply voltage and a second power supply voltage at a bias circuit; generating a bias voltage using the bias circuit based on the greater of a first voltage level of the first power supply voltage or a second voltage level of the second power supply voltage; receiving the first power supply voltage at a first S / D terminal of a first PMOS transistor of a level shifter; receiving the second power supply voltage at a second S / D terminal of a second PMOS transistor of a level shifter; and biasing an n-well comprising the first PMOS transistor and the second PMOS transistor using the bias voltage. In some embodiments, receiving the first power supply voltage and the second power supply voltage at the bias circuit includes: receiving the first power supply voltage at a third S / D terminal of a third PMOS transistor of the bias circuit; and receiving the second power supply voltage at a fourth S / D terminal of a fourth PMOS transistor of the bias circuit, wherein the n-well comprises the third PMOS transistor and the fourth PMOS transistor. In some embodiments, generating the bias voltage using the bias circuit includes: generating the bias voltage using a fifth S / D terminal of the third PMOS transistor, the fifth S / D terminal being coupled to a sixth S / D terminal of the fourth PMOS transistor. In some embodiments, generating a bias voltage using a bias circuit based on the greater of a first voltage level or a second voltage level includes: generating a bias voltage having a first voltage level by turning on a third PMOS transistor; and generating a bias voltage having a second voltage level by turning on a fourth PMOS transistor. In some embodiments, generating a bias voltage using a bias circuit based on the greater of a first voltage level or a second voltage level includes: generating a bias voltage having a first voltage level when the second voltage level corresponds to a power domain of a second power supply voltage operating in a power-off mode; and generating a bias voltage having a second voltage level when the first voltage level corresponds to a power domain of a first power supply voltage operating in a power-off mode. In some embodiments, receiving the first power supply voltage at a first S / D terminal of a first PMOS transistor includes: receiving the first power supply voltage at an inverter including the first PMOS transistor, and receiving the second power supply voltage at a second S / D terminal of a second PMOS transistor includes: receiving the second power supply voltage at a cross-coupled transistor pair including the second PMOS transistor.

[0204] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0205] Example 1. A level shifting circuit, comprising: a bias circuit including: a first input terminal configured to receive a first power supply voltage; and a second input terminal configured to receive a second power supply voltage, wherein the bias circuit is configured to generate a bias voltage having a greater of a first voltage level of the first power supply voltage or a second voltage level of the second power supply voltage; and a level shifter including: a first PMOS transistor configured to receive the first power supply voltage; and a second PMOS transistor configured to receive the second power supply voltage, wherein each of the first PMOS transistor and the second PMOS transistor includes a body terminal configured to receive the bias voltage.

[0206] Example 2. The circuit according to Example 1, wherein the bias circuit includes: a third PMOS transistor configured to receive the first power supply voltage; and a fourth PMOS transistor configured to receive the second power supply voltage, wherein each of the third PMOS transistor and the fourth PMOS transistor includes a body terminal configured to receive the bias voltage.

[0207] Example 3. The circuit according to Example 2, wherein the third PMOS transistor includes a gate configured to receive the second power supply voltage, a first source / drain S / D terminal configured to receive the first power supply voltage, and a second S / D terminal, and the fourth PMOS transistor includes a gate configured to receive the first power supply voltage, a third S / D terminal configured to receive the second power supply voltage, and a fourth S / D terminal, and the second S / D terminal and the fourth S / D terminal are coupled together and configured to generate the bias voltage.

[0208] Example 4. The circuit according to Example 2, wherein the bias circuit further includes an inverter configured to receive one of a first power supply voltage or a second power supply voltage, the inverter including a fifth PMOS transistor including a body terminal configured to receive the bias voltage, a third PMOS transistor including a gate configured to receive one of the first power supply voltage or the second power supply voltage, a first source / drain S / D terminal configured to receive the other of the first power supply voltage or the second power supply voltage, and a second S / D terminal, and a fourth PMOS transistor including a gate coupled to a node of the inverter, a third S / D terminal configured to receive one of the first power supply voltage or the second power supply voltage, and a fourth S / D terminal, wherein the second S / D terminal and the fourth S / D terminal are coupled together and configured to generate the bias voltage.

[0209] Example 5. The circuit according to Example 1, wherein the level shifter includes: a third PMOS transistor configured to receive the second power supply voltage, the third PMOS transistor including a body terminal configured to receive the bias voltage.

[0210] Example 6. The circuit according to Example 5, wherein the level shifter includes: a first NMOS transistor coupled in series with a first PMOS transistor; a second NMOS transistor coupled in series with the second PMOS transistor; and a third NMOS transistor coupled in series with the third PMOS transistor, wherein the first NMOS transistor and the first PMOS transistor are arranged as inverters, the inverters are configured to receive an input signal, the second NMOS transistor is configured to receive a signal output from the inverters, and the third NMOS transistor is configured to receive the input signal.

[0211] Example 7. The circuit according to Example 1, wherein the body terminals of the first PMOS transistor and the second PMOS transistor are coupled to the same n-well.

[0212] Example 8. An integrated circuit (IC) includes: an n-well; a first power node configured to have a first power supply voltage; a second power node configured to have a second power supply voltage; a bias circuit including: a first PMOS transistor located in the n-well and including a first source / drain S / D terminal coupled to the first power node; and a second PMOS transistor located in the n-well and including a second S / D terminal coupled to the second power node, wherein the bias circuit is configured to bias the n-well using a bias voltage having a bias voltage level based on the greater of a first voltage level of the first power supply voltage or a second voltage level of the second power supply voltage; and a level shifter including: a third PMOS transistor located in the n-well and including a third S / D terminal coupled to the first power node; and a fourth PMOS transistor located in the n-well and including a fourth S / D terminal coupled to the second power node.

[0213] Example 9. The IC according to Example 8, wherein the bias circuit is configured to bias the n-well using the bias voltage having a bias voltage level, the bias voltage level being equal to the greater of the first voltage level or the second voltage level.

[0214] Example 10. The IC according to Example 8, wherein the first PMOS transistor includes a fifth S / D terminal, the second PMOS transistor includes a sixth S / D terminal, and the fifth S / D terminal and the sixth S / D terminal are coupled together and configured to generate the bias voltage.

[0215] Example 11. The IC according to Example 10, wherein the first PMOS transistor includes a gate coupled to the second power node, and the second PMOS transistor includes a gate coupled to the first power node.

[0216] Example 12. The IC according to Example 10, wherein the bias circuit further includes: a fifth PMOS transistor located in the n-well and including a seventh S / D terminal coupled to the first power node, a gate coupled to the second power node, and an eighth S / D terminal coupled to an internal node; and an NMOS transistor including a ninth S / D terminal coupled to the internal node, a gate coupled to the second power node, and a tenth S / D terminal coupled to a reference node configured to have a reference voltage, wherein the first PMOS transistor includes a gate coupled to the second power node, and the second PMOS transistor includes a gate coupled to the internal node.

[0217] Example 13. The IC according to Example 10, wherein the bias circuit further includes: a fifth PMOS transistor located in the n-well and including a gate coupled to the first power node, a seventh S / D terminal coupled to the second power node, and an eighth S / D terminal coupled to an internal node; and an NMOS transistor including a ninth S / D terminal coupled to the internal node, a gate coupled to the first power node, and a tenth S / D terminal coupled to a reference node configured to have a reference voltage, wherein the first PMOS transistor includes a gate coupled to the internal node, and the second PMOS transistor includes a gate coupled to the second power node.

[0218] Example 14. The IC according to Example 8, wherein the level shifter includes: a fifth PMOS transistor located in the n-well and including a fifth S / D terminal coupled to the second power node; a first NMOS transistor coupled between the third PMOS transistor and a reference node configured to have a reference voltage; a second NMOS transistor coupled between the fourth PMOS transistor and the reference node; and a third NMOS transistor coupled between the fifth PMOS transistor and the reference node, wherein each of the first to third NMOS transistors includes a body terminal coupled to the reference node.

[0219] Example 15. A method of operating a level shifting circuit, the method comprising: receiving a first power supply voltage and a second power supply voltage at a bias circuit; generating a bias voltage using the bias circuit based on the greater of a first voltage level of the first power supply voltage or a second voltage level of the second power supply voltage; receiving the first power supply voltage at a first source / drain S / D terminal of a first PMOS transistor of a level shifter; receiving the second power supply voltage at a second S / D terminal of a second PMOS transistor of the level shifter; and using the bias voltage to bias an n-well comprising the first PMOS transistor and the second PMOS transistor.

[0220] Example 16. The method according to Example 15, wherein receiving the first power supply voltage and the second power supply voltage at the bias circuit comprises: receiving the first power supply voltage at a third S / D terminal of a third PMOS transistor in the bias circuit; and receiving the second power supply voltage at a fourth S / D terminal of a fourth PMOS transistor in the bias circuit; wherein the n-well comprises the third PMOS transistor and the fourth PMOS transistor.

[0221] Example 17. The method according to Example 16, wherein using the bias circuit to generate the bias voltage includes: using the fifth S / D terminal of the third PMOS transistor to generate the bias voltage, the fifth S / D terminal being coupled to the sixth S / D terminal of the fourth PMOS transistor.

[0222] Example 18. The method according to Example 17, wherein generating the bias voltage using the bias circuit based on the greater of the first voltage level or the second voltage level comprises: generating a bias voltage having the first voltage level by turning on the third PMOS transistor; and generating a bias voltage having the second voltage level by turning on the fourth PMOS transistor.

[0223] Example 19. The method according to Example 15, wherein generating the bias voltage using the bias circuit based on the greater of the first voltage level or the second voltage level comprises: generating a bias voltage having the first voltage level when the second voltage level corresponds to a power domain of the second power supply voltage operating in a power-off mode; and generating a bias voltage having the second voltage level when the first voltage level corresponds to a power domain of the first power supply voltage operating in a power-off mode.

[0224] Example 20. The method according to Example 15, wherein receiving the first power supply voltage at the first S / D terminal of the first PMOS transistor includes: receiving the first power supply voltage at an inverter including the first PMOS transistor, and receiving the second power supply voltage at the second S / D terminal of the second PMOS transistor includes: receiving the second power supply voltage at a cross-coupled transistor pair including the second PMOS transistor.

Claims

1. A level shifting circuit, comprising: Bias circuit, including: The first input terminal is configured to receive a first power supply voltage; and The second input terminal is configured to receive a second power supply voltage. The bias circuit is configured to generate a bias voltage having the greater of a first voltage level of the first power supply voltage or a second voltage level of the second power supply voltage; and Level shifter, including: A first PMOS transistor is configured to receive the first power supply voltage; and The second PMOS transistor is configured to receive the second power supply voltage. Each of the first PMOS transistor and the second PMOS transistor includes a body terminal configured to receive the bias voltage. The bias circuit includes: A third PMOS transistor is configured to receive the first power supply voltage. The third PMOS transistor includes a gate configured to receive the second power supply voltage, a first source / drain S / D terminal configured to receive the first power supply voltage, and a second S / D terminal. A fourth PMOS transistor is configured to receive the second power supply voltage. The fourth PMOS transistor includes a gate configured to receive the first power supply voltage, a third S / D terminal configured to receive the second power supply voltage, and a fourth S / D terminal. Each of the third PMOS transistor and the fourth PMOS transistor includes a body terminal configured to receive the bias voltage, and the second S / D terminal and the fourth S / D terminal are coupled together and configured to generate the bias voltage.

2. The circuit according to claim 1, wherein, The bias circuit further includes an inverter configured to receive either the first power supply voltage or the second power supply voltage. The inverter includes a fifth PMOS transistor, which includes a body terminal configured to receive the bias voltage.

3. The circuit according to claim 1, wherein, The level shifter includes: A fifth PMOS transistor is configured to receive the second power supply voltage, the fifth PMOS transistor including a body terminal configured to receive the bias voltage.

4. The circuit according to claim 3, wherein, The level shifter includes: The first NMOS transistor is coupled in series with the first PMOS transistor; The second NMOS transistor is coupled in series with the second PMOS transistor; and The third NMOS transistor is coupled in series with the fifth PMOS transistor. in, The first NMOS transistor and the first PMOS transistor are arranged as an inverter, and the inverter is configured to receive an input signal. The second NMOS transistor is configured to receive the signal output from the inverter, and The third NMOS transistor is configured to receive the input signal.

5. The circuit according to claim 1, wherein, The body terminals of the first PMOS transistor and the second PMOS transistor are coupled to the same n-well.

6. An integrated circuit IC, comprising: n-well; The first power node is configured to have a first power supply voltage; The second power node is configured to have a second power supply voltage; Bias circuit, including: A first PMOS transistor, located in the n-well and including a first source / drain S / D terminal coupled to the first power node, the first PMOS transistor further including a fifth S / D terminal; and A second PMOS transistor, located in the n-well and including a second S / D terminal coupled to the second power node, further includes a sixth S / D terminal. The bias circuit is configured to bias the n-well using a bias voltage having a bias voltage level, the bias voltage level being based on the greater of a first voltage level of the first power supply voltage or a second voltage level of the second power supply voltage, and the fifth S / D terminal and the sixth S / D terminal are coupled together and configured to generate the bias voltage; and Level shifter, including: A third PMOS transistor, located in the n-well and including a third S / D terminal coupled to the first power node; and A fourth PMOS transistor is located in the n-well and includes a fourth S / D terminal coupled to the second power node.

7. The IC according to claim 6, wherein, The bias circuit is configured to bias the n-well using the bias voltage having a bias voltage level equal to the greater of the first voltage level or the second voltage level.

8. The IC according to claim 6, wherein, The first PMOS transistor includes a gate coupled to the second power node, and The second PMOS transistor includes a gate coupled to the first power node.

9. The IC according to claim 6, wherein, The bias circuit further includes: A fifth PMOS transistor, located in the n-well, includes a seventh S / D terminal coupled to the first power node, a gate coupled to the second power node, and an eighth S / D terminal coupled to an internal node; and The NMOS transistor includes a ninth S / D terminal coupled to the internal node, a gate coupled to the second power supply node, and a tenth S / D terminal coupled to a reference node configured to have a reference voltage. in, The first PMOS transistor includes a gate coupled to the second power node, and The second PMOS transistor includes a gate coupled to the internal node.

10. The IC according to claim 6, wherein, The bias circuit further includes: A fifth PMOS transistor, located in the n-well, includes a gate coupled to the second power node, a seventh S / D terminal coupled to the first power node, and an eighth S / D terminal coupled to the inner node; and The NMOS transistor includes a ninth S / D terminal coupled to the internal node, a gate coupled to the second power supply node, and a tenth S / D terminal coupled to a reference node configured to have a reference voltage. in, The first PMOS transistor includes a gate coupled to the internal node, and The second PMOS transistor includes a gate coupled to the second power node.

11. The IC according to claim 6, wherein, The level shifter includes: The fifth PMOS transistor is located in the n-well and includes a fifth S / D terminal coupled to the second power supply node; A first NMOS transistor is coupled between the third PMOS transistor and a reference node configured to have a reference voltage; A second NMOS transistor is coupled between the fourth PMOS transistor and the reference node; and A third NMOS transistor is coupled between the fifth PMOS transistor and the reference node. Each of the first to the third NMOS transistors includes a body terminal coupled to the reference node.

12. A method for operating a level shifting circuit, the method comprising: The first and second power supply voltages are received at the bias circuit. The bias circuit generates a bias voltage based on the greater of a first voltage level of the first power supply voltage or a second voltage level of the second power supply voltage. The first power supply voltage is received at the first source / drain S / D terminal of the first PMOS transistor of the level shifter; The second power supply voltage is received at the second S / D terminal of the second PMOS transistor of the level shifter; as well as The bias voltage is used to bias the n-well containing the first PMOS transistor and the second PMOS transistor. The function of receiving the first power supply voltage and the second power supply voltage at the bias circuit includes: The first power supply voltage is received at the third S / D terminal of the third PMOS transistor in the bias circuit; and The second power supply voltage is received at the fourth S / D terminal of the fourth PMOS transistor in the bias circuit. The n-well includes the third PMOS transistor and the fourth PMOS transistor; Using the bias circuit to generate the bias voltage includes: The bias voltage is generated using the fifth S / D terminal of the third PMOS transistor, which is coupled to the sixth S / D terminal of the fourth PMOS transistor.

13. The method according to claim 12, wherein, Generating the bias voltage using the bias circuit based on the greater of the first voltage level or the second voltage level includes: A bias voltage having the first voltage level is generated by turning on the third PMOS transistor; and A bias voltage with the second voltage level is generated by turning on the fourth PMOS transistor.

14. The method according to claim 12, wherein, Generating the bias voltage using the bias circuit based on the greater of the first voltage level or the second voltage level includes: When the second voltage level corresponds to the power domain of the second power supply voltage operating in power-down mode, a bias voltage having the first voltage level is generated; and When the first voltage level corresponds to the power domain of the first power supply voltage operating in power-down mode, a bias voltage with the second voltage level is generated.

15. The method according to claim 12, wherein, Receiving the first power supply voltage at the first S / D terminal of the first PMOS transistor includes: receiving the first power supply voltage at an inverter including the first PMOS transistor, and Receiving the second power supply voltage at the second S / D terminal of the second PMOS transistor includes receiving the second power supply voltage at a cross-coupled transistor pair including the second PMOS transistor.

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