Semiconductor layer, method for manufacturing the same, and transistor including the same

Abstract

A method for manufacturing a semiconductor layer is provided. The method may include the following steps: preparing a substrate, and forming a semiconductor layer including indium (In) and gallium (Ga) on the substrate by performing a first unit process of reacting a first reaction source with a first precursor including In, and a second unit process of reacting a second reaction source with a second precursor including Ga.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor layer, a method for manufacturing the same, and a transistor including the same, and more particularly to a semiconductor layer formed on a substrate by providing a precursor including indium and a reaction source, a method for manufacturing the same, and a transistor including the same. Background Art

[0002] In the current display market, especially in the field of LCD, a-Si based transistors are mainly used. However, in order to meet the recent market demand for high resolution and OLED applications, research is underway on oxide semiconductor based transistors.

[0003] For example, Korean Patent Application Publication No. 10-2019-0067556 (Application No. 10-2017-016714, Applicant: Yonsei University Industry-Academia-Research Cooperation Foundation) discloses an oxide semiconductor thin film transistor and a method for manufacturing the same. The method includes: forming a gate electrode on a substrate; forming a gate insulating film on the gate electrode; forming a semiconductor thin film on the gate insulating film; and forming source / drain electrodes spaced apart from each other on the semiconductor thin film. During the formation of the semiconductor thin film, the semiconductor thin film is formed using a co-sputtering method using an oxide semiconductor target and a polymer target to improve the hydrophobicity of the semiconductor thin film.

[0004] However, the disadvantage of using an oxide thin film semiconductor layer using an existing sputtering system is that it is difficult to control reliability and mobility. In addition, high-mobility materials generally have the disadvantage of poor reliability, while materials with good reliability, on the contrary, have the disadvantage of low mobility. In addition, there are disadvantages in that it is difficult to accurately control the thickness and difficult to control the performance by adjusting the composition. In addition, there is a disadvantage in that it is difficult to use in a low-temperature process because high-temperature heat treatment is inevitably required even in the process after the film is deposited. Accordingly, a variety of technologies related to the formation of oxide semiconductor films that can solve the above problems have been studied and developed.

[0005] [Prior Art Document]

[0006] [Patent Document]

[0007] (Patent Document 1) Korean Patent Application Publication No. 10-2019-0067556. Summary of the Invention

[0008] [Technical Issues]

[0009] An object of the present disclosure is to provide a semiconductor layer with improved mobility, a method for manufacturing the same, and a transistor including the same.

[0010] Another object of the present disclosure is to provide a device having an improved on / off ratio (I开 / I 关 ) semiconductor layer, a method for manufacturing the same, and a transistor including the same.

[0011] Yet another object of the present disclosure is to provide a semiconductor layer whose composition is easily controlled, a method for manufacturing the same, and a transistor including the same.

[0012] Yet another object of the present disclosure is to provide a semiconductor layer with improved reliability, a method for manufacturing the same, and a transistor including the same.

[0013] The objects of the present disclosure are not limited to the above objects.

[0014] [Technical solution]

[0015] In view of the above, one embodiment of the present disclosure provides a method of manufacturing a semiconductor layer.

[0016] According to one embodiment, the method for manufacturing a semiconductor layer may include: preparing a substrate; and performing a first unit process of reacting a first precursor including indium (In) with a first reaction source and a second unit process of reacting a second precursor including gallium (Ga) with a second reaction source to form a semiconductor layer including the indium and the gallium on the substrate, wherein the first precursor and the second precursor have ligands with the same chemical structure.

[0017] According to one embodiment, the first precursor may include a compound represented by the following Chemical Formula 1, and the second precursor may include a compound represented by the following Chemical Formula 2.

[0018] [Chemical Formula 1]

[0019]

[0020] [Chemical Formula 2]

[0021]

[0022] According to one embodiment, the method further includes, after forming the semiconductor layer, heat-treating the semiconductor layer, wherein a temperature of the heat treatment of the semiconductor layer is controlled according to a number of repetitions of the first unit process and a number of repetitions of the second unit process.

[0023] According to one embodiment, when the ratio of the number of repetitions of the first unit process to the number of repetitions of the second unit process is 4:1, the semiconductor layer may be heat-treated at a temperature higher than 350° C. and lower than 450° C.

[0024] According to one embodiment, when the ratio of the number of repetitions of the first unit process to the number of repetitions of the second unit process is 6:1, the semiconductor layer may be heat-treated at a temperature higher than 300° C. and lower than 400° C.

[0025] According to one embodiment, the semiconductor layer may be heat-treated by ultraviolet (UV) rays.

[0026] According to one embodiment, the first reaction source and the second reaction source may include plasma of a mixture of oxygen (O 2 ) and argon (Ar).

[0027] According to another embodiment, the method for manufacturing a semiconductor layer includes: preparing a substrate; providing a precursor including indium on the substrate; providing a reaction source on the substrate provided with the precursor to form a semiconductor layer, wherein the precursor is reacted with the reaction source at a first temperature; and heat-treating the semiconductor layer at a second temperature, wherein the temperature of the heat treatment of the semiconductor layer is controlled according to the type of the reaction source.

[0028] According to another embodiment, the reaction source includes a plasma of a mixture of oxygen (O 2 ) and argon (Ar), and the first temperature is controlled to be higher than 100° C. and lower than 250° C.

[0029] According to another embodiment, the reaction source includes water (H2O), and the first temperature is controlled to be higher than 100°C and lower than 200°C.

[0030] According to another embodiment, the precursor may include a compound represented by the following Chemical Formula 1.

[0031] [Chemical Formula 1]

[0032]

[0033] In view of the above, one embodiment of the present disclosure provides a transistor.

[0034] According to one embodiment, the transistor includes: a substrate; a gate insulating film disposed on the substrate; an active layer disposed on the gate insulating film and including indium (In) and gallium (Ga); and a source electrode disposed on the gate insulating film so as to contact one side of the active layer and a drain electrode disposed on the gate insulating film so as to contact the other side of the active layer, wherein, in the active layer, the indium content is greater than 25.3 wt% and less than 33.5 wt%, and the gallium content is greater than 6.8 wt% and less than 16.9 wt%.

[0035] According to one embodiment, the active layer may have a thickness of 26.0 cm 2 / Vs or greater mobility.

[0036] According to one embodiment, the on / off ratio (I 开 / I 关 ) can be 6.2E+10 or greater.

[0037] [Beneficial Effects]

[0038] A method for manufacturing a semiconductor layer according to one embodiment of the present disclosure includes: preparing a substrate; and performing a first unit process of reacting a first precursor including indium (In) with a first reaction source and a second unit process of reacting a second precursor including gallium (Ga) with a second reaction source to form a semiconductor layer including the indium and gallium on the substrate, wherein the first precursor and the second precursor may have the same ligand. Accordingly, the composition ratio in the semiconductor layer is easily controlled, and thus, a transistor including the semiconductor layer can have improved electrical performance and reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 1 is a flowchart illustrating a method for manufacturing a semiconductor layer according to a first embodiment of the present disclosure.

[0040] Figures 2 to 7 2 are schematic diagrams each showing a process of manufacturing a semiconductor layer according to the first embodiment of the present disclosure.

[0041] Figure 8 FIG1 is a schematic diagram illustrating a transistor including a semiconductor layer according to a first embodiment of the present disclosure.

[0042] Figure 9 1 is a flowchart illustrating a method for manufacturing a semiconductor layer according to a second embodiment of the present disclosure.

[0043] Figure 10 Schematic diagram showing a semiconductor layer according to a second embodiment of the present disclosure.

[0044] Figure 11 and Figure 12 2 are schematic diagrams each showing a process of manufacturing a semiconductor layer according to a reaction source.

[0045] Figure 13 Graph showing the In growth rate in the semiconductor thin film according to Example 1 of the present disclosure.

[0046] Figure 14 is a graph showing the Ga growth rate in the semiconductor thin film according to Example 1 of the present disclosure.

[0047] Figure 15 and Figure 16Graphs showing electrical properties of the transistor according to Example 1, including the UV-annealed semiconductor thin film according to Example 1. FIG.

[0048] Figures 17 to 20 Graphs showing electrical properties of a transistor according to Example 1 including the semiconductor thin film according to Example 1 heat-treated in a furnace.

[0049] Figure 21 is a graph showing the electrical properties of the semiconductor thin film according to Example 2 of the present disclosure.

[0050] Figure 22 is a graph showing the structure of a semiconductor thin film according to Example 2 of the present disclosure.

[0051] Figures 23 to 26 is a graph showing the electrical performance of the transistor according to Example 2 of the present disclosure.

[0052] Figure 27 is a graph showing the electrical properties of the semiconductor thin film according to Example 3 of the present disclosure.

[0053] Figure 28 is a graph showing the structure of a semiconductor thin film according to Example 3 of the present disclosure.

[0054] Figures 29 to 32 is a graph showing the electrical performance of the transistor according to Example 3 of the present disclosure. DETAILED DESCRIPTION

[0055] Hereinafter, preferred embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. However, the technical ideas of the present disclosure are not limited to the embodiments described herein and can also be implemented in other forms. More specifically, the embodiments introduced herein are provided to make the content of the present disclosure comprehensive and complete and to fully convey the ideas of the present disclosure to those skilled in the art.

[0056] In this specification, the description of a certain component on another component means that the component can be directly formed on the other component or a third component can be provided between them. In addition, in the drawings, in order to effectively describe the technical content, the area and film thickness are exaggerated.

[0057] In addition, in each embodiment of this specification, terms such as first, second and third are used to describe various components, however, these components should not be limited by these terms. These terms are only used to distinguish one component from another component. Accordingly, a component referred to as a first component in any one embodiment may also be referred to as a second component in another embodiment. Each embodiment described and illustrated herein also includes its supplementary embodiments. In addition, 'and / or' in this specification is used as a meaning including at least one of the components listed before and after it.

[0058] In this specification, singular expressions include plural expressions unless the context clearly indicates otherwise. In addition, terms such as "including" or "having" are used to indicate the presence of features, numbers, steps, components, or combinations thereof described in the specification, and should not be understood as excluding the possibility of the presence or addition of one or more other features, numbers, steps, components, or combinations thereof. In addition, in this specification, "connected" is used to include both indirect and direct connections of multiple components.

[0059] Furthermore, in the following description of the present disclosure, if it is determined that the detailed description of related known functions or components would unnecessarily obscure the gist of the present disclosure, the detailed description thereon will not be included.

[0060] Figure 1 1 is a flowchart illustrating a method for manufacturing a semiconductor layer according to a first embodiment of the present disclosure. Figures 2 to 7 8 is a schematic diagram illustrating a transistor including the semiconductor layer according to the first embodiment of the present disclosure.

[0061] Reference Figures 1 to 3 , preparing a substrate 100 (S110). According to one embodiment, the substrate 100 may be a semiconductor substrate. For example, the substrate 100 may be a silicon (Si) substrate. Conversely, according to another embodiment, the substrate 100 may be a metal substrate, a plastic substrate, or a glass substrate. The type of the substrate 100 is not limited.

[0062] Reference Figures 1 to 7 , a semiconductor layer 200 may be formed on the substrate 100 (S120). According to one embodiment, the semiconductor layer 200 may be formed using an atomic layer deposition method. Specifically, as Figure 1 and Figure 2As shown, the formation of the semiconductor layer 200 may include: providing a first precursor on the substrate 100, purge, providing a first reaction source on the substrate 100 provided with the first precursor, purge, providing a second precursor on the substrate 100, purge, providing a second reaction source on the substrate 100 provided with the second precursor, and purge.

[0063] According to one embodiment, the first precursor may include indium (In). In contrast, the second precursor may include gallium (Ga). However, the first precursor and the second precursor may have the same ligand. More specifically, the first precursor may include a compound represented by the following Chemical Formula 1, and the second precursor may include a compound represented by the following Chemical Formula 2.

[0064] [Chemical Formula 1]

[0065]

[0066] [Chemical Formula 2]

[0067]

[0068] According to one embodiment, the first reaction source and the second reaction source may be identical. For example, the first reaction source and the second reaction source may include a plasma in which oxygen (O2) and argon (Ar) are mixed at a ratio of 50:50 wt%. When thin films are manufactured using this plasma, the quality is improved compared to thin films manufactured using existing sputtering systems.

[0069] As described above, when the first precursor includes indium (In), the second precursor includes gallium (Ga), and the first and second reaction sources include oxygen (O 2 ), the semiconductor layer 200 may include IGO.

[0070] A first unit process can be defined as providing a first precursor, purging, providing a first reaction source, and purging. In contrast, a second unit process can be defined as providing a second precursor, purging, providing a second reaction source, and purging. Furthermore, when the first and second unit processes are performed sequentially, they can be defined as a group process.

[0071] According to one embodiment, when the first unit process is performed, the first material layer 210 may be formed. In other words, the first precursor and the first reaction source may react to form the first material layer 210. In contrast, when the second unit process is performed, the second material layer 220 may be formed. In other words, the second precursor and the second reaction source may react to form the second material layer 220.

[0072] According to one embodiment, the group process may be repeated. Accordingly, the first material layer 210 and the second material layer 220 may be alternately and repeatedly formed on the substrate 100. In this case, the plurality of first material layers 210 and the plurality of second material layers 220 may be defined as the semiconductor layer 200.

[0073] According to another embodiment, the first unit process and the second unit process may each be repeated multiple times. When the first unit process and the second unit process are repeated multiple times, the thickness of each of the first material layer 210 and the second material layer 220 can be controlled. For example, as the number of repetitions of the first unit process increases, the thickness of the first material layer 210 increases. Furthermore, as the number of repetitions of the second unit process increases, the thickness of the second material layer 220 increases. As a result, the first material layer 210 and the second material layer 220 having controlled thicknesses can be deposited on the substrate 100. In this case, the first material layer 210 and the second material layer 220 having controlled thicknesses can be defined as the semiconductor layer 200.

[0074] As described above, the first precursor and the second precursor include the same ligand, and the semiconductor layer 200 can be formed by providing the first precursor, providing the second precursor, purging, providing a reaction source, and purging. The reaction source can be the same as the first and second reaction sources described above. This has the advantages of reducing process costs and simplifying the process because the number of purges is reduced compared to the case where the first unit process and the second unit process are performed sequentially.

[0075] According to one embodiment, the semiconductor layer 200 may not be divided into the first material layer 210 and the second material layer 220. More specifically, when the first material layer 210 and the second material layer 220 do not each have a predetermined thickness, the first material layer 210 and the second material layer 220 cannot be visually separated in the semiconductor layer 200.

[0076] On the contrary, according to another embodiment, the first material layer 210 and the second material layer 220 may be separated in the semiconductor layer 200. More specifically, when the first material layer 210 and the second material layer 220 are each formed to a predetermined thickness or more, the first material layer 210 and the second material layer 220 can be visually separated in the semiconductor layer 200.

[0077] According to one embodiment, the ratio of indium (In) and gallium (Ga) in the semiconductor layer 200 can be controlled by controlling the ratio of the first unit process and the second unit process. For example, the repetition rate of the first unit process can be controlled to be greater than 3 times and less than 9 times the repetition rate of the second unit process. In this case, in the semiconductor layer 200, the indium (In) content can be controlled to be greater than 25.3wt% and less than 33.5wt%, and the gallium (Ga) content can be controlled to be greater than 6.8wt% and less than 16.9wt%. Accordingly, the performance of the transistor including the semiconductor layer 200 can be improved. The specific structure of the transistor including the semiconductor layer 200 will be described later.

[0078] More specifically, when the repetition rate of the first unit process: the repetition rate of the second unit process is controlled to be 4:1 or 6:1, the electrical properties of the transistor including the semiconductor layer 200, such as mobility and on / off ratio (I 开 / I 关 ). When the repetition rate of the first unit process: the repetition rate of the second unit process is 4:1, the indium (In) content in the semiconductor layer 200 may be 28.6 wt %, and the gallium (Ga) content may be 12.6 wt %. In contrast, when the repetition rate of the first unit process: the repetition rate of the second unit process is 6:1, the indium (In) content in the semiconductor layer 200 may be 31.3 wt %, and the gallium (Ga) content may be 9.3 wt %.

[0079] According to one embodiment, when the first precursor and the second precursor have the same ligand, the ratio of the increase in the number of repetitions of the first unit process relative to the number of repetitions of the second unit process and the ratio of the decrease in the gallium (Ga) content relative to the indium (In) content in the semiconductor layer 200 can be substantially constant. For example, when the number of repetitions of the first unit process increases by 100% relative to the number of repetitions of the second unit process, the gallium (Ga) content relative to the indium (In) content in the semiconductor layer 200 decreases by approximately 100%.

[0080] Specifically, when the repetition rate of the first unit process: the repetition rate of the second unit process changes from 3:1 to 6:1, the indium (In) content: gallium (Ga) content in the semiconductor layer 200 changes from 1:0.67 to 1:0.30. As a result, when the first precursor and the second precursor have the same ligand, it is easy to control the indium (In) content and gallium (Ga) content in the semiconductor layer 200.

[0081] The semiconductor layer 200 may be heat-treated. For example, the semiconductor layer 200 may be heat-treated by ultraviolet (UV) rays. In contrast, as another example, the semiconductor layer 200 may be heat-treated in a furnace.

[0082] According to one embodiment, the temperature of the heat treatment of the semiconductor layer 200 can be controlled according to the number of repetitions of the first unit process and the number of repetitions of the second unit process. For example, when the number of repetitions of the first unit process: the number of repetitions of the second unit process is 4:1, the semiconductor layer 200 can be heat-treated at a temperature higher than 350° C. and lower than 450° C. In contrast, as another example, when the number of repetitions of the first unit process: the number of repetitions of the second unit process is 6:1, the semiconductor layer 200 can be heat-treated at a temperature higher than 300° C. and lower than 400° C. In this case, the performance (e.g., mobility, on / off ratio, etc.) of the transistor including the semiconductor layer 200 can be improved.

[0083] The semiconductor layer 200 can be used as the active layer of the transistor. Figure 8 As shown, the transistor may include: a substrate 100; a gate insulating film 110 arranged on the substrate 100; an active layer 200 arranged on the gate insulating film 110; and a source electrode (source, S) arranged on the gate insulating film 110 so as to contact one side of the active layer 200 and a drain electrode (drain, D) arranged on the gate insulating film 110 so as to contact the other side of the active layer 200.

[0084] In this case, in the active layer 200, the indium (In) content can be controlled to be greater than 25.3 wt% and less than 33.5 wt%, and the gallium (Ga) content can be controlled to be greater than 6.8 wt% and less than 16.9 wt%. In addition, during the manufacture of the active layer 200, the heat treatment temperature can be controlled to be greater than 300° C. and less than 400° C. or greater than 350° C. and less than 450° C. Accordingly, a 26.0 cm 2 / Vs or greater and a high on / off ratio (I 开 / I 关 ) transistor.

[0085] The method for manufacturing a semiconductor layer according to the first embodiment of the present disclosure includes: preparing a substrate 100; and performing a first unit process of reacting a first precursor including indium (In) with a first reaction source and a second unit process of reacting a second precursor including gallium (Ga) with a second reaction source to form a semiconductor layer 200 including indium and gallium on the substrate 100. The first precursor and the second precursor have the same ligand. Accordingly, the composition ratio of the semiconductor layer 200 is easily controlled, and thus, a transistor including the semiconductor layer 200 can have improved electrical performance and reliability.

[0086] Hereinafter, a method for manufacturing a semiconductor layer according to a first embodiment of the present disclosure will be described. Hereinafter, a method for manufacturing a semiconductor layer according to a second embodiment of the present disclosure will be described, which forms a semiconductor layer by reacting a precursor including indium (In) with a reaction source.

[0087] Figure 9 1 is a flowchart illustrating a method for manufacturing a semiconductor layer according to a second embodiment of the present disclosure. Figure 10 Schematic diagram showing a semiconductor layer according to a second embodiment of the present disclosure. Figure 11 and Figure 12 2 are schematic diagrams each showing a process of manufacturing a semiconductor layer according to a reaction source.

[0088] Reference Figure 9 and Figure 10 , preparing a substrate 100 (S210). According to one embodiment, the substrate 100 may be a semiconductor substrate. For example, the substrate 100 may be a silicon (Si) substrate. In contrast, according to another embodiment, the substrate 100 may be a metal substrate, a plastic substrate, or a glass substrate. The type of the substrate 100 is not limited.

[0089] A precursor including indium (In) may be provided on the substrate 100 (S220). For example, the precursor may include a compound represented by the following Chemical Formula 1.

[0090] [Chemical Formula 1]

[0091]

[0092] A reaction source may be provided on the substrate 100 provided with the precursor. In this case, the precursor and the reaction source may react. Accordingly, a semiconductor layer 200 may be formed (S230). According to one embodiment, a purge process may be performed before and after providing the reaction source. In other words, the semiconductor layer 200 may be formed by providing a precursor - purging - providing a reaction source - purging. The formation of the semiconductor layer may be performed at a first temperature.

[0093] According to one embodiment, the reaction source may include plasma in which oxygen (O2) and argon (Ar) are mixed in a ratio of 50:50 wt%. In contrast, according to another embodiment, the reaction source may include water (H2O). Therefore, the semiconductor layer 200 may include indium oxide (In x O y , x,y>0).

[0094] In other words, one can Figure 11 Provide precursor - purge - provide O2 / Ar plasma - purge, or by Figure 12As shown, the semiconductor layer 200 is formed by providing a precursor, purge, providing H 2 O, and purge.

[0095] According to one embodiment, the first temperature may be controlled according to the type of reaction source. For example, when the reaction source includes plasma in which oxygen (O2) and argon (Ar) are mixed, the first temperature may be a heat treatment temperature higher than 100°C and lower than 250°C. In contrast, as another example, when the reaction source includes water (H2O), the first temperature may be a heat treatment temperature higher than 100°C and lower than 200°C. In this case, the performance (e.g., mobility, on / off ratio, etc.) of the transistor including the semiconductor layer 200 may be improved.

[0096] The semiconductor layer 200 may be heat-treated at the second temperature (S240). For example, the semiconductor layer 200 may be heat-treated by ultraviolet (UV) rays. In contrast, as another example, the semiconductor layer 200 may be heat-treated in a furnace.

[0097] A method for manufacturing a semiconductor layer according to a second embodiment of the present disclosure includes: preparing a substrate 100; providing a precursor including indium on the substrate 100; providing a reaction source on the substrate 100 provided with the precursor to form a semiconductor layer 200, wherein the precursor reacts with the reaction source; and thermally treating the semiconductor layer 200, wherein the temperature of the thermal treatment of the semiconductor layer 200 is controlled according to the type of the reaction source. Accordingly, the electrical performance of a transistor including the semiconductor layer 200 can be improved.

[0098] In the above, the method of manufacturing a semiconductor layer and a transistor according to the embodiment of the present disclosure has been described. Hereinafter, specific experimental examples and performance evaluation results of the method of manufacturing a semiconductor layer and a transistor according to the embodiment of the present disclosure will be described.

[0099] Manufacturing of a Semiconductor Thin Film According to Example 1

[0100] The IGO semiconductor thin film according to Example 1 was manufactured on a substrate by performing a process of providing a first precursor, purging, providing an O2 / Ar (50:50 wt%) plasma, purging, providing a second precursor, purging, providing an O2 / Ar (50:50 wt%) plasma, and purging. As the first precursor and the second precursor, compounds represented by the following Chemical Formula 1 and Chemical Formula 2 were used, respectively.

[0101] [Chemical Formula 1]

[0102]

[0103] [Chemical Formula 2]

[0104]

[0105] In the above process, providing a first precursor-purging-providing O2 / Ar plasma-purging is defined as a first unit process, providing a second precursor-purging-providing O2 / Ar plasma-purging is defined as a second unit process, and each unit process is repeated.

[0106] More specifically, the first unit process and the second unit process were repeated at a ratio of 2:1, 3:1, 4:1, 6:1, 9:1, and 19:1, and the semiconductor thin films manufactured according to these ratios were defined as semiconductor thin films according to Example 1-1, Example 1-2, Example 1-3, Example 1-4, Example 1-5, and Example 1-6, respectively. The ratios of the first unit process to the second unit process in manufacturing the semiconductor thin films according to Examples 1-1 to 1-6 are summarized in Table 1 below.

[0107] [Table 1]

[0108] Classification First unit process (In): Second unit process (Ga) Example 1-1 2:1 Example 1-2 3:1 Examples 1-3 4:1 Examples 1-4 6:1 Examples 1-5 9:1 Examples 1-6 19:1

[0109] Fabrication of a semiconductor thin film according to Comparative Example 1

[0110] The IGO semiconductor thin film according to Comparative Example 1 was manufactured on a substrate by performing the steps of providing a first precursor, purging, providing O2 / Ar (50:50 wt%) plasma, purging, providing a second precursor, purging, providing O2 / Ar (50:50 wt%) plasma, and purging. DADI ([3-(dimethylamino)propyl]dimethylindium) was used as the first precursor, and TMGa (trimethylgallium) was used as the second precursor.

[0111] Furthermore, as described in the semiconductor thin film according to Example 1, the ratio of the first unit process to the second unit process was controlled to 2:1, 3:1, 4:1, 6:1, 9:1, and 19:1, and semiconductor thin films were manufactured according to each ratio. The semiconductor thin films manufactured according to each ratio were respectively defined as semiconductor thin films according to Comparative Examples 1-1 to 1-6.

[0112] Fabrication of a Transistor According to Example 1

[0113] After forming a SiO2 gate insulating film (thickness 100nm) on the Si gate, each semiconductor film (thickness 20nm), an ITO source electrode (thickness 100nm), and an ITO drain electrode (thickness 100nm) according to Examples 1-1 to 1-6 are formed on the gate insulating film to manufacture transistors according to Examples 1-1 to 1-6, respectively.

[0114] Figure 13 Graph showing the In growth rate in the semiconductor thin film according to Example 1 of the present disclosure. Figure 14is a graph showing the Ga growth rate in the semiconductor thin film according to Example 1 of the present disclosure.

[0115] Reference Figure 13 and Figure 14 , a semiconductor film according to Example 1 was prepared, and GPC ( / cycle) and refractive index as a function of the temperature of the first precursor and the second precursor (precursor temperature, ° C). The total growth temperature of the semiconductor film was controlled to 200 ° C, and the O2 / Ar plasma was controlled at 300 W and 5 s. In addition, the calculated deposition rate and actual deposition rate of the semiconductor films according to Examples 1-2 to 1-6 were measured, and the results are summarized in Table 2 below.

[0116] [Table 2]

[0117]

[0118] As shown in Table 2, the calculated deposition rates and the actual deposition rates of the semiconductor films according to Examples 1-3 were equal. Furthermore, the composition ratios of the semiconductor films according to Examples 1-2 to 1-6 were measured, and the composition ratios of the semiconductor films according to Comparative Examples 1-2 to 1-6 were measured. The composition ratios of the semiconductor films according to Examples 1-2 to 1-6 are summarized in Table 3 below, and the composition ratios of the semiconductor films according to Comparative Examples 1-2 to 1-6 are summarized in Table 4 below.

[0119] [Table 3]

[0120] Classification C％ In% Ga% O％ In:Ga ratio Example 1-2 (3:1) 2.0 25.3 16.9 55.8 1:0.67 Example 1-3 (4:1) 2.0 28.6 12.6 56.8 1:0.44 Example 1-4 (6:1) 1.9 31.3 9.3 57.4 1:0.30 Example 1-5 (9:1) 1.8 33.5 6.8 57.9 1:0.20 Example 1-6 (19:1) 1.7 36.0 3.6 58.7 1:0.10

[0121] [Table 4]

[0122] Classification C％ In% Ga% O％ In:Ga ratio Comparative Example 1-2 (3:1) 0.5 22.2 23.9 53.5 1:1.07 Comparative Example 1-3 (4:1) 0.4 24.6 20.7 54.4 1:0.84 Comparative Example 1-4 (6:1) 0.5 27.6 17.5 54.4 1:0.71 Comparative Example 1-5 (9:1) 0.2 31.0 13.5 55.2 1:0.44 Comparative Example 1-6 (19:1) 0.5 35.1 8.1 56.3 1:0.23

[0123] As shown in Table 3, in the semiconductor thin film according to Example 1, which was manufactured using precursors with the same ligands, the In:Ga ratio decreased from 1:0.67 to 1:0.30 when the ratio of the first unit process to the second unit process increased from 3:1 to 6:1. In other words, when the ratio of the number of repetitions of the first unit process to the second unit process increased by 100% (3 → 6), the Ga:In ratio decreased by approximately 100% (0.67 → 0.30). On the other hand, as shown in Table 4, in the semiconductor thin film according to Comparative Example 1, which was manufactured using precursors with different ligands, the In:Ga ratio decreased from 1:1.07 to 1:0.71 when the ratio of the first unit process to the second unit process increased from 3:1 to 6:1. In other words, when the ratio of the number of repetitions of the first unit process to the second unit process increased by 100% (3 → 6), the Ga:In ratio decreased by approximately 50% (1.07 → 0.71).

[0124] In other words, it can be seen that when a semiconductor film is manufactured using precursors having the same ligand, the ratio of the increase in the number of repetitions of the first unit process relative to the number of repetitions of the second unit process and the ratio of the decrease in the gallium (Ga) content relative to the indium (In) content in the semiconductor film are substantially constant. Consequently, it can be seen that when an IGO film is manufactured using precursors having the same ligand, the In and Ga contents in the IGO film can be easily controlled by controlling the order of the ALD processes.

[0125] Figure 15 and Figure 16 FIG1 is a graph showing electrical properties of a transistor according to Example 1, wherein the transistor includes the UV-annealed semiconductor thin film according to Example 1. ...

[0126] Reference Figure 15 and Figure 16 , transistors according to Examples 1-2 to 1-6 were prepared, the semiconductor thin film included in each transistor was UV annealed at a temperature of 250° C. and a temperature of 300° C., and the electrical properties of each transistor were measured and shown.

[0127] As in Figure 15 and Figure 16 As shown in the figure, it is shown that as the Ga ratio in the semiconductor film increases, the V th Specifically, it is shown that the transistor according to Example 1-3 (4:1) has the highest mobility (μ sat , cm 2 / Vs) and on / off ratio (I 开 / I 关 ), and is independent of UV annealing temperature.

[0128] Figures 17 to 20 Graphs showing electrical properties of a transistor according to Example 1 including the semiconductor thin film according to Example 1 heat-treated in a furnace.

[0129] Reference Figures 17 to 20 , transistors according to Examples 1-1 to 1-6 were prepared, the semiconductor thin film included in each transistor was heat-treated at temperatures of 300°C, 350°C, 400°C, and 450°C for 3 hours, and the electrical properties of each transistor were measured and shown. More specifically, Figure 17 The electrical properties of the transistor including the semiconductor thin film heat-treated at 300° C. are shown, and the results are summarized in the following Table 5. In addition, Figure 18 The electrical properties of the transistor including the semiconductor thin film heat-treated at 350° C. are shown, and the results are summarized in the following Table 6. In addition, Figure 19 The electrical properties of the transistor including the semiconductor thin film heat-treated at 400° C. are shown, and the results are summarized in the following Table 7. In addition, Figure 20 The electrical properties of the transistor including the semiconductor thin film heat-treated at 450° C. are shown, and the results are summarized in Table 8 below.

[0130] [Table 5]

[0131]

[0132]

[0133] [Table 6]

[0134]

[0135] [Table 7]

[0136]

[0137] [Table 8]

[0138]

[0139]

[0140] Furthermore, the mobility and on / off ratio of each semiconductor thin film of the transistors according to Examples 1-3 and 1-4 based on the heat treatment temperature are summarized in Tables 9 and 10 below.

[0141] [Table 9]

[0142] Classification <![CDATA[μ sat [cm 2 / Vs]]]> <![CDATA[I 开 / I 关 ]]> 300℃ 11.7±0.3 1.6E+9 350℃ 14.2±0.5 4.5E+9 400℃ 25.0±1.3 6.2E+10 450℃ 26.0±0.3 8.7E+9

[0143] As shown in Table 9, it is shown that when the number of repetitions of the first unit process: the number of repetitions of the second unit process is 4:1, the mobility (μ sat ) increases with increasing temperature. However, it is shown that before the temperature reaches 400°C, the on / off ratio (I 开 / I 关 ) gradually increases and then decreases again after 400 °C.

[0144] [Table 10]

[0145] Classification <![CDATA[μ sat [cm 2 / Vs]]]> <![CDATA[I 开 / I 关 ]]> 300℃ 15.1±0.6 7.5E+11 350℃ 19.2±0.3 1.1E+10 400℃ 17.9±1.7 8.5E+9 450℃ 17.8±0.4 1.4E+10

[0146] As shown in Table 10, it is shown that when the number of repetitions of the first unit process: the number of repetitions of the second unit process is 6:1, before the temperature is high to 350°C, the mobility (μ sat ) and on / off ratio (I 开 / I 关 ) increases and decreases thereafter. As a result, it can be seen from Tables 9 and 10 that when the ratio of the number of repetitions of the first unit process: the number of repetitions of the second unit process is 4:1, the electrical performance of the transistor is improved by controlling the heat treatment temperature of the semiconductor film to be higher than 350°C and lower than 450°C; and when the ratio of the number of repetitions of the first unit process: the number of repetitions of the second unit process is 6:1, the electrical performance of the transistor is improved by controlling the heat treatment temperature of the semiconductor film to be higher than 300°C and lower than 400°C.

[0147] Manufacturing of a Semiconductor Thin Film According to Example 2

[0148] The In2O3 semiconductor thin film according to Example 2 was manufactured by performing the steps of providing an In precursor, purging, providing O2 / Ar (50:50 wt %) plasma, purging, fabricating a thin film on a substrate, and UV annealing the fabricated thin film at a temperature of 250° C. for 1 hour. As the In precursor, a compound represented by the following Chemical Formula 1 was used.

[0149] [Chemical Formula 1]

[0150]

[0151] Furthermore, the process temperatures of providing an In precursor, purging, providing O2 / Ar (50:50 wt%) plasma, and purging were controlled at 100°C, 150°C, 200°C, and 250°C to manufacture semiconductor thin films, and the films manufactured at each temperature were defined as semiconductor thin films according to Examples 2-1, 2-2, 2-3, and 2-4, respectively. The process temperatures of the semiconductor thin films according to Examples 2-1, 2-2, 2-3, and 2-4 are summarized in Table 11 below.

[0152] [Table 11]

[0153] Classification ALD process temperature Example 2-1 100℃ Example 2-2 150℃ Example 2-3 200℃ Examples 2-4 250℃

[0154] Fabrication of a Transistor According to Example 2

[0155] After forming a SiO2 gate insulating film (thickness 100nm) on the Si gate, each semiconductor film (thickness 20nm), an ITO source electrode (thickness 100nm), and an ITO drain electrode (thickness 100nm) according to Examples 2-1 to 2-4 are formed on the gate insulating film to manufacture each transistor according to Examples 2-1 to 2-4.

[0156] Figure 21 is a graph showing the electrical properties of the semiconductor thin film according to Example 2 of the present disclosure.

[0157] Reference Figure 21 The carrier concentration (cm2) of each semiconductor thin film according to Examples 2-1 (100°C), 2-2 (150°C), 2-3 (200°C) and 2-4 (250°C) was measured and shown. -3 ), Hall mobility (cm 2 / Vsec) and resistivity (Ohmcm).

[0158] As in Figure 21 As shown in , it is shown that, in the semiconductor thin film according to Example 2, as the process temperature of the semiconductor thin film increases, the carrier concentration and the Hall mobility increase, while the resistivity decreases.

[0159] Figure 22 is a graph showing the structure of a semiconductor thin film according to Example 2 of the present disclosure.

[0160] Reference Figure 22 , the crystal structures of the semiconductor thin films according to Examples 2-1 (100°C), 2-2 (150°C), 2-3 (200°C) and 2-4 (250°C) were measured and shown. Figure 22 As shown in , it is shown that all semiconductor thin films according to Examples 2-1 to 2-4 have a cubic structure, that is, the general structure of In2O3.

[0161] Furthermore, the O / In ratios and impurities of the semiconductor thin films according to Examples 2-1 to 2-4 were measured, and the results are summarized in Table 12 below.

[0162] [Table 12]

[0163]

[0164] As shown in Table 12, it is shown that, in the semiconductor thin films according to Examples 2-1 to 2-4, there are no carbon and nitrogen impurities, and In / O shows an ideal value of 1:2. Figures 23 to 26 is a graph showing the electrical performance of the transistor according to Example 2 of the present disclosure.

[0165] Reference Figures 23 to 26 , the gate voltage (V)-dependent drain current of each transistor according to Examples 2-1 to 2-4 of the present disclosure is measured and shown. Figure 23 and Figure 26 As shown in , it is shown that a transistor including a semiconductor thin film deposited at a temperature of 100° C. has an insulating property, while a transistor including a semiconductor thin film deposited at a temperature of 250° C. has a conductive property. On the other hand, as shown in Figure 24 and Figure 25 As shown in , it is shown that, in transistors including semiconductor thin films deposited at temperatures of 150° C. and 200° C., the semiconductor thin films exhibit semiconductor properties because these semiconductor thin films are subjected to UV heat treatment.

[0166] As a result, it can be seen that when an In2O3 semiconductor film is manufactured using a process of providing an In precursor-purge-providing O2 / Ar (50:50wt%) plasma-purge, in order to improve the electrical performance of the transistor, it is effective to control the deposition temperature of the semiconductor film to be higher than 100°C and lower than 250°C.

[0167] Manufacturing of a Semiconductor Thin Film According to Example 3

[0168] The In2O3 semiconductor thin film according to Example 3 was manufactured by performing In precursor supply-purge-H2O supply-purge, fabricating a thin film on a substrate, and UV annealing the fabricated thin film at a temperature of 250°C for 1 hour. As the In precursor, a compound represented by the following Chemical Formula 1 was used.

[0169] [Chemical Formula 1]

[0170]

[0171] Furthermore, the process temperatures of providing an In precursor, purging, providing H2O, and purging were controlled at 100°C, 150°C, 200°C, and 250°C to produce semiconductor thin films, and the films produced at each temperature were defined as semiconductor thin films according to Examples 3-1, 3-2, 3-3, and 3-4. The process temperatures of the semiconductor thin films according to Examples 3-1, 3-2, 3-3, and 3-4 are summarized in Table 11 below.

[0172] [Table 13]

[0173] Classification ALD process temperature Example 3-1 100℃ Example 3-2 150℃ Example 3-3 200℃ Examples 3-4 250℃

[0174] Fabrication of a Transistor According to Example 3

[0175] After forming a SiO2 gate insulating film (thickness 100nm) on the Si gate, each semiconductor thin film (thickness 20nm), an ITO source electrode (thickness 100nm), and an ITO drain electrode (thickness 100nm) according to Examples 3-1 to 3-4 are formed on the gate insulating film to manufacture each transistor according to Examples 3-1 to 3-4.

[0176] Figure 27 is a graph showing the electrical properties of the semiconductor thin film according to Example 3 of the present disclosure.

[0177] Reference Figure 27 The carrier concentration (cm2) of each semiconductor thin film according to Examples 3-1 (100°C), 3-2 (150°C), 3-3 (200°C) and 3-4 (250°C) was measured and shown. -3 ), Hall mobility (cm 2 / Vsec) and resistivity (Ohmcm).

[0178] As in Figure 27 As shown in , it is shown that, in the semiconductor thin film according to Example 3, as the process temperature of the semiconductor thin film increases, the carrier concentration increases, the resistivity decreases, and the Hall mobility remains constant.

[0179] Figure 28 is a graph showing the structure of a semiconductor thin film according to Example 3 of the present disclosure.

[0180] Reference Figure 28 , the crystal structures of the semiconductor thin films according to Examples 3-1 (100°C), 3-2 (150°C), 3-3 (200°C) and 3-4 (250°C) are measured and shown. Figure 28 As shown in , it is shown that the semiconductor films according to Examples 3-1 (100°C) and 3-2 (150°C) both have a cubic structure, that is, the general structure of In2O3, while the semiconductor films according to Examples 3-3 (200°C) and 3-4 (250°C) both have a rhombohedral structure.

[0181] Furthermore, the O / In ratios and impurities of the semiconductor thin films according to Examples 3-1 to 3-4 were measured, and the results are summarized in Table 14 below.

[0182] [Table 14]

[0183] Classification O / In ratio impurities Example 3-1 (100°C) 1.27 C:14.62 Example 3-2 (150°C) 1.29 C:1.51 Example 3-3 (200°C) 1.60 C:1.24 Example 3-4 (250°C) 1.62 C:1.43

[0184] As shown in Table 14, it is shown that in the semiconductor thin films according to Examples 3-1 to 3-4, the O / In ratio is approximately 1.3 when the process temperatures are 100°C and 150°C, and is approximately 1.6 when the process temperatures are 200°C and 250°C, which is the same as the trend of the crystal structure, and includes approximately 14% of carbon impurities when the process temperature is 100°C. Figures 29 to 32 is a graph showing the electrical performance of the transistor according to Example 3 of the present disclosure.

[0185] Reference Figures 29 to 32 , the gate voltage (V)-dependent drain current (A) of each transistor according to Examples 3-1 to 3-4 of the present disclosure is measured and shown. Figure 29 As shown in FIG, it is shown that a transistor including a semiconductor thin film deposited at a temperature of 100° C. has an insulator property, as shown in FIG. Figure 31 and Figure 32 As shown in , transistors comprising semiconductor thin films deposited at temperatures of 200°C and 250°C have conductive properties. On the other hand, as shown in Figure 30 As shown in , it is shown that, in a transistor including a semiconductor thin film deposited at a temperature of 150° C., the semiconductor thin film exhibits semiconductor properties because the semiconductor thin film is subjected to UV heat treatment.

[0186] As a result, it can be seen that when an In2O3 semiconductor film is manufactured using the process of providing an In precursor-purging-providing H2O-purging, in order to improve the electrical performance of the transistor, it is effective to control the deposition temperature of the semiconductor film to be higher than 100°C and lower than 200°C.

[0187] In the above, the present disclosure has been described in detail using the preferred embodiments, however, the scope of the present disclosure is not limited to the specific embodiments, but should be interpreted by the appended claims. In addition, it should be understood that various modifications and changes can be made by those skilled in the art without departing from the scope of the present disclosure.

[0188] Industrial Applicability

[0189] The method for manufacturing a semiconductor layer according to the present disclosure includes: preparing a substrate; and performing a first unit process of reacting a first precursor including indium (In) with a first reaction source and a second unit process of reacting a second precursor including gallium (Ga) with a second reaction source to form a semiconductor layer including indium and gallium on the substrate, wherein the first precursor and the second precursor may have the same ligand. As a result, the composition ratio in the semiconductor layer is easily controlled, and therefore, a transistor including the semiconductor layer can have improved electrical performance and reliability.

Claims

1. A method for manufacturing a semiconductor layer, the method comprising: preparing the substrate; and performing a first unit process of reacting a first precursor including indium (In) with a first reaction source and a second unit process of reacting a second precursor including gallium (Ga) with a second reaction source to form a semiconductor layer including the indium and the gallium on the substrate, wherein the first precursor and the second precursor have ligands with the same chemical structure, The first precursor includes a compound represented by the following chemical formula 1, and the second precursor includes a compound represented by the following chemical formula 2: [Chemical Formula 1] [Chemical Formula 2] 2. The method according to claim 1, further comprising: After forming the semiconductor layer, heat-treating the semiconductor layer, Wherein, the temperature of the heat treatment of the semiconductor layer is controlled according to the number of repetitions of the first unit process and the number of repetitions of the second unit process.

3. The method according to claim 2, wherein: When the ratio of the number of repetitions of the first unit process to the number of repetitions of the second unit process is 4:1, the semiconductor layer is heat-treated at a temperature higher than 350° C. and lower than 450° C.

4. The method according to claim 2, wherein: When the ratio of the number of repetitions of the first unit process to the number of repetitions of the second unit process is 6:1, the semiconductor layer is heat-treated at a temperature higher than 300° C. and lower than 400° C.

5. The method according to claim 2, wherein: The semiconductor layer is heat-treated by ultraviolet (UV) rays.

6. The method according to claim 1, wherein The first reaction source and the second reaction source include plasma of a mixture of oxygen (O2) and argon (Ar).

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