Method for implementing integrated all-optical logic gates based on chip plating structure

Abstract

The application realizes free switching of seven operation functions of and, or, not, and not, or not, exclusive or and same or by using single device structure and simple electrical control. Transition metal sulfide and other plating materials are transferred to waveguide structures such as micro ring cavities; the resonance intrinsic wavelength of the micro ring cavity is tuned by controlling the free carrier concentration of the plating layer by bias voltage, the two light fields carrying input bits change the free carrier concentration of the plating layer to cause the resonance wavelength shift of the micro ring cavity; the output light fields from the straight-through port and the upload and download ports will have characteristics related to the incident light fields; by adjusting the resonance intrinsic wavelength and selecting the output port, various logic operations are realized. The application can realize various all-optical logic operations by using a single structure, does not need high-speed electrical signal control and is highly compatible with the existing preparation process, as a kind of general all-optical logic gate device, lays a solid foundation for building a chip integrated super large scale all-optical computing system.

Description

TECHNICAL FIELD

[0001] The present application belongs to the cross-disciplinary field of integrated optics, optical computing and microwave photonics, and specifically refers to a full-optical logic gate system for realizing seven operations of and, or, not, and not, or not, XOR and XNOR by adjusting the refractive index of the chip-integrated waveguide using the plating layer material such as transition metal sulfide to generate free carriers. BACKGROUND

[0002] The full-optical computing system mainly realizes various complex computing functions through optical effects, and may have higher computing performance than traditional computers in solving specific problems. At present, the full-optical computing system is mainly based on free-space optical path or all-optical fiber optical path, and faces problems such as large volume, high power consumption, poor stability, high failure rate and the like. More importantly, with the exponential increase in the scale of the full-optical computing system, the existing free-space optical path and all-optical fiber optical path coupling mode seriously lags behind the upgrading of the large-scale full-optical computing system. On the other hand, the chip-integrated optical path has the advantages of small volume, low power consumption, rich functions, stable performance, board card integration, batch production and the like, and is highly compatible with the traditional chip-integrated circuit technology, and can mix and integrate functional optical paths and logic circuits on a single chip, and is expected to become the preferred technical solution for the future full-optical computing system.

[0003] The full-optical logic gate is the core of the full-optical computing, and its main function is to realize the logical operation of optical bits. The smaller the size of the full-optical logic gate, the lower the power consumption, the simpler the structure, and the larger the scale of the full-optical computing system that can be constructed. However, at present, the full-optical logic gate is mainly realized by optical interference and optical switch, and the structures of the optical paths of the gates for different logic functions are quite different, which are difficult to be integrated and always need to be controlled by high-speed electrical signals. SUMMARY

[0004] In view of the above defects, the technical problem to be solved by the present application is how to realize the integration of micro-ring cavities, carrier straight waveguides, incident straight waveguides and the like on a single chip, and cover the plating layer material such as transition metal sulfide on the waveguide, input two light fields carrying incident bits from the incident straight waveguide, and input the reference light field for generating the output bits from the carrier straight waveguide; apply a bias voltage on the external electrode, change the free carrier concentration of the plating layer material, adjust the intrinsic resonance wavelength of the micro-ring cavity, input the incident light field into the incident straight waveguide, change the free carrier concentration of the plating layer material, and adjust the resonance wavelength of the micro-ring cavity; under the dual action of the external voltage and the incident light field, the reference light field carrying the output bits is output from different ports, and the chip-integrated full-optical logic gate function is realized.

[0005] In view of the above defects, the purpose of the present application is to provide a method for realizing integrated all-optical logic gates based on plating layer structure of chip, which realizes free switching of seven operation functions of AND, OR, NOT, NAND, NOR, XOR and XNOR by using single device structure and simple electrical control. Specifically, transition metal sulfide and other plating layer materials are transferred to waveguide structures such as micro-ring cavities; the plating layer free carrier concentration is controlled by bias voltage to tune the micro-ring cavity resonance intrinsic wavelength, and two light fields carrying input bits change the plating layer free carrier concentration to cause the micro-ring cavity resonance wavelength shift; the reference light field and the resonance condition of the micro-ring cavity change, and the output light field from the all-pass port and the add-drop port will have characteristics related to the incident light field; by adjusting the resonance intrinsic wavelength and selecting the output port, various logic operations can be realized.

[0006] In order to achieve the above effects, the method for realizing integrated all-optical logic gates based on plating layer structure of chip provided by the present application prepares double-carrier straight waveguide micro-ring cavities on a single chip, prepares two incident straight waveguides near the micro-ring cavities, transfers transition metal sulfide and other plating layer materials to the surfaces of all waveguides and prepares external electrodes, inputs two light fields carrying incident bits into the incident straight waveguides and causes the plating layer free carrier concentration to change and adjust the micro-ring cavity resonance wavelength, changes the plating layer free carrier concentration by applying a bias voltage to the external electrodes and adjusts the micro-ring cavity intrinsic resonance wavelength, and changes the truth table of the input light field and the output light field to realize all-optical logic gate function switching.

[0007] Preferably, the reference light field of the incident carrier straight waveguide in the above method will switch between the in-tune and off-tune states and be output from different ports to realize all-optical logic operation.

[0008] Preferably, the above method specifically includes the following steps:

[0009] S1, preparing micro-ring cavities, carrier straight waveguides and incident straight waveguide optical structures by chip integrated optical path standard process, transferring transition metal sulfide and other plating layer materials to the surfaces of all waveguides and preparing external electrodes;

[0010] S2, inputting two light fields carrying incident bits into the incident straight waveguides, causing the plating layer free carrier concentration to change and tuning the micro-ring cavity resonance wavelength, inputting the reference light field into the carrier straight waveguide, outputting from one output port under the in-tune condition and outputting from another output port under the off-tune condition;

[0011] S3, applying different bias voltages to the plating layer through the external electrodes to adjust the micro-ring cavity intrinsic resonance frequency to realize the in-tune or off-tune state of the reference light field, under the dual action of electrical control tuning and optical control tuning of the micro-ring cavity resonance frequency, the reference light field is output from different ports to realize free switching of seven operation functions of AND, OR, NOT, NAND, NOR, XOR and XNOR.

[0012] Preferably, the above method changes the micro-ring cavity resonance wavelength by the photo-induced free carriers of the plating layer material through the transmission of the two incident straight waveguide light fields and the electro-induced free carriers of the plating layer material through the external electrode, so that the reference light field input by the carrier straight waveguide is output from different ports as needed.

[0013] Preferably, the above method realizes various logic operations by adjusting the resonant intrinsic wavelength and selecting the output port.

[0014] Preferably, in the all-optical logic operation of the above method, two light fields carry the logic bit input logic gate, and the high / low of the light field intensity corresponds to the 1 / 0 of the logic bit; in various logic operations, the center frequencies of the input light field and the output light field are consistent.

[0015] Preferably, the plating layer is transferred to the surface of the integrated waveguide of the chip through the growth process control parameter and the standard process without damage, and is tightly attached to realize the accurate regulation of the electro-optical parameter with the crystal structure and the layered thickness as the degrees of freedom.

[0016] The application provides a system for realizing integrated all-optical logic gates based on a plating layer structure of a chip, which comprises a single chip integrated with a micro-ring cavity, a carrier straight waveguide, an incident straight waveguide and other optical devices, a double-carrier straight waveguide micro-ring cavity is prepared on the single chip, two incident straight waveguides are prepared near the micro-ring cavity, a plating layer material such as a transition metal sulfide is transferred to the surfaces of all waveguides and an external electrode is prepared, two light fields carrying incident bits are input into the incident straight waveguides to cause the change of the free carrier concentration of the plating layer and the adjustment of the micro-ring cavity resonance wavelength, a bias voltage is applied to the external electrode to change the free carrier concentration of the plating layer and adjust the intrinsic resonance wavelength of the micro-ring cavity, and the truth table of the input light field and the output light field is changed to realize the switching of the all-optical logic gate function.

[0017] Preferably, the above system realizes the free switching of the seven operation functions of and, or, not, and not, or not, exclusive or and same or by using a single device structure and electrical control, changes the micro-ring cavity resonance wavelength by the photo-induced free carriers of the plating layer material through the transmission of the two incident straight waveguide light fields and the electro-induced free carriers of the plating layer material through the external electrode, so that the reference light field input by the carrier straight waveguide is output from different ports as needed; various logic operations can be realized by adjusting the resonant intrinsic wavelength and selecting the output port.

[0018] Compared with the prior art, the application achieves the following technical effects:

[0019] Firstly, the application provides a device design scheme highly compatible with the existing preparation process for a chip integrated all-optical computing system, which can realize various logic operations through simple structures such as a micro-ring cavity, a straight waveguide, a plating layer material and an external electrode, and greatly improves the universality and adaptability of the all-optical logic gate;

[0020] Secondly, the all-optical logic gate can be switched between various logic operations flexibly, and the main function of the external electrode is to maintain the micro-ring cavity resonant wavelength stable and tune the micro-ring cavity intrinsic resonant wavelength without high-speed electrical signal control.

[0021] In addition, the method can provide a feasible means for all-optical signal interoperation, that is, using the plating layer material as a medium, realizing the interaction of two light fields by controlling the free carrier concentration of the plating layer material without light field coupling. BRIEF DESCRIPTION OF DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments of the present application will be briefly introduced as follows, and other drawings can also be obtained by those of ordinary skill in the art without creative labor on the premise that there is no creative labor.

[0023] Figure 1 The chip integrated all-optical logic gate structure based on the plating layer structure of the present application is shown in the schematic diagram.

[0024] Figure 2 The method for realizing integrated all-optical logic gate based on the plating layer structure of the present application is shown in the schematic diagram. DETAILED DESCRIPTION

[0025] The features and exemplary embodiments of various aspects of the present application will be described in detail below, in order to make the purposes, technical solutions and advantages of the present application more clear and apparent, the present application will be further described in detail below in combination with the drawings and embodiments. It should be understood that the specific embodiments described herein are only configured to explain the present application, and are not configured to limit the present application. The present application can be implemented without some of these specific details for those skilled in the art. The following description of the embodiments is only to provide a better understanding of the present application by showing examples of the present application.

[0026] It should be noted that in this paper, relationship terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between the entities or operations. Moreover, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or equipment. Without more limitations, the elements defined by the statement "include" do not exclude the presence of other identical elements in the process, method, article or equipment including the elements.

[0027] The application provides an embodiment of a method for realizing integrated all-optical logic gates based on a plating layer structure chip, comprising the following steps:

[0028] In S101, micro-ring cavities, carrier straight waveguides, incident straight waveguides and other optical structures are prepared through a chip integrated optical path standard process, plating layer materials such as transition metal sulfides are transferred to the surfaces of all the waveguides, and external electrodes are prepared;

[0029] In S102, two light field inputs carrying incident bits are input into the incident straight waveguides, the plating layer free carrier concentration is changed, and the micro-ring cavity resonance wavelength is tuned, the reference light field is input into the carrier straight waveguide, and under the harmonic condition, the reference light field is output from the upload and download Add-drop ports, and under the detuning condition, the reference light field is output from the straight-through All-pass port;

[0030] In S103, different bias voltages are applied to the plating layer through the external electrodes, the intrinsic resonance frequency of the micro-ring cavity is adjusted to realize the in-harmonic or detuning state of the reference light field, and under the electrically controlled tuning and optically controlled tuning of the micro-ring cavity resonance frequency, the reference light field is output from different ports, and the free switching of the and, or, not, and not, or not, exclusive or and same or common seven operation functions is realized.

[0031] As shown in the figure, Figure 1 The embodiment shows a structural embodiment of a chip integrated all-optical logic gate based on a plating layer structure: incident light fields are input from two ports I1 and I2 on the right through a grating coupler, a reference light field is input from a port in the lower left corner through a grating coupler, the incident light fields and the reference light field are subjected to intensity modulation, the repetition frequency and the arrival time are consistent, the incident light fields input from I1 and I2 carry logic bit sequences to be calculated, and the reference light field carries a full-1 logic bit sequence; when the wavelength of the reference light field is consistent with the micro-ring resonance wavelength (in the harmonic condition), the reference light field is output from the Add-drop port (O1) through micro-ring coupling, and when the wavelength of the reference light field is different from the micro-ring resonance wavelength (detuning condition), the reference light field is output from the All-pass port (O2); the incident light field will generate photo-induced free carriers in the plating layer material and change the micro-ring cavity resonance wavelength, the tuning value of a single incident light field on the micro-ring cavity resonance wavelength is A, and the tuning value of a double incident light field on the micro-ring cavity resonance wavelength is 2A; after the light field is removed, the micro-ring cavity resonance wavelength recovery time is much smaller than the pulse period of the reference light field and the incident light field, and then the working principles of each logic gate are as follows:

[0032] (1) Not operation: a bias voltage is applied through an external electrode, the electrically controlled bias tuning value between the intrinsic resonance wavelength of the micro-ring cavity and the wavelength of the reference light is -A, I1 is taken as an input end, and O2 is taken as an output end. When I1=1, the reference light field satisfies the harmonic condition and is output from O1, at this time, O2=0; when I2=0, the reference light field satisfies the detuning condition and is output from O2, at this time, O2=1;

[0033] (2) AND operation: A bias voltage is applied through an external electrode. The electrically controlled bias tuning value between the intrinsic resonant wavelength of the micro-ring cavity and the reference light wavelength is -2A. I1 and I2 are the input terminals, and O1 is the output terminal. When I1=1 and I2=1, the reference light field satisfies the in-tuning condition and is output from O1, at which time O1=1; in other cases, the reference light field satisfies the detuning condition and is output from O2, at which time O1=0.

[0034] (3) NAND operation: A bias voltage is applied through an external electrode. The electrically controlled bias tuning value between the intrinsic resonant wavelength of the micro-ring cavity and the reference light wavelength is -2A. I1 and I2 are the input terminals, and O2 is the output terminal. When I1=1 and I2=1, the reference light field satisfies the in-tuning condition and is output from O1. At this time, O2=1. In other cases, the reference light field satisfies the detuning condition and is output from O2. At this time, O2=1.

[0035] (4) OR operation: A bias voltage is applied through an external electrode, and the electrically controlled bias tuning value between the intrinsic resonant wavelength of the micro-ring cavity and the reference light wavelength is 0. I1 and I2 are the input terminals, and O2 is the output terminal. When I1=0 and I2=0, the reference light field satisfies the in-tuning condition and is output from O1, at which time O2=0; in other cases, the reference light field satisfies the detuning condition and is output from O2, at which time O2=1.

[0036] (5) NOR operation: A bias voltage is applied through an external electrode, and the electrically controlled bias tuning value between the intrinsic resonant wavelength of the micro-ring cavity and the reference light wavelength is 0. I1 and I2 are the input terminals, and O1 is the output terminal. When I1=0 and I2=0, the reference light field satisfies the in-tuning condition and is output from O1, at which time O1=1; in other cases, the reference light field satisfies the detuning condition and is output from O2, at which time O1=0.

[0037] (6) XOR operation: A bias voltage is applied through an external electrode. The electrically controlled bias tuning value between the intrinsic resonant wavelength of the micro-ring cavity and the reference light wavelength is -A. I1 and I2 are the input terminals, and O1 is the output terminal. When I1=I2, the reference light field satisfies the detuning condition (A or -A) and is output from O2. At this time, O1=0. In other cases, the reference light field satisfies the in-tuning condition and is output from O1. At this time, O1=1.

[0038] (7) XOR operation: A bias voltage is applied through an external electrode, and the electrically controlled bias tuning value between the intrinsic resonant wavelength of the micro-ring cavity and the reference light wavelength is -A. I1 and I2 are the input terminals, and O2 is the output terminal. When I1=I2, the reference light field satisfies the detuning condition (A or -A) and is output from O2, at which time O2=1. In other cases, the reference light field satisfies the in-tuning condition and is output from O1, at which time O2=0.

[0039] like Figure 2 As shown, this embodiment also provides a method for implementing integrated all-optical logic gates on a chip based on a coating structure, including:

[0040] S201, device preparation, prepare a dual-carrier straight waveguide micro-ring cavity on a single chip, prepare two incident straight waveguides near the micro-ring cavity, transfer transition metal sulfide coating materials to the surfaces of all waveguides and prepare external electrodes;

[0041] S202, all-optical logic gate function implementation, input two light fields carrying incident bits into the incident straight waveguide and cause the coating free carrier concentration to change and adjust the micro-ring cavity resonance wavelength, at this time the reference light field of the incident carrier straight waveguide will switch between "in resonance" and "off resonance" and be output from different ports, that is, all-optical logic operation is realized;

[0042] S203, all-optical logic gate function switching, change the free carrier concentration by applying a bias voltage to the external electrode and adjust the intrinsic resonance wavelength of the micro-ring cavity, change the truth table of the input light field and the output light field to realize the switching of the all-optical logic gate function.

[0043] In some embodiments, step two adjusts the refractive index of the chip-integrated waveguide by changing the free carrier concentration and realizes electro-optic phase modulation of the transmitted light field, at this time the phase distribution of the transmitted light field will reproduce the modulation electrical signal distribution.

[0044] In some embodiments, the chip-integrated waveguide is prepared by chip-integrated optical path standard process, has a certain degree of freedom in structure design, efficiently and losslessly transmits light field, and produces refractive index change under the action of free carrier. The material platform used by the chip-integrated waveguide includes but is not limited to silicon-on-insulator, hydrogen-loaded amorphous silicon, silicon nitride, silicon carbide, sulfur glass, high refractive index quartz, group III-V aluminum gallium arsenide, group III-V indium phosphide, etc. Both single material integration method and multi-material mixed integration method can be used.

[0045] In some embodiments, the coating is transferred to the surface of the chip-integrated waveguide by growth process control parameters and standard process without loss and realizes close adhesion, and the electro-optic parameters are accurately controlled with the freedom of crystal structure and layer thickness; The voltage-sensitive two-dimensional layered material coating can be used as a substrate to stably grow an electrode and produce free carrier concentration changes under the action of external voltage; The environment variable-sensitive two-dimensional layered material coating produces a physical response under the action of an environmental variable, the physical response causes the optical refractive index to change, and the coating material includes but is not limited to graphene, molybdenum disulfide, tungsten sulfide, perovskite, etc., without limitation on specific structure parameters and preparation process.

[0046] In some embodiments, in all-optical logic operation, two light fields carry logic bit inputs into the logic gate, and the high / low of the light field intensity corresponds to the 1 / 0 of the logic bit; In various logic operations, the center frequencies of the input light field and the output light field are consistent, and the intensity is not strictly required to be uniform as long as it can distinguish the logic bit.

[0047] In some embodiments, the optical switch carrier includes, but is not limited to, a micro-ring cavity, a micro-disk cavity, a Fabry-Perot cavity, a photonic crystal microcavity, etc., and the coating layer tuning parameters include, but are not limited to, a free carrier concentration, a conductivity, a refractive index, etc., without limiting the all-optical logic operation frequency, the optical field coupling mode, the circuit control mode, the specific parameters of the photonic device and the electronic device, the combination mode of the all-optical logic gate, the specific function, and the application scenario.

[0048] Compared with the prior art, the present application has the following advantages:

[0049] Firstly, the present application provides a device design scheme highly compatible with the existing preparation process for a chip integrated all-optical computing system, which can realize various logic operations through simple structures such as a micro-ring cavity, a straight waveguide, a coating material, and an external electrode, greatly improving the versatility and universality of the all-optical logic gate.

[0050] Secondly, the all-optical logic gate described in the present application can be flexibly switched between various logic operations, and the main function of the external electrode is to maintain the stability of the micro-ring cavity resonance wavelength and tune the intrinsic resonance wavelength of the micro-ring cavity without the need for high-speed electrical signal control.

[0051] In addition, the method described in the present application can also provide a feasible means for all-optical signal interoperation, i.e., using the coating material as a medium, controlling the free carrier concentration of the coating material, and realizing the interaction between two optical fields without optical field coupling.

[0052] For the convenience of description, the above device is described as various units divided by functions. Of course, the functions of each unit can be implemented in the same or multiple software and / or hardware in the implementation of the present application.

[0053] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can take the form of a computer program product implemented on one or more computer usable storage media (including, but not limited to, magnetic disk storage, CD-ROM, optical storage, etc.) containing computer usable program code.

[0054] The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks or in conjunction with the flowcharts described above. Figure 1 one or more flowcharts and / or blocks Figure 1 means for functionally implementing each of the flowchart blocks or the functions noted in the blocks or a combination of flows and / or blocks.

[0055] The application can be described in the general context of computer-executable instructions, such as program modules, being executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, and the like, that perform particular tasks or implement particular abstract data types. The application can also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network. In a distributed computing environment, program modules can be located in local and remote computer storage media including memory storage devices.

[0056] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instructions which implement the flowchart Figure 1 one or more flowcharts and / or blocks Figure 1 means for functionally implementing each of the flowchart blocks or the functions noted in the blocks or a combination of flows and / or blocks.

[0057] The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart Figure 1 one or more flowcharts and / or blocks Figure 1 means for functionally implementing each of the flowchart blocks or the functions noted in the blocks or a combination of flows and / or blocks.

[0058] In a typical configuration, a computing device includes one or more processors (CPUs), input / output interfaces, network interfaces, and memory.

[0059] The memory can include non-persistent memory and / or volatile memory, such as random access memory (RAM) and / or cache memory, non-volatile memory, such as read-only memory (ROM), optical or optical disk storage, flash memory, etc. The memory is an example of computer-readable media.

[0060] Computer-readable media includes permanent and non-permanent, movable and non-movable media that can be implemented by any method or technology to store information. The information can be computer-readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassette, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information accessible to a computing device. According to the definition herein, computer-readable media does not include transitory media such as modulated data signals and carriers.

[0061] It should also be noted that the terms "comprising", "containing", or any other variant thereof are intended to cover non-exclusive inclusion, so that processes, methods, articles or devices that include a series of elements not only include those elements, but also include other elements not explicitly listed or inherent to such processes, methods, articles or devices. Without more limitations, the element defined by the statement "comprising a" does not exclude the presence of additional identical elements in the process, method, article or device that includes the element.

[0062] Each of the embodiments in the specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other. Each embodiment focuses on the difference from other embodiments. In particular, for system embodiments, since they are basically similar to method embodiments, the description is relatively simple, and the relevant parts can be referred to the part of the method embodiment.

[0063] The above only describes the embodiments of the present application and does not limit the present application. Those skilled in the art can make various modifications and changes to the present application. Any modification, equivalent replacement, improvement, etc. within the spirit and principle of the present application shall be included in the scope of claims of the present application.

Claims

1. A method for implementing integrated all-optical logic gates based on plating layer structure on a chip, comprising the following steps: preparing a dual-carrier straight waveguide micro-ring cavity on a single chip, preparing two incident straight waveguides near the micro-ring cavity, transferring transition metal sulfide to the surfaces of all waveguides and preparing external electrodes, inputting two optical fields carrying incident bits into the incident straight waveguides and causing the plating layer free carrier concentration to change and the micro-ring cavity resonance wavelength to adjust, changing the plating layer free carrier concentration by applying a bias voltage to the external electrodes and adjusting the micro-ring cavity resonance wavelength, and changing the truth table of input optical fields and output optical fields to realize all-optical logic gate function switching.

2. The method of claim 1, wherein the chip implementation of integrated all-optical logic gates based on the plating layer structure is characterized by, The reference optical field of the incident carrier straight waveguide in the method will switch between the harmonic and detuned states and be output from different ports to realize all-optical logic operation.

3. The method of claim 1, wherein the chip implementation of integrated all-optical logic gates based on the plating layer structure is characterized by, The method specifically comprises the following steps: S1, preparing a micro-ring cavity, a carrier straight waveguide and an incident straight waveguide optical structure by a standard chip integrated optical path process, transferring transition metal sulfide to the surfaces of all waveguides and preparing external electrodes; S2, inputting two optical fields carrying incident bits into the incident straight waveguides, causing the plating layer free carrier concentration to change and the micro-ring cavity resonance wavelength to adjust, inputting a reference optical field into the carrier straight waveguide, outputting from one output port in the harmonic condition and from another output port in the detuned condition; S3, adjusting the micro-ring cavity intrinsic resonance frequency by applying different bias voltages to the plating layer through the external electrodes to realize the harmonic or detuned state of the reference optical field, and outputting the reference optical field from different ports under the dual action of electrically controlled tuning and optically controlled tuning of the micro-ring cavity resonance frequency to realize the free switching of the and, or, not, and not, or not, exclusive or and same or common seven operation functions.

4. The method of claim 1, wherein the chip implementation of integrated all-optical logic gates based on the plating layer structure is characterized by, The method realizes various logic operations by adjusting the micro-ring cavity resonance wavelength and selecting the output port.

5. The method of claim 1, wherein the chip implementation of integrated all-optical logic gates based on the plating layer structure is characterized by, In the all-optical logic operation of the method, two optical fields carry logic bits into the logic gate, and the high / low of the optical field intensity corresponds to 1 / 0 of the logic bits; in various logic operations, the center frequencies of the input optical field and the output optical field are consistent.

6. The method of claim 1, wherein the chip implementation of integrated all-optical logic gates based on the plating layer structure is characterized by, The plating layer is transferred to the chip integrated waveguide surface by the growth process control parameters and standard process without damage and realizes close fitting, and the crystal structure and layered thickness are used as the degrees of freedom to accurately regulate the electro-optical parameters. 7.A system for implementing the method for implementing integrated all-optical logic gates based on plating layer structure on a chip according to any one of claims 1-6, comprising a single chip integrated with a micro-ring cavity, a carrier straight waveguide and an incident straight waveguide, the single chip prepares a dual-carrier straight waveguide micro-ring cavity, two incident straight waveguides are prepared near the micro-ring cavity, transition metal sulfide is transferred to the surfaces of all waveguides and external electrodes are prepared, two optical fields carrying incident bits are input into the incident straight waveguides and the plating layer free carrier concentration changes and the micro-ring cavity resonance wavelength adjusts, the plating layer free carrier concentration changes by applying a bias voltage to the external electrodes and the micro-ring cavity resonance wavelength adjusts, and the truth table of input optical fields and output optical fields changes to realize all-optical logic gate function switching.

8. The system of claim 7, wherein, The system uses a single device structure and electrical control to realize free switching of seven operation functions of and, or, not, and not, or not, XOR, and XNOR, changes the micro-ring cavity resonance wavelength by the photo-induced free carrier of the coating material and the electric-induced free carrier of the coating material of the external electrode through the transmission of the light field in the two-way incident straight waveguide, so that the reference light field input by the carrier straight waveguide is output from different ports as needed; by adjusting the micro-ring cavity resonance wavelength and selecting the output port, various logic operations can be realized. 9.A computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the method of any one of claims 1-6.

Images